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iwlagn: generic bt coex functions
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
f0832f13 60#include "iwl-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
bee008b7 90static int iwlagn_ant_coupling;
f37837c9 91static bool iwlagn_bt_ch_announce = 1;
bee008b7 92
b481de9c 93/**
5b9f8cd3 94 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 95 *
01ebd063 96 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
100 */
e0158e61 101int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 102{
103 /* cast away the const for active_rxon in this function */
c1adf9fb 104 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG		 105 int ret;
106 bool new_assoc =
107 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 108
fee1247a 109 if (!iwl_is_alive(priv))
43d59b32 110 return -EBUSY;
b481de9c
ZY		 111
112 /* always get timestamp with Rx frame */
113 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
114
8ccde88a 115 ret = iwl_check_rxon_cmd(priv);
43d59b32 116 if (ret) {
15b1687c 117 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 118 return -EINVAL;
119 }
120
0924e519
WYG		 121 /*
122 * receive commit_rxon request
123 * abort any previous channel switch if still in process
124 */
125 if (priv->switch_rxon.switch_in_progress &&
126 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
127 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
128 le16_to_cpu(priv->switch_rxon.channel));
79d07325 129 iwl_chswitch_done(priv, false);
0924e519
WYG		 130 }
131
b481de9c 132 /* If we don't need to send a full RXON, we can use
5b9f8cd3 133 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 134 * and other flags for the current radio configuration. */
54559703 135 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG		 136 ret = iwl_send_rxon_assoc(priv);
137 if (ret) {
15b1687c 138 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 139 return ret;
b481de9c
ZY		 140 }
141
142 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 143 iwl_print_rx_config_cmd(priv);
b481de9c
ZY		 144 return 0;
145 }
146
b481de9c
ZY		 147 /* If we are currently associated and the new config requires
148 * an RXON_ASSOC and the new config wants the associated mask enabled,
149 * we must clear the associated from the active configuration
150 * before we apply the new config */
43d59b32 151 if (iwl_is_associated(priv) && new_assoc) {
e1623446 152 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 153 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
154
43d59b32 155 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 156 sizeof(struct iwl_rxon_cmd),
b481de9c
ZY		 157 &priv->active_rxon);
158
159 /* If the mask clearing failed then we set
160 * active_rxon back to what it was previously */
43d59b32 161 if (ret) {
b481de9c 162 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 163 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 164 return ret;
b481de9c 165 }
2c810ccd 166 iwl_clear_ucode_stations(priv);
7e246191 167 iwl_restore_stations(priv);
335348b1
JB		 168 ret = iwl_restore_default_wep_keys(priv);
169 if (ret) {
170 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
171 return ret;
172 }
b481de9c
ZY		 173 }
174
e1623446 175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 176 "* with%s RXON_FILTER_ASSOC_MSK\n"
177 "* channel = %d\n"
e174961c 178 "* bssid = %pM\n",
43d59b32 179 (new_assoc ? "" : "out"),
b481de9c 180 le16_to_cpu(priv->staging_rxon.channel),
e174961c 181 priv->staging_rxon.bssid_addr);
b481de9c 182
90e8e424 183 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG		 184
185 /* Apply the new configuration
7e246191
RC		 186 * RXON unassoc clears the station table in uCode so restoration of
187 * stations is needed after it (the RXON command) completes
43d59b32
EG		 188 */
189 if (!new_assoc) {
190 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 191 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 192 if (ret) {
15b1687c 193 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 194 return ret;
195 }
91dd6c27 196 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
43d59b32 197 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
2c810ccd 198 iwl_clear_ucode_stations(priv);
7e246191 199 iwl_restore_stations(priv);
335348b1
JB		 200 ret = iwl_restore_default_wep_keys(priv);
201 if (ret) {
202 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
203 return ret;
204 }
b481de9c
ZY		 205 }
206
19cc1087 207 priv->start_calib = 0;
9185159d 208 if (new_assoc) {
43d59b32
EG		 209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
211 */
212 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
213 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
214 if (ret) {
15b1687c 215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 216 return ret;
217 }
218 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 219 }
a643565e 220 iwl_print_rx_config_cmd(priv);
b481de9c 221
36da7d70
ZY		 222 iwl_init_sensitivity(priv);
223
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227 if (ret) {
15b1687c 228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 229 return ret;
230 }
231
b481de9c
ZY		 232 return 0;
233}
234
5b9f8cd3 235void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA		 236{
237
45823531
AK		 238 if (priv->cfg->ops->hcmd->set_rxon_chain)
239 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 240 iwlcore_commit_rxon(priv);
5da4b55f
MA		 241}
242
fcab423d 243static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 244{
245 struct list_head *element;
246
e1623446 247 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 248 priv->frames_count);
249
250 while (!list_empty(&priv->free_frames)) {
251 element = priv->free_frames.next;
252 list_del(element);
fcab423d 253 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 254 priv->frames_count--;
255 }
256
257 if (priv->frames_count) {
39aadf8c 258 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 259 priv->frames_count);
260 priv->frames_count = 0;
261 }
262}
263
fcab423d 264static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 265{
fcab423d 266 struct iwl_frame *frame;
b481de9c
ZY		 267 struct list_head *element;
268 if (list_empty(&priv->free_frames)) {
269 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
270 if (!frame) {
15b1687c 271 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 272 return NULL;
273 }
274
275 priv->frames_count++;
276 return frame;
277 }
278
279 element = priv->free_frames.next;
280 list_del(element);
fcab423d 281 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 282}
283
fcab423d 284static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 285{
286 memset(frame, 0, sizeof(*frame));
287 list_add(&frame->list, &priv->free_frames);
288}
289
47ff65c4 290static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 291 struct ieee80211_hdr *hdr,
73ec1cc2 292 int left)
b481de9c 293{
6abbe554 294 if (!priv->ibss_beacon)
b481de9c
ZY		 295 return 0;
296
297 if (priv->ibss_beacon->len > left)
298 return 0;
299
300 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
301
302 return priv->ibss_beacon->len;
303}
304
47ff65c4
DH		 305/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
306static void iwl_set_beacon_tim(struct iwl_priv *priv,
307 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
308 u8 *beacon, u32 frame_size)
309{
310 u16 tim_idx;
311 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
312
313 /*
314 * The index is relative to frame start but we start looking at the
315 * variable-length part of the beacon.
316 */
317 tim_idx = mgmt->u.beacon.variable - beacon;
318
319 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
320 while ((tim_idx < (frame_size - 2)) &&
321 (beacon[tim_idx] != WLAN_EID_TIM))
322 tim_idx += beacon[tim_idx+1] + 2;
323
324 /* If TIM field was found, set variables */
325 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
326 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
327 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
328 } else
329 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
330}
331
5b9f8cd3 332static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 333 struct iwl_frame *frame)
4bf64efd
TW		 334{
335 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 336 u32 frame_size;
337 u32 rate_flags;
338 u32 rate;
339 /*
340 * We have to set up the TX command, the TX Beacon command, and the
341 * beacon contents.
342 */
4bf64efd 343
47ff65c4 344 /* Initialize memory */
4bf64efd
TW		 345 tx_beacon_cmd = &frame->u.beacon;
346 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
347
47ff65c4 348 /* Set up TX beacon contents */
4bf64efd 349 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 350 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 351 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
352 return 0;
4bf64efd 353
47ff65c4 354 /* Set up TX command fields */
4bf64efd 355 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH		 356 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
357 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
358 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
359 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 360
47ff65c4
DH		 361 /* Set up TX beacon command fields */
362 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
363 frame_size);
4bf64efd 364
47ff65c4
DH		 365 /* Set up packet rate and flags */
366 rate = iwl_rate_get_lowest_plcp(priv);
0e1654fa
JB		 367 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
368 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 369 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
370 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
371 rate_flags |= RATE_MCS_CCK_MSK;
372 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
373 rate_flags);
4bf64efd
TW		 374
375 return sizeof(*tx_beacon_cmd) + frame_size;
376}
5b9f8cd3 377static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 378{
fcab423d 379 struct iwl_frame *frame;
b481de9c
ZY		 380 unsigned int frame_size;
381 int rc;
b481de9c 382
fcab423d 383 frame = iwl_get_free_frame(priv);
b481de9c 384 if (!frame) {
15b1687c 385 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 386 "command.\n");
387 return -ENOMEM;
388 }
389
47ff65c4
DH		 390 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
391 if (!frame_size) {
392 IWL_ERR(priv, "Error configuring the beacon command\n");
393 iwl_free_frame(priv, frame);
394 return -EINVAL;
395 }
b481de9c 396
857485c0 397 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 398 &frame->u.cmd[0]);
399
fcab423d 400 iwl_free_frame(priv, frame);
b481de9c
ZY		 401
402 return rc;
403}
404
7aaa1d79
SO		 405static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
406{
407 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
408
409 dma_addr_t addr = get_unaligned_le32(&tb->lo);
410 if (sizeof(dma_addr_t) > sizeof(u32))
411 addr |=
412 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
413
414 return addr;
415}
416
417static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
418{
419 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
420
421 return le16_to_cpu(tb->hi_n_len) >> 4;
422}
423
424static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
425 dma_addr_t addr, u16 len)
426{
427 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
428 u16 hi_n_len = len << 4;
429
430 put_unaligned_le32(addr, &tb->lo);
431 if (sizeof(dma_addr_t) > sizeof(u32))
432 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
433
434 tb->hi_n_len = cpu_to_le16(hi_n_len);
435
436 tfd->num_tbs = idx + 1;
437}
438
439static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
440{
441 return tfd->num_tbs & 0x1f;
442}
443
444/**
445 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
446 * @priv - driver private data
447 * @txq - tx queue
448 *
449 * Does NOT advance any TFD circular buffer read/write indexes
450 * Does NOT free the TFD itself (which is within circular buffer)
451 */
452void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
453{
59606ffa 454 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 455 struct iwl_tfd *tfd;
456 struct pci_dev *dev = priv->pci_dev;
457 int index = txq->q.read_ptr;
458 int i;
459 int num_tbs;
460
461 tfd = &tfd_tmp[index];
462
463 /* Sanity check on number of chunks */
464 num_tbs = iwl_tfd_get_num_tbs(tfd);
465
466 if (num_tbs >= IWL_NUM_OF_TBS) {
467 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
468 /* @todo issue fatal error, it is quite serious situation */
469 return;
470 }
471
472 /* Unmap tx_cmd */
473 if (num_tbs)
474 pci_unmap_single(dev,
2e724443
FT		 475 dma_unmap_addr(&txq->meta[index], mapping),
476 dma_unmap_len(&txq->meta[index], len),
96891cee 477 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 478
479 /* Unmap chunks, if any. */
ff0d91c3 480 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 481 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
482 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
483
ff0d91c3
JB		 484 /* free SKB */
485 if (txq->txb) {
486 struct sk_buff *skb;
6f80240e 487
ff0d91c3 488 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 489
ff0d91c3
JB		 490 /* can be called from irqs-disabled context */
491 if (skb) {
492 dev_kfree_skb_any(skb);
493 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 494 }
495 }
496}
497
498int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
499 struct iwl_tx_queue *txq,
500 dma_addr_t addr, u16 len,
501 u8 reset, u8 pad)
502{
503 struct iwl_queue *q;
59606ffa 504 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 505 u32 num_tbs;
506
507 q = &txq->q;
59606ffa
SO		 508 tfd_tmp = (struct iwl_tfd *)txq->tfds;
509 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 510
511 if (reset)
512 memset(tfd, 0, sizeof(*tfd));
513
514 num_tbs = iwl_tfd_get_num_tbs(tfd);
515
516 /* Each TFD can point to a maximum 20 Tx buffers */
517 if (num_tbs >= IWL_NUM_OF_TBS) {
518 IWL_ERR(priv, "Error can not send more than %d chunks\n",
519 IWL_NUM_OF_TBS);
520 return -EINVAL;
521 }
522
523 BUG_ON(addr & ~DMA_BIT_MASK(36));
524 if (unlikely(addr & ~IWL_TX_DMA_MASK))
525 IWL_ERR(priv, "Unaligned address = %llx\n",
526 (unsigned long long)addr);
527
528 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
529
530 return 0;
531}
532
a8e74e27
SO		 533/*
534 * Tell nic where to find circular buffer of Tx Frame Descriptors for
535 * given Tx queue, and enable the DMA channel used for that queue.
536 *
537 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
538 * channels supported in hardware.
539 */
540int iwl_hw_tx_queue_init(struct iwl_priv *priv,
541 struct iwl_tx_queue *txq)
542{
a8e74e27
SO		 543 int txq_id = txq->q.id;
544
a8e74e27
SO		 545 /* Circular buffer (TFD queue in DRAM) physical base address */
546 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
547 txq->q.dma_addr >> 8);
548
a8e74e27
SO		 549 return 0;
550}
551
b481de9c
ZY		 552/******************************************************************************
553 *
554 * Generic RX handler implementations
555 *
556 ******************************************************************************/
885ba202
TW		 557static void iwl_rx_reply_alive(struct iwl_priv *priv,
558 struct iwl_rx_mem_buffer *rxb)
b481de9c 559{
2f301227 560 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 561 struct iwl_alive_resp *palive;
b481de9c
ZY		 562 struct delayed_work *pwork;
563
564 palive = &pkt->u.alive_frame;
565
e1623446 566 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 567 "0x%01X 0x%01X\n",
568 palive->is_valid, palive->ver_type,
569 palive->ver_subtype);
570
571 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 572 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 573 memcpy(&priv->card_alive_init,
574 &pkt->u.alive_frame,
885ba202 575 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 576 pwork = &priv->init_alive_start;
577 } else {
e1623446 578 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 579 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 580 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 581 pwork = &priv->alive_start;
582 }
583
584 /* We delay the ALIVE response by 5ms to
585 * give the HW RF Kill time to activate... */
586 if (palive->is_valid == UCODE_VALID_OK)
587 queue_delayed_work(priv->workqueue, pwork,
588 msecs_to_jiffies(5));
589 else
39aadf8c 590 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 591}
592
5b9f8cd3 593static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 594{
c79dd5b5
TW		 595 struct iwl_priv *priv =
596 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 597 struct sk_buff *beacon;
598
599 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 600 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 601
602 if (!beacon) {
15b1687c 603 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 604 return;
605 }
606
607 mutex_lock(&priv->mutex);
608 /* new beacon skb is allocated every time; dispose previous.*/
609 if (priv->ibss_beacon)
610 dev_kfree_skb(priv->ibss_beacon);
611
612 priv->ibss_beacon = beacon;
613 mutex_unlock(&priv->mutex);
614
5b9f8cd3 615 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 616}
617
fbba9410
WYG		 618static void iwl_bg_bt_runtime_config(struct work_struct *work)
619{
620 struct iwl_priv *priv =
621 container_of(work, struct iwl_priv, bt_runtime_config);
622
623 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
624 return;
625
626 /* dont send host command if rf-kill is on */
627 if (!iwl_is_ready_rf(priv))
628 return;
629 priv->cfg->ops->hcmd->send_bt_config(priv);
630}
631
bee008b7
WYG		 632static void iwl_bg_bt_full_concurrency(struct work_struct *work)
633{
634 struct iwl_priv *priv =
635 container_of(work, struct iwl_priv, bt_full_concurrency);
636
637 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
638 return;
639
640 /* dont send host command if rf-kill is on */
641 if (!iwl_is_ready_rf(priv))
642 return;
643
644 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
645 priv->bt_full_concurrent ?
646 "full concurrency" : "3-wire");
647
648 /*
649 * LQ & RXON updated cmds must be sent before BT Config cmd
650 * to avoid 3-wire collisions
651 */
652 if (priv->cfg->ops->hcmd->set_rxon_chain)
653 priv->cfg->ops->hcmd->set_rxon_chain(priv);
654 iwlcore_commit_rxon(priv);
655
656 priv->cfg->ops->hcmd->send_bt_config(priv);
657}
658
4e39317d 659/**
5b9f8cd3 660 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 661 *
662 * This callback is provided in order to send a statistics request.
663 *
664 * This timer function is continually reset to execute within
665 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
666 * was received. We need to ensure we receive the statistics in order
667 * to update the temperature used for calibrating the TXPOWER.
668 */
5b9f8cd3 669static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 670{
671 struct iwl_priv *priv = (struct iwl_priv *)data;
672
673 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
674 return;
675
61780ee3
MA		 676 /* dont send host command if rf-kill is on */
677 if (!iwl_is_ready_rf(priv))
678 return;
679
ef8d5529 680 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 681}
682
a9e1cb6a
WYG		 683
684static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
685 u32 start_idx, u32 num_events,
686 u32 mode)
687{
688 u32 i;
689 u32 ptr; /* SRAM byte address of log data */
690 u32 ev, time, data; /* event log data */
691 unsigned long reg_flags;
692
693 if (mode == 0)
694 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
695 else
696 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
697
698 /* Make sure device is powered up for SRAM reads */
699 spin_lock_irqsave(&priv->reg_lock, reg_flags);
700 if (iwl_grab_nic_access(priv)) {
701 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
702 return;
703 }
704
705 /* Set starting address; reads will auto-increment */
706 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
707 rmb();
708
709 /*
710 * "time" is actually "data" for mode 0 (no timestamp).
711 * place event id # at far right for easier visual parsing.
712 */
713 for (i = 0; i < num_events; i++) {
714 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
715 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
716 if (mode == 0) {
717 trace_iwlwifi_dev_ucode_cont_event(priv,
718 0, time, ev);
719 } else {
720 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
721 trace_iwlwifi_dev_ucode_cont_event(priv,
722 time, data, ev);
723 }
724 }
725 /* Allow device to power down */
726 iwl_release_nic_access(priv);
727 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
728}
729
875295f1 730static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 731{
732 u32 capacity; /* event log capacity in # entries */
733 u32 base; /* SRAM byte address of event log header */
734 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
735 u32 num_wraps; /* # times uCode wrapped to top of log */
736 u32 next_entry; /* index of next entry to be written by uCode */
737
738 if (priv->ucode_type == UCODE_INIT)
739 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
740 else
741 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
742 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
743 capacity = iwl_read_targ_mem(priv, base);
744 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
745 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
746 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
747 } else
748 return;
749
750 if (num_wraps == priv->event_log.num_wraps) {
751 iwl_print_cont_event_trace(priv,
752 base, priv->event_log.next_entry,
753 next_entry - priv->event_log.next_entry,
754 mode);
755 priv->event_log.non_wraps_count++;
756 } else {
757 if ((num_wraps - priv->event_log.num_wraps) > 1)
758 priv->event_log.wraps_more_count++;
759 else
760 priv->event_log.wraps_once_count++;
761 trace_iwlwifi_dev_ucode_wrap_event(priv,
762 num_wraps - priv->event_log.num_wraps,
763 next_entry, priv->event_log.next_entry);
764 if (next_entry < priv->event_log.next_entry) {
765 iwl_print_cont_event_trace(priv, base,
766 priv->event_log.next_entry,
767 capacity - priv->event_log.next_entry,
768 mode);
769
770 iwl_print_cont_event_trace(priv, base, 0,
771 next_entry, mode);
772 } else {
773 iwl_print_cont_event_trace(priv, base,
774 next_entry, capacity - next_entry,
775 mode);
776
777 iwl_print_cont_event_trace(priv, base, 0,
778 next_entry, mode);
779 }
780 }
781 priv->event_log.num_wraps = num_wraps;
782 priv->event_log.next_entry = next_entry;
783}
784
785/**
786 * iwl_bg_ucode_trace - Timer callback to log ucode event
787 *
788 * The timer is continually set to execute every
789 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
790 * this function is to perform continuous uCode event logging operation
791 * if enabled
792 */
793static void iwl_bg_ucode_trace(unsigned long data)
794{
795 struct iwl_priv *priv = (struct iwl_priv *)data;
796
797 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
798 return;
799
800 if (priv->event_log.ucode_trace) {
801 iwl_continuous_event_trace(priv);
802 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
803 mod_timer(&priv->ucode_trace,
804 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
805 }
806}
807
5b9f8cd3 808static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 809 struct iwl_rx_mem_buffer *rxb)
b481de9c 810{
2f301227 811 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 812 struct iwl4965_beacon_notif *beacon =
813 (struct iwl4965_beacon_notif *)pkt->u.raw;
a85d7cca 814#ifdef CONFIG_IWLWIFI_DEBUG
e7d326ac 815 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 816
e1623446 817 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 818 "tsf %d %d rate %d\n",
25a6572c 819 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 820 beacon->beacon_notify_hdr.failure_frame,
821 le32_to_cpu(beacon->ibss_mgr_status),
822 le32_to_cpu(beacon->high_tsf),
823 le32_to_cpu(beacon->low_tsf), rate);
824#endif
825
a85d7cca
JB		 826 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
827
05c914fe 828 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 829 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
830 queue_work(priv->workqueue, &priv->beacon_update);
831}
832
b481de9c
ZY		 833/* Handle notification from uCode that card's power state is changing
834 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 835static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 836 struct iwl_rx_mem_buffer *rxb)
b481de9c 837{
2f301227 838 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 839 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
840 unsigned long status = priv->status;
841
3a41bbd5 842 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 843 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 844 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
845 (flags & CT_CARD_DISABLED) ?
846 "Reached" : "Not reached");
b481de9c
ZY		 847
848 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 849 CT_CARD_DISABLED)) {
b481de9c 850
3395f6e9 851 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 852 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
853
a8b50a0a
MA		 854 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
855 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 856
857 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 858 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 859 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 860 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 861 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 862 }
3a41bbd5 863 if (flags & CT_CARD_DISABLED)
39b73fb1 864 iwl_tt_enter_ct_kill(priv);
b481de9c 865 }
3a41bbd5 866 if (!(flags & CT_CARD_DISABLED))
39b73fb1 867 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 868
869 if (flags & HW_CARD_DISABLED)
870 set_bit(STATUS_RF_KILL_HW, &priv->status);
871 else
872 clear_bit(STATUS_RF_KILL_HW, &priv->status);
873
874
b481de9c 875 if (!(flags & RXON_CARD_DISABLED))
2a421b91 876 iwl_scan_cancel(priv);
b481de9c
ZY		 877
878 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 879 test_bit(STATUS_RF_KILL_HW, &priv->status)))
880 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
881 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 882 else
883 wake_up_interruptible(&priv->wait_command_queue);
884}
885
5b9f8cd3 886int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 887{
e2e3c57b 888 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 889 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 890 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
891 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
892 ~APMG_PS_CTRL_MSK_PWR_SRC);
893 } else {
894 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
895 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
896 ~APMG_PS_CTRL_MSK_PWR_SRC);
897 }
898
a8b50a0a 899 return 0;
e2e3c57b
TW		 900}
901
65550636
WYG		 902static void iwl_bg_tx_flush(struct work_struct *work)
903{
904 struct iwl_priv *priv =
905 container_of(work, struct iwl_priv, tx_flush);
906
907 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
908 return;
909
910 /* do nothing if rf-kill is on */
911 if (!iwl_is_ready_rf(priv))
912 return;
913
914 if (priv->cfg->ops->lib->txfifo_flush) {
915 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
916 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
917 }
918}
919
b481de9c 920/**
5b9f8cd3 921 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 922 *
923 * Setup the RX handlers for each of the reply types sent from the uCode
924 * to the host.
925 *
926 * This function chains into the hardware specific files for them to setup
927 * any hardware specific handlers as well.
928 */
653fa4a0 929static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 930{
885ba202 931 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 932 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
933 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 934 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
935 iwl_rx_spectrum_measure_notif;
5b9f8cd3 936 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 937 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 938 iwl_rx_pm_debug_statistics_notif;
939 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 940
9fbab516
BC		 941 /*
942 * The same handler is used for both the REPLY to a discrete
943 * statistics request from the host as well as for the periodic
944 * statistics notifications (after received beacons) from the uCode.
b481de9c 945 */
ef8d5529 946 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 947 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 948
949 iwl_setup_rx_scan_handlers(priv);
950
37a44211 951 /* status change handler */
5b9f8cd3 952 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 953
c1354754
TW		 954 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
955 iwl_rx_missed_beacon_notif;
37a44211 956 /* Rx handlers */
8d801080
WYG		 957 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
958 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 959 /* block ack */
74bcdb33 960 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 961 /* Set up hardware specific Rx handlers */
d4789efe 962 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 963}
964
b481de9c 965/**
a55360e4 966 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 967 *
968 * Uses the priv->rx_handlers callback function array to invoke
969 * the appropriate handlers, including command responses,
970 * frame-received notifications, and other notifications.
971 */
a55360e4 972void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 973{
a55360e4 974 struct iwl_rx_mem_buffer *rxb;
db11d634 975 struct iwl_rx_packet *pkt;
a55360e4 976 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 977 u32 r, i;
978 int reclaim;
979 unsigned long flags;
5c0eef96 980 u8 fill_rx = 0;
d68ab680 981 u32 count = 8;
4752c93c 982 int total_empty;
b481de9c 983
6440adb5
CB		 984 /* uCode's read index (stored in shared DRAM) indicates the last Rx
985 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 986 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 987 i = rxq->read;
988
989 /* Rx interrupt, but nothing sent from uCode */
990 if (i == r)
e1623446 991 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 992
4752c93c 993 /* calculate total frames need to be restock after handling RX */
7300515d 994 total_empty = r - rxq->write_actual;
4752c93c
MA		 995 if (total_empty < 0)
996 total_empty += RX_QUEUE_SIZE;
997
998 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 999 fill_rx = 1;
1000
b481de9c 1001 while (i != r) {
f4989d9b
JB		 1002 int len;
1003
b481de9c
ZY		 1004 rxb = rxq->queue[i];
1005
9fbab516 1006 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 1007 * then a bug has been introduced in the queue refilling
1008 * routines -- catch it here */
1009 BUG_ON(rxb == NULL);
1010
1011 rxq->queue[i] = NULL;
1012
2f301227
ZY		 1013 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1014 PAGE_SIZE << priv->hw_params.rx_page_order,
1015 PCI_DMA_FROMDEVICE);
1016 pkt = rxb_addr(rxb);
b481de9c 1017
f4989d9b
JB		 1018 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1019 len += sizeof(u32); /* account for status word */
1020 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 1021
b481de9c
ZY		 1022 /* Reclaim a command buffer only if this packet is a response
1023 * to a (driver-originated) command.
1024 * If the packet (e.g. Rx frame) originated from uCode,
1025 * there is no command buffer to reclaim.
1026 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1027 * but apparently a few don't get set; catch them here. */
1028 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1029 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 1030 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 1031 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 1032 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 1033 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1034 (pkt->hdr.cmd != REPLY_TX);
1035
1036 /* Based on type of command response or notification,
1037 * handle those that need handling via function in
5b9f8cd3 1038 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1039 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1040 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1041 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1042 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1043 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1044 } else {
1045 /* No handling needed */
e1623446 1046 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1047 "r %d i %d No handler needed for %s, 0x%02x\n",
1048 r, i, get_cmd_string(pkt->hdr.cmd),
1049 pkt->hdr.cmd);
1050 }
1051
29b1b268
ZY		 1052 /*
1053 * XXX: After here, we should always check rxb->page
1054 * against NULL before touching it or its virtual
1055 * memory (pkt). Because some rx_handler might have
1056 * already taken or freed the pages.
1057 */
1058
b481de9c 1059 if (reclaim) {
2f301227
ZY		 1060 /* Invoke any callbacks, transfer the buffer to caller,
1061 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1062 * as we reclaim the driver command queue */
29b1b268 1063 if (rxb->page)
17b88929 1064 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1065 else
39aadf8c 1066 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1067 }
1068
7300515d
ZY		 1069 /* Reuse the page if possible. For notification packets and
1070 * SKBs that fail to Rx correctly, add them back into the
1071 * rx_free list for reuse later. */
1072 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1073 if (rxb->page != NULL) {
7300515d
ZY		 1074 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1075 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1076 PCI_DMA_FROMDEVICE);
1077 list_add_tail(&rxb->list, &rxq->rx_free);
1078 rxq->free_count++;
1079 } else
1080 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1081
b481de9c 1082 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1083
b481de9c 1084 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1085 /* If there are a lot of unused frames,
1086 * restock the Rx queue so ucode wont assert. */
1087 if (fill_rx) {
1088 count++;
1089 if (count >= 8) {
7300515d 1090 rxq->read = i;
54b81550 1091 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1092 count = 0;
1093 }
1094 }
b481de9c
ZY		 1095 }
1096
1097 /* Backtrack one entry */
7300515d 1098 rxq->read = i;
4752c93c 1099 if (fill_rx)
54b81550 1100 iwlagn_rx_replenish_now(priv);
4752c93c 1101 else
54b81550 1102 iwlagn_rx_queue_restock(priv);
a55360e4 1103}
a55360e4 1104
0359facc
MA		 1105/* call this function to flush any scheduled tasklet */
1106static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1107{
a96a27f9 1108 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1109 synchronize_irq(priv->pci_dev->irq);
1110 tasklet_kill(&priv->irq_tasklet);
1111}
1112
ef850d7c 1113static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1114{
1115 u32 inta, handled = 0;
1116 u32 inta_fh;
1117 unsigned long flags;
c2e61da2 1118 u32 i;
0a6857e7 1119#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1120 u32 inta_mask;
1121#endif
1122
1123 spin_lock_irqsave(&priv->lock, flags);
1124
1125 /* Ack/clear/reset pending uCode interrupts.
1126 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1127 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1128 inta = iwl_read32(priv, CSR_INT);
1129 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1130
1131 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1132 * Any new interrupts that happen after this, either while we're
1133 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1134 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1135 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1136
0a6857e7 1137#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1138 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1139 /* just for debug */
3395f6e9 1140 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1141 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1142 inta, inta_mask, inta_fh);
1143 }
1144#endif
1145
2f301227
ZY		 1146 spin_unlock_irqrestore(&priv->lock, flags);
1147
b481de9c
ZY		 1148 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1149 * atomic, make sure that inta covers all the interrupts that
1150 * we've discovered, even if FH interrupt came in just after
1151 * reading CSR_INT. */
6f83eaa1 1152 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1153 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1154 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1155 inta |= CSR_INT_BIT_FH_TX;
1156
1157 /* Now service all interrupt bits discovered above. */
1158 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1159 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1160
1161 /* Tell the device to stop sending interrupts */
5b9f8cd3 1162 iwl_disable_interrupts(priv);
b481de9c 1163
a83b9141 1164 priv->isr_stats.hw++;
5b9f8cd3 1165 iwl_irq_handle_error(priv);
b481de9c
ZY		 1166
1167 handled |= CSR_INT_BIT_HW_ERR;
1168
b481de9c
ZY		 1169 return;
1170 }
1171
0a6857e7 1172#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1173 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1174 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1175 if (inta & CSR_INT_BIT_SCD) {
e1623446 1176 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1177 "the frame/frames.\n");
a83b9141
WYG		 1178 priv->isr_stats.sch++;
1179 }
b481de9c
ZY		 1180
1181 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1182 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1183 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1184 priv->isr_stats.alive++;
1185 }
b481de9c
ZY		 1186 }
1187#endif
1188 /* Safely ignore these bits for debug checks below */
25c03d8e 1189 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1190
9fbab516 1191 /* HW RF KILL switch toggled */
b481de9c
ZY		 1192 if (inta & CSR_INT_BIT_RF_KILL) {
1193 int hw_rf_kill = 0;
3395f6e9 1194 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1195 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1196 hw_rf_kill = 1;
1197
4c423a2b 1198 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1199 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1200
a83b9141
WYG		 1201 priv->isr_stats.rfkill++;
1202
a9efa652 1203 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1204 * the driver allows loading the ucode even if the radio
1205 * is killed. Hence update the killswitch state here. The
1206 * rfkill handler will care about restarting if needed.
a9efa652 1207 */
6cd0b1cb
HS		 1208 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1209 if (hw_rf_kill)
1210 set_bit(STATUS_RF_KILL_HW, &priv->status);
1211 else
1212 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1213 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1214 }
b481de9c
ZY		 1215
1216 handled |= CSR_INT_BIT_RF_KILL;
1217 }
1218
9fbab516 1219 /* Chip got too hot and stopped itself */
b481de9c 1220 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1221 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1222 priv->isr_stats.ctkill++;
b481de9c
ZY		 1223 handled |= CSR_INT_BIT_CT_KILL;
1224 }
1225
1226 /* Error detected by uCode */
1227 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1228 IWL_ERR(priv, "Microcode SW error detected. "
1229 " Restarting 0x%X.\n", inta);
a83b9141
WYG		 1230 priv->isr_stats.sw++;
1231 priv->isr_stats.sw_err = inta;
5b9f8cd3 1232 iwl_irq_handle_error(priv);
b481de9c
ZY		 1233 handled |= CSR_INT_BIT_SW_ERR;
1234 }
1235
c2e61da2
BC		 1236 /*
1237 * uCode wakes up after power-down sleep.
1238 * Tell device about any new tx or host commands enqueued,
1239 * and about any Rx buffers made available while asleep.
1240 */
b481de9c 1241 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1242 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1243 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1244 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1245 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1246 priv->isr_stats.wakeup++;
b481de9c
ZY		 1247 handled |= CSR_INT_BIT_WAKEUP;
1248 }
1249
1250 /* All uCode command responses, including Tx command responses,
1251 * Rx "responses" (frame-received notification), and other
1252 * notifications from uCode come through here*/
1253 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1254 iwl_rx_handle(priv);
a83b9141 1255 priv->isr_stats.rx++;
b481de9c
ZY		 1256 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1257 }
1258
c72cd19f 1259 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1260 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1261 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1262 priv->isr_stats.tx++;
b481de9c 1263 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1264 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1265 priv->ucode_write_complete = 1;
1266 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1267 }
1268
a83b9141 1269 if (inta & ~handled) {
15b1687c 1270 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1271 priv->isr_stats.unhandled++;
1272 }
b481de9c 1273
40cefda9 1274 if (inta & ~(priv->inta_mask)) {
39aadf8c 1275 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1276 inta & ~priv->inta_mask);
39aadf8c 1277 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1278 }
1279
1280 /* Re-enable all interrupts */
0359facc
MA		 1281 /* only Re-enable if diabled by irq */
1282 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1283 iwl_enable_interrupts(priv);
b481de9c 1284
0a6857e7 1285#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1286 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1287 inta = iwl_read32(priv, CSR_INT);
1288 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1289 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1290 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1291 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1292 }
1293#endif
b481de9c
ZY		 1294}
1295
ef850d7c
MA		 1296/* tasklet for iwlagn interrupt */
1297static void iwl_irq_tasklet(struct iwl_priv *priv)
1298{
1299 u32 inta = 0;
1300 u32 handled = 0;
1301 unsigned long flags;
8756990f 1302 u32 i;
ef850d7c
MA		 1303#ifdef CONFIG_IWLWIFI_DEBUG
1304 u32 inta_mask;
1305#endif
1306
1307 spin_lock_irqsave(&priv->lock, flags);
1308
1309 /* Ack/clear/reset pending uCode interrupts.
1310 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1311 */
48a6be6a
SZ		 1312 /* There is a hardware bug in the interrupt mask function that some
1313 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1314 * they are disabled in the CSR_INT_MASK register. Furthermore the
1315 * ICT interrupt handling mechanism has another bug that might cause
1316 * these unmasked interrupts fail to be detected. We workaround the
1317 * hardware bugs here by ACKing all the possible interrupts so that
1318 * interrupt coalescing can still be achieved.
1319 */
4a35ecf8 1320 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1321
a4c8b2a6 1322 inta = priv->_agn.inta;
ef850d7c
MA		 1323
1324#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1325 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1326 /* just for debug */
1327 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1328 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1329 inta, inta_mask);
1330 }
1331#endif
2f301227
ZY		 1332
1333 spin_unlock_irqrestore(&priv->lock, flags);
1334
a4c8b2a6
JB		 1335 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1336 priv->_agn.inta = 0;
ef850d7c
MA		 1337
1338 /* Now service all interrupt bits discovered above. */
1339 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1340 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1341
1342 /* Tell the device to stop sending interrupts */
1343 iwl_disable_interrupts(priv);
1344
1345 priv->isr_stats.hw++;
1346 iwl_irq_handle_error(priv);
1347
1348 handled |= CSR_INT_BIT_HW_ERR;
1349
ef850d7c
MA		 1350 return;
1351 }
1352
1353#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1354 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1355 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1356 if (inta & CSR_INT_BIT_SCD) {
1357 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1358 "the frame/frames.\n");
1359 priv->isr_stats.sch++;
1360 }
1361
1362 /* Alive notification via Rx interrupt will do the real work */
1363 if (inta & CSR_INT_BIT_ALIVE) {
1364 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1365 priv->isr_stats.alive++;
1366 }
1367 }
1368#endif
1369 /* Safely ignore these bits for debug checks below */
1370 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1371
1372 /* HW RF KILL switch toggled */
1373 if (inta & CSR_INT_BIT_RF_KILL) {
1374 int hw_rf_kill = 0;
1375 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1376 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1377 hw_rf_kill = 1;
1378
4c423a2b 1379 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1380 hw_rf_kill ? "disable radio" : "enable radio");
1381
1382 priv->isr_stats.rfkill++;
1383
1384 /* driver only loads ucode once setting the interface up.
1385 * the driver allows loading the ucode even if the radio
1386 * is killed. Hence update the killswitch state here. The
1387 * rfkill handler will care about restarting if needed.
1388 */
1389 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1390 if (hw_rf_kill)
1391 set_bit(STATUS_RF_KILL_HW, &priv->status);
1392 else
1393 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1394 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1395 }
1396
1397 handled |= CSR_INT_BIT_RF_KILL;
1398 }
1399
1400 /* Chip got too hot and stopped itself */
1401 if (inta & CSR_INT_BIT_CT_KILL) {
1402 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1403 priv->isr_stats.ctkill++;
1404 handled |= CSR_INT_BIT_CT_KILL;
1405 }
1406
1407 /* Error detected by uCode */
1408 if (inta & CSR_INT_BIT_SW_ERR) {
1409 IWL_ERR(priv, "Microcode SW error detected. "
1410 " Restarting 0x%X.\n", inta);
1411 priv->isr_stats.sw++;
1412 priv->isr_stats.sw_err = inta;
1413 iwl_irq_handle_error(priv);
1414 handled |= CSR_INT_BIT_SW_ERR;
1415 }
1416
1417 /* uCode wakes up after power-down sleep */
1418 if (inta & CSR_INT_BIT_WAKEUP) {
1419 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1420 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1421 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1422 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1423
1424 priv->isr_stats.wakeup++;
1425
1426 handled |= CSR_INT_BIT_WAKEUP;
1427 }
1428
1429 /* All uCode command responses, including Tx command responses,
1430 * Rx "responses" (frame-received notification), and other
1431 * notifications from uCode come through here*/
40cefda9
MA		 1432 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1433 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1434 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1435 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1436 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1437 iwl_write32(priv, CSR_FH_INT_STATUS,
1438 CSR49_FH_INT_RX_MASK);
1439 }
1440 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1441 handled |= CSR_INT_BIT_RX_PERIODIC;
1442 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1443 }
1444 /* Sending RX interrupt require many steps to be done in the
1445 * the device:
1446 * 1- write interrupt to current index in ICT table.
1447 * 2- dma RX frame.
1448 * 3- update RX shared data to indicate last write index.
1449 * 4- send interrupt.
1450 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1451 * but the shared data changes does not reflect this;
1452 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1453 */
74ba67ed
BC		 1454
1455 /* Disable periodic interrupt; we use it as just a one-shot. */
1456 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1457 CSR_INT_PERIODIC_DIS);
ef850d7c 1458 iwl_rx_handle(priv);
74ba67ed
BC		 1459
1460 /*
1461 * Enable periodic interrupt in 8 msec only if we received
1462 * real RX interrupt (instead of just periodic int), to catch
1463 * any dangling Rx interrupt. If it was just the periodic
1464 * interrupt, there was no dangling Rx activity, and no need
1465 * to extend the periodic interrupt; one-shot is enough.
1466 */
40cefda9 1467 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1468 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1469 CSR_INT_PERIODIC_ENA);
1470
ef850d7c 1471 priv->isr_stats.rx++;
ef850d7c
MA		 1472 }
1473
c72cd19f 1474 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1475 if (inta & CSR_INT_BIT_FH_TX) {
1476 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1477 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1478 priv->isr_stats.tx++;
1479 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1480 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1481 priv->ucode_write_complete = 1;
1482 wake_up_interruptible(&priv->wait_command_queue);
1483 }
1484
1485 if (inta & ~handled) {
1486 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1487 priv->isr_stats.unhandled++;
1488 }
1489
40cefda9 1490 if (inta & ~(priv->inta_mask)) {
ef850d7c 1491 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1492 inta & ~priv->inta_mask);
ef850d7c
MA		 1493 }
1494
ef850d7c
MA		 1495 /* Re-enable all interrupts */
1496 /* only Re-enable if diabled by irq */
1497 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1498 iwl_enable_interrupts(priv);
ef850d7c
MA		 1499}
1500
872c8ddc
WYG		 1501/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1502#define ACK_CNT_RATIO (50)
1503#define BA_TIMEOUT_CNT (5)
1504#define BA_TIMEOUT_MAX (16)
1505
1506/**
1507 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1508 *
1509 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1510 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1511 * operation state.
1512 */
1513bool iwl_good_ack_health(struct iwl_priv *priv,
1514 struct iwl_rx_packet *pkt)
1515{
1516 bool rc = true;
1517 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1518 int ba_timeout_delta;
1519
1520 actual_ack_cnt_delta =
1521 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1522 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1523 expected_ack_cnt_delta =
1524 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1525 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1526 ba_timeout_delta =
1527 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1528 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1529 if ((priv->_agn.agg_tids_count > 0) &&
1530 (expected_ack_cnt_delta > 0) &&
1531 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1532 < ACK_CNT_RATIO) &&
1533 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1534 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1535 " expected_ack_cnt = %d\n",
1536 actual_ack_cnt_delta, expected_ack_cnt_delta);
1537
d73e4923
JB		 1538#ifdef CONFIG_IWLWIFI_DEBUGFS
1539 /*
1540 * This is ifdef'ed on DEBUGFS because otherwise the
1541 * statistics aren't available. If DEBUGFS is set but
1542 * DEBUG is not, these will just compile out.
1543 */
872c8ddc 1544 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1545 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1546 IWL_DEBUG_RADIO(priv,
1547 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1548 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1549 ack_or_ba_timeout_collision);
1550#endif
1551 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1552 ba_timeout_delta);
1553 if (!actual_ack_cnt_delta &&
1554 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1555 rc = false;
1556 }
1557 return rc;
1558}
1559
a83b9141 1560
7d47618a
EG		 1561/*****************************************************************************
1562 *
1563 * sysfs attributes
1564 *
1565 *****************************************************************************/
1566
1567#ifdef CONFIG_IWLWIFI_DEBUG
1568
1569/*
1570 * The following adds a new attribute to the sysfs representation
1571 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1572 * used for controlling the debug level.
1573 *
1574 * See the level definitions in iwl for details.
1575 *
1576 * The debug_level being managed using sysfs below is a per device debug
1577 * level that is used instead of the global debug level if it (the per
1578 * device debug level) is set.
1579 */
1580static ssize_t show_debug_level(struct device *d,
1581 struct device_attribute *attr, char *buf)
1582{
1583 struct iwl_priv *priv = dev_get_drvdata(d);
1584 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1585}
1586static ssize_t store_debug_level(struct device *d,
1587 struct device_attribute *attr,
1588 const char *buf, size_t count)
1589{
1590 struct iwl_priv *priv = dev_get_drvdata(d);
1591 unsigned long val;
1592 int ret;
1593
1594 ret = strict_strtoul(buf, 0, &val);
1595 if (ret)
1596 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1597 else {
1598 priv->debug_level = val;
1599 if (iwl_alloc_traffic_mem(priv))
1600 IWL_ERR(priv,
1601 "Not enough memory to generate traffic log\n");
1602 }
1603 return strnlen(buf, count);
1604}
1605
1606static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1607 show_debug_level, store_debug_level);
1608
1609
1610#endif /* CONFIG_IWLWIFI_DEBUG */
1611
1612
1613static ssize_t show_temperature(struct device *d,
1614 struct device_attribute *attr, char *buf)
1615{
1616 struct iwl_priv *priv = dev_get_drvdata(d);
1617
1618 if (!iwl_is_alive(priv))
1619 return -EAGAIN;
1620
1621 return sprintf(buf, "%d\n", priv->temperature);
1622}
1623
1624static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1625
1626static ssize_t show_tx_power(struct device *d,
1627 struct device_attribute *attr, char *buf)
1628{
1629 struct iwl_priv *priv = dev_get_drvdata(d);
1630
1631 if (!iwl_is_ready_rf(priv))
1632 return sprintf(buf, "off\n");
1633 else
1634 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1635}
1636
1637static ssize_t store_tx_power(struct device *d,
1638 struct device_attribute *attr,
1639 const char *buf, size_t count)
1640{
1641 struct iwl_priv *priv = dev_get_drvdata(d);
1642 unsigned long val;
1643 int ret;
1644
1645 ret = strict_strtoul(buf, 10, &val);
1646 if (ret)
1647 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1648 else {
1649 ret = iwl_set_tx_power(priv, val, false);
1650 if (ret)
1651 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1652 ret);
1653 else
1654 ret = count;
1655 }
1656 return ret;
1657}
1658
1659static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1660
7d47618a
EG		 1661static struct attribute *iwl_sysfs_entries[] = {
1662 &dev_attr_temperature.attr,
1663 &dev_attr_tx_power.attr,
7d47618a
EG		 1664#ifdef CONFIG_IWLWIFI_DEBUG
1665 &dev_attr_debug_level.attr,
1666#endif
1667 NULL
1668};
1669
1670static struct attribute_group iwl_attribute_group = {
1671 .name = NULL, /* put in device directory */
1672 .attrs = iwl_sysfs_entries,
1673};
1674
b481de9c
ZY		 1675/******************************************************************************
1676 *
1677 * uCode download functions
1678 *
1679 ******************************************************************************/
1680
5b9f8cd3 1681static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1682{
98c92211
TW		 1683 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1684 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1685 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1686 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1687 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1688 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1689}
1690
5b9f8cd3 1691static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1692{
1693 /* Remove all resets to allow NIC to operate */
1694 iwl_write32(priv, CSR_RESET, 0);
1695}
1696
dd7a2509
JB		 1697struct iwlagn_ucode_capabilities {
1698 u32 max_probe_length;
6a822d06 1699 u32 standard_phy_calibration_size;
dd7a2509 1700};
edcdf8b2 1701
b08dfd04 1702static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1703static int iwl_mac_setup_register(struct iwl_priv *priv,
1704 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1705
39396085
JS		 1706#define UCODE_EXPERIMENTAL_INDEX 100
1707#define UCODE_EXPERIMENTAL_TAG "exp"
1708
b08dfd04
JB		 1709static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1710{
1711 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1712 char tag[8];
b08dfd04 1713
39396085
JS		 1714 if (first) {
1715#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1716 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1717 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1718 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1719#endif
b08dfd04 1720 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1721 sprintf(tag, "%d", priv->fw_index);
1722 } else {
b08dfd04 1723 priv->fw_index--;
39396085
JS		 1724 sprintf(tag, "%d", priv->fw_index);
1725 }
b08dfd04
JB		 1726
1727 if (priv->fw_index < priv->cfg->ucode_api_min) {
1728 IWL_ERR(priv, "no suitable firmware found!\n");
1729 return -ENOENT;
1730 }
1731
39396085 1732 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1733
39396085
JS		 1734 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1735 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1736 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1737 priv->firmware_name);
1738
1739 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1740 &priv->pci_dev->dev, GFP_KERNEL, priv,
1741 iwl_ucode_callback);
1742}
1743
0e9a44dc
JB		 1744struct iwlagn_firmware_pieces {
1745 const void *inst, *data, *init, *init_data, *boot;
1746 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1747
1748 u32 build;
b2e640d4
JB		 1749
1750 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1751 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1752};
1753
1754static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1755 const struct firmware *ucode_raw,
1756 struct iwlagn_firmware_pieces *pieces)
1757{
1758 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1759 u32 api_ver, hdr_size;
1760 const u8 *src;
1761
1762 priv->ucode_ver = le32_to_cpu(ucode->ver);
1763 api_ver = IWL_UCODE_API(priv->ucode_ver);
1764
1765 switch (api_ver) {
1766 default:
1767 /*
1768 * 4965 doesn't revision the firmware file format
1769 * along with the API version, it always uses v1
1770 * file format.
1771 */
1772 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1773 CSR_HW_REV_TYPE_4965) {
1774 hdr_size = 28;
1775 if (ucode_raw->size < hdr_size) {
1776 IWL_ERR(priv, "File size too small!\n");
1777 return -EINVAL;
1778 }
1779 pieces->build = le32_to_cpu(ucode->u.v2.build);
1780 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1781 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1782 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1783 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1784 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1785 src = ucode->u.v2.data;
1786 break;
1787 }
1788 /* fall through for 4965 */
1789 case 0:
1790 case 1:
1791 case 2:
1792 hdr_size = 24;
1793 if (ucode_raw->size < hdr_size) {
1794 IWL_ERR(priv, "File size too small!\n");
1795 return -EINVAL;
1796 }
1797 pieces->build = 0;
1798 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1799 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1800 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1801 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1802 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1803 src = ucode->u.v1.data;
1804 break;
1805 }
1806
1807 /* Verify size of file vs. image size info in file's header */
1808 if (ucode_raw->size != hdr_size + pieces->inst_size +
1809 pieces->data_size + pieces->init_size +
1810 pieces->init_data_size + pieces->boot_size) {
1811
1812 IWL_ERR(priv,
1813 "uCode file size %d does not match expected size\n",
1814 (int)ucode_raw->size);
1815 return -EINVAL;
1816 }
1817
1818 pieces->inst = src;
1819 src += pieces->inst_size;
1820 pieces->data = src;
1821 src += pieces->data_size;
1822 pieces->init = src;
1823 src += pieces->init_size;
1824 pieces->init_data = src;
1825 src += pieces->init_data_size;
1826 pieces->boot = src;
1827 src += pieces->boot_size;
1828
1829 return 0;
1830}
1831
dd7a2509
JB		 1832static int iwlagn_wanted_ucode_alternative = 1;
1833
1834static int iwlagn_load_firmware(struct iwl_priv *priv,
1835 const struct firmware *ucode_raw,
1836 struct iwlagn_firmware_pieces *pieces,
1837 struct iwlagn_ucode_capabilities *capa)
1838{
1839 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1840 struct iwl_ucode_tlv *tlv;
1841 size_t len = ucode_raw->size;
1842 const u8 *data;
1843 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1844 u64 alternatives;
ad8d8333
WYG		 1845 u32 tlv_len;
1846 enum iwl_ucode_tlv_type tlv_type;
1847 const u8 *tlv_data;
dd7a2509 1848
ad8d8333
WYG		 1849 if (len < sizeof(*ucode)) {
1850 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1851 return -EINVAL;
ad8d8333 1852 }
dd7a2509 1853
ad8d8333
WYG		 1854 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1855 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1856 le32_to_cpu(ucode->magic));
dd7a2509 1857 return -EINVAL;
ad8d8333 1858 }
dd7a2509
JB		 1859
1860 /*
1861 * Check which alternatives are present, and "downgrade"
1862 * when the chosen alternative is not present, warning
1863 * the user when that happens. Some files may not have
1864 * any alternatives, so don't warn in that case.
1865 */
1866 alternatives = le64_to_cpu(ucode->alternatives);
1867 tmp = wanted_alternative;
1868 if (wanted_alternative > 63)
1869 wanted_alternative = 63;
1870 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1871 wanted_alternative--;
1872 if (wanted_alternative && wanted_alternative != tmp)
1873 IWL_WARN(priv,
1874 "uCode alternative %d not available, choosing %d\n",
1875 tmp, wanted_alternative);
1876
1877 priv->ucode_ver = le32_to_cpu(ucode->ver);
1878 pieces->build = le32_to_cpu(ucode->build);
1879 data = ucode->data;
1880
1881 len -= sizeof(*ucode);
1882
704da534 1883 while (len >= sizeof(*tlv)) {
dd7a2509 1884 u16 tlv_alt;
dd7a2509
JB		 1885
1886 len -= sizeof(*tlv);
1887 tlv = (void *)data;
1888
1889 tlv_len = le32_to_cpu(tlv->length);
1890 tlv_type = le16_to_cpu(tlv->type);
1891 tlv_alt = le16_to_cpu(tlv->alternative);
1892 tlv_data = tlv->data;
1893
ad8d8333
WYG		 1894 if (len < tlv_len) {
1895 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1896 len, tlv_len);
dd7a2509 1897 return -EINVAL;
ad8d8333 1898 }
dd7a2509
JB		 1899 len -= ALIGN(tlv_len, 4);
1900 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1901
1902 /*
1903 * Alternative 0 is always valid.
1904 *
1905 * Skip alternative TLVs that are not selected.
1906 */
1907 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1908 continue;
1909
1910 switch (tlv_type) {
1911 case IWL_UCODE_TLV_INST:
1912 pieces->inst = tlv_data;
1913 pieces->inst_size = tlv_len;
1914 break;
1915 case IWL_UCODE_TLV_DATA:
1916 pieces->data = tlv_data;
1917 pieces->data_size = tlv_len;
1918 break;
1919 case IWL_UCODE_TLV_INIT:
1920 pieces->init = tlv_data;
1921 pieces->init_size = tlv_len;
1922 break;
1923 case IWL_UCODE_TLV_INIT_DATA:
1924 pieces->init_data = tlv_data;
1925 pieces->init_data_size = tlv_len;
1926 break;
1927 case IWL_UCODE_TLV_BOOT:
1928 pieces->boot = tlv_data;
1929 pieces->boot_size = tlv_len;
1930 break;
1931 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1932 if (tlv_len != sizeof(u32))
1933 goto invalid_tlv_len;
1934 capa->max_probe_length =
ad8d8333 1935 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1936 break;
b2e640d4 1937 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1938 if (tlv_len != sizeof(u32))
1939 goto invalid_tlv_len;
1940 pieces->init_evtlog_ptr =
ad8d8333 1941 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1942 break;
1943 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1944 if (tlv_len != sizeof(u32))
1945 goto invalid_tlv_len;
1946 pieces->init_evtlog_size =
ad8d8333 1947 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1948 break;
1949 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1950 if (tlv_len != sizeof(u32))
1951 goto invalid_tlv_len;
1952 pieces->init_errlog_ptr =
ad8d8333 1953 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1954 break;
1955 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1956 if (tlv_len != sizeof(u32))
1957 goto invalid_tlv_len;
1958 pieces->inst_evtlog_ptr =
ad8d8333 1959 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1960 break;
1961 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 1962 if (tlv_len != sizeof(u32))
1963 goto invalid_tlv_len;
1964 pieces->inst_evtlog_size =
ad8d8333 1965 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1966 break;
1967 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 1968 if (tlv_len != sizeof(u32))
1969 goto invalid_tlv_len;
1970 pieces->inst_errlog_ptr =
ad8d8333 1971 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1972 break;
c8312fac
WYG		 1973 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1974 if (tlv_len)
704da534
JB		 1975 goto invalid_tlv_len;
1976 priv->enhance_sensitivity_table = true;
c8312fac 1977 break;
6a822d06 1978 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 1979 if (tlv_len != sizeof(u32))
1980 goto invalid_tlv_len;
1981 capa->standard_phy_calibration_size =
6a822d06
WYG		 1982 le32_to_cpup((__le32 *)tlv_data);
1983 break;
dd7a2509 1984 default:
ad8d8333 1985 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 1986 break;
1987 }
1988 }
1989
ad8d8333
WYG		 1990 if (len) {
1991 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1992 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 1993 return -EINVAL;
ad8d8333 1994 }
dd7a2509 1995
704da534
JB		 1996 return 0;
1997
1998 invalid_tlv_len:
1999 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2000 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2001
2002 return -EINVAL;
dd7a2509
JB		 2003}
2004
b481de9c 2005/**
b08dfd04 2006 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 2007 *
b08dfd04
JB		 2008 * If loaded successfully, copies the firmware into buffers
2009 * for the card to fetch (via DMA).
b481de9c 2010 */
b08dfd04 2011static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 2012{
b08dfd04 2013 struct iwl_priv *priv = context;
cc0f555d 2014 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 2015 int err;
2016 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2017 const unsigned int api_max = priv->cfg->ucode_api_max;
2018 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2019 u32 api_ver;
3e4de761 2020 char buildstr[25];
0e9a44dc 2021 u32 build;
dd7a2509
JB		 2022 struct iwlagn_ucode_capabilities ucode_capa = {
2023 .max_probe_length = 200,
6a822d06
WYG		 2024 .standard_phy_calibration_size =
2025 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 2026 };
0e9a44dc
JB		 2027
2028 memset(&pieces, 0, sizeof(pieces));
b481de9c 2029
b08dfd04 2030 if (!ucode_raw) {
39396085
JS		 2031 if (priv->fw_index <= priv->cfg->ucode_api_max)
2032 IWL_ERR(priv,
2033 "request for firmware file '%s' failed.\n",
2034 priv->firmware_name);
b08dfd04 2035 goto try_again;
b481de9c
ZY		 2036 }
2037
b08dfd04
JB		 2038 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2039 priv->firmware_name, ucode_raw->size);
b481de9c 2040
22adba2a
JB		 2041 /* Make sure that we got at least the API version number */
2042 if (ucode_raw->size < 4) {
15b1687c 2043 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2044 goto try_again;
b481de9c
ZY		 2045 }
2046
2047 /* Data from ucode file: header followed by uCode images */
cc0f555d 2048 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2049
0e9a44dc
JB		 2050 if (ucode->ver)
2051 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2052 else
dd7a2509
JB		 2053 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2054 &ucode_capa);
22adba2a 2055
0e9a44dc
JB		 2056 if (err)
2057 goto try_again;
b481de9c 2058
a0987a8d 2059 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2060 build = pieces.build;
a0987a8d 2061
0e9a44dc
JB		 2062 /*
2063 * api_ver should match the api version forming part of the
2064 * firmware filename ... but we don't check for that and only rely
2065 * on the API version read from firmware header from here on forward
2066 */
a0987a8d 2067 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2068 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2069 "Driver supports v%u, firmware is v%u.\n",
2070 api_max, api_ver);
b08dfd04 2071 goto try_again;
a0987a8d 2072 }
b08dfd04 2073
a0987a8d 2074 if (api_ver != api_max)
978785a3 2075 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2076 "got v%u. New firmware can be obtained "
2077 "from http://www.intellinuxwireless.org.\n",
2078 api_max, api_ver);
2079
3e4de761 2080 if (build)
39396085
JS		 2081 sprintf(buildstr, " build %u%s", build,
2082 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2083 ? " (EXP)" : "");
3e4de761
JB		 2084 else
2085 buildstr[0] = '\0';
2086
2087 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2088 IWL_UCODE_MAJOR(priv->ucode_ver),
2089 IWL_UCODE_MINOR(priv->ucode_ver),
2090 IWL_UCODE_API(priv->ucode_ver),
2091 IWL_UCODE_SERIAL(priv->ucode_ver),
2092 buildstr);
a0987a8d 2093
5ebeb5a6
RC		 2094 snprintf(priv->hw->wiphy->fw_version,
2095 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2096 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2097 IWL_UCODE_MAJOR(priv->ucode_ver),
2098 IWL_UCODE_MINOR(priv->ucode_ver),
2099 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2100 IWL_UCODE_SERIAL(priv->ucode_ver),
2101 buildstr);
b481de9c 2102
b08dfd04
JB		 2103 /*
2104 * For any of the failures below (before allocating pci memory)
2105 * we will try to load a version with a smaller API -- maybe the
2106 * user just got a corrupted version of the latest API.
2107 */
2108
0e9a44dc
JB		 2109 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2110 priv->ucode_ver);
2111 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2112 pieces.inst_size);
2113 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2114 pieces.data_size);
2115 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2116 pieces.init_size);
2117 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2118 pieces.init_data_size);
2119 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2120 pieces.boot_size);
b481de9c
ZY		 2121
2122 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2123 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2124 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2125 pieces.inst_size);
b08dfd04 2126 goto try_again;
b481de9c
ZY		 2127 }
2128
0e9a44dc
JB		 2129 if (pieces.data_size > priv->hw_params.max_data_size) {
2130 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2131 pieces.data_size);
b08dfd04 2132 goto try_again;
b481de9c 2133 }
0e9a44dc
JB		 2134
2135 if (pieces.init_size > priv->hw_params.max_inst_size) {
2136 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2137 pieces.init_size);
b08dfd04 2138 goto try_again;
b481de9c 2139 }
0e9a44dc
JB		 2140
2141 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2142 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2143 pieces.init_data_size);
b08dfd04 2144 goto try_again;
b481de9c 2145 }
0e9a44dc
JB		 2146
2147 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2148 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2149 pieces.boot_size);
b08dfd04 2150 goto try_again;
b481de9c
ZY		 2151 }
2152
2153 /* Allocate ucode buffers for card's bus-master loading ... */
2154
2155 /* Runtime instructions and 2 copies of data:
2156 * 1) unmodified from disk
2157 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2158 priv->ucode_code.len = pieces.inst_size;
98c92211 2159 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2160
0e9a44dc 2161 priv->ucode_data.len = pieces.data_size;
98c92211 2162 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2163
0e9a44dc 2164 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2165 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2166
1f304e4e
ZY		 2167 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2168 !priv->ucode_data_backup.v_addr)
2169 goto err_pci_alloc;
2170
b481de9c 2171 /* Initialization instructions and data */
0e9a44dc
JB		 2172 if (pieces.init_size && pieces.init_data_size) {
2173 priv->ucode_init.len = pieces.init_size;
98c92211 2174 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2175
0e9a44dc 2176 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2177 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2178
2179 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2180 goto err_pci_alloc;
2181 }
b481de9c
ZY		 2182
2183 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2184 if (pieces.boot_size) {
2185 priv->ucode_boot.len = pieces.boot_size;
98c92211 2186 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2187
90e759d1
TW		 2188 if (!priv->ucode_boot.v_addr)
2189 goto err_pci_alloc;
2190 }
b481de9c 2191
b2e640d4
JB		 2192 /* Now that we can no longer fail, copy information */
2193
2194 /*
2195 * The (size - 16) / 12 formula is based on the information recorded
2196 * for each event, which is of mode 1 (including timestamp) for all
2197 * new microcodes that include this information.
2198 */
2199 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2200 if (pieces.init_evtlog_size)
2201 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2202 else
2203 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2204 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2205 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2206 if (pieces.inst_evtlog_size)
2207 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2208 else
2209 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2210 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2211
b481de9c
ZY		 2212 /* Copy images into buffers for card's bus-master reads ... */
2213
2214 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2215 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2216 pieces.inst_size);
2217 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2218
e1623446 2219 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2220 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2221
0e9a44dc
JB		 2222 /*
2223 * Runtime data
2224 * NOTE: Copy into backup buffer will be done in iwl_up()
2225 */
2226 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2227 pieces.data_size);
2228 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2229 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2230
2231 /* Initialization instructions */
2232 if (pieces.init_size) {
e1623446 2233 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2234 pieces.init_size);
2235 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2236 }
2237
0e9a44dc
JB		 2238 /* Initialization data */
2239 if (pieces.init_data_size) {
e1623446 2240 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2241 pieces.init_data_size);
2242 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2243 pieces.init_data_size);
b481de9c
ZY		 2244 }
2245
0e9a44dc
JB		 2246 /* Bootstrap instructions */
2247 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2248 pieces.boot_size);
2249 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2250
6a822d06
WYG		 2251 /*
2252 * figure out the offset of chain noise reset and gain commands
2253 * base on the size of standard phy calibration commands table size
2254 */
2255 if (ucode_capa.standard_phy_calibration_size >
2256 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2257 ucode_capa.standard_phy_calibration_size =
2258 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2259
2260 priv->_agn.phy_calib_chain_noise_reset_cmd =
2261 ucode_capa.standard_phy_calibration_size;
2262 priv->_agn.phy_calib_chain_noise_gain_cmd =
2263 ucode_capa.standard_phy_calibration_size + 1;
2264
b08dfd04
JB		 2265 /**************************************************
2266 * This is still part of probe() in a sense...
2267 *
2268 * 9. Setup and register with mac80211 and debugfs
2269 **************************************************/
dd7a2509 2270 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2271 if (err)
2272 goto out_unbind;
2273
2274 err = iwl_dbgfs_register(priv, DRV_NAME);
2275 if (err)
2276 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2277
7d47618a
EG		 2278 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2279 &iwl_attribute_group);
2280 if (err) {
2281 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2282 goto out_unbind;
2283 }
2284
b481de9c
ZY		 2285 /* We have our copies now, allow OS release its copies */
2286 release_firmware(ucode_raw);
a15707d8 2287 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2288 return;
2289
2290 try_again:
2291 /* try next, if any */
2292 if (iwl_request_firmware(priv, false))
2293 goto out_unbind;
2294 release_firmware(ucode_raw);
2295 return;
b481de9c
ZY		 2296
2297 err_pci_alloc:
15b1687c 2298 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2299 iwl_dealloc_ucode_pci(priv);
b08dfd04 2300 out_unbind:
a15707d8 2301 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2302 device_release_driver(&priv->pci_dev->dev);
b481de9c 2303 release_firmware(ucode_raw);
b481de9c
ZY		 2304}
2305
b7a79404
RC		 2306static const char *desc_lookup_text[] = {
2307 "OK",
2308 "FAIL",
2309 "BAD_PARAM",
2310 "BAD_CHECKSUM",
2311 "NMI_INTERRUPT_WDG",
2312 "SYSASSERT",
2313 "FATAL_ERROR",
2314 "BAD_COMMAND",
2315 "HW_ERROR_TUNE_LOCK",
2316 "HW_ERROR_TEMPERATURE",
2317 "ILLEGAL_CHAN_FREQ",
2318 "VCC_NOT_STABLE",
2319 "FH_ERROR",
2320 "NMI_INTERRUPT_HOST",
2321 "NMI_INTERRUPT_ACTION_PT",
2322 "NMI_INTERRUPT_UNKNOWN",
2323 "UCODE_VERSION_MISMATCH",
2324 "HW_ERROR_ABS_LOCK",
2325 "HW_ERROR_CAL_LOCK_FAIL",
2326 "NMI_INTERRUPT_INST_ACTION_PT",
2327 "NMI_INTERRUPT_DATA_ACTION_PT",
2328 "NMI_TRM_HW_ER",
2329 "NMI_INTERRUPT_TRM",
2330 "NMI_INTERRUPT_BREAK_POINT"
2331 "DEBUG_0",
2332 "DEBUG_1",
2333 "DEBUG_2",
2334 "DEBUG_3",
b7a79404
RC		 2335};
2336
4b58645c
JS		 2337static struct { char *name; u8 num; } advanced_lookup[] = {
2338 { "NMI_INTERRUPT_WDG", 0x34 },
2339 { "SYSASSERT", 0x35 },
2340 { "UCODE_VERSION_MISMATCH", 0x37 },
2341 { "BAD_COMMAND", 0x38 },
2342 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2343 { "FATAL_ERROR", 0x3D },
2344 { "NMI_TRM_HW_ERR", 0x46 },
2345 { "NMI_INTERRUPT_TRM", 0x4C },
2346 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2347 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2348 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2349 { "NMI_INTERRUPT_HOST", 0x66 },
2350 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2351 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2352 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2353 { "ADVANCED_SYSASSERT", 0 },
2354};
2355
2356static const char *desc_lookup(u32 num)
b7a79404 2357{
4b58645c
JS		 2358 int i;
2359 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2360
4b58645c
JS		 2361 if (num < max)
2362 return desc_lookup_text[num];
b7a79404 2363
4b58645c
JS		 2364 max = ARRAY_SIZE(advanced_lookup) - 1;
2365 for (i = 0; i < max; i++) {
2366 if (advanced_lookup[i].num == num)
2367 break;;
2368 }
2369 return advanced_lookup[i].name;
b7a79404
RC		 2370}
2371
2372#define ERROR_START_OFFSET (1 * sizeof(u32))
2373#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2374
2375void iwl_dump_nic_error_log(struct iwl_priv *priv)
2376{
2377 u32 data2, line;
2378 u32 desc, time, count, base, data1;
2379 u32 blink1, blink2, ilink1, ilink2;
461ef382 2380 u32 pc, hcmd;
b7a79404 2381
b2e640d4 2382 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2383 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2384 if (!base)
2385 base = priv->_agn.init_errlog_ptr;
2386 } else {
b7a79404 2387 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2388 if (!base)
2389 base = priv->_agn.inst_errlog_ptr;
2390 }
b7a79404
RC		 2391
2392 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2393 IWL_ERR(priv,
2394 "Not valid error log pointer 0x%08X for %s uCode\n",
2395 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2396 return;
2397 }
2398
2399 count = iwl_read_targ_mem(priv, base);
2400
2401 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2402 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2403 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2404 priv->status, count);
2405 }
2406
2407 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 2408 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2409 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2410 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2411 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2412 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2413 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2414 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2415 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2416 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2417 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2418
be1a71a1
JB		 2419 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2420 blink1, blink2, ilink1, ilink2);
2421
87563715 2422 IWL_ERR(priv, "Desc Time "
b7a79404 2423 "data1 data2 line\n");
87563715 2424 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2425 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2426 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2427 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2428 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2429}
2430
2431#define EVENT_START_OFFSET (4 * sizeof(u32))
2432
2433/**
2434 * iwl_print_event_log - Dump error event log to syslog
2435 *
2436 */
b03d7d0f
WYG		 2437static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2438 u32 num_events, u32 mode,
2439 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2440{
2441 u32 i;
2442 u32 base; /* SRAM byte address of event log header */
2443 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2444 u32 ptr; /* SRAM byte address of log data */
2445 u32 ev, time, data; /* event log data */
e5854471 2446 unsigned long reg_flags;
b7a79404
RC		 2447
2448 if (num_events == 0)
b03d7d0f 2449 return pos;
b2e640d4
JB		 2450
2451 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2452 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2453 if (!base)
2454 base = priv->_agn.init_evtlog_ptr;
2455 } else {
b7a79404 2456 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2457 if (!base)
2458 base = priv->_agn.inst_evtlog_ptr;
2459 }
b7a79404
RC		 2460
2461 if (mode == 0)
2462 event_size = 2 * sizeof(u32);
2463 else
2464 event_size = 3 * sizeof(u32);
2465
2466 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2467
e5854471
BC		 2468 /* Make sure device is powered up for SRAM reads */
2469 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2470 iwl_grab_nic_access(priv);
2471
2472 /* Set starting address; reads will auto-increment */
2473 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2474 rmb();
2475
b7a79404
RC		 2476 /* "time" is actually "data" for mode 0 (no timestamp).
2477 * place event id # at far right for easier visual parsing. */
2478 for (i = 0; i < num_events; i++) {
e5854471
BC		 2479 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2480 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2481 if (mode == 0) {
2482 /* data, ev */
b03d7d0f
WYG		 2483 if (bufsz) {
2484 pos += scnprintf(*buf + pos, bufsz - pos,
2485 "EVT_LOG:0x%08x:%04u\n",
2486 time, ev);
2487 } else {
2488 trace_iwlwifi_dev_ucode_event(priv, 0,
2489 time, ev);
2490 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2491 time, ev);
2492 }
b7a79404 2493 } else {
e5854471 2494 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2495 if (bufsz) {
2496 pos += scnprintf(*buf + pos, bufsz - pos,
2497 "EVT_LOGT:%010u:0x%08x:%04u\n",
2498 time, data, ev);
2499 } else {
2500 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2501 time, data, ev);
b03d7d0f
WYG		 2502 trace_iwlwifi_dev_ucode_event(priv, time,
2503 data, ev);
2504 }
b7a79404
RC		 2505 }
2506 }
e5854471
BC		 2507
2508 /* Allow device to power down */
2509 iwl_release_nic_access(priv);
2510 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2511 return pos;
b7a79404
RC		 2512}
2513
c341ddb2
WYG		 2514/**
2515 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2516 */
b03d7d0f
WYG		 2517static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2518 u32 num_wraps, u32 next_entry,
2519 u32 size, u32 mode,
2520 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2521{
2522 /*
2523 * display the newest DEFAULT_LOG_ENTRIES entries
2524 * i.e the entries just before the next ont that uCode would fill.
2525 */
2526 if (num_wraps) {
2527 if (next_entry < size) {
b03d7d0f
WYG		 2528 pos = iwl_print_event_log(priv,
2529 capacity - (size - next_entry),
2530 size - next_entry, mode,
2531 pos, buf, bufsz);
2532 pos = iwl_print_event_log(priv, 0,
2533 next_entry, mode,
2534 pos, buf, bufsz);
c341ddb2 2535 } else
b03d7d0f
WYG		 2536 pos = iwl_print_event_log(priv, next_entry - size,
2537 size, mode, pos, buf, bufsz);
c341ddb2 2538 } else {
b03d7d0f
WYG		 2539 if (next_entry < size) {
2540 pos = iwl_print_event_log(priv, 0, next_entry,
2541 mode, pos, buf, bufsz);
2542 } else {
2543 pos = iwl_print_event_log(priv, next_entry - size,
2544 size, mode, pos, buf, bufsz);
2545 }
c341ddb2 2546 }
b03d7d0f 2547 return pos;
c341ddb2
WYG		 2548}
2549
c341ddb2
WYG		 2550#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2551
b03d7d0f
WYG		 2552int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2553 char **buf, bool display)
b7a79404
RC		 2554{
2555 u32 base; /* SRAM byte address of event log header */
2556 u32 capacity; /* event log capacity in # entries */
2557 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2558 u32 num_wraps; /* # times uCode wrapped to top of log */
2559 u32 next_entry; /* index of next entry to be written by uCode */
2560 u32 size; /* # entries that we'll print */
b2e640d4 2561 u32 logsize;
b03d7d0f
WYG		 2562 int pos = 0;
2563 size_t bufsz = 0;
b7a79404 2564
b2e640d4 2565 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2566 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2567 logsize = priv->_agn.init_evtlog_size;
2568 if (!base)
2569 base = priv->_agn.init_evtlog_ptr;
2570 } else {
b7a79404 2571 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2572 logsize = priv->_agn.inst_evtlog_size;
2573 if (!base)
2574 base = priv->_agn.inst_evtlog_ptr;
2575 }
b7a79404
RC		 2576
2577 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2578 IWL_ERR(priv,
2579 "Invalid event log pointer 0x%08X for %s uCode\n",
2580 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2581 return -EINVAL;
b7a79404
RC		 2582 }
2583
2584 /* event log header */
2585 capacity = iwl_read_targ_mem(priv, base);
2586 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2587 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2588 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2589
b2e640d4 2590 if (capacity > logsize) {
84c40692 2591 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2592 capacity, logsize);
2593 capacity = logsize;
84c40692
BC		 2594 }
2595
b2e640d4 2596 if (next_entry > logsize) {
84c40692 2597 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2598 next_entry, logsize);
2599 next_entry = logsize;
84c40692
BC		 2600 }
2601
b7a79404
RC		 2602 size = num_wraps ? capacity : next_entry;
2603
2604 /* bail out if nothing in log */
2605 if (size == 0) {
2606 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2607 return pos;
b7a79404
RC		 2608 }
2609
f37837c9
WYG		 2610 /* enable/disable bt channel announcement */
2611 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2612
c341ddb2 2613#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2614 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2615 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2616 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2617#else
2618 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2619 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2620#endif
2621 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2622 size);
b7a79404 2623
c341ddb2 2624#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2625 if (display) {
2626 if (full_log)
2627 bufsz = capacity * 48;
2628 else
2629 bufsz = size * 48;
2630 *buf = kmalloc(bufsz, GFP_KERNEL);
2631 if (!*buf)
937c397e 2632 return -ENOMEM;
b03d7d0f 2633 }
c341ddb2
WYG		 2634 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2635 /*
2636 * if uCode has wrapped back to top of log,
2637 * start at the oldest entry,
2638 * i.e the next one that uCode would fill.
2639 */
2640 if (num_wraps)
b03d7d0f
WYG		 2641 pos = iwl_print_event_log(priv, next_entry,
2642 capacity - next_entry, mode,
2643 pos, buf, bufsz);
c341ddb2 2644 /* (then/else) start at top of log */
b03d7d0f
WYG		 2645 pos = iwl_print_event_log(priv, 0,
2646 next_entry, mode, pos, buf, bufsz);
c341ddb2 2647 } else
b03d7d0f
WYG		 2648 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2649 next_entry, size, mode,
2650 pos, buf, bufsz);
c341ddb2 2651#else
b03d7d0f
WYG		 2652 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2653 next_entry, size, mode,
2654 pos, buf, bufsz);
b7a79404 2655#endif
b03d7d0f 2656 return pos;
c341ddb2 2657}
b7a79404 2658
0975cc8f
WYG		 2659static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2660{
2661 struct iwl_ct_kill_config cmd;
2662 struct iwl_ct_kill_throttling_config adv_cmd;
2663 unsigned long flags;
2664 int ret = 0;
2665
2666 spin_lock_irqsave(&priv->lock, flags);
2667 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2668 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2669 spin_unlock_irqrestore(&priv->lock, flags);
2670 priv->thermal_throttle.ct_kill_toggle = false;
2671
2672 if (priv->cfg->support_ct_kill_exit) {
2673 adv_cmd.critical_temperature_enter =
2674 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2675 adv_cmd.critical_temperature_exit =
2676 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2677
2678 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2679 sizeof(adv_cmd), &adv_cmd);
2680 if (ret)
2681 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2682 else
2683 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2684 "succeeded, "
2685 "critical temperature enter is %d,"
2686 "exit is %d\n",
2687 priv->hw_params.ct_kill_threshold,
2688 priv->hw_params.ct_kill_exit_threshold);
2689 } else {
2690 cmd.critical_temperature_R =
2691 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2692
2693 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2694 sizeof(cmd), &cmd);
2695 if (ret)
2696 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2697 else
2698 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2699 "succeeded, "
2700 "critical temperature is %d\n",
2701 priv->hw_params.ct_kill_threshold);
2702 }
2703}
2704
b481de9c 2705/**
4a4a9e81 2706 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2707 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2708 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2709 */
4a4a9e81 2710static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2711{
57aab75a 2712 int ret = 0;
b481de9c 2713
e1623446 2714 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2715
2716 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2717 /* We had an error bringing up the hardware, so take it
2718 * all the way back down so we can try again */
e1623446 2719 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2720 goto restart;
2721 }
2722
2723 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2724 * This is a paranoid check, because we would not have gotten the
2725 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2726 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2727 /* Runtime instruction load was bad;
2728 * take it all the way back down so we can try again */
e1623446 2729 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2730 goto restart;
2731 }
2732
57aab75a
TW		 2733 ret = priv->cfg->ops->lib->alive_notify(priv);
2734 if (ret) {
39aadf8c
WT		 2735 IWL_WARN(priv,
2736 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2737 goto restart;
2738 }
2739
5b9f8cd3 2740 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2741 set_bit(STATUS_ALIVE, &priv->status);
2742
b74e31a9
WYG		 2743 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2744 /* Enable timer to monitor the driver queues */
2745 mod_timer(&priv->monitor_recover,
2746 jiffies +
2747 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2748 }
2749
fee1247a 2750 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2751 return;
2752
36d6825b 2753 ieee80211_wake_queues(priv->hw);
b481de9c 2754
470ab2dd 2755 priv->active_rate = IWL_RATES_MASK;
b481de9c 2756
2f748dec
WYG		 2757 /* Configure Tx antenna selection based on H/W config */
2758 if (priv->cfg->ops->hcmd->set_tx_ant)
2759 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2760
3109ece1 2761 if (iwl_is_associated(priv)) {
c1adf9fb
GG		 2762 struct iwl_rxon_cmd *active_rxon =
2763 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA		 2764 /* apply any changes in staging */
2765 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2766 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2767 } else {
2768 /* Initialize our rx_config data */
1dda6d28 2769 iwl_connection_init_rx_config(priv, NULL);
45823531
AK		 2770
2771 if (priv->cfg->ops->hcmd->set_rxon_chain)
2772 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY		 2773 }
2774
aeb4a2ee
WYG		 2775 if (!priv->cfg->advanced_bt_coexist) {
2776 /* Configure Bluetooth device coexistence support */
2777 priv->cfg->ops->hcmd->send_bt_config(priv);
2778 }
b481de9c 2779
4a4a9e81
TW		 2780 iwl_reset_run_time_calib(priv);
2781
b481de9c 2782 /* Configure the adapter for unassociated operation */
e0158e61 2783 iwlcore_commit_rxon(priv);
b481de9c
ZY		 2784
2785 /* At this point, the NIC is initialized and operational */
47f4a587 2786 iwl_rf_kill_ct_config(priv);
5a66926a 2787
e932a609 2788 iwl_leds_init(priv);
fe00b5a5 2789
e1623446 2790 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2791 set_bit(STATUS_READY, &priv->status);
5a66926a 2792 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2793
e312c24c 2794 iwl_power_update_mode(priv, true);
7e246191
RC		 2795 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2796
c46fbefa 2797
b481de9c
ZY		 2798 return;
2799
2800 restart:
2801 queue_work(priv->workqueue, &priv->restart);
2802}
2803
4e39317d 2804static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2805
5b9f8cd3 2806static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2807{
2808 unsigned long flags;
2809 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2810
e1623446 2811 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2812
b481de9c
ZY		 2813 if (!exit_pending)
2814 set_bit(STATUS_EXIT_PENDING, &priv->status);
2815
b62177a0
SG		 2816 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2817 * to prevent rearm timer */
2818 if (priv->cfg->ops->lib->recover_from_tx_stall)
2819 del_timer_sync(&priv->monitor_recover);
2820
2c810ccd
JB		 2821 iwl_clear_ucode_stations(priv);
2822 iwl_dealloc_bcast_station(priv);
db125c78 2823 iwl_clear_driver_stations(priv);
b481de9c 2824
a1174138 2825 /* reset BT coex data */
da5dbb97 2826 priv->bt_status = 0;
a4b96cc4 2827 priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
a1174138 2828 priv->bt_sco_active = false;
bee008b7
WYG		 2829 priv->bt_full_concurrent = false;
2830 priv->bt_ci_compliance = 0;
a1174138 2831
b481de9c
ZY		 2832 /* Unblock any waiting calls */
2833 wake_up_interruptible_all(&priv->wait_command_queue);
2834
b481de9c
ZY		 2835 /* Wipe out the EXIT_PENDING status bit if we are not actually
2836 * exiting the module */
2837 if (!exit_pending)
2838 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2839
2840 /* stop and reset the on-board processor */
3395f6e9 2841 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2842
2843 /* tell the device to stop sending interrupts */
0359facc 2844 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2845 iwl_disable_interrupts(priv);
0359facc
MA		 2846 spin_unlock_irqrestore(&priv->lock, flags);
2847 iwl_synchronize_irq(priv);
b481de9c
ZY		 2848
2849 if (priv->mac80211_registered)
2850 ieee80211_stop_queues(priv->hw);
2851
5b9f8cd3 2852 /* If we have not previously called iwl_init() then
a60e77e5 2853 * clear all bits but the RF Kill bit and return */
fee1247a 2854 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2855 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2856 STATUS_RF_KILL_HW |
9788864e
RC		 2857 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2858 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2859 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2860 STATUS_EXIT_PENDING;
b481de9c
ZY		 2861 goto exit;
2862 }
2863
6da3a13e 2864 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2865 * bit and continue taking the NIC down. */
b481de9c
ZY		 2866 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2867 STATUS_RF_KILL_HW |
9788864e
RC		 2868 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2869 STATUS_GEO_CONFIGURED |
b481de9c 2870 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2871 STATUS_FW_ERROR |
2872 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2873 STATUS_EXIT_PENDING;
b481de9c 2874
ef850d7c
MA		 2875 /* device going down, Stop using ICT table */
2876 iwl_disable_ict(priv);
b481de9c 2877
74bcdb33 2878 iwlagn_txq_ctx_stop(priv);
54b81550 2879 iwlagn_rxq_stop(priv);
b481de9c 2880
309e731a
BC		 2881 /* Power-down device's busmaster DMA clocks */
2882 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2883 udelay(5);
2884
309e731a
BC		 2885 /* Make sure (redundant) we've released our request to stay awake */
2886 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2887
4d2ccdb9
BC		 2888 /* Stop the device, and put it in low power state */
2889 priv->cfg->ops->lib->apm_ops.stop(priv);
2890
b481de9c 2891 exit:
885ba202 2892 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2893
2894 if (priv->ibss_beacon)
2895 dev_kfree_skb(priv->ibss_beacon);
2896 priv->ibss_beacon = NULL;
2897
2898 /* clear out any free frames */
fcab423d 2899 iwl_clear_free_frames(priv);
b481de9c
ZY		 2900}
2901
5b9f8cd3 2902static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2903{
2904 mutex_lock(&priv->mutex);
5b9f8cd3 2905 __iwl_down(priv);
b481de9c 2906 mutex_unlock(&priv->mutex);
b24d22b1 2907
4e39317d 2908 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2909}
2910
086ed117
MA		 2911#define HW_READY_TIMEOUT (50)
2912
2913static int iwl_set_hw_ready(struct iwl_priv *priv)
2914{
2915 int ret = 0;
2916
2917 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2918 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2919
2920 /* See if we got it */
2921 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2922 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2923 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2924 HW_READY_TIMEOUT);
2925 if (ret != -ETIMEDOUT)
2926 priv->hw_ready = true;
2927 else
2928 priv->hw_ready = false;
2929
2930 IWL_DEBUG_INFO(priv, "hardware %s\n",
2931 (priv->hw_ready == 1) ? "ready" : "not ready");
2932 return ret;
2933}
2934
2935static int iwl_prepare_card_hw(struct iwl_priv *priv)
2936{
2937 int ret = 0;
2938
91dd6c27 2939 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2940
3354a0f6
MA		 2941 ret = iwl_set_hw_ready(priv);
2942 if (priv->hw_ready)
2943 return ret;
2944
2945 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2946 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2947 CSR_HW_IF_CONFIG_REG_PREPARE);
2948
2949 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2950 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2951 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2952
3354a0f6 2953 /* HW should be ready by now, check again. */
086ed117
MA		 2954 if (ret != -ETIMEDOUT)
2955 iwl_set_hw_ready(priv);
2956
2957 return ret;
2958}
2959
b481de9c
ZY		 2960#define MAX_HW_RESTARTS 5
2961
5b9f8cd3 2962static int __iwl_up(struct iwl_priv *priv)
b481de9c 2963{
57aab75a
TW		 2964 int i;
2965 int ret;
b481de9c
ZY		 2966
2967 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2968 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2969 return -EIO;
2970 }
2971
e903fbd4 2972 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2973 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2974 return -EIO;
2975 }
2976
2c810ccd
JB		 2977 ret = iwl_alloc_bcast_station(priv, true);
2978 if (ret)
2979 return ret;
2980
086ed117
MA		 2981 iwl_prepare_card_hw(priv);
2982
2983 if (!priv->hw_ready) {
2984 IWL_WARN(priv, "Exit HW not ready\n");
2985 return -EIO;
2986 }
2987
e655b9f0 2988 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2989 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2990 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2991 else
e655b9f0 2992 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2993
c1842d61 2994 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 2995 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2996
5b9f8cd3 2997 iwl_enable_interrupts(priv);
a60e77e5 2998 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2999 return 0;
b481de9c
ZY		 3000 }
3001
3395f6e9 3002 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 3003
74bcdb33 3004 ret = iwlagn_hw_nic_init(priv);
57aab75a 3005 if (ret) {
15b1687c 3006 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 3007 return ret;
b481de9c
ZY		 3008 }
3009
3010 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3011 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3012 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 3013 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3014
3015 /* clear (again), then enable host interrupts */
3395f6e9 3016 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 3017 iwl_enable_interrupts(priv);
b481de9c
ZY		 3018
3019 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3020 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3021 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3022
3023 /* Copy original ucode data image from disk into backup cache.
3024 * This will be used to initialize the on-board processor's
3025 * data SRAM for a clean start when the runtime program first loads. */
3026 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 3027 priv->ucode_data.len);
b481de9c 3028
b481de9c
ZY		 3029 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3030
b481de9c
ZY		 3031 /* load bootstrap state machine,
3032 * load bootstrap program into processor's memory,
3033 * prepare to load the "initialize" uCode */
57aab75a 3034 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 3035
57aab75a 3036 if (ret) {
15b1687c
WT		 3037 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3038 ret);
b481de9c
ZY		 3039 continue;
3040 }
3041
3042 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 3043 iwl_nic_start(priv);
b481de9c 3044
e1623446 3045 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 3046
3047 return 0;
3048 }
3049
3050 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3051 __iwl_down(priv);
64e72c3e 3052 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3053
3054 /* tried to restart and config the device for as long as our
3055 * patience could withstand */
15b1687c 3056 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3057 return -EIO;
3058}
3059
3060
3061/*****************************************************************************
3062 *
3063 * Workqueue callbacks
3064 *
3065 *****************************************************************************/
3066
4a4a9e81 3067static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3068{
c79dd5b5
TW		 3069 struct iwl_priv *priv =
3070 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3071
3072 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3073 return;
3074
3075 mutex_lock(&priv->mutex);
f3ccc08c 3076 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3077 mutex_unlock(&priv->mutex);
3078}
3079
4a4a9e81 3080static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3081{
c79dd5b5
TW		 3082 struct iwl_priv *priv =
3083 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3084
3085 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3086 return;
3087
258c44a0
MA		 3088 /* enable dram interrupt */
3089 iwl_reset_ict(priv);
3090
b481de9c 3091 mutex_lock(&priv->mutex);
4a4a9e81 3092 iwl_alive_start(priv);
b481de9c
ZY		 3093 mutex_unlock(&priv->mutex);
3094}
3095
16e727e8
EG		 3096static void iwl_bg_run_time_calib_work(struct work_struct *work)
3097{
3098 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3099 run_time_calib_work);
3100
3101 mutex_lock(&priv->mutex);
3102
3103 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3104 test_bit(STATUS_SCANNING, &priv->status)) {
3105 mutex_unlock(&priv->mutex);
3106 return;
3107 }
3108
3109 if (priv->start_calib) {
7980fba5
WYG		 3110 if (priv->cfg->bt_statistics) {
3111 iwl_chain_noise_calibration(priv,
3112 (void *)&priv->_agn.statistics_bt);
3113 iwl_sensitivity_calibration(priv,
3114 (void *)&priv->_agn.statistics_bt);
3115 } else {
3116 iwl_chain_noise_calibration(priv,
3117 (void *)&priv->_agn.statistics);
3118 iwl_sensitivity_calibration(priv,
3119 (void *)&priv->_agn.statistics);
3120 }
16e727e8
EG		 3121 }
3122
3123 mutex_unlock(&priv->mutex);
16e727e8
EG		 3124}
3125
5b9f8cd3 3126static void iwl_bg_restart(struct work_struct *data)
b481de9c 3127{
c79dd5b5 3128 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3129
3130 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3131 return;
3132
19cc1087 3133 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
bee008b7
WYG		 3134 bool bt_sco, bt_full_concurrent;
3135 u8 bt_ci_compliance;
511b082d 3136 u8 bt_load;
da5dbb97 3137 u8 bt_status;
511b082d 3138
19cc1087
JB		 3139 mutex_lock(&priv->mutex);
3140 priv->vif = NULL;
3141 priv->is_open = 0;
511b082d
JB		 3142
3143 /*
3144 * __iwl_down() will clear the BT status variables,
3145 * which is correct, but when we restart we really
3146 * want to keep them so restore them afterwards.
3147 *
3148 * The restart process will later pick them up and
3149 * re-configure the hw when we reconfigure the BT
3150 * command.
3151 */
3152 bt_sco = priv->bt_sco_active;
bee008b7
WYG		 3153 bt_full_concurrent = priv->bt_full_concurrent;
3154 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3155 bt_load = priv->bt_traffic_load;
da5dbb97 3156 bt_status = priv->bt_status;
511b082d 3157
a1174138 3158 __iwl_down(priv);
511b082d
JB		 3159
3160 priv->bt_sco_active = bt_sco;
bee008b7
WYG		 3161 priv->bt_full_concurrent = bt_full_concurrent;
3162 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3163 priv->bt_traffic_load = bt_load;
da5dbb97 3164 priv->bt_status = bt_status;
511b082d 3165
19cc1087 3166 mutex_unlock(&priv->mutex);
a1174138 3167 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3168 ieee80211_restart_hw(priv->hw);
3169 } else {
3170 iwl_down(priv);
80676518
JB		 3171
3172 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3173 return;
3174
3175 mutex_lock(&priv->mutex);
3176 __iwl_up(priv);
3177 mutex_unlock(&priv->mutex);
19cc1087 3178 }
b481de9c
ZY		 3179}
3180
5b9f8cd3 3181static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3182{
c79dd5b5
TW		 3183 struct iwl_priv *priv =
3184 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3185
3186 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3187 return;
3188
3189 mutex_lock(&priv->mutex);
54b81550 3190 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3191 mutex_unlock(&priv->mutex);
3192}
3193
7878a5a4
MA		 3194#define IWL_DELAY_NEXT_SCAN (HZ*2)
3195
1dda6d28 3196void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3197{
b481de9c 3198 struct ieee80211_conf *conf = NULL;
857485c0 3199 int ret = 0;
b481de9c 3200
1dda6d28
JB		 3201 if (!vif || !priv->is_open)
3202 return;
3203
3204 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3205 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3206 return;
3207 }
3208
b481de9c
ZY		 3209 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3210 return;
3211
2a421b91 3212 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3213
b481de9c
ZY		 3214 conf = ieee80211_get_hw_conf(priv->hw);
3215
3216 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3217 iwlcore_commit_rxon(priv);
b481de9c 3218
948f5a2f 3219 ret = iwl_send_rxon_timing(priv, vif);
857485c0 3220 if (ret)
39aadf8c 3221 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3222 "Attempting to continue.\n");
3223
3224 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3225
42eb7c64 3226 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3227
45823531
AK		 3228 if (priv->cfg->ops->hcmd->set_rxon_chain)
3229 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3230
1dda6d28 3231 priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3232
e1623446 3233 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3234 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3235
c213d745 3236 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3237 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3238 else
3239 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3240
3241 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3242 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3243 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
3244 else
3245 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3246 }
3247
e0158e61 3248 iwlcore_commit_rxon(priv);
b481de9c 3249
fe6b23dd 3250 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
1dda6d28 3251 vif->bss_conf.aid, priv->active_rxon.bssid_addr);
fe6b23dd 3252
1dda6d28 3253 switch (vif->type) {
05c914fe 3254 case NL80211_IFTYPE_STATION:
b481de9c 3255 break;
05c914fe 3256 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3257 iwl_send_beacon_cmd(priv);
b481de9c 3258 break;
b481de9c 3259 default:
15b1687c 3260 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3261 __func__, vif->type);
b481de9c
ZY		 3262 break;
3263 }
3264
04816448
GE		 3265 /* the chain noise calibration will enabled PM upon completion
3266 * If chain noise has already been run, then we need to enable
3267 * power management here */
3268 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3269 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3270
3271 /* Enable Rx differential gain and sensitivity calibrations */
3272 iwl_chain_noise_reset(priv);
3273 priv->start_calib = 1;
3274
508e32e1
RC		 3275}
3276
b481de9c
ZY		 3277/*****************************************************************************
3278 *
3279 * mac80211 entry point functions
3280 *
3281 *****************************************************************************/
3282
154b25ce 3283#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3284
f0b6e2e8
RC		 3285/*
3286 * Not a mac80211 entry point function, but it fits in with all the
3287 * other mac80211 functions grouped here.
3288 */
dd7a2509
JB		 3289static int iwl_mac_setup_register(struct iwl_priv *priv,
3290 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3291{
3292 int ret;
3293 struct ieee80211_hw *hw = priv->hw;
3294 hw->rate_control_algorithm = "iwl-agn-rs";
3295
3296 /* Tell mac80211 our characteristics */
3297 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8
RC		 3298 IEEE80211_HW_AMPDU_AGGREGATION |
3299 IEEE80211_HW_SPECTRUM_MGMT;
3300
3301 if (!priv->cfg->broken_powersave)
3302 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3303 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3304
ba37a3d0
JB		 3305 if (priv->cfg->sku & IWL_SKU_N)
3306 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3307 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3308
8d9698b3 3309 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3310 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3311
f0b6e2e8
RC		 3312 hw->wiphy->interface_modes =
3313 BIT(NL80211_IFTYPE_STATION) |
3314 BIT(NL80211_IFTYPE_ADHOC);
3315
f6c8f152 3316 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3317 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3318
3319 /*
3320 * For now, disable PS by default because it affects
3321 * RX performance significantly.
3322 */
5be83de5 3323 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3324
1382c71c 3325 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3326 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3327 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3328
3329 /* Default value; 4 EDCA QOS priorities */
3330 hw->queues = 4;
3331
3332 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3333
3334 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3335 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3336 &priv->bands[IEEE80211_BAND_2GHZ];
3337 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3338 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3339 &priv->bands[IEEE80211_BAND_5GHZ];
3340
3341 ret = ieee80211_register_hw(priv->hw);
3342 if (ret) {
3343 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3344 return ret;
3345 }
3346 priv->mac80211_registered = 1;
3347
3348 return 0;
3349}
3350
3351
5b9f8cd3 3352static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3353{
c79dd5b5 3354 struct iwl_priv *priv = hw->priv;
5a66926a 3355 int ret;
b481de9c 3356
e1623446 3357 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3358
3359 /* we should be verifying the device is ready to be opened */
3360 mutex_lock(&priv->mutex);
5b9f8cd3 3361 ret = __iwl_up(priv);
b481de9c 3362 mutex_unlock(&priv->mutex);
5a66926a 3363
e655b9f0 3364 if (ret)
6cd0b1cb 3365 return ret;
e655b9f0 3366
c1842d61
TW		 3367 if (iwl_is_rfkill(priv))
3368 goto out;
3369
e1623446 3370 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3371
fe9b6b72 3372 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3373 * mac80211 will not be run successfully. */
154b25ce
EG		 3374 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3375 test_bit(STATUS_READY, &priv->status),
3376 UCODE_READY_TIMEOUT);
3377 if (!ret) {
3378 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3379 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3380 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3381 return -ETIMEDOUT;
5a66926a 3382 }
fe9b6b72 3383 }
0a078ffa 3384
e932a609
JB		 3385 iwl_led_start(priv);
3386
c1842d61 3387out:
0a078ffa 3388 priv->is_open = 1;
e1623446 3389 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3390 return 0;
3391}
3392
5b9f8cd3 3393static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3394{
c79dd5b5 3395 struct iwl_priv *priv = hw->priv;
b481de9c 3396
e1623446 3397 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3398
19cc1087 3399 if (!priv->is_open)
e655b9f0 3400 return;
e655b9f0 3401
b481de9c 3402 priv->is_open = 0;
5a66926a 3403
5bddf549 3404 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY		 3405 /* stop mac, cancel any scan request and clear
3406 * RXON_FILTER_ASSOC_MSK BIT
3407 */
5a66926a 3408 mutex_lock(&priv->mutex);
2a421b91 3409 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3410 mutex_unlock(&priv->mutex);
fde3571f
MA		 3411 }
3412
5b9f8cd3 3413 iwl_down(priv);
5a66926a
ZY		 3414
3415 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3416
3417 /* enable interrupts again in order to receive rfkill changes */
3418 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3419 iwl_enable_interrupts(priv);
948c171c 3420
e1623446 3421 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3422}
3423
5b9f8cd3 3424static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3425{
c79dd5b5 3426 struct iwl_priv *priv = hw->priv;
b481de9c 3427
e1623446 3428 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3429
e1623446 3430 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3431 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3432
74bcdb33 3433 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3434 dev_kfree_skb_any(skb);
3435
e1623446 3436 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3437 return NETDEV_TX_OK;
b481de9c
ZY		 3438}
3439
1dda6d28 3440void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3441{
857485c0 3442 int ret = 0;
b481de9c 3443
d986bcd1 3444 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3445 return;
3446
3447 /* The following should be done only at AP bring up */
3195c1f3 3448 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 3449
3450 /* RXON - unassoc (to set timing command) */
3451 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3452 iwlcore_commit_rxon(priv);
b481de9c
ZY		 3453
3454 /* RXON Timing */
948f5a2f 3455 ret = iwl_send_rxon_timing(priv, vif);
857485c0 3456 if (ret)
39aadf8c 3457 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3458 "Attempting to continue.\n");
3459
f513dfff
DH		 3460 /* AP has all antennas */
3461 priv->chain_noise_data.active_chains =
3462 priv->hw_params.valid_rx_ant;
3463 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK		 3464 if (priv->cfg->ops->hcmd->set_rxon_chain)
3465 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c 3466
1dda6d28
JB		 3467 priv->staging_rxon.assoc_id = 0;
3468
c213d745 3469 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3470 priv->staging_rxon.flags |=
3471 RXON_FLG_SHORT_PREAMBLE_MSK;
3472 else
3473 priv->staging_rxon.flags &=
3474 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3475
3476 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3477 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3478 priv->staging_rxon.flags |=
3479 RXON_FLG_SHORT_SLOT_MSK;
3480 else
3481 priv->staging_rxon.flags &=
3482 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3483 }
3484 /* restore RXON assoc */
3485 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3486 iwlcore_commit_rxon(priv);
e1493deb 3487 }
5b9f8cd3 3488 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3489
3490 /* FIXME - we need to add code here to detect a totally new
3491 * configuration, reset the AP, unassoc, rxon timing, assoc,
3492 * clear sta table, add BCAST sta... */
3493}
3494
5b9f8cd3 3495static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3496 struct ieee80211_vif *vif,
3497 struct ieee80211_key_conf *keyconf,
3498 struct ieee80211_sta *sta,
3499 u32 iv32, u16 *phase1key)
ab885f8c 3500{
ab885f8c 3501
9f58671e 3502 struct iwl_priv *priv = hw->priv;
e1623446 3503 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3504
bdbb612f 3505 iwl_update_tkip_key(priv, keyconf, sta,
b3fbdcf4 3506 iv32, phase1key);
ab885f8c 3507
e1623446 3508 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3509}
3510
5b9f8cd3 3511static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3512 struct ieee80211_vif *vif,
3513 struct ieee80211_sta *sta,
b481de9c
ZY		 3514 struct ieee80211_key_conf *key)
3515{
c79dd5b5 3516 struct iwl_priv *priv = hw->priv;
42986796
WT		 3517 int ret;
3518 u8 sta_id;
3519 bool is_default_wep_key = false;
b481de9c 3520
e1623446 3521 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3522
90e8e424 3523 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3524 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3525 return -EOPNOTSUPP;
3526 }
b481de9c 3527
0af8bcae
JB		 3528 sta_id = iwl_sta_id_or_broadcast(priv, sta);
3529 if (sta_id == IWL_INVALID_STATION)
3530 return -EINVAL;
b481de9c 3531
6974e363 3532 mutex_lock(&priv->mutex);
2a421b91 3533 iwl_scan_cancel_timeout(priv, 100);
6974e363 3534
a90178fa
JB		 3535 /*
3536 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3537 * so far, we are in legacy wep mode (group key only), otherwise we are
3538 * in 1X mode.
a90178fa
JB		 3539 * In legacy wep mode, we use another host command to the uCode.
3540 */
97359d12
JB		 3541 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3542 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3543 !sta) {
6974e363
EG		 3544 if (cmd == SET_KEY)
3545 is_default_wep_key = !priv->key_mapping_key;
3546 else
ccc038ab
EG		 3547 is_default_wep_key =
3548 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3549 }
052c4b9f 3550
b481de9c 3551 switch (cmd) {
deb09c43 3552 case SET_KEY:
6974e363
EG		 3553 if (is_default_wep_key)
3554 ret = iwl_set_default_wep_key(priv, key);
deb09c43 3555 else
7480513f 3556 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 3557
e1623446 3558 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3559 break;
3560 case DISABLE_KEY:
6974e363
EG		 3561 if (is_default_wep_key)
3562 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 3563 else
3ec47732 3564 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 3565
e1623446 3566 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3567 break;
3568 default:
deb09c43 3569 ret = -EINVAL;
b481de9c
ZY		 3570 }
3571
72e15d71 3572 mutex_unlock(&priv->mutex);
e1623446 3573 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3574
deb09c43 3575 return ret;
b481de9c
ZY		 3576}
3577
5b9f8cd3 3578static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3579 struct ieee80211_vif *vif,
832f47e3
JB		 3580 enum ieee80211_ampdu_mlme_action action,
3581 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3582{
3583 struct iwl_priv *priv = hw->priv;
4620fefa 3584 int ret = -EINVAL;
d783b061 3585
e1623446 3586 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3587 sta->addr, tid);
d783b061
TW		 3588
3589 if (!(priv->cfg->sku & IWL_SKU_N))
3590 return -EACCES;
3591
4620fefa
JB		 3592 mutex_lock(&priv->mutex);
3593
d783b061
TW		 3594 switch (action) {
3595 case IEEE80211_AMPDU_RX_START:
e1623446 3596 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3597 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3598 break;
d783b061 3599 case IEEE80211_AMPDU_RX_STOP:
e1623446 3600 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3601 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3602 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3603 ret = 0;
3604 break;
d783b061 3605 case IEEE80211_AMPDU_TX_START:
e1623446 3606 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3607 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3608 if (ret == 0) {
3609 priv->_agn.agg_tids_count++;
3610 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3611 priv->_agn.agg_tids_count);
3612 }
4620fefa 3613 break;
d783b061 3614 case IEEE80211_AMPDU_TX_STOP:
e1623446 3615 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3616 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3617 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3618 priv->_agn.agg_tids_count--;
3619 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3620 priv->_agn.agg_tids_count);
3621 }
5c2207c6 3622 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3623 ret = 0;
94597ab2
JB		 3624 if (priv->cfg->use_rts_for_aggregation) {
3625 struct iwl_station_priv *sta_priv =
3626 (void *) sta->drv_priv;
3627 /*
3628 * switch off RTS/CTS if it was previously enabled
3629 */
3630
3631 sta_priv->lq_sta.lq.general_params.flags &=
3632 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3633 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3634 CMD_ASYNC, false);
3635 }
4620fefa 3636 break;
f0527971 3637 case IEEE80211_AMPDU_TX_OPERATIONAL:
94597ab2
JB		 3638 if (priv->cfg->use_rts_for_aggregation) {
3639 struct iwl_station_priv *sta_priv =
3640 (void *) sta->drv_priv;
3641
cfecc6b4
WYG		 3642 /*
3643 * switch to RTS/CTS if it is the prefer protection
3644 * method for HT traffic
3645 */
94597ab2
JB		 3646
3647 sta_priv->lq_sta.lq.general_params.flags |=
3648 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3649 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3650 CMD_ASYNC, false);
cfecc6b4
WYG		 3651 }
3652 ret = 0;
d783b061
TW		 3653 break;
3654 }
4620fefa
JB		 3655 mutex_unlock(&priv->mutex);
3656
3657 return ret;
d783b061 3658}
9f58671e 3659
6ab10ff8
JB		 3660static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3661 struct ieee80211_vif *vif,
3662 enum sta_notify_cmd cmd,
3663 struct ieee80211_sta *sta)
3664{
3665 struct iwl_priv *priv = hw->priv;
3666 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3667 int sta_id;
3668
6ab10ff8 3669 switch (cmd) {
6ab10ff8
JB		 3670 case STA_NOTIFY_SLEEP:
3671 WARN_ON(!sta_priv->client);
3672 sta_priv->asleep = true;
3673 if (atomic_read(&sta_priv->pending_frames) > 0)
3674 ieee80211_sta_block_awake(hw, sta, true);
3675 break;
3676 case STA_NOTIFY_AWAKE:
3677 WARN_ON(!sta_priv->client);
49dcc819
DH		 3678 if (!sta_priv->asleep)
3679 break;
6ab10ff8 3680 sta_priv->asleep = false;
2a87c26b 3681 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3682 if (sta_id != IWL_INVALID_STATION)
3683 iwl_sta_modify_ps_wake(priv, sta_id);
3684 break;
3685 default:
3686 break;
3687 }
3688}
3689
fe6b23dd
RC		 3690static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3691 struct ieee80211_vif *vif,
3692 struct ieee80211_sta *sta)
3693{
3694 struct iwl_priv *priv = hw->priv;
3695 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
eafdfbd3 3696 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3697 int ret;
3698 u8 sta_id;
3699
3700 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3701 sta->addr);
da5ae1cf
RC		 3702 mutex_lock(&priv->mutex);
3703 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3704 sta->addr);
3705 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3706
3707 atomic_set(&sta_priv->pending_frames, 0);
3708 if (vif->type == NL80211_IFTYPE_AP)
3709 sta_priv->client = true;
3710
3711 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3712 &sta_id);
3713 if (ret) {
3714 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3715 sta->addr, ret);
3716 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3717 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3718 return ret;
3719 }
3720
fd1af15d
JB		 3721 sta_priv->common.sta_id = sta_id;
3722
fe6b23dd 3723 /* Initialize rate scaling */
91dd6c27 3724 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3725 sta->addr);
3726 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3727 mutex_unlock(&priv->mutex);
fe6b23dd 3728
fd1af15d 3729 return 0;
fe6b23dd
RC		 3730}
3731
79d07325
WYG		 3732static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3733 struct ieee80211_channel_switch *ch_switch)
3734{
3735 struct iwl_priv *priv = hw->priv;
3736 const struct iwl_channel_info *ch_info;
3737 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3738 struct ieee80211_channel *channel = ch_switch->channel;
79d07325
WYG		 3739 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3740 u16 ch;
3741 unsigned long flags = 0;
3742
3743 IWL_DEBUG_MAC80211(priv, "enter\n");
3744
3745 if (iwl_is_rfkill(priv))
3746 goto out_exit;
3747
3748 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3749 test_bit(STATUS_SCANNING, &priv->status))
3750 goto out_exit;
3751
3752 if (!iwl_is_associated(priv))
3753 goto out_exit;
3754
3755 /* channel switch in progress */
3756 if (priv->switch_rxon.switch_in_progress == true)
3757 goto out_exit;
3758
3759 mutex_lock(&priv->mutex);
3760 if (priv->cfg->ops->lib->set_channel_switch) {
3761
aa2dc6b5 3762 ch = channel->hw_value;
79d07325
WYG		 3763 if (le16_to_cpu(priv->active_rxon.channel) != ch) {
3764 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3765 channel->band,
79d07325
WYG		 3766 ch);
3767 if (!is_channel_valid(ch_info)) {
3768 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3769 goto out;
3770 }
3771 spin_lock_irqsave(&priv->lock, flags);
3772
3773 priv->current_ht_config.smps = conf->smps_mode;
3774
3775 /* Configure HT40 channels */
3776 ht_conf->is_ht = conf_is_ht(conf);
3777 if (ht_conf->is_ht) {
3778 if (conf_is_ht40_minus(conf)) {
3779 ht_conf->extension_chan_offset =
3780 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3781 ht_conf->is_40mhz = true;
3782 } else if (conf_is_ht40_plus(conf)) {
3783 ht_conf->extension_chan_offset =
3784 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3785 ht_conf->is_40mhz = true;
3786 } else {
3787 ht_conf->extension_chan_offset =
3788 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3789 ht_conf->is_40mhz = false;
3790 }
3791 } else
3792 ht_conf->is_40mhz = false;
3793
aa2dc6b5 3794 if (le16_to_cpu(priv->staging_rxon.channel) != ch)
79d07325
WYG		 3795 priv->staging_rxon.flags = 0;
3796
aa2dc6b5 3797 iwl_set_rxon_channel(priv, channel);
79d07325 3798 iwl_set_rxon_ht(priv, ht_conf);
aa2dc6b5 3799 iwl_set_flags_for_band(priv, channel->band,
79d07325
WYG		 3800 priv->vif);
3801 spin_unlock_irqrestore(&priv->lock, flags);
3802
3803 iwl_set_rate(priv);
3804 /*
3805 * at this point, staging_rxon has the
3806 * configuration for channel switch
3807 */
3808 if (priv->cfg->ops->lib->set_channel_switch(priv,
3809 ch_switch))
3810 priv->switch_rxon.switch_in_progress = false;
3811 }
3812 }
3813out:
3814 mutex_unlock(&priv->mutex);
3815out_exit:
3816 if (!priv->switch_rxon.switch_in_progress)
3817 ieee80211_chswitch_done(priv->vif, false);
3818 IWL_DEBUG_MAC80211(priv, "leave\n");
3819}
3820
8b8ab9d5
JB		 3821static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3822 unsigned int changed_flags,
3823 unsigned int *total_flags,
3824 u64 multicast)
3825{
3826 struct iwl_priv *priv = hw->priv;
3827 __le32 filter_or = 0, filter_nand = 0;
3828
3829#define CHK(test, flag) do { \
3830 if (*total_flags & (test)) \
3831 filter_or |= (flag); \
3832 else \
3833 filter_nand |= (flag); \
3834 } while (0)
3835
3836 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3837 changed_flags, *total_flags);
3838
3839 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3840 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3841 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3842
3843#undef CHK
3844
3845 mutex_lock(&priv->mutex);
3846
3847 priv->staging_rxon.filter_flags &= ~filter_nand;
3848 priv->staging_rxon.filter_flags |= filter_or;
3849
3850 iwlcore_commit_rxon(priv);
3851
3852 mutex_unlock(&priv->mutex);
3853
3854 /*
3855 * Receiving all multicast frames is always enabled by the
3856 * default flags setup in iwl_connection_init_rx_config()
3857 * since we currently do not support programming multicast
3858 * filters into the device.
3859 */
3860 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3861 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3862}
3863
716c74b0
WYG		 3864static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3865{
3866 struct iwl_priv *priv = hw->priv;
3867
3868 mutex_lock(&priv->mutex);
3869 IWL_DEBUG_MAC80211(priv, "enter\n");
3870
3871 /* do not support "flush" */
3872 if (!priv->cfg->ops->lib->txfifo_flush)
3873 goto done;
3874
3875 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3876 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3877 goto done;
3878 }
3879 if (iwl_is_rfkill(priv)) {
3880 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3881 goto done;
3882 }
3883
3884 /*
3885 * mac80211 will not push any more frames for transmit
3886 * until the flush is completed
3887 */
3888 if (drop) {
3889 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3890 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3891 IWL_ERR(priv, "flush request fail\n");
3892 goto done;
3893 }
3894 }
3895 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3896 iwlagn_wait_tx_queue_empty(priv);
3897done:
3898 mutex_unlock(&priv->mutex);
3899 IWL_DEBUG_MAC80211(priv, "leave\n");
3900}
3901
b481de9c
ZY		 3902/*****************************************************************************
3903 *
3904 * driver setup and teardown
3905 *
3906 *****************************************************************************/
3907
4e39317d 3908static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3909{
d21050c7 3910 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3911
3912 init_waitqueue_head(&priv->wait_command_queue);
3913
5b9f8cd3
EG		 3914 INIT_WORK(&priv->restart, iwl_bg_restart);
3915 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3916 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3917 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3918 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 3919 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 3920 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 3921 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3922 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3923
2a421b91 3924 iwl_setup_scan_deferred_work(priv);
bb8c093b 3925
4e39317d
EG		 3926 if (priv->cfg->ops->lib->setup_deferred_work)
3927 priv->cfg->ops->lib->setup_deferred_work(priv);
3928
3929 init_timer(&priv->statistics_periodic);
3930 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3931 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3932
a9e1cb6a
WYG		 3933 init_timer(&priv->ucode_trace);
3934 priv->ucode_trace.data = (unsigned long)priv;
3935 priv->ucode_trace.function = iwl_bg_ucode_trace;
3936
b74e31a9
WYG		 3937 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3938 init_timer(&priv->monitor_recover);
3939 priv->monitor_recover.data = (unsigned long)priv;
3940 priv->monitor_recover.function =
3941 priv->cfg->ops->lib->recover_from_tx_stall;
3942 }
3943
ef850d7c
MA		 3944 if (!priv->cfg->use_isr_legacy)
3945 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3946 iwl_irq_tasklet, (unsigned long)priv);
3947 else
3948 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3949 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3950}
3951
4e39317d 3952static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3953{
4e39317d
EG		 3954 if (priv->cfg->ops->lib->cancel_deferred_work)
3955 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3956
3ae6a054 3957 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3958 cancel_delayed_work(&priv->scan_check);
88be0264 3959 cancel_work_sync(&priv->start_internal_scan);
b481de9c 3960 cancel_delayed_work(&priv->alive_start);
815e629b 3961 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 3962 cancel_work_sync(&priv->beacon_update);
bee008b7 3963 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 3964 cancel_work_sync(&priv->bt_runtime_config);
4e39317d 3965 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3966 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 3967}
3968
89f186a8
RC		 3969static void iwl_init_hw_rates(struct iwl_priv *priv,
3970 struct ieee80211_rate *rates)
3971{
3972 int i;
3973
3974 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3975 rates[i].bitrate = iwl_rates[i].ieee * 5;
3976 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3977 rates[i].hw_value_short = i;
3978 rates[i].flags = 0;
3979 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3980 /*
3981 * If CCK != 1M then set short preamble rate flag.
3982 */
3983 rates[i].flags |=
3984 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3985 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3986 }
3987 }
3988}
3989
3990static int iwl_init_drv(struct iwl_priv *priv)
3991{
3992 int ret;
3993
3994 priv->ibss_beacon = NULL;
3995
89f186a8
RC		 3996 spin_lock_init(&priv->sta_lock);
3997 spin_lock_init(&priv->hcmd_lock);
3998
3999 INIT_LIST_HEAD(&priv->free_frames);
4000
4001 mutex_init(&priv->mutex);
d2dfe6df 4002 mutex_init(&priv->sync_cmd_mutex);
89f186a8 4003
89f186a8
RC		 4004 priv->ieee_channels = NULL;
4005 priv->ieee_rates = NULL;
4006 priv->band = IEEE80211_BAND_2GHZ;
4007
4008 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 4009 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 4010 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 4011 priv->_agn.agg_tids_count = 0;
89f186a8 4012
8a472da4
WYG		 4013 /* initialize force reset */
4014 priv->force_reset[IWL_RF_RESET].reset_duration =
4015 IWL_DELAY_NEXT_FORCE_RF_RESET;
4016 priv->force_reset[IWL_FW_RESET].reset_duration =
4017 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 4018
4019 /* Choose which receivers/antennas to use */
4020 if (priv->cfg->ops->hcmd->set_rxon_chain)
4021 priv->cfg->ops->hcmd->set_rxon_chain(priv);
4022
4023 iwl_init_scan_params(priv);
4024
22bf59a0
WYG		 4025 /* init bt coex */
4026 if (priv->cfg->advanced_bt_coexist) {
b6e116e8
WYG		 4027 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4028 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4029 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 4030 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4031 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4032 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4033 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4034 }
4035
89f186a8
RC		 4036 /* Set the tx_power_user_lmt to the lowest power level
4037 * this value will get overwritten by channel max power avg
4038 * from eeprom */
b744cb79 4039 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 4040
4041 ret = iwl_init_channel_map(priv);
4042 if (ret) {
4043 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4044 goto err;
4045 }
4046
4047 ret = iwlcore_init_geos(priv);
4048 if (ret) {
4049 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4050 goto err_free_channel_map;
4051 }
4052 iwl_init_hw_rates(priv, priv->ieee_rates);
4053
4054 return 0;
4055
4056err_free_channel_map:
4057 iwl_free_channel_map(priv);
4058err:
4059 return ret;
4060}
4061
4062static void iwl_uninit_drv(struct iwl_priv *priv)
4063{
4064 iwl_calib_free_results(priv);
4065 iwlcore_free_geos(priv);
4066 iwl_free_channel_map(priv);
811ecc99 4067 kfree(priv->scan_cmd);
89f186a8
RC		 4068}
4069
5b9f8cd3
EG		 4070static struct ieee80211_ops iwl_hw_ops = {
4071 .tx = iwl_mac_tx,
4072 .start = iwl_mac_start,
4073 .stop = iwl_mac_stop,
4074 .add_interface = iwl_mac_add_interface,
4075 .remove_interface = iwl_mac_remove_interface,
4076 .config = iwl_mac_config,
8b8ab9d5 4077 .configure_filter = iwlagn_configure_filter,
5b9f8cd3
EG		 4078 .set_key = iwl_mac_set_key,
4079 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 4080 .conf_tx = iwl_mac_conf_tx,
4081 .reset_tsf = iwl_mac_reset_tsf,
4082 .bss_info_changed = iwl_bss_info_changed,
4083 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 4084 .hw_scan = iwl_mac_hw_scan,
4085 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 4086 .sta_add = iwlagn_mac_sta_add,
4087 .sta_remove = iwl_mac_sta_remove,
79d07325 4088 .channel_switch = iwl_mac_channel_switch,
716c74b0 4089 .flush = iwl_mac_flush,
a85d7cca 4090 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c
ZY		 4091};
4092
3867fe04
WYG		 4093static void iwl_hw_detect(struct iwl_priv *priv)
4094{
4095 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4096 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4097 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 4098 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 4099}
4100
07d4f1ad
WYG		 4101static int iwl_set_hw_params(struct iwl_priv *priv)
4102{
4103 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4104 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4105 if (priv->cfg->mod_params->amsdu_size_8K)
4106 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4107 else
4108 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4109
4110 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4111
4112 if (priv->cfg->mod_params->disable_11n)
4113 priv->cfg->sku &= ~IWL_SKU_N;
4114
4115 /* Device-specific setup */
4116 return priv->cfg->ops->lib->set_hw_params(priv);
4117}
4118
5b9f8cd3 4119static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 4120{
4121 int err = 0;
c79dd5b5 4122 struct iwl_priv *priv;
b481de9c 4123 struct ieee80211_hw *hw;
82b9a121 4124 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 4125 unsigned long flags;
c6fa17ed 4126 u16 pci_cmd, num_mac;
b481de9c 4127
316c30d9
AK		 4128 /************************
4129 * 1. Allocating HW data
4130 ************************/
4131
6440adb5
CB		 4132 /* Disabling hardware scan means that mac80211 will perform scans
4133 * "the hard way", rather than using device's scan. */
1ea87396 4134 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 4135 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK		 4136 dev_printk(KERN_DEBUG, &(pdev->dev),
4137 "Disabling hw_scan\n");
5b9f8cd3 4138 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 4139 }
4140
5b9f8cd3 4141 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 4142 if (!hw) {
b481de9c
ZY		 4143 err = -ENOMEM;
4144 goto out;
4145 }
1d0a082d
AK		 4146 priv = hw->priv;
4147 /* At this point both hw and priv are allocated. */
4148
b481de9c
ZY		 4149 SET_IEEE80211_DEV(hw, &pdev->dev);
4150
e1623446 4151 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4152 priv->cfg = cfg;
b481de9c 4153 priv->pci_dev = pdev;
40cefda9 4154 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4155
bee008b7
WYG		 4156 /* is antenna coupling more than 35dB ? */
4157 priv->bt_ant_couple_ok =
4158 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4159 true : false;
4160
f37837c9
WYG		 4161 /* enable/disable bt channel announcement */
4162 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4163
20594eb0
WYG		 4164 if (iwl_alloc_traffic_mem(priv))
4165 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4166
316c30d9
AK		 4167 /**************************
4168 * 2. Initializing PCI bus
4169 **************************/
1a7123cd
JL		 4170 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4171 PCIE_LINK_STATE_CLKPM);
4172
316c30d9
AK		 4173 if (pci_enable_device(pdev)) {
4174 err = -ENODEV;
4175 goto out_ieee80211_free_hw;
4176 }
4177
4178 pci_set_master(pdev);
4179
093d874c 4180 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4181 if (!err)
093d874c 4182 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4183 if (err) {
093d874c 4184 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4185 if (!err)
093d874c 4186 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4187 /* both attempts failed: */
316c30d9 4188 if (err) {
978785a3 4189 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4190 goto out_pci_disable_device;
cc2a8ea8 4191 }
316c30d9
AK		 4192 }
4193
4194 err = pci_request_regions(pdev, DRV_NAME);
4195 if (err)
4196 goto out_pci_disable_device;
4197
4198 pci_set_drvdata(pdev, priv);
4199
316c30d9
AK		 4200
4201 /***********************
4202 * 3. Read REV register
4203 ***********************/
4204 priv->hw_base = pci_iomap(pdev, 0, 0);
4205 if (!priv->hw_base) {
4206 err = -ENODEV;
4207 goto out_pci_release_regions;
4208 }
4209
e1623446 4210 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4211 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4212 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4213
731a29b7 4214 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4215 * we should init now
4216 */
4217 spin_lock_init(&priv->reg_lock);
731a29b7 4218 spin_lock_init(&priv->lock);
4843b5a7
RC		 4219
4220 /*
4221 * stop and reset the on-board processor just in case it is in a
4222 * strange state ... like being left stranded by a primary kernel
4223 * and this is now the kdump kernel trying to start up
4224 */
4225 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4226
b661c819 4227 iwl_hw_detect(priv);
c11362c0 4228 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4229 priv->cfg->name, priv->hw_rev);
316c30d9 4230
e7b63581
TW		 4231 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4232 * PCI Tx retries from interfering with C3 CPU state */
4233 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4234
086ed117
MA		 4235 iwl_prepare_card_hw(priv);
4236 if (!priv->hw_ready) {
4237 IWL_WARN(priv, "Failed, HW not ready\n");
4238 goto out_iounmap;
4239 }
4240
91238714
TW		 4241 /*****************
4242 * 4. Read EEPROM
4243 *****************/
316c30d9
AK		 4244 /* Read the EEPROM */
4245 err = iwl_eeprom_init(priv);
4246 if (err) {
15b1687c 4247 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4248 goto out_iounmap;
4249 }
8614f360
TW		 4250 err = iwl_eeprom_check_version(priv);
4251 if (err)
c8f16138 4252 goto out_free_eeprom;
8614f360 4253
02883017 4254 /* extract MAC Address */
c6fa17ed
WYG		 4255 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4256 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4257 priv->hw->wiphy->addresses = priv->addresses;
4258 priv->hw->wiphy->n_addresses = 1;
4259 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4260 if (num_mac > 1) {
4261 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4262 ETH_ALEN);
4263 priv->addresses[1].addr[5]++;
4264 priv->hw->wiphy->n_addresses++;
4265 }
316c30d9
AK		 4266
4267 /************************
4268 * 5. Setup HW constants
4269 ************************/
da154e30 4270 if (iwl_set_hw_params(priv)) {
15b1687c 4271 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4272 goto out_free_eeprom;
316c30d9
AK		 4273 }
4274
4275 /*******************
6ba87956 4276 * 6. Setup priv
316c30d9 4277 *******************/
b481de9c 4278
6ba87956 4279 err = iwl_init_drv(priv);
bf85ea4f 4280 if (err)
399f4900 4281 goto out_free_eeprom;
bf85ea4f 4282 /* At this point both hw and priv are initialized. */
316c30d9 4283
316c30d9 4284 /********************
09f9bf79 4285 * 7. Setup services
316c30d9 4286 ********************/
0359facc 4287 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4288 iwl_disable_interrupts(priv);
0359facc 4289 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4290
6cd0b1cb
HS		 4291 pci_enable_msi(priv->pci_dev);
4292
ef850d7c
MA		 4293 iwl_alloc_isr_ict(priv);
4294 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4295 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4296 if (err) {
4297 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4298 goto out_disable_msi;
4299 }
316c30d9 4300
4e39317d 4301 iwl_setup_deferred_work(priv);
653fa4a0 4302 iwl_setup_rx_handlers(priv);
316c30d9 4303
158bea07
JB		 4304 /*********************************************
4305 * 8. Enable interrupts and read RFKILL state
4306 *********************************************/
6ba87956 4307
6cd0b1cb
HS		 4308 /* enable interrupts if needed: hw bug w/a */
4309 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4310 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4311 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4312 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4313 }
4314
4315 iwl_enable_interrupts(priv);
4316
6cd0b1cb
HS		 4317 /* If platform's RF_KILL switch is NOT set to KILL */
4318 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4319 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4320 else
4321 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4322
a60e77e5
JB		 4323 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4324 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4325
58d0f361 4326 iwl_power_initialize(priv);
39b73fb1 4327 iwl_tt_initialize(priv);
158bea07 4328
a15707d8 4329 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4330
b08dfd04 4331 err = iwl_request_firmware(priv, true);
158bea07 4332 if (err)
7d47618a 4333 goto out_destroy_workqueue;
158bea07 4334
b481de9c
ZY		 4335 return 0;
4336
7d47618a 4337 out_destroy_workqueue:
c8f16138
RC		 4338 destroy_workqueue(priv->workqueue);
4339 priv->workqueue = NULL;
795cc0ad 4340 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4341 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4342 out_disable_msi:
4343 pci_disable_msi(priv->pci_dev);
6ba87956 4344 iwl_uninit_drv(priv);
073d3f5f
TW		 4345 out_free_eeprom:
4346 iwl_eeprom_free(priv);
b481de9c
ZY		 4347 out_iounmap:
4348 pci_iounmap(pdev, priv->hw_base);
4349 out_pci_release_regions:
316c30d9 4350 pci_set_drvdata(pdev, NULL);
623d563e 4351 pci_release_regions(pdev);
b481de9c
ZY		 4352 out_pci_disable_device:
4353 pci_disable_device(pdev);
b481de9c 4354 out_ieee80211_free_hw:
20594eb0 4355 iwl_free_traffic_mem(priv);
d7c76f4c 4356 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4357 out:
4358 return err;
4359}
4360
5b9f8cd3 4361static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4362{
c79dd5b5 4363 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4364 unsigned long flags;
b481de9c
ZY		 4365
4366 if (!priv)
4367 return;
4368
a15707d8 4369 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4370
e1623446 4371 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4372
67249625 4373 iwl_dbgfs_unregister(priv);
5b9f8cd3 4374 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4375
5b9f8cd3
EG		 4376 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4377 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4378 * we need to set STATUS_EXIT_PENDING bit.
4379 */
4380 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4381 if (priv->mac80211_registered) {
4382 ieee80211_unregister_hw(priv->hw);
4383 priv->mac80211_registered = 0;
0b124c31 4384 } else {
5b9f8cd3 4385 iwl_down(priv);
c4f55232
RR		 4386 }
4387
c166b25a
BC		 4388 /*
4389 * Make sure device is reset to low power before unloading driver.
4390 * This may be redundant with iwl_down(), but there are paths to
4391 * run iwl_down() without calling apm_ops.stop(), and there are
4392 * paths to avoid running iwl_down() at all before leaving driver.
4393 * This (inexpensive) call *makes sure* device is reset.
4394 */
4395 priv->cfg->ops->lib->apm_ops.stop(priv);
4396
39b73fb1
WYG		 4397 iwl_tt_exit(priv);
4398
0359facc
MA		 4399 /* make sure we flush any pending irq or
4400 * tasklet for the driver
4401 */
4402 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4403 iwl_disable_interrupts(priv);
0359facc
MA		 4404 spin_unlock_irqrestore(&priv->lock, flags);
4405
4406 iwl_synchronize_irq(priv);
4407
5b9f8cd3 4408 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4409
4410 if (priv->rxq.bd)
54b81550 4411 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4412 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4413
073d3f5f 4414 iwl_eeprom_free(priv);
b481de9c 4415
b481de9c 4416
948c171c
MA		 4417 /*netif_stop_queue(dev); */
4418 flush_workqueue(priv->workqueue);
4419
5b9f8cd3 4420 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4421 * priv->workqueue... so we can't take down the workqueue
4422 * until now... */
4423 destroy_workqueue(priv->workqueue);
4424 priv->workqueue = NULL;
20594eb0 4425 iwl_free_traffic_mem(priv);
b481de9c 4426
6cd0b1cb
HS		 4427 free_irq(priv->pci_dev->irq, priv);
4428 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4429 pci_iounmap(pdev, priv->hw_base);
4430 pci_release_regions(pdev);
4431 pci_disable_device(pdev);
4432 pci_set_drvdata(pdev, NULL);
4433
6ba87956 4434 iwl_uninit_drv(priv);
b481de9c 4435
ef850d7c
MA		 4436 iwl_free_isr_ict(priv);
4437
b481de9c
ZY		 4438 if (priv->ibss_beacon)
4439 dev_kfree_skb(priv->ibss_beacon);
4440
4441 ieee80211_free_hw(priv->hw);
4442}
4443
b481de9c
ZY		 4444
4445/*****************************************************************************
4446 *
4447 * driver and module entry point
4448 *
4449 *****************************************************************************/
4450
fed9017e 4451/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4452static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4453#ifdef CONFIG_IWL4965
fed9017e
RR		 4454 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4455 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4456#endif /* CONFIG_IWL4965 */
5a6a256e 4457#ifdef CONFIG_IWL5000
ac592574
WYG		 4458/* 5100 Series WiFi */
4459 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4460 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4461 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4462 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4463 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4464 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4465 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4466 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4467 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4468 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4469 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4470 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4471 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4472 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4473 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4474 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4475 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4476 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4477 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4478 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4479 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4480 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4481 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4482 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4483
4484/* 5300 Series WiFi */
4485 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4486 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4487 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4488 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4489 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4490 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4491 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4492 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4493 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4494 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4495 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4496 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4497
4498/* 5350 Series WiFi/WiMax */
4499 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4500 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4501 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4502
4503/* 5150 Series Wifi/WiMax */
4504 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4505 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4506 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4507 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4508 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4509 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4510
4511 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4512 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4513 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4514 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4515
4516/* 6x00 Series */
5953a62e
WYG		 4517 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4518 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4519 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4520 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4521 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4522 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4523 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4524 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4525 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4526 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4527
95b13014
SZ		 4528/* 6x00 Series Gen2a */
4529 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4530 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4531 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4532 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4533 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4534 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4535 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4536 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4537 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4538 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4539 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4540 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4541 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4542 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4543
4544/* 6x00 Series Gen2b */
4545 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4546 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4547 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4548 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4549 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4550 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4551 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4552 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4553 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4554 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4555 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4556 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4557 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4558 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4559 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4560 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4561 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4562 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4563 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4564 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4565 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4566 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4567 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4568 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4569 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4570 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4571 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4572 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4573
4574/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4575 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4576 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4577 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4578 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4579 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4580 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4581
03264339
SZ		 4582/* 6x50 WiFi/WiMax Series Gen2 */
4583 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4584 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4585 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4586 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4587 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4588 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4589
77dcb6a9 4590/* 1000 Series WiFi */
4bd0914f
WYG		 4591 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4592 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4593 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4594 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4595 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4596 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4597 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4598 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4599 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4600 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4601 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4602 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 4603#endif /* CONFIG_IWL5000 */
7100e924 4604
fed9017e
RR		 4605 {0}
4606};
4607MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4608
4609static struct pci_driver iwl_driver = {
b481de9c 4610 .name = DRV_NAME,
fed9017e 4611 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4612 .probe = iwl_pci_probe,
4613 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4614#ifdef CONFIG_PM
5b9f8cd3
EG		 4615 .suspend = iwl_pci_suspend,
4616 .resume = iwl_pci_resume,
b481de9c
ZY		 4617#endif
4618};
4619
5b9f8cd3 4620static int __init iwl_init(void)
b481de9c
ZY		 4621{
4622
4623 int ret;
c96c31e4
JP		 4624 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4625 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4626
e227ceac 4627 ret = iwlagn_rate_control_register();
897e1cf2 4628 if (ret) {
c96c31e4 4629 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4630 return ret;
4631 }
4632
fed9017e 4633 ret = pci_register_driver(&iwl_driver);
b481de9c 4634 if (ret) {
c96c31e4 4635 pr_err("Unable to initialize PCI module\n");
897e1cf2 4636 goto error_register;
b481de9c 4637 }
b481de9c
ZY		 4638
4639 return ret;
897e1cf2 4640
897e1cf2 4641error_register:
e227ceac 4642 iwlagn_rate_control_unregister();
897e1cf2 4643 return ret;
b481de9c
ZY		 4644}
4645
5b9f8cd3 4646static void __exit iwl_exit(void)
b481de9c 4647{
fed9017e 4648 pci_unregister_driver(&iwl_driver);
e227ceac 4649 iwlagn_rate_control_unregister();
b481de9c
ZY		 4650}
4651
5b9f8cd3
EG		 4652module_exit(iwl_exit);
4653module_init(iwl_init);
a562a9dd
RC		 4654
4655#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4656module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4657MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4658module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4659MODULE_PARM_DESC(debug, "debug output mask");
4660#endif
4661
2b068618
WYG		 4662module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4663MODULE_PARM_DESC(swcrypto50,
4664 "using crypto in software (default 0 [hardware]) (deprecated)");
4665module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4666MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4667module_param_named(queues_num50,
4668 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4669MODULE_PARM_DESC(queues_num50,
4670 "number of hw queues in 50xx series (deprecated)");
4671module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4672MODULE_PARM_DESC(queues_num, "number of hw queues.");
4673module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4674MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4675module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4676MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4677module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4678 int, S_IRUGO);
4679MODULE_PARM_DESC(amsdu_size_8K50,
4680 "enable 8K amsdu size in 50XX series (deprecated)");
4681module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4682 int, S_IRUGO);
4683MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4684module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4685MODULE_PARM_DESC(fw_restart50,
4686 "restart firmware in case of error (deprecated)");
4687module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4688MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4689module_param_named(
4690 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4691MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
dd7a2509
JB		 4692
4693module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4694 S_IRUGO);
4695MODULE_PARM_DESC(ucode_alternative,
4696 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4697
4698module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4699MODULE_PARM_DESC(antenna_coupling,
4700 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9
WYG		 4701
4702module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4703MODULE_PARM_DESC(bt_ch_announce,
4704 "Enable BT channel announcement mode (default: enable)");
Linux kernel - Deliverables
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