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iwlwifi: use iwl_sta_id() for TKIP key update
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
b481de9c
ZY		 37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
b481de9c
ZY		 44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO		 48#define DRV_NAME "iwlagn"
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
f0832f13 56#include "iwl-calib.h"
a1175124 57#include "iwl-agn.h"
b481de9c 58
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
b481de9c
ZY		 66/*
67 * module name, copyright, version, etc.
b481de9c 68 */
d783b061 69#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 70
0a6857e7 71#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 72#define VD "d"
73#else
74#define VD
75#endif
76
81963d68 77#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 78
b481de9c
ZY		 79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_VERSION(DRV_VERSION);
a7b75207 82MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 83MODULE_LICENSE("GPL");
4fc22b21 84MODULE_ALIAS("iwl4965");
b481de9c 85
b481de9c 86/**
5b9f8cd3 87 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 88 *
01ebd063 89 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 90 * the active_rxon structure is updated with the new data. This
91 * function correctly transitions out of the RXON_ASSOC_MSK state if
92 * a HW tune is required based on the RXON structure changes.
93 */
e0158e61 94int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 95{
96 /* cast away the const for active_rxon in this function */
c1adf9fb 97 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG		 98 int ret;
99 bool new_assoc =
100 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 101
fee1247a 102 if (!iwl_is_alive(priv))
43d59b32 103 return -EBUSY;
b481de9c
ZY		 104
105 /* always get timestamp with Rx frame */
106 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
107
8ccde88a 108 ret = iwl_check_rxon_cmd(priv);
43d59b32 109 if (ret) {
15b1687c 110 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 111 return -EINVAL;
112 }
113
0924e519
WYG		 114 /*
115 * receive commit_rxon request
116 * abort any previous channel switch if still in process
117 */
118 if (priv->switch_rxon.switch_in_progress &&
119 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
120 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
121 le16_to_cpu(priv->switch_rxon.channel));
122 priv->switch_rxon.switch_in_progress = false;
123 }
124
b481de9c 125 /* If we don't need to send a full RXON, we can use
5b9f8cd3 126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 127 * and other flags for the current radio configuration. */
54559703 128 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG		 129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
15b1687c 131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 132 return ret;
b481de9c
ZY		 133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 136 iwl_print_rx_config_cmd(priv);
b481de9c
ZY		 137 return 0;
138 }
139
b481de9c
ZY		 140 /* If we are currently associated and the new config requires
141 * an RXON_ASSOC and the new config wants the associated mask enabled,
142 * we must clear the associated from the active configuration
143 * before we apply the new config */
43d59b32 144 if (iwl_is_associated(priv) && new_assoc) {
e1623446 145 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 146 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
147
43d59b32 148 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 149 sizeof(struct iwl_rxon_cmd),
b481de9c
ZY		 150 &priv->active_rxon);
151
152 /* If the mask clearing failed then we set
153 * active_rxon back to what it was previously */
43d59b32 154 if (ret) {
b481de9c 155 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 156 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 157 return ret;
b481de9c 158 }
2c810ccd 159 iwl_clear_ucode_stations(priv);
7e246191 160 iwl_restore_stations(priv);
335348b1
JB		 161 ret = iwl_restore_default_wep_keys(priv);
162 if (ret) {
163 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
164 return ret;
165 }
b481de9c
ZY		 166 }
167
e1623446 168 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 169 "* with%s RXON_FILTER_ASSOC_MSK\n"
170 "* channel = %d\n"
e174961c 171 "* bssid = %pM\n",
43d59b32 172 (new_assoc ? "" : "out"),
b481de9c 173 le16_to_cpu(priv->staging_rxon.channel),
e174961c 174 priv->staging_rxon.bssid_addr);
b481de9c 175
90e8e424 176 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG		 177
178 /* Apply the new configuration
7e246191
RC		 179 * RXON unassoc clears the station table in uCode so restoration of
180 * stations is needed after it (the RXON command) completes
43d59b32
EG		 181 */
182 if (!new_assoc) {
183 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 184 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 185 if (ret) {
15b1687c 186 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 187 return ret;
188 }
91dd6c27 189 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
43d59b32 190 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
2c810ccd 191 iwl_clear_ucode_stations(priv);
7e246191 192 iwl_restore_stations(priv);
335348b1
JB		 193 ret = iwl_restore_default_wep_keys(priv);
194 if (ret) {
195 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
196 return ret;
197 }
b481de9c
ZY		 198 }
199
19cc1087 200 priv->start_calib = 0;
9185159d 201 if (new_assoc) {
47eef9bd
WYG		 202 /*
203 * allow CTS-to-self if possible for new association.
204 * this is relevant only for 5000 series and up,
205 * but will not damage 4965
206 */
207 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
208
43d59b32
EG		 209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
211 */
212 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
213 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
214 if (ret) {
15b1687c 215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 216 return ret;
217 }
218 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 219 }
a643565e 220 iwl_print_rx_config_cmd(priv);
b481de9c 221
36da7d70
ZY		 222 iwl_init_sensitivity(priv);
223
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227 if (ret) {
15b1687c 228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 229 return ret;
230 }
231
b481de9c
ZY		 232 return 0;
233}
234
5b9f8cd3 235void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA		 236{
237
45823531
AK		 238 if (priv->cfg->ops->hcmd->set_rxon_chain)
239 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 240 iwlcore_commit_rxon(priv);
5da4b55f
MA		 241}
242
fcab423d 243static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 244{
245 struct list_head *element;
246
e1623446 247 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 248 priv->frames_count);
249
250 while (!list_empty(&priv->free_frames)) {
251 element = priv->free_frames.next;
252 list_del(element);
fcab423d 253 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 254 priv->frames_count--;
255 }
256
257 if (priv->frames_count) {
39aadf8c 258 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 259 priv->frames_count);
260 priv->frames_count = 0;
261 }
262}
263
fcab423d 264static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 265{
fcab423d 266 struct iwl_frame *frame;
b481de9c
ZY		 267 struct list_head *element;
268 if (list_empty(&priv->free_frames)) {
269 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
270 if (!frame) {
15b1687c 271 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 272 return NULL;
273 }
274
275 priv->frames_count++;
276 return frame;
277 }
278
279 element = priv->free_frames.next;
280 list_del(element);
fcab423d 281 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 282}
283
fcab423d 284static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 285{
286 memset(frame, 0, sizeof(*frame));
287 list_add(&frame->list, &priv->free_frames);
288}
289
47ff65c4 290static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 291 struct ieee80211_hdr *hdr,
73ec1cc2 292 int left)
b481de9c 293{
3109ece1 294 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 295 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
296 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 297 return 0;
298
299 if (priv->ibss_beacon->len > left)
300 return 0;
301
302 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
303
304 return priv->ibss_beacon->len;
305}
306
47ff65c4
DH		 307/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
308static void iwl_set_beacon_tim(struct iwl_priv *priv,
309 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
310 u8 *beacon, u32 frame_size)
311{
312 u16 tim_idx;
313 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
314
315 /*
316 * The index is relative to frame start but we start looking at the
317 * variable-length part of the beacon.
318 */
319 tim_idx = mgmt->u.beacon.variable - beacon;
320
321 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
322 while ((tim_idx < (frame_size - 2)) &&
323 (beacon[tim_idx] != WLAN_EID_TIM))
324 tim_idx += beacon[tim_idx+1] + 2;
325
326 /* If TIM field was found, set variables */
327 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
328 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
329 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
330 } else
331 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
332}
333
5b9f8cd3 334static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 335 struct iwl_frame *frame)
4bf64efd
TW		 336{
337 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 338 u32 frame_size;
339 u32 rate_flags;
340 u32 rate;
341 /*
342 * We have to set up the TX command, the TX Beacon command, and the
343 * beacon contents.
344 */
4bf64efd 345
47ff65c4 346 /* Initialize memory */
4bf64efd
TW		 347 tx_beacon_cmd = &frame->u.beacon;
348 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
349
47ff65c4 350 /* Set up TX beacon contents */
4bf64efd 351 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 352 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 353 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
354 return 0;
4bf64efd 355
47ff65c4 356 /* Set up TX command fields */
4bf64efd 357 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH		 358 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
359 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
360 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
361 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 362
47ff65c4
DH		 363 /* Set up TX beacon command fields */
364 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
365 frame_size);
4bf64efd 366
47ff65c4
DH		 367 /* Set up packet rate and flags */
368 rate = iwl_rate_get_lowest_plcp(priv);
369 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
370 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
371 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
372 rate_flags |= RATE_MCS_CCK_MSK;
373 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
374 rate_flags);
4bf64efd
TW		 375
376 return sizeof(*tx_beacon_cmd) + frame_size;
377}
5b9f8cd3 378static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 379{
fcab423d 380 struct iwl_frame *frame;
b481de9c
ZY		 381 unsigned int frame_size;
382 int rc;
b481de9c 383
fcab423d 384 frame = iwl_get_free_frame(priv);
b481de9c 385 if (!frame) {
15b1687c 386 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 387 "command.\n");
388 return -ENOMEM;
389 }
390
47ff65c4
DH		 391 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
392 if (!frame_size) {
393 IWL_ERR(priv, "Error configuring the beacon command\n");
394 iwl_free_frame(priv, frame);
395 return -EINVAL;
396 }
b481de9c 397
857485c0 398 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 399 &frame->u.cmd[0]);
400
fcab423d 401 iwl_free_frame(priv, frame);
b481de9c
ZY		 402
403 return rc;
404}
405
7aaa1d79
SO		 406static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
407{
408 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
409
410 dma_addr_t addr = get_unaligned_le32(&tb->lo);
411 if (sizeof(dma_addr_t) > sizeof(u32))
412 addr |=
413 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
414
415 return addr;
416}
417
418static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
419{
420 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
421
422 return le16_to_cpu(tb->hi_n_len) >> 4;
423}
424
425static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
426 dma_addr_t addr, u16 len)
427{
428 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
429 u16 hi_n_len = len << 4;
430
431 put_unaligned_le32(addr, &tb->lo);
432 if (sizeof(dma_addr_t) > sizeof(u32))
433 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
434
435 tb->hi_n_len = cpu_to_le16(hi_n_len);
436
437 tfd->num_tbs = idx + 1;
438}
439
440static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
441{
442 return tfd->num_tbs & 0x1f;
443}
444
445/**
446 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
447 * @priv - driver private data
448 * @txq - tx queue
449 *
450 * Does NOT advance any TFD circular buffer read/write indexes
451 * Does NOT free the TFD itself (which is within circular buffer)
452 */
453void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
454{
59606ffa 455 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 456 struct iwl_tfd *tfd;
457 struct pci_dev *dev = priv->pci_dev;
458 int index = txq->q.read_ptr;
459 int i;
460 int num_tbs;
461
462 tfd = &tfd_tmp[index];
463
464 /* Sanity check on number of chunks */
465 num_tbs = iwl_tfd_get_num_tbs(tfd);
466
467 if (num_tbs >= IWL_NUM_OF_TBS) {
468 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
469 /* @todo issue fatal error, it is quite serious situation */
470 return;
471 }
472
473 /* Unmap tx_cmd */
474 if (num_tbs)
475 pci_unmap_single(dev,
c2acea8e
JB		 476 pci_unmap_addr(&txq->meta[index], mapping),
477 pci_unmap_len(&txq->meta[index], len),
96891cee 478 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 479
480 /* Unmap chunks, if any. */
481 for (i = 1; i < num_tbs; i++) {
482 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
483 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
484
485 if (txq->txb) {
486 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
487 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
488 }
489 }
490}
491
492int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
493 struct iwl_tx_queue *txq,
494 dma_addr_t addr, u16 len,
495 u8 reset, u8 pad)
496{
497 struct iwl_queue *q;
59606ffa 498 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 499 u32 num_tbs;
500
501 q = &txq->q;
59606ffa
SO		 502 tfd_tmp = (struct iwl_tfd *)txq->tfds;
503 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 504
505 if (reset)
506 memset(tfd, 0, sizeof(*tfd));
507
508 num_tbs = iwl_tfd_get_num_tbs(tfd);
509
510 /* Each TFD can point to a maximum 20 Tx buffers */
511 if (num_tbs >= IWL_NUM_OF_TBS) {
512 IWL_ERR(priv, "Error can not send more than %d chunks\n",
513 IWL_NUM_OF_TBS);
514 return -EINVAL;
515 }
516
517 BUG_ON(addr & ~DMA_BIT_MASK(36));
518 if (unlikely(addr & ~IWL_TX_DMA_MASK))
519 IWL_ERR(priv, "Unaligned address = %llx\n",
520 (unsigned long long)addr);
521
522 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
523
524 return 0;
525}
526
a8e74e27
SO		 527/*
528 * Tell nic where to find circular buffer of Tx Frame Descriptors for
529 * given Tx queue, and enable the DMA channel used for that queue.
530 *
531 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
532 * channels supported in hardware.
533 */
534int iwl_hw_tx_queue_init(struct iwl_priv *priv,
535 struct iwl_tx_queue *txq)
536{
a8e74e27
SO		 537 int txq_id = txq->q.id;
538
a8e74e27
SO		 539 /* Circular buffer (TFD queue in DRAM) physical base address */
540 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
541 txq->q.dma_addr >> 8);
542
a8e74e27
SO		 543 return 0;
544}
545
b481de9c
ZY		 546/******************************************************************************
547 *
548 * Generic RX handler implementations
549 *
550 ******************************************************************************/
885ba202
TW		 551static void iwl_rx_reply_alive(struct iwl_priv *priv,
552 struct iwl_rx_mem_buffer *rxb)
b481de9c 553{
2f301227 554 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 555 struct iwl_alive_resp *palive;
b481de9c
ZY		 556 struct delayed_work *pwork;
557
558 palive = &pkt->u.alive_frame;
559
e1623446 560 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 561 "0x%01X 0x%01X\n",
562 palive->is_valid, palive->ver_type,
563 palive->ver_subtype);
564
565 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 566 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 567 memcpy(&priv->card_alive_init,
568 &pkt->u.alive_frame,
885ba202 569 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 570 pwork = &priv->init_alive_start;
571 } else {
e1623446 572 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 573 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 574 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 575 pwork = &priv->alive_start;
576 }
577
578 /* We delay the ALIVE response by 5ms to
579 * give the HW RF Kill time to activate... */
580 if (palive->is_valid == UCODE_VALID_OK)
581 queue_delayed_work(priv->workqueue, pwork,
582 msecs_to_jiffies(5));
583 else
39aadf8c 584 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 585}
586
5b9f8cd3 587static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 588{
c79dd5b5
TW		 589 struct iwl_priv *priv =
590 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 591 struct sk_buff *beacon;
592
593 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 594 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 595
596 if (!beacon) {
15b1687c 597 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 598 return;
599 }
600
601 mutex_lock(&priv->mutex);
602 /* new beacon skb is allocated every time; dispose previous.*/
603 if (priv->ibss_beacon)
604 dev_kfree_skb(priv->ibss_beacon);
605
606 priv->ibss_beacon = beacon;
607 mutex_unlock(&priv->mutex);
608
5b9f8cd3 609 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 610}
611
4e39317d 612/**
5b9f8cd3 613 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 614 *
615 * This callback is provided in order to send a statistics request.
616 *
617 * This timer function is continually reset to execute within
618 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
619 * was received. We need to ensure we receive the statistics in order
620 * to update the temperature used for calibrating the TXPOWER.
621 */
5b9f8cd3 622static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 623{
624 struct iwl_priv *priv = (struct iwl_priv *)data;
625
626 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
627 return;
628
61780ee3
MA		 629 /* dont send host command if rf-kill is on */
630 if (!iwl_is_ready_rf(priv))
631 return;
632
ef8d5529 633 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 634}
635
a9e1cb6a
WYG		 636
637static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
638 u32 start_idx, u32 num_events,
639 u32 mode)
640{
641 u32 i;
642 u32 ptr; /* SRAM byte address of log data */
643 u32 ev, time, data; /* event log data */
644 unsigned long reg_flags;
645
646 if (mode == 0)
647 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
648 else
649 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
650
651 /* Make sure device is powered up for SRAM reads */
652 spin_lock_irqsave(&priv->reg_lock, reg_flags);
653 if (iwl_grab_nic_access(priv)) {
654 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
655 return;
656 }
657
658 /* Set starting address; reads will auto-increment */
659 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
660 rmb();
661
662 /*
663 * "time" is actually "data" for mode 0 (no timestamp).
664 * place event id # at far right for easier visual parsing.
665 */
666 for (i = 0; i < num_events; i++) {
667 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
668 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
669 if (mode == 0) {
670 trace_iwlwifi_dev_ucode_cont_event(priv,
671 0, time, ev);
672 } else {
673 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
674 trace_iwlwifi_dev_ucode_cont_event(priv,
675 time, data, ev);
676 }
677 }
678 /* Allow device to power down */
679 iwl_release_nic_access(priv);
680 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
681}
682
875295f1 683static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 684{
685 u32 capacity; /* event log capacity in # entries */
686 u32 base; /* SRAM byte address of event log header */
687 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
688 u32 num_wraps; /* # times uCode wrapped to top of log */
689 u32 next_entry; /* index of next entry to be written by uCode */
690
691 if (priv->ucode_type == UCODE_INIT)
692 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
693 else
694 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
695 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
696 capacity = iwl_read_targ_mem(priv, base);
697 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
698 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
699 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
700 } else
701 return;
702
703 if (num_wraps == priv->event_log.num_wraps) {
704 iwl_print_cont_event_trace(priv,
705 base, priv->event_log.next_entry,
706 next_entry - priv->event_log.next_entry,
707 mode);
708 priv->event_log.non_wraps_count++;
709 } else {
710 if ((num_wraps - priv->event_log.num_wraps) > 1)
711 priv->event_log.wraps_more_count++;
712 else
713 priv->event_log.wraps_once_count++;
714 trace_iwlwifi_dev_ucode_wrap_event(priv,
715 num_wraps - priv->event_log.num_wraps,
716 next_entry, priv->event_log.next_entry);
717 if (next_entry < priv->event_log.next_entry) {
718 iwl_print_cont_event_trace(priv, base,
719 priv->event_log.next_entry,
720 capacity - priv->event_log.next_entry,
721 mode);
722
723 iwl_print_cont_event_trace(priv, base, 0,
724 next_entry, mode);
725 } else {
726 iwl_print_cont_event_trace(priv, base,
727 next_entry, capacity - next_entry,
728 mode);
729
730 iwl_print_cont_event_trace(priv, base, 0,
731 next_entry, mode);
732 }
733 }
734 priv->event_log.num_wraps = num_wraps;
735 priv->event_log.next_entry = next_entry;
736}
737
738/**
739 * iwl_bg_ucode_trace - Timer callback to log ucode event
740 *
741 * The timer is continually set to execute every
742 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
743 * this function is to perform continuous uCode event logging operation
744 * if enabled
745 */
746static void iwl_bg_ucode_trace(unsigned long data)
747{
748 struct iwl_priv *priv = (struct iwl_priv *)data;
749
750 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
751 return;
752
753 if (priv->event_log.ucode_trace) {
754 iwl_continuous_event_trace(priv);
755 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
756 mod_timer(&priv->ucode_trace,
757 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
758 }
759}
760
5b9f8cd3 761static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 762 struct iwl_rx_mem_buffer *rxb)
b481de9c 763{
0a6857e7 764#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 765 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 766 struct iwl4965_beacon_notif *beacon =
767 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 768 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 769
e1623446 770 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 771 "tsf %d %d rate %d\n",
25a6572c 772 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 773 beacon->beacon_notify_hdr.failure_frame,
774 le32_to_cpu(beacon->ibss_mgr_status),
775 le32_to_cpu(beacon->high_tsf),
776 le32_to_cpu(beacon->low_tsf), rate);
777#endif
778
05c914fe 779 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 780 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
781 queue_work(priv->workqueue, &priv->beacon_update);
782}
783
b481de9c
ZY		 784/* Handle notification from uCode that card's power state is changing
785 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 786static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 787 struct iwl_rx_mem_buffer *rxb)
b481de9c 788{
2f301227 789 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 790 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
791 unsigned long status = priv->status;
792
3a41bbd5 793 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 794 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 795 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
796 (flags & CT_CARD_DISABLED) ?
797 "Reached" : "Not reached");
b481de9c
ZY		 798
799 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 800 CT_CARD_DISABLED)) {
b481de9c 801
3395f6e9 802 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 803 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
804
a8b50a0a
MA		 805 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
806 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 807
808 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 809 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 810 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 811 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 812 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 813 }
3a41bbd5 814 if (flags & CT_CARD_DISABLED)
39b73fb1 815 iwl_tt_enter_ct_kill(priv);
b481de9c 816 }
3a41bbd5 817 if (!(flags & CT_CARD_DISABLED))
39b73fb1 818 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 819
820 if (flags & HW_CARD_DISABLED)
821 set_bit(STATUS_RF_KILL_HW, &priv->status);
822 else
823 clear_bit(STATUS_RF_KILL_HW, &priv->status);
824
825
b481de9c 826 if (!(flags & RXON_CARD_DISABLED))
2a421b91 827 iwl_scan_cancel(priv);
b481de9c
ZY		 828
829 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 830 test_bit(STATUS_RF_KILL_HW, &priv->status)))
831 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
832 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 833 else
834 wake_up_interruptible(&priv->wait_command_queue);
835}
836
5b9f8cd3 837int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 838{
e2e3c57b 839 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 840 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 841 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
842 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
843 ~APMG_PS_CTRL_MSK_PWR_SRC);
844 } else {
845 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
846 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
847 ~APMG_PS_CTRL_MSK_PWR_SRC);
848 }
849
a8b50a0a 850 return 0;
e2e3c57b
TW		 851}
852
b481de9c 853/**
5b9f8cd3 854 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 855 *
856 * Setup the RX handlers for each of the reply types sent from the uCode
857 * to the host.
858 *
859 * This function chains into the hardware specific files for them to setup
860 * any hardware specific handlers as well.
861 */
653fa4a0 862static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 863{
885ba202 864 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 865 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
866 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 867 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
868 iwl_rx_spectrum_measure_notif;
5b9f8cd3 869 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 870 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 871 iwl_rx_pm_debug_statistics_notif;
872 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 873
9fbab516
BC		 874 /*
875 * The same handler is used for both the REPLY to a discrete
876 * statistics request from the host as well as for the periodic
877 * statistics notifications (after received beacons) from the uCode.
b481de9c 878 */
ef8d5529 879 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 880 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 881
882 iwl_setup_rx_scan_handlers(priv);
883
37a44211 884 /* status change handler */
5b9f8cd3 885 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 886
c1354754
TW		 887 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
888 iwl_rx_missed_beacon_notif;
37a44211 889 /* Rx handlers */
8d801080
WYG		 890 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
891 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 892 /* block ack */
74bcdb33 893 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 894 /* Set up hardware specific Rx handlers */
d4789efe 895 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 896}
897
b481de9c 898/**
a55360e4 899 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 900 *
901 * Uses the priv->rx_handlers callback function array to invoke
902 * the appropriate handlers, including command responses,
903 * frame-received notifications, and other notifications.
904 */
a55360e4 905void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 906{
a55360e4 907 struct iwl_rx_mem_buffer *rxb;
db11d634 908 struct iwl_rx_packet *pkt;
a55360e4 909 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 910 u32 r, i;
911 int reclaim;
912 unsigned long flags;
5c0eef96 913 u8 fill_rx = 0;
d68ab680 914 u32 count = 8;
4752c93c 915 int total_empty;
b481de9c 916
6440adb5
CB		 917 /* uCode's read index (stored in shared DRAM) indicates the last Rx
918 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 919 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 920 i = rxq->read;
921
922 /* Rx interrupt, but nothing sent from uCode */
923 if (i == r)
e1623446 924 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 925
4752c93c 926 /* calculate total frames need to be restock after handling RX */
7300515d 927 total_empty = r - rxq->write_actual;
4752c93c
MA		 928 if (total_empty < 0)
929 total_empty += RX_QUEUE_SIZE;
930
931 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 932 fill_rx = 1;
933
b481de9c
ZY		 934 while (i != r) {
935 rxb = rxq->queue[i];
936
9fbab516 937 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 938 * then a bug has been introduced in the queue refilling
939 * routines -- catch it here */
940 BUG_ON(rxb == NULL);
941
942 rxq->queue[i] = NULL;
943
2f301227
ZY		 944 pci_unmap_page(priv->pci_dev, rxb->page_dma,
945 PAGE_SIZE << priv->hw_params.rx_page_order,
946 PCI_DMA_FROMDEVICE);
947 pkt = rxb_addr(rxb);
b481de9c 948
be1a71a1
JB		 949 trace_iwlwifi_dev_rx(priv, pkt,
950 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
951
b481de9c
ZY		 952 /* Reclaim a command buffer only if this packet is a response
953 * to a (driver-originated) command.
954 * If the packet (e.g. Rx frame) originated from uCode,
955 * there is no command buffer to reclaim.
956 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
957 * but apparently a few don't get set; catch them here. */
958 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
959 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 960 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 961 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 962 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 963 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
964 (pkt->hdr.cmd != REPLY_TX);
965
966 /* Based on type of command response or notification,
967 * handle those that need handling via function in
5b9f8cd3 968 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 969 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 970 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 971 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 972 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 973 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 974 } else {
975 /* No handling needed */
e1623446 976 IWL_DEBUG_RX(priv,
b481de9c
ZY		 977 "r %d i %d No handler needed for %s, 0x%02x\n",
978 r, i, get_cmd_string(pkt->hdr.cmd),
979 pkt->hdr.cmd);
980 }
981
29b1b268
ZY		 982 /*
983 * XXX: After here, we should always check rxb->page
984 * against NULL before touching it or its virtual
985 * memory (pkt). Because some rx_handler might have
986 * already taken or freed the pages.
987 */
988
b481de9c 989 if (reclaim) {
2f301227
ZY		 990 /* Invoke any callbacks, transfer the buffer to caller,
991 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 992 * as we reclaim the driver command queue */
29b1b268 993 if (rxb->page)
17b88929 994 iwl_tx_cmd_complete(priv, rxb);
b481de9c 995 else
39aadf8c 996 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 997 }
998
7300515d
ZY		 999 /* Reuse the page if possible. For notification packets and
1000 * SKBs that fail to Rx correctly, add them back into the
1001 * rx_free list for reuse later. */
1002 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1003 if (rxb->page != NULL) {
7300515d
ZY		 1004 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1005 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1006 PCI_DMA_FROMDEVICE);
1007 list_add_tail(&rxb->list, &rxq->rx_free);
1008 rxq->free_count++;
1009 } else
1010 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1011
b481de9c 1012 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1013
b481de9c 1014 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1015 /* If there are a lot of unused frames,
1016 * restock the Rx queue so ucode wont assert. */
1017 if (fill_rx) {
1018 count++;
1019 if (count >= 8) {
7300515d 1020 rxq->read = i;
54b81550 1021 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1022 count = 0;
1023 }
1024 }
b481de9c
ZY		 1025 }
1026
1027 /* Backtrack one entry */
7300515d 1028 rxq->read = i;
4752c93c 1029 if (fill_rx)
54b81550 1030 iwlagn_rx_replenish_now(priv);
4752c93c 1031 else
54b81550 1032 iwlagn_rx_queue_restock(priv);
a55360e4 1033}
a55360e4 1034
0359facc
MA		 1035/* call this function to flush any scheduled tasklet */
1036static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1037{
a96a27f9 1038 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1039 synchronize_irq(priv->pci_dev->irq);
1040 tasklet_kill(&priv->irq_tasklet);
1041}
1042
ef850d7c 1043static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1044{
1045 u32 inta, handled = 0;
1046 u32 inta_fh;
1047 unsigned long flags;
c2e61da2 1048 u32 i;
0a6857e7 1049#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1050 u32 inta_mask;
1051#endif
1052
1053 spin_lock_irqsave(&priv->lock, flags);
1054
1055 /* Ack/clear/reset pending uCode interrupts.
1056 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1057 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1058 inta = iwl_read32(priv, CSR_INT);
1059 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1060
1061 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1062 * Any new interrupts that happen after this, either while we're
1063 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1064 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1065 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1066
0a6857e7 1067#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1068 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1069 /* just for debug */
3395f6e9 1070 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1071 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1072 inta, inta_mask, inta_fh);
1073 }
1074#endif
1075
2f301227
ZY		 1076 spin_unlock_irqrestore(&priv->lock, flags);
1077
b481de9c
ZY		 1078 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1079 * atomic, make sure that inta covers all the interrupts that
1080 * we've discovered, even if FH interrupt came in just after
1081 * reading CSR_INT. */
6f83eaa1 1082 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1083 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1084 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1085 inta |= CSR_INT_BIT_FH_TX;
1086
1087 /* Now service all interrupt bits discovered above. */
1088 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1089 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1090
1091 /* Tell the device to stop sending interrupts */
5b9f8cd3 1092 iwl_disable_interrupts(priv);
b481de9c 1093
a83b9141 1094 priv->isr_stats.hw++;
5b9f8cd3 1095 iwl_irq_handle_error(priv);
b481de9c
ZY		 1096
1097 handled |= CSR_INT_BIT_HW_ERR;
1098
b481de9c
ZY		 1099 return;
1100 }
1101
0a6857e7 1102#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1103 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1104 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1105 if (inta & CSR_INT_BIT_SCD) {
e1623446 1106 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1107 "the frame/frames.\n");
a83b9141
WYG		 1108 priv->isr_stats.sch++;
1109 }
b481de9c
ZY		 1110
1111 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1112 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1113 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1114 priv->isr_stats.alive++;
1115 }
b481de9c
ZY		 1116 }
1117#endif
1118 /* Safely ignore these bits for debug checks below */
25c03d8e 1119 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1120
9fbab516 1121 /* HW RF KILL switch toggled */
b481de9c
ZY		 1122 if (inta & CSR_INT_BIT_RF_KILL) {
1123 int hw_rf_kill = 0;
3395f6e9 1124 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1125 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1126 hw_rf_kill = 1;
1127
4c423a2b 1128 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1129 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1130
a83b9141
WYG		 1131 priv->isr_stats.rfkill++;
1132
a9efa652 1133 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1134 * the driver allows loading the ucode even if the radio
1135 * is killed. Hence update the killswitch state here. The
1136 * rfkill handler will care about restarting if needed.
a9efa652 1137 */
6cd0b1cb
HS		 1138 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1139 if (hw_rf_kill)
1140 set_bit(STATUS_RF_KILL_HW, &priv->status);
1141 else
1142 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1143 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1144 }
b481de9c
ZY		 1145
1146 handled |= CSR_INT_BIT_RF_KILL;
1147 }
1148
9fbab516 1149 /* Chip got too hot and stopped itself */
b481de9c 1150 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1151 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1152 priv->isr_stats.ctkill++;
b481de9c
ZY		 1153 handled |= CSR_INT_BIT_CT_KILL;
1154 }
1155
1156 /* Error detected by uCode */
1157 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1158 IWL_ERR(priv, "Microcode SW error detected. "
1159 " Restarting 0x%X.\n", inta);
a83b9141
WYG		 1160 priv->isr_stats.sw++;
1161 priv->isr_stats.sw_err = inta;
5b9f8cd3 1162 iwl_irq_handle_error(priv);
b481de9c
ZY		 1163 handled |= CSR_INT_BIT_SW_ERR;
1164 }
1165
c2e61da2
BC		 1166 /*
1167 * uCode wakes up after power-down sleep.
1168 * Tell device about any new tx or host commands enqueued,
1169 * and about any Rx buffers made available while asleep.
1170 */
b481de9c 1171 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1172 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1173 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1174 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1175 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1176 priv->isr_stats.wakeup++;
b481de9c
ZY		 1177 handled |= CSR_INT_BIT_WAKEUP;
1178 }
1179
1180 /* All uCode command responses, including Tx command responses,
1181 * Rx "responses" (frame-received notification), and other
1182 * notifications from uCode come through here*/
1183 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1184 iwl_rx_handle(priv);
a83b9141 1185 priv->isr_stats.rx++;
b481de9c
ZY		 1186 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1187 }
1188
c72cd19f 1189 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1190 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1191 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1192 priv->isr_stats.tx++;
b481de9c 1193 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1194 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1195 priv->ucode_write_complete = 1;
1196 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1197 }
1198
a83b9141 1199 if (inta & ~handled) {
15b1687c 1200 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1201 priv->isr_stats.unhandled++;
1202 }
b481de9c 1203
40cefda9 1204 if (inta & ~(priv->inta_mask)) {
39aadf8c 1205 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1206 inta & ~priv->inta_mask);
39aadf8c 1207 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1208 }
1209
1210 /* Re-enable all interrupts */
0359facc
MA		 1211 /* only Re-enable if diabled by irq */
1212 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1213 iwl_enable_interrupts(priv);
b481de9c 1214
0a6857e7 1215#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1216 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1217 inta = iwl_read32(priv, CSR_INT);
1218 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1219 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1220 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1221 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1222 }
1223#endif
b481de9c
ZY		 1224}
1225
ef850d7c
MA		 1226/* tasklet for iwlagn interrupt */
1227static void iwl_irq_tasklet(struct iwl_priv *priv)
1228{
1229 u32 inta = 0;
1230 u32 handled = 0;
1231 unsigned long flags;
8756990f 1232 u32 i;
ef850d7c
MA		 1233#ifdef CONFIG_IWLWIFI_DEBUG
1234 u32 inta_mask;
1235#endif
1236
1237 spin_lock_irqsave(&priv->lock, flags);
1238
1239 /* Ack/clear/reset pending uCode interrupts.
1240 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1241 */
48a6be6a
SZ		 1242 /* There is a hardware bug in the interrupt mask function that some
1243 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1244 * they are disabled in the CSR_INT_MASK register. Furthermore the
1245 * ICT interrupt handling mechanism has another bug that might cause
1246 * these unmasked interrupts fail to be detected. We workaround the
1247 * hardware bugs here by ACKing all the possible interrupts so that
1248 * interrupt coalescing can still be achieved.
1249 */
0f2df9ea 1250 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1251
a4c8b2a6 1252 inta = priv->_agn.inta;
ef850d7c
MA		 1253
1254#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1255 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1256 /* just for debug */
1257 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1258 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1259 inta, inta_mask);
1260 }
1261#endif
2f301227
ZY		 1262
1263 spin_unlock_irqrestore(&priv->lock, flags);
1264
a4c8b2a6
JB		 1265 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1266 priv->_agn.inta = 0;
ef850d7c
MA		 1267
1268 /* Now service all interrupt bits discovered above. */
1269 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1270 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1271
1272 /* Tell the device to stop sending interrupts */
1273 iwl_disable_interrupts(priv);
1274
1275 priv->isr_stats.hw++;
1276 iwl_irq_handle_error(priv);
1277
1278 handled |= CSR_INT_BIT_HW_ERR;
1279
ef850d7c
MA		 1280 return;
1281 }
1282
1283#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1284 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1285 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1286 if (inta & CSR_INT_BIT_SCD) {
1287 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1288 "the frame/frames.\n");
1289 priv->isr_stats.sch++;
1290 }
1291
1292 /* Alive notification via Rx interrupt will do the real work */
1293 if (inta & CSR_INT_BIT_ALIVE) {
1294 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1295 priv->isr_stats.alive++;
1296 }
1297 }
1298#endif
1299 /* Safely ignore these bits for debug checks below */
1300 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1301
1302 /* HW RF KILL switch toggled */
1303 if (inta & CSR_INT_BIT_RF_KILL) {
1304 int hw_rf_kill = 0;
1305 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1306 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1307 hw_rf_kill = 1;
1308
4c423a2b 1309 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1310 hw_rf_kill ? "disable radio" : "enable radio");
1311
1312 priv->isr_stats.rfkill++;
1313
1314 /* driver only loads ucode once setting the interface up.
1315 * the driver allows loading the ucode even if the radio
1316 * is killed. Hence update the killswitch state here. The
1317 * rfkill handler will care about restarting if needed.
1318 */
1319 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1320 if (hw_rf_kill)
1321 set_bit(STATUS_RF_KILL_HW, &priv->status);
1322 else
1323 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1324 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1325 }
1326
1327 handled |= CSR_INT_BIT_RF_KILL;
1328 }
1329
1330 /* Chip got too hot and stopped itself */
1331 if (inta & CSR_INT_BIT_CT_KILL) {
1332 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1333 priv->isr_stats.ctkill++;
1334 handled |= CSR_INT_BIT_CT_KILL;
1335 }
1336
1337 /* Error detected by uCode */
1338 if (inta & CSR_INT_BIT_SW_ERR) {
1339 IWL_ERR(priv, "Microcode SW error detected. "
1340 " Restarting 0x%X.\n", inta);
1341 priv->isr_stats.sw++;
1342 priv->isr_stats.sw_err = inta;
1343 iwl_irq_handle_error(priv);
1344 handled |= CSR_INT_BIT_SW_ERR;
1345 }
1346
1347 /* uCode wakes up after power-down sleep */
1348 if (inta & CSR_INT_BIT_WAKEUP) {
1349 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1350 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1351 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1352 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1353
1354 priv->isr_stats.wakeup++;
1355
1356 handled |= CSR_INT_BIT_WAKEUP;
1357 }
1358
1359 /* All uCode command responses, including Tx command responses,
1360 * Rx "responses" (frame-received notification), and other
1361 * notifications from uCode come through here*/
40cefda9
MA		 1362 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1363 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1364 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1365 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1366 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1367 iwl_write32(priv, CSR_FH_INT_STATUS,
1368 CSR49_FH_INT_RX_MASK);
1369 }
1370 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1371 handled |= CSR_INT_BIT_RX_PERIODIC;
1372 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1373 }
1374 /* Sending RX interrupt require many steps to be done in the
1375 * the device:
1376 * 1- write interrupt to current index in ICT table.
1377 * 2- dma RX frame.
1378 * 3- update RX shared data to indicate last write index.
1379 * 4- send interrupt.
1380 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1381 * but the shared data changes does not reflect this;
1382 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1383 */
74ba67ed
BC		 1384
1385 /* Disable periodic interrupt; we use it as just a one-shot. */
1386 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1387 CSR_INT_PERIODIC_DIS);
ef850d7c 1388 iwl_rx_handle(priv);
74ba67ed
BC		 1389
1390 /*
1391 * Enable periodic interrupt in 8 msec only if we received
1392 * real RX interrupt (instead of just periodic int), to catch
1393 * any dangling Rx interrupt. If it was just the periodic
1394 * interrupt, there was no dangling Rx activity, and no need
1395 * to extend the periodic interrupt; one-shot is enough.
1396 */
40cefda9 1397 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1398 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1399 CSR_INT_PERIODIC_ENA);
1400
ef850d7c 1401 priv->isr_stats.rx++;
ef850d7c
MA		 1402 }
1403
c72cd19f 1404 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1405 if (inta & CSR_INT_BIT_FH_TX) {
1406 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1407 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1408 priv->isr_stats.tx++;
1409 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1410 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1411 priv->ucode_write_complete = 1;
1412 wake_up_interruptible(&priv->wait_command_queue);
1413 }
1414
1415 if (inta & ~handled) {
1416 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1417 priv->isr_stats.unhandled++;
1418 }
1419
40cefda9 1420 if (inta & ~(priv->inta_mask)) {
ef850d7c 1421 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1422 inta & ~priv->inta_mask);
ef850d7c
MA		 1423 }
1424
ef850d7c
MA		 1425 /* Re-enable all interrupts */
1426 /* only Re-enable if diabled by irq */
1427 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1428 iwl_enable_interrupts(priv);
ef850d7c
MA		 1429}
1430
872c8ddc
WYG		 1431/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1432#define ACK_CNT_RATIO (50)
1433#define BA_TIMEOUT_CNT (5)
1434#define BA_TIMEOUT_MAX (16)
1435
1436/**
1437 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1438 *
1439 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1440 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1441 * operation state.
1442 */
1443bool iwl_good_ack_health(struct iwl_priv *priv,
1444 struct iwl_rx_packet *pkt)
1445{
1446 bool rc = true;
1447 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1448 int ba_timeout_delta;
1449
1450 actual_ack_cnt_delta =
1451 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1452 le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
1453 expected_ack_cnt_delta =
1454 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1455 le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
1456 ba_timeout_delta =
1457 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1458 le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
1459 if ((priv->_agn.agg_tids_count > 0) &&
1460 (expected_ack_cnt_delta > 0) &&
1461 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1462 < ACK_CNT_RATIO) &&
1463 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1464 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1465 " expected_ack_cnt = %d\n",
1466 actual_ack_cnt_delta, expected_ack_cnt_delta);
1467
1468#ifdef CONFIG_IWLWIFI_DEBUG
1469 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1470 priv->delta_statistics.tx.rx_detected_cnt);
1471 IWL_DEBUG_RADIO(priv,
1472 "ack_or_ba_timeout_collision delta = %d\n",
1473 priv->delta_statistics.tx.
1474 ack_or_ba_timeout_collision);
1475#endif
1476 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1477 ba_timeout_delta);
1478 if (!actual_ack_cnt_delta &&
1479 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1480 rc = false;
1481 }
1482 return rc;
1483}
1484
a83b9141 1485
b481de9c
ZY		 1486/******************************************************************************
1487 *
1488 * uCode download functions
1489 *
1490 ******************************************************************************/
1491
5b9f8cd3 1492static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1493{
98c92211
TW		 1494 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1495 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1496 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1497 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1498 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1499 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1500}
1501
5b9f8cd3 1502static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1503{
1504 /* Remove all resets to allow NIC to operate */
1505 iwl_write32(priv, CSR_RESET, 0);
1506}
1507
dd7a2509
JB		 1508struct iwlagn_ucode_capabilities {
1509 u32 max_probe_length;
1510};
edcdf8b2 1511
b08dfd04 1512static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1513static int iwl_mac_setup_register(struct iwl_priv *priv,
1514 struct iwlagn_ucode_capabilities *capa);
b08dfd04
JB		 1515
1516static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1517{
1518 const char *name_pre = priv->cfg->fw_name_pre;
1519
1520 if (first)
1521 priv->fw_index = priv->cfg->ucode_api_max;
1522 else
1523 priv->fw_index--;
1524
1525 if (priv->fw_index < priv->cfg->ucode_api_min) {
1526 IWL_ERR(priv, "no suitable firmware found!\n");
1527 return -ENOENT;
1528 }
1529
1530 sprintf(priv->firmware_name, "%s%d%s",
1531 name_pre, priv->fw_index, ".ucode");
1532
1533 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1534 priv->firmware_name);
1535
1536 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1537 &priv->pci_dev->dev, GFP_KERNEL, priv,
1538 iwl_ucode_callback);
1539}
1540
0e9a44dc
JB		 1541struct iwlagn_firmware_pieces {
1542 const void *inst, *data, *init, *init_data, *boot;
1543 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1544
1545 u32 build;
1546};
1547
1548static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1549 const struct firmware *ucode_raw,
1550 struct iwlagn_firmware_pieces *pieces)
1551{
1552 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1553 u32 api_ver, hdr_size;
1554 const u8 *src;
1555
1556 priv->ucode_ver = le32_to_cpu(ucode->ver);
1557 api_ver = IWL_UCODE_API(priv->ucode_ver);
1558
1559 switch (api_ver) {
1560 default:
1561 /*
1562 * 4965 doesn't revision the firmware file format
1563 * along with the API version, it always uses v1
1564 * file format.
1565 */
1566 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1567 CSR_HW_REV_TYPE_4965) {
1568 hdr_size = 28;
1569 if (ucode_raw->size < hdr_size) {
1570 IWL_ERR(priv, "File size too small!\n");
1571 return -EINVAL;
1572 }
1573 pieces->build = le32_to_cpu(ucode->u.v2.build);
1574 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1575 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1576 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1577 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1578 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1579 src = ucode->u.v2.data;
1580 break;
1581 }
1582 /* fall through for 4965 */
1583 case 0:
1584 case 1:
1585 case 2:
1586 hdr_size = 24;
1587 if (ucode_raw->size < hdr_size) {
1588 IWL_ERR(priv, "File size too small!\n");
1589 return -EINVAL;
1590 }
1591 pieces->build = 0;
1592 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1593 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1594 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1595 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1596 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1597 src = ucode->u.v1.data;
1598 break;
1599 }
1600
1601 /* Verify size of file vs. image size info in file's header */
1602 if (ucode_raw->size != hdr_size + pieces->inst_size +
1603 pieces->data_size + pieces->init_size +
1604 pieces->init_data_size + pieces->boot_size) {
1605
1606 IWL_ERR(priv,
1607 "uCode file size %d does not match expected size\n",
1608 (int)ucode_raw->size);
1609 return -EINVAL;
1610 }
1611
1612 pieces->inst = src;
1613 src += pieces->inst_size;
1614 pieces->data = src;
1615 src += pieces->data_size;
1616 pieces->init = src;
1617 src += pieces->init_size;
1618 pieces->init_data = src;
1619 src += pieces->init_data_size;
1620 pieces->boot = src;
1621 src += pieces->boot_size;
1622
1623 return 0;
1624}
1625
dd7a2509
JB		 1626static int iwlagn_wanted_ucode_alternative = 1;
1627
1628static int iwlagn_load_firmware(struct iwl_priv *priv,
1629 const struct firmware *ucode_raw,
1630 struct iwlagn_firmware_pieces *pieces,
1631 struct iwlagn_ucode_capabilities *capa)
1632{
1633 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1634 struct iwl_ucode_tlv *tlv;
1635 size_t len = ucode_raw->size;
1636 const u8 *data;
1637 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1638 u64 alternatives;
1639
1640 if (len < sizeof(*ucode))
1641 return -EINVAL;
1642
1643 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC))
1644 return -EINVAL;
1645
1646 /*
1647 * Check which alternatives are present, and "downgrade"
1648 * when the chosen alternative is not present, warning
1649 * the user when that happens. Some files may not have
1650 * any alternatives, so don't warn in that case.
1651 */
1652 alternatives = le64_to_cpu(ucode->alternatives);
1653 tmp = wanted_alternative;
1654 if (wanted_alternative > 63)
1655 wanted_alternative = 63;
1656 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1657 wanted_alternative--;
1658 if (wanted_alternative && wanted_alternative != tmp)
1659 IWL_WARN(priv,
1660 "uCode alternative %d not available, choosing %d\n",
1661 tmp, wanted_alternative);
1662
1663 priv->ucode_ver = le32_to_cpu(ucode->ver);
1664 pieces->build = le32_to_cpu(ucode->build);
1665 data = ucode->data;
1666
1667 len -= sizeof(*ucode);
1668
1669 while (len >= sizeof(*tlv)) {
1670 u32 tlv_len;
1671 enum iwl_ucode_tlv_type tlv_type;
1672 u16 tlv_alt;
1673 const u8 *tlv_data;
1674
1675 len -= sizeof(*tlv);
1676 tlv = (void *)data;
1677
1678 tlv_len = le32_to_cpu(tlv->length);
1679 tlv_type = le16_to_cpu(tlv->type);
1680 tlv_alt = le16_to_cpu(tlv->alternative);
1681 tlv_data = tlv->data;
1682
1683 if (len < tlv_len)
1684 return -EINVAL;
1685 len -= ALIGN(tlv_len, 4);
1686 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1687
1688 /*
1689 * Alternative 0 is always valid.
1690 *
1691 * Skip alternative TLVs that are not selected.
1692 */
1693 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1694 continue;
1695
1696 switch (tlv_type) {
1697 case IWL_UCODE_TLV_INST:
1698 pieces->inst = tlv_data;
1699 pieces->inst_size = tlv_len;
1700 break;
1701 case IWL_UCODE_TLV_DATA:
1702 pieces->data = tlv_data;
1703 pieces->data_size = tlv_len;
1704 break;
1705 case IWL_UCODE_TLV_INIT:
1706 pieces->init = tlv_data;
1707 pieces->init_size = tlv_len;
1708 break;
1709 case IWL_UCODE_TLV_INIT_DATA:
1710 pieces->init_data = tlv_data;
1711 pieces->init_data_size = tlv_len;
1712 break;
1713 case IWL_UCODE_TLV_BOOT:
1714 pieces->boot = tlv_data;
1715 pieces->boot_size = tlv_len;
1716 break;
1717 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1718 if (tlv_len != 4)
1719 return -EINVAL;
1720 capa->max_probe_length =
1721 le32_to_cpup((__le32 *)tlv_data);
1722 break;
1723 default:
1724 break;
1725 }
1726 }
1727
1728 if (len)
1729 return -EINVAL;
1730
1731 return 0;
1732}
1733
b481de9c 1734/**
b08dfd04 1735 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1736 *
b08dfd04
JB		 1737 * If loaded successfully, copies the firmware into buffers
1738 * for the card to fetch (via DMA).
b481de9c 1739 */
b08dfd04 1740static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1741{
b08dfd04 1742 struct iwl_priv *priv = context;
cc0f555d 1743 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 1744 int err;
1745 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 1746 const unsigned int api_max = priv->cfg->ucode_api_max;
1747 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 1748 u32 api_ver;
3e4de761 1749 char buildstr[25];
0e9a44dc 1750 u32 build;
dd7a2509
JB		 1751 struct iwlagn_ucode_capabilities ucode_capa = {
1752 .max_probe_length = 200,
1753 };
0e9a44dc
JB		 1754
1755 memset(&pieces, 0, sizeof(pieces));
b481de9c 1756
b08dfd04
JB		 1757 if (!ucode_raw) {
1758 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1759 priv->firmware_name);
1760 goto try_again;
b481de9c
ZY		 1761 }
1762
b08dfd04
JB		 1763 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1764 priv->firmware_name, ucode_raw->size);
b481de9c 1765
22adba2a
JB		 1766 /* Make sure that we got at least the API version number */
1767 if (ucode_raw->size < 4) {
15b1687c 1768 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1769 goto try_again;
b481de9c
ZY		 1770 }
1771
1772 /* Data from ucode file: header followed by uCode images */
cc0f555d 1773 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1774
0e9a44dc
JB		 1775 if (ucode->ver)
1776 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1777 else
dd7a2509
JB		 1778 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1779 &ucode_capa);
22adba2a 1780
0e9a44dc
JB		 1781 if (err)
1782 goto try_again;
b481de9c 1783
0e9a44dc
JB		 1784 api_ver = IWL_UCODE_API(priv->ucode_ver);
1785 build = pieces.build;
a0987a8d 1786
0e9a44dc
JB		 1787 /*
1788 * api_ver should match the api version forming part of the
1789 * firmware filename ... but we don't check for that and only rely
1790 * on the API version read from firmware header from here on forward
1791 */
a0987a8d 1792 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1793 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 1794 "Driver supports v%u, firmware is v%u.\n",
1795 api_max, api_ver);
b08dfd04 1796 goto try_again;
a0987a8d 1797 }
b08dfd04 1798
a0987a8d 1799 if (api_ver != api_max)
978785a3 1800 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 1801 "got v%u. New firmware can be obtained "
1802 "from http://www.intellinuxwireless.org.\n",
1803 api_max, api_ver);
1804
3e4de761
JB		 1805 if (build)
1806 sprintf(buildstr, " build %u", build);
1807 else
1808 buildstr[0] = '\0';
1809
1810 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1811 IWL_UCODE_MAJOR(priv->ucode_ver),
1812 IWL_UCODE_MINOR(priv->ucode_ver),
1813 IWL_UCODE_API(priv->ucode_ver),
1814 IWL_UCODE_SERIAL(priv->ucode_ver),
1815 buildstr);
a0987a8d 1816
5ebeb5a6
RC		 1817 snprintf(priv->hw->wiphy->fw_version,
1818 sizeof(priv->hw->wiphy->fw_version),
3e4de761 1819 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 1820 IWL_UCODE_MAJOR(priv->ucode_ver),
1821 IWL_UCODE_MINOR(priv->ucode_ver),
1822 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 1823 IWL_UCODE_SERIAL(priv->ucode_ver),
1824 buildstr);
cc0f555d 1825
b08dfd04
JB		 1826 /*
1827 * For any of the failures below (before allocating pci memory)
1828 * we will try to load a version with a smaller API -- maybe the
1829 * user just got a corrupted version of the latest API.
1830 */
1831
0e9a44dc
JB		 1832 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1833 priv->ucode_ver);
1834 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1835 pieces.inst_size);
1836 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1837 pieces.data_size);
1838 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1839 pieces.init_size);
1840 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1841 pieces.init_data_size);
1842 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1843 pieces.boot_size);
b481de9c
ZY		 1844
1845 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 1846 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1847 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1848 pieces.inst_size);
b08dfd04 1849 goto try_again;
b481de9c
ZY		 1850 }
1851
0e9a44dc
JB		 1852 if (pieces.data_size > priv->hw_params.max_data_size) {
1853 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1854 pieces.data_size);
b08dfd04 1855 goto try_again;
b481de9c 1856 }
0e9a44dc
JB		 1857
1858 if (pieces.init_size > priv->hw_params.max_inst_size) {
1859 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1860 pieces.init_size);
b08dfd04 1861 goto try_again;
b481de9c 1862 }
0e9a44dc
JB		 1863
1864 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1865 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1866 pieces.init_data_size);
b08dfd04 1867 goto try_again;
b481de9c 1868 }
0e9a44dc
JB		 1869
1870 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1871 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1872 pieces.boot_size);
b08dfd04 1873 goto try_again;
b481de9c
ZY		 1874 }
1875
1876 /* Allocate ucode buffers for card's bus-master loading ... */
1877
1878 /* Runtime instructions and 2 copies of data:
1879 * 1) unmodified from disk
1880 * 2) backup cache for save/restore during power-downs */
0e9a44dc 1881 priv->ucode_code.len = pieces.inst_size;
98c92211 1882 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 1883
0e9a44dc 1884 priv->ucode_data.len = pieces.data_size;
98c92211 1885 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 1886
0e9a44dc 1887 priv->ucode_data_backup.len = pieces.data_size;
98c92211 1888 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1889
1f304e4e
ZY		 1890 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1891 !priv->ucode_data_backup.v_addr)
1892 goto err_pci_alloc;
1893
b481de9c 1894 /* Initialization instructions and data */
0e9a44dc
JB		 1895 if (pieces.init_size && pieces.init_data_size) {
1896 priv->ucode_init.len = pieces.init_size;
98c92211 1897 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 1898
0e9a44dc 1899 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 1900 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 1901
1902 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1903 goto err_pci_alloc;
1904 }
b481de9c
ZY		 1905
1906 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 1907 if (pieces.boot_size) {
1908 priv->ucode_boot.len = pieces.boot_size;
98c92211 1909 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1910
90e759d1
TW		 1911 if (!priv->ucode_boot.v_addr)
1912 goto err_pci_alloc;
1913 }
b481de9c
ZY		 1914
1915 /* Copy images into buffers for card's bus-master reads ... */
1916
1917 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 1918 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1919 pieces.inst_size);
1920 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 1921
e1623446 1922 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 1923 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1924
0e9a44dc
JB		 1925 /*
1926 * Runtime data
1927 * NOTE: Copy into backup buffer will be done in iwl_up()
1928 */
1929 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1930 pieces.data_size);
1931 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1932 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1933
1934 /* Initialization instructions */
1935 if (pieces.init_size) {
e1623446 1936 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 1937 pieces.init_size);
1938 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 1939 }
1940
0e9a44dc
JB		 1941 /* Initialization data */
1942 if (pieces.init_data_size) {
e1623446 1943 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 1944 pieces.init_data_size);
1945 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1946 pieces.init_data_size);
b481de9c
ZY		 1947 }
1948
0e9a44dc
JB		 1949 /* Bootstrap instructions */
1950 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1951 pieces.boot_size);
1952 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 1953
b08dfd04
JB		 1954 /**************************************************
1955 * This is still part of probe() in a sense...
1956 *
1957 * 9. Setup and register with mac80211 and debugfs
1958 **************************************************/
dd7a2509 1959 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 1960 if (err)
1961 goto out_unbind;
1962
1963 err = iwl_dbgfs_register(priv, DRV_NAME);
1964 if (err)
1965 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1966
b481de9c
ZY		 1967 /* We have our copies now, allow OS release its copies */
1968 release_firmware(ucode_raw);
a15707d8 1969 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 1970 return;
1971
1972 try_again:
1973 /* try next, if any */
1974 if (iwl_request_firmware(priv, false))
1975 goto out_unbind;
1976 release_firmware(ucode_raw);
1977 return;
b481de9c
ZY		 1978
1979 err_pci_alloc:
15b1687c 1980 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 1981 iwl_dealloc_ucode_pci(priv);
b08dfd04 1982 out_unbind:
a15707d8 1983 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 1984 device_release_driver(&priv->pci_dev->dev);
b481de9c 1985 release_firmware(ucode_raw);
b481de9c
ZY		 1986}
1987
b7a79404
RC		 1988static const char *desc_lookup_text[] = {
1989 "OK",
1990 "FAIL",
1991 "BAD_PARAM",
1992 "BAD_CHECKSUM",
1993 "NMI_INTERRUPT_WDG",
1994 "SYSASSERT",
1995 "FATAL_ERROR",
1996 "BAD_COMMAND",
1997 "HW_ERROR_TUNE_LOCK",
1998 "HW_ERROR_TEMPERATURE",
1999 "ILLEGAL_CHAN_FREQ",
2000 "VCC_NOT_STABLE",
2001 "FH_ERROR",
2002 "NMI_INTERRUPT_HOST",
2003 "NMI_INTERRUPT_ACTION_PT",
2004 "NMI_INTERRUPT_UNKNOWN",
2005 "UCODE_VERSION_MISMATCH",
2006 "HW_ERROR_ABS_LOCK",
2007 "HW_ERROR_CAL_LOCK_FAIL",
2008 "NMI_INTERRUPT_INST_ACTION_PT",
2009 "NMI_INTERRUPT_DATA_ACTION_PT",
2010 "NMI_TRM_HW_ER",
2011 "NMI_INTERRUPT_TRM",
2012 "NMI_INTERRUPT_BREAK_POINT"
2013 "DEBUG_0",
2014 "DEBUG_1",
2015 "DEBUG_2",
2016 "DEBUG_3",
a7fce6ee 2017 "ADVANCED SYSASSERT"
b7a79404
RC		 2018};
2019
2020static const char *desc_lookup(int i)
2021{
2022 int max = ARRAY_SIZE(desc_lookup_text) - 1;
2023
2024 if (i < 0 || i > max)
2025 i = max;
2026
2027 return desc_lookup_text[i];
2028}
2029
2030#define ERROR_START_OFFSET (1 * sizeof(u32))
2031#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2032
2033void iwl_dump_nic_error_log(struct iwl_priv *priv)
2034{
2035 u32 data2, line;
2036 u32 desc, time, count, base, data1;
2037 u32 blink1, blink2, ilink1, ilink2;
461ef382 2038 u32 pc, hcmd;
b7a79404
RC		 2039
2040 if (priv->ucode_type == UCODE_INIT)
2041 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2042 else
2043 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2044
2045 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2046 IWL_ERR(priv,
2047 "Not valid error log pointer 0x%08X for %s uCode\n",
2048 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2049 return;
2050 }
2051
2052 count = iwl_read_targ_mem(priv, base);
2053
2054 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2055 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2056 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2057 priv->status, count);
2058 }
2059
2060 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 2061 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2062 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2063 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2064 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2065 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2066 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2067 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2068 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2069 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2070 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2071
be1a71a1
JB		 2072 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2073 blink1, blink2, ilink1, ilink2);
2074
b7a79404
RC		 2075 IWL_ERR(priv, "Desc Time "
2076 "data1 data2 line\n");
2077 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
2078 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2079 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2080 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2081 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2082}
2083
2084#define EVENT_START_OFFSET (4 * sizeof(u32))
2085
2086/**
2087 * iwl_print_event_log - Dump error event log to syslog
2088 *
2089 */
b03d7d0f
WYG		 2090static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2091 u32 num_events, u32 mode,
2092 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2093{
2094 u32 i;
2095 u32 base; /* SRAM byte address of event log header */
2096 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2097 u32 ptr; /* SRAM byte address of log data */
2098 u32 ev, time, data; /* event log data */
e5854471 2099 unsigned long reg_flags;
b7a79404
RC		 2100
2101 if (num_events == 0)
b03d7d0f 2102 return pos;
b7a79404
RC		 2103 if (priv->ucode_type == UCODE_INIT)
2104 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2105 else
2106 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2107
2108 if (mode == 0)
2109 event_size = 2 * sizeof(u32);
2110 else
2111 event_size = 3 * sizeof(u32);
2112
2113 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2114
e5854471
BC		 2115 /* Make sure device is powered up for SRAM reads */
2116 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2117 iwl_grab_nic_access(priv);
2118
2119 /* Set starting address; reads will auto-increment */
2120 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2121 rmb();
2122
b7a79404
RC		 2123 /* "time" is actually "data" for mode 0 (no timestamp).
2124 * place event id # at far right for easier visual parsing. */
2125 for (i = 0; i < num_events; i++) {
e5854471
BC		 2126 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2127 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2128 if (mode == 0) {
2129 /* data, ev */
b03d7d0f
WYG		 2130 if (bufsz) {
2131 pos += scnprintf(*buf + pos, bufsz - pos,
2132 "EVT_LOG:0x%08x:%04u\n",
2133 time, ev);
2134 } else {
2135 trace_iwlwifi_dev_ucode_event(priv, 0,
2136 time, ev);
2137 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2138 time, ev);
2139 }
b7a79404 2140 } else {
e5854471 2141 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2142 if (bufsz) {
2143 pos += scnprintf(*buf + pos, bufsz - pos,
2144 "EVT_LOGT:%010u:0x%08x:%04u\n",
2145 time, data, ev);
2146 } else {
2147 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2148 time, data, ev);
b03d7d0f
WYG		 2149 trace_iwlwifi_dev_ucode_event(priv, time,
2150 data, ev);
2151 }
b7a79404
RC		 2152 }
2153 }
e5854471
BC		 2154
2155 /* Allow device to power down */
2156 iwl_release_nic_access(priv);
2157 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2158 return pos;
b7a79404
RC		 2159}
2160
c341ddb2
WYG		 2161/**
2162 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2163 */
b03d7d0f
WYG		 2164static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2165 u32 num_wraps, u32 next_entry,
2166 u32 size, u32 mode,
2167 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2168{
2169 /*
2170 * display the newest DEFAULT_LOG_ENTRIES entries
2171 * i.e the entries just before the next ont that uCode would fill.
2172 */
2173 if (num_wraps) {
2174 if (next_entry < size) {
b03d7d0f
WYG		 2175 pos = iwl_print_event_log(priv,
2176 capacity - (size - next_entry),
2177 size - next_entry, mode,
2178 pos, buf, bufsz);
2179 pos = iwl_print_event_log(priv, 0,
2180 next_entry, mode,
2181 pos, buf, bufsz);
c341ddb2 2182 } else
b03d7d0f
WYG		 2183 pos = iwl_print_event_log(priv, next_entry - size,
2184 size, mode, pos, buf, bufsz);
c341ddb2 2185 } else {
b03d7d0f
WYG		 2186 if (next_entry < size) {
2187 pos = iwl_print_event_log(priv, 0, next_entry,
2188 mode, pos, buf, bufsz);
2189 } else {
2190 pos = iwl_print_event_log(priv, next_entry - size,
2191 size, mode, pos, buf, bufsz);
2192 }
c341ddb2 2193 }
b03d7d0f 2194 return pos;
c341ddb2
WYG		 2195}
2196
c341ddb2
WYG		 2197#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2198
b03d7d0f
WYG		 2199int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2200 char **buf, bool display)
b7a79404
RC		 2201{
2202 u32 base; /* SRAM byte address of event log header */
2203 u32 capacity; /* event log capacity in # entries */
2204 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2205 u32 num_wraps; /* # times uCode wrapped to top of log */
2206 u32 next_entry; /* index of next entry to be written by uCode */
2207 u32 size; /* # entries that we'll print */
b03d7d0f
WYG		 2208 int pos = 0;
2209 size_t bufsz = 0;
b7a79404
RC		 2210
2211 if (priv->ucode_type == UCODE_INIT)
2212 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2213 else
2214 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2215
2216 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2217 IWL_ERR(priv,
2218 "Invalid event log pointer 0x%08X for %s uCode\n",
2219 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2220 return -EINVAL;
b7a79404
RC		 2221 }
2222
2223 /* event log header */
2224 capacity = iwl_read_targ_mem(priv, base);
2225 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2226 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2227 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2228
678b385d 2229 if (capacity > priv->cfg->max_event_log_size) {
84c40692 2230 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
678b385d
WYG		 2231 capacity, priv->cfg->max_event_log_size);
2232 capacity = priv->cfg->max_event_log_size;
84c40692
BC		 2233 }
2234
678b385d 2235 if (next_entry > priv->cfg->max_event_log_size) {
84c40692 2236 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
678b385d
WYG		 2237 next_entry, priv->cfg->max_event_log_size);
2238 next_entry = priv->cfg->max_event_log_size;
84c40692
BC		 2239 }
2240
b7a79404
RC		 2241 size = num_wraps ? capacity : next_entry;
2242
2243 /* bail out if nothing in log */
2244 if (size == 0) {
2245 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2246 return pos;
b7a79404
RC		 2247 }
2248
c341ddb2 2249#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2250 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2251 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2252 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2253#else
2254 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2255 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2256#endif
2257 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2258 size);
b7a79404 2259
c341ddb2 2260#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2261 if (display) {
2262 if (full_log)
2263 bufsz = capacity * 48;
2264 else
2265 bufsz = size * 48;
2266 *buf = kmalloc(bufsz, GFP_KERNEL);
2267 if (!*buf)
937c397e 2268 return -ENOMEM;
b03d7d0f 2269 }
c341ddb2
WYG		 2270 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2271 /*
2272 * if uCode has wrapped back to top of log,
2273 * start at the oldest entry,
2274 * i.e the next one that uCode would fill.
2275 */
2276 if (num_wraps)
b03d7d0f
WYG		 2277 pos = iwl_print_event_log(priv, next_entry,
2278 capacity - next_entry, mode,
2279 pos, buf, bufsz);
c341ddb2 2280 /* (then/else) start at top of log */
b03d7d0f
WYG		 2281 pos = iwl_print_event_log(priv, 0,
2282 next_entry, mode, pos, buf, bufsz);
c341ddb2 2283 } else
b03d7d0f
WYG		 2284 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2285 next_entry, size, mode,
2286 pos, buf, bufsz);
c341ddb2 2287#else
b03d7d0f
WYG		 2288 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2289 next_entry, size, mode,
2290 pos, buf, bufsz);
b7a79404 2291#endif
b03d7d0f 2292 return pos;
c341ddb2 2293}
b7a79404 2294
b481de9c 2295/**
4a4a9e81 2296 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2297 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2298 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2299 */
4a4a9e81 2300static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2301{
57aab75a 2302 int ret = 0;
b481de9c 2303
e1623446 2304 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2305
2306 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2307 /* We had an error bringing up the hardware, so take it
2308 * all the way back down so we can try again */
e1623446 2309 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2310 goto restart;
2311 }
2312
2313 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2314 * This is a paranoid check, because we would not have gotten the
2315 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2316 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2317 /* Runtime instruction load was bad;
2318 * take it all the way back down so we can try again */
e1623446 2319 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2320 goto restart;
2321 }
2322
57aab75a
TW		 2323 ret = priv->cfg->ops->lib->alive_notify(priv);
2324 if (ret) {
39aadf8c
WT		 2325 IWL_WARN(priv,
2326 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2327 goto restart;
2328 }
2329
5b9f8cd3 2330 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2331 set_bit(STATUS_ALIVE, &priv->status);
2332
b74e31a9
WYG		 2333 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2334 /* Enable timer to monitor the driver queues */
2335 mod_timer(&priv->monitor_recover,
2336 jiffies +
2337 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2338 }
2339
fee1247a 2340 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2341 return;
2342
36d6825b 2343 ieee80211_wake_queues(priv->hw);
b481de9c 2344
470ab2dd 2345 priv->active_rate = IWL_RATES_MASK;
b481de9c 2346
2f748dec
WYG		 2347 /* Configure Tx antenna selection based on H/W config */
2348 if (priv->cfg->ops->hcmd->set_tx_ant)
2349 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2350
3109ece1 2351 if (iwl_is_associated(priv)) {
c1adf9fb
GG		 2352 struct iwl_rxon_cmd *active_rxon =
2353 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA		 2354 /* apply any changes in staging */
2355 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2356 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2357 } else {
2358 /* Initialize our rx_config data */
1dda6d28 2359 iwl_connection_init_rx_config(priv, NULL);
45823531
AK		 2360
2361 if (priv->cfg->ops->hcmd->set_rxon_chain)
2362 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2363
b481de9c
ZY		 2364 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2365 }
2366
9fbab516 2367 /* Configure Bluetooth device coexistence support */
65b52bde 2368 priv->cfg->ops->hcmd->send_bt_config(priv);
b481de9c 2369
4a4a9e81
TW		 2370 iwl_reset_run_time_calib(priv);
2371
b481de9c 2372 /* Configure the adapter for unassociated operation */
e0158e61 2373 iwlcore_commit_rxon(priv);
b481de9c
ZY		 2374
2375 /* At this point, the NIC is initialized and operational */
47f4a587 2376 iwl_rf_kill_ct_config(priv);
5a66926a 2377
e932a609 2378 iwl_leds_init(priv);
fe00b5a5 2379
e1623446 2380 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2381 set_bit(STATUS_READY, &priv->status);
5a66926a 2382 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2383
e312c24c 2384 iwl_power_update_mode(priv, true);
7e246191
RC		 2385 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2386
c46fbefa 2387
b481de9c
ZY		 2388 return;
2389
2390 restart:
2391 queue_work(priv->workqueue, &priv->restart);
2392}
2393
4e39317d 2394static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2395
5b9f8cd3 2396static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2397{
2398 unsigned long flags;
2399 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2400
e1623446 2401 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2402
b481de9c
ZY		 2403 if (!exit_pending)
2404 set_bit(STATUS_EXIT_PENDING, &priv->status);
2405
2c810ccd
JB		 2406 iwl_clear_ucode_stations(priv);
2407 iwl_dealloc_bcast_station(priv);
b481de9c
ZY		 2408
2409 /* Unblock any waiting calls */
2410 wake_up_interruptible_all(&priv->wait_command_queue);
2411
b481de9c
ZY		 2412 /* Wipe out the EXIT_PENDING status bit if we are not actually
2413 * exiting the module */
2414 if (!exit_pending)
2415 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2416
2417 /* stop and reset the on-board processor */
3395f6e9 2418 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2419
2420 /* tell the device to stop sending interrupts */
0359facc 2421 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2422 iwl_disable_interrupts(priv);
0359facc
MA		 2423 spin_unlock_irqrestore(&priv->lock, flags);
2424 iwl_synchronize_irq(priv);
b481de9c
ZY		 2425
2426 if (priv->mac80211_registered)
2427 ieee80211_stop_queues(priv->hw);
2428
5b9f8cd3 2429 /* If we have not previously called iwl_init() then
a60e77e5 2430 * clear all bits but the RF Kill bit and return */
fee1247a 2431 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2432 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2433 STATUS_RF_KILL_HW |
9788864e
RC		 2434 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2435 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2436 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2437 STATUS_EXIT_PENDING;
b481de9c
ZY		 2438 goto exit;
2439 }
2440
6da3a13e 2441 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2442 * bit and continue taking the NIC down. */
b481de9c
ZY		 2443 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2444 STATUS_RF_KILL_HW |
9788864e
RC		 2445 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2446 STATUS_GEO_CONFIGURED |
b481de9c 2447 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2448 STATUS_FW_ERROR |
2449 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2450 STATUS_EXIT_PENDING;
b481de9c 2451
ef850d7c
MA		 2452 /* device going down, Stop using ICT table */
2453 iwl_disable_ict(priv);
b481de9c 2454
74bcdb33 2455 iwlagn_txq_ctx_stop(priv);
54b81550 2456 iwlagn_rxq_stop(priv);
b481de9c 2457
309e731a
BC		 2458 /* Power-down device's busmaster DMA clocks */
2459 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2460 udelay(5);
2461
309e731a
BC		 2462 /* Make sure (redundant) we've released our request to stay awake */
2463 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2464
4d2ccdb9
BC		 2465 /* Stop the device, and put it in low power state */
2466 priv->cfg->ops->lib->apm_ops.stop(priv);
2467
b481de9c 2468 exit:
885ba202 2469 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2470
2471 if (priv->ibss_beacon)
2472 dev_kfree_skb(priv->ibss_beacon);
2473 priv->ibss_beacon = NULL;
2474
2475 /* clear out any free frames */
fcab423d 2476 iwl_clear_free_frames(priv);
b481de9c
ZY		 2477}
2478
5b9f8cd3 2479static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2480{
2481 mutex_lock(&priv->mutex);
5b9f8cd3 2482 __iwl_down(priv);
b481de9c 2483 mutex_unlock(&priv->mutex);
b24d22b1 2484
4e39317d 2485 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2486}
2487
086ed117
MA		 2488#define HW_READY_TIMEOUT (50)
2489
2490static int iwl_set_hw_ready(struct iwl_priv *priv)
2491{
2492 int ret = 0;
2493
2494 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2495 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2496
2497 /* See if we got it */
2498 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2499 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2500 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2501 HW_READY_TIMEOUT);
2502 if (ret != -ETIMEDOUT)
2503 priv->hw_ready = true;
2504 else
2505 priv->hw_ready = false;
2506
2507 IWL_DEBUG_INFO(priv, "hardware %s\n",
2508 (priv->hw_ready == 1) ? "ready" : "not ready");
2509 return ret;
2510}
2511
2512static int iwl_prepare_card_hw(struct iwl_priv *priv)
2513{
2514 int ret = 0;
2515
91dd6c27 2516 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2517
3354a0f6
MA		 2518 ret = iwl_set_hw_ready(priv);
2519 if (priv->hw_ready)
2520 return ret;
2521
2522 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2523 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2524 CSR_HW_IF_CONFIG_REG_PREPARE);
2525
2526 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2527 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2528 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2529
3354a0f6 2530 /* HW should be ready by now, check again. */
086ed117
MA		 2531 if (ret != -ETIMEDOUT)
2532 iwl_set_hw_ready(priv);
2533
2534 return ret;
2535}
2536
b481de9c
ZY		 2537#define MAX_HW_RESTARTS 5
2538
5b9f8cd3 2539static int __iwl_up(struct iwl_priv *priv)
b481de9c 2540{
57aab75a
TW		 2541 int i;
2542 int ret;
b481de9c
ZY		 2543
2544 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2545 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2546 return -EIO;
2547 }
2548
e903fbd4 2549 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2550 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2551 return -EIO;
2552 }
2553
2c810ccd
JB		 2554 ret = iwl_alloc_bcast_station(priv, true);
2555 if (ret)
2556 return ret;
2557
086ed117
MA		 2558 iwl_prepare_card_hw(priv);
2559
2560 if (!priv->hw_ready) {
2561 IWL_WARN(priv, "Exit HW not ready\n");
2562 return -EIO;
2563 }
2564
e655b9f0 2565 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2566 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2567 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2568 else
e655b9f0 2569 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2570
c1842d61 2571 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 2572 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2573
5b9f8cd3 2574 iwl_enable_interrupts(priv);
a60e77e5 2575 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2576 return 0;
b481de9c
ZY		 2577 }
2578
3395f6e9 2579 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2580
74bcdb33 2581 ret = iwlagn_hw_nic_init(priv);
57aab75a 2582 if (ret) {
15b1687c 2583 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2584 return ret;
b481de9c
ZY		 2585 }
2586
2587 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2588 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2589 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 2590 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2591
2592 /* clear (again), then enable host interrupts */
3395f6e9 2593 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2594 iwl_enable_interrupts(priv);
b481de9c
ZY		 2595
2596 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2597 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2598 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2599
2600 /* Copy original ucode data image from disk into backup cache.
2601 * This will be used to initialize the on-board processor's
2602 * data SRAM for a clean start when the runtime program first loads. */
2603 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2604 priv->ucode_data.len);
b481de9c 2605
b481de9c
ZY		 2606 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2607
b481de9c
ZY		 2608 /* load bootstrap state machine,
2609 * load bootstrap program into processor's memory,
2610 * prepare to load the "initialize" uCode */
57aab75a 2611 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2612
57aab75a 2613 if (ret) {
15b1687c
WT		 2614 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2615 ret);
b481de9c
ZY		 2616 continue;
2617 }
2618
2619 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2620 iwl_nic_start(priv);
b481de9c 2621
e1623446 2622 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 2623
2624 return 0;
2625 }
2626
2627 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2628 __iwl_down(priv);
64e72c3e 2629 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 2630
2631 /* tried to restart and config the device for as long as our
2632 * patience could withstand */
15b1687c 2633 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 2634 return -EIO;
2635}
2636
2637
2638/*****************************************************************************
2639 *
2640 * Workqueue callbacks
2641 *
2642 *****************************************************************************/
2643
4a4a9e81 2644static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2645{
c79dd5b5
TW		 2646 struct iwl_priv *priv =
2647 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 2648
2649 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2650 return;
2651
2652 mutex_lock(&priv->mutex);
f3ccc08c 2653 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 2654 mutex_unlock(&priv->mutex);
2655}
2656
4a4a9e81 2657static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2658{
c79dd5b5
TW		 2659 struct iwl_priv *priv =
2660 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 2661
2662 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2663 return;
2664
258c44a0
MA		 2665 /* enable dram interrupt */
2666 iwl_reset_ict(priv);
2667
b481de9c 2668 mutex_lock(&priv->mutex);
4a4a9e81 2669 iwl_alive_start(priv);
b481de9c
ZY		 2670 mutex_unlock(&priv->mutex);
2671}
2672
16e727e8
EG		 2673static void iwl_bg_run_time_calib_work(struct work_struct *work)
2674{
2675 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2676 run_time_calib_work);
2677
2678 mutex_lock(&priv->mutex);
2679
2680 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2681 test_bit(STATUS_SCANNING, &priv->status)) {
2682 mutex_unlock(&priv->mutex);
2683 return;
2684 }
2685
2686 if (priv->start_calib) {
2687 iwl_chain_noise_calibration(priv, &priv->statistics);
2688
2689 iwl_sensitivity_calibration(priv, &priv->statistics);
2690 }
2691
2692 mutex_unlock(&priv->mutex);
2693 return;
2694}
2695
5b9f8cd3 2696static void iwl_bg_restart(struct work_struct *data)
b481de9c 2697{
c79dd5b5 2698 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 2699
2700 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2701 return;
2702
19cc1087
JB		 2703 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2704 mutex_lock(&priv->mutex);
2705 priv->vif = NULL;
2706 priv->is_open = 0;
2707 mutex_unlock(&priv->mutex);
2708 iwl_down(priv);
2709 ieee80211_restart_hw(priv->hw);
2710 } else {
2711 iwl_down(priv);
80676518
JB		 2712
2713 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2714 return;
2715
2716 mutex_lock(&priv->mutex);
2717 __iwl_up(priv);
2718 mutex_unlock(&priv->mutex);
19cc1087 2719 }
b481de9c
ZY		 2720}
2721
5b9f8cd3 2722static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2723{
c79dd5b5
TW		 2724 struct iwl_priv *priv =
2725 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 2726
2727 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2728 return;
2729
2730 mutex_lock(&priv->mutex);
54b81550 2731 iwlagn_rx_replenish(priv);
b481de9c
ZY		 2732 mutex_unlock(&priv->mutex);
2733}
2734
7878a5a4
MA		 2735#define IWL_DELAY_NEXT_SCAN (HZ*2)
2736
1dda6d28 2737void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 2738{
b481de9c 2739 struct ieee80211_conf *conf = NULL;
857485c0 2740 int ret = 0;
b481de9c 2741
1dda6d28
JB		 2742 if (!vif || !priv->is_open)
2743 return;
2744
2745 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 2746 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 2747 return;
2748 }
2749
b481de9c
ZY		 2750 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2751 return;
2752
2a421b91 2753 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2754
b481de9c
ZY		 2755 conf = ieee80211_get_hw_conf(priv->hw);
2756
2757 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2758 iwlcore_commit_rxon(priv);
b481de9c 2759
1dda6d28 2760 iwl_setup_rxon_timing(priv, vif);
857485c0 2761 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2762 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2763 if (ret)
39aadf8c 2764 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 2765 "Attempting to continue.\n");
2766
2767 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2768
42eb7c64 2769 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2770
45823531
AK		 2771 if (priv->cfg->ops->hcmd->set_rxon_chain)
2772 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2773
1dda6d28 2774 priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 2775
e1623446 2776 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 2777 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 2778
1dda6d28 2779 if (vif->bss_conf.assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
b481de9c
ZY		 2780 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2781 else
2782 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2783
2784 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
1dda6d28
JB		 2785 if (vif->bss_conf.assoc_capability &
2786 WLAN_CAPABILITY_SHORT_SLOT_TIME)
b481de9c
ZY		 2787 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2788 else
2789 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2790
1dda6d28 2791 if (vif->type == NL80211_IFTYPE_ADHOC)
b481de9c 2792 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 2793 }
2794
e0158e61 2795 iwlcore_commit_rxon(priv);
b481de9c 2796
fe6b23dd 2797 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
1dda6d28 2798 vif->bss_conf.aid, priv->active_rxon.bssid_addr);
fe6b23dd 2799
1dda6d28 2800 switch (vif->type) {
05c914fe 2801 case NL80211_IFTYPE_STATION:
b481de9c 2802 break;
05c914fe 2803 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 2804 iwl_send_beacon_cmd(priv);
b481de9c 2805 break;
b481de9c 2806 default:
15b1687c 2807 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 2808 __func__, vif->type);
b481de9c
ZY		 2809 break;
2810 }
2811
04816448
GE		 2812 /* the chain noise calibration will enabled PM upon completion
2813 * If chain noise has already been run, then we need to enable
2814 * power management here */
2815 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2816 iwl_power_update_mode(priv, false);
c90a74ba
EG		 2817
2818 /* Enable Rx differential gain and sensitivity calibrations */
2819 iwl_chain_noise_reset(priv);
2820 priv->start_calib = 1;
2821
508e32e1
RC		 2822}
2823
b481de9c
ZY		 2824/*****************************************************************************
2825 *
2826 * mac80211 entry point functions
2827 *
2828 *****************************************************************************/
2829
154b25ce 2830#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2831
f0b6e2e8
RC		 2832/*
2833 * Not a mac80211 entry point function, but it fits in with all the
2834 * other mac80211 functions grouped here.
2835 */
dd7a2509
JB		 2836static int iwl_mac_setup_register(struct iwl_priv *priv,
2837 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 2838{
2839 int ret;
2840 struct ieee80211_hw *hw = priv->hw;
2841 hw->rate_control_algorithm = "iwl-agn-rs";
2842
2843 /* Tell mac80211 our characteristics */
2844 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8
RC		 2845 IEEE80211_HW_AMPDU_AGGREGATION |
2846 IEEE80211_HW_SPECTRUM_MGMT;
2847
2848 if (!priv->cfg->broken_powersave)
2849 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2850 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2851
ba37a3d0
JB		 2852 if (priv->cfg->sku & IWL_SKU_N)
2853 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2854 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2855
8d9698b3 2856 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 2857 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2858
f0b6e2e8
RC		 2859 hw->wiphy->interface_modes =
2860 BIT(NL80211_IFTYPE_STATION) |
2861 BIT(NL80211_IFTYPE_ADHOC);
2862
f6c8f152 2863 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 2864 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 2865
2866 /*
2867 * For now, disable PS by default because it affects
2868 * RX performance significantly.
2869 */
5be83de5 2870 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 2871
1382c71c 2872 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 2873 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 2874 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 2875
2876 /* Default value; 4 EDCA QOS priorities */
2877 hw->queues = 4;
2878
2879 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2880
2881 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2882 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2883 &priv->bands[IEEE80211_BAND_2GHZ];
2884 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2885 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2886 &priv->bands[IEEE80211_BAND_5GHZ];
2887
2888 ret = ieee80211_register_hw(priv->hw);
2889 if (ret) {
2890 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2891 return ret;
2892 }
2893 priv->mac80211_registered = 1;
2894
2895 return 0;
2896}
2897
2898
5b9f8cd3 2899static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2900{
c79dd5b5 2901 struct iwl_priv *priv = hw->priv;
5a66926a 2902 int ret;
b481de9c 2903
e1623446 2904 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 2905
2906 /* we should be verifying the device is ready to be opened */
2907 mutex_lock(&priv->mutex);
5b9f8cd3 2908 ret = __iwl_up(priv);
b481de9c 2909 mutex_unlock(&priv->mutex);
5a66926a 2910
e655b9f0 2911 if (ret)
6cd0b1cb 2912 return ret;
e655b9f0 2913
c1842d61
TW		 2914 if (iwl_is_rfkill(priv))
2915 goto out;
2916
e1623446 2917 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2918
fe9b6b72 2919 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2920 * mac80211 will not be run successfully. */
154b25ce
EG		 2921 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2922 test_bit(STATUS_READY, &priv->status),
2923 UCODE_READY_TIMEOUT);
2924 if (!ret) {
2925 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2926 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2927 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2928 return -ETIMEDOUT;
5a66926a 2929 }
fe9b6b72 2930 }
0a078ffa 2931
e932a609
JB		 2932 iwl_led_start(priv);
2933
c1842d61 2934out:
0a078ffa 2935 priv->is_open = 1;
e1623446 2936 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2937 return 0;
2938}
2939
5b9f8cd3 2940static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2941{
c79dd5b5 2942 struct iwl_priv *priv = hw->priv;
b481de9c 2943
e1623446 2944 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2945
19cc1087 2946 if (!priv->is_open)
e655b9f0 2947 return;
e655b9f0 2948
b481de9c 2949 priv->is_open = 0;
5a66926a 2950
5bddf549 2951 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY		 2952 /* stop mac, cancel any scan request and clear
2953 * RXON_FILTER_ASSOC_MSK BIT
2954 */
5a66926a 2955 mutex_lock(&priv->mutex);
2a421b91 2956 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2957 mutex_unlock(&priv->mutex);
fde3571f
MA		 2958 }
2959
5b9f8cd3 2960 iwl_down(priv);
5a66926a
ZY		 2961
2962 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 2963
2964 /* enable interrupts again in order to receive rfkill changes */
2965 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2966 iwl_enable_interrupts(priv);
948c171c 2967
e1623446 2968 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2969}
2970
5b9f8cd3 2971static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2972{
c79dd5b5 2973 struct iwl_priv *priv = hw->priv;
b481de9c 2974
e1623446 2975 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2976
e1623446 2977 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2978 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2979
74bcdb33 2980 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 2981 dev_kfree_skb_any(skb);
2982
e1623446 2983 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2984 return NETDEV_TX_OK;
b481de9c
ZY		 2985}
2986
1dda6d28 2987void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 2988{
857485c0 2989 int ret = 0;
b481de9c 2990
d986bcd1 2991 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 2992 return;
2993
2994 /* The following should be done only at AP bring up */
3195c1f3 2995 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 2996
2997 /* RXON - unassoc (to set timing command) */
2998 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2999 iwlcore_commit_rxon(priv);
b481de9c
ZY		 3000
3001 /* RXON Timing */
1dda6d28 3002 iwl_setup_rxon_timing(priv, vif);
857485c0 3003 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 3004 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 3005 if (ret)
39aadf8c 3006 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3007 "Attempting to continue.\n");
3008
f513dfff
DH		 3009 /* AP has all antennas */
3010 priv->chain_noise_data.active_chains =
3011 priv->hw_params.valid_rx_ant;
3012 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK		 3013 if (priv->cfg->ops->hcmd->set_rxon_chain)
3014 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c 3015
1dda6d28
JB		 3016 priv->staging_rxon.assoc_id = 0;
3017
3018 if (vif->bss_conf.assoc_capability &
3019 WLAN_CAPABILITY_SHORT_PREAMBLE)
b481de9c
ZY		 3020 priv->staging_rxon.flags |=
3021 RXON_FLG_SHORT_PREAMBLE_MSK;
3022 else
3023 priv->staging_rxon.flags &=
3024 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3025
3026 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
1dda6d28
JB		 3027 if (vif->bss_conf.assoc_capability &
3028 WLAN_CAPABILITY_SHORT_SLOT_TIME)
b481de9c
ZY		 3029 priv->staging_rxon.flags |=
3030 RXON_FLG_SHORT_SLOT_MSK;
3031 else
3032 priv->staging_rxon.flags &=
3033 ~RXON_FLG_SHORT_SLOT_MSK;
3034
1dda6d28 3035 if (vif->type == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 3036 priv->staging_rxon.flags &=
3037 ~RXON_FLG_SHORT_SLOT_MSK;
3038 }
3039 /* restore RXON assoc */
3040 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3041 iwlcore_commit_rxon(priv);
e1493deb 3042 }
5b9f8cd3 3043 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3044
3045 /* FIXME - we need to add code here to detect a totally new
3046 * configuration, reset the AP, unassoc, rxon timing, assoc,
3047 * clear sta table, add BCAST sta... */
3048}
3049
5b9f8cd3 3050static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3051 struct ieee80211_vif *vif,
3052 struct ieee80211_key_conf *keyconf,
3053 struct ieee80211_sta *sta,
3054 u32 iv32, u16 *phase1key)
ab885f8c 3055{
ab885f8c 3056
9f58671e 3057 struct iwl_priv *priv = hw->priv;
e1623446 3058 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3059
bdbb612f 3060 iwl_update_tkip_key(priv, keyconf, sta,
b3fbdcf4 3061 iv32, phase1key);
ab885f8c 3062
e1623446 3063 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3064}
3065
5b9f8cd3 3066static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3067 struct ieee80211_vif *vif,
3068 struct ieee80211_sta *sta,
b481de9c
ZY		 3069 struct ieee80211_key_conf *key)
3070{
c79dd5b5 3071 struct iwl_priv *priv = hw->priv;
42986796
WT		 3072 int ret;
3073 u8 sta_id;
3074 bool is_default_wep_key = false;
b481de9c 3075
e1623446 3076 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3077
90e8e424 3078 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3079 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3080 return -EOPNOTSUPP;
3081 }
b481de9c 3082
2a87c26b
JB		 3083 if (sta) {
3084 sta_id = iwl_sta_id(sta);
3085
3086 if (sta_id == IWL_INVALID_STATION) {
3087 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
3088 sta->addr);
3089 return -EINVAL;
3090 }
3091 } else {
3092 sta_id = priv->hw_params.bcast_sta_id;
deb09c43 3093 }
b481de9c 3094
6974e363 3095 mutex_lock(&priv->mutex);
2a421b91 3096 iwl_scan_cancel_timeout(priv, 100);
6974e363 3097
a90178fa
JB		 3098 /*
3099 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3100 * so far, we are in legacy wep mode (group key only), otherwise we are
3101 * in 1X mode.
a90178fa
JB		 3102 * In legacy wep mode, we use another host command to the uCode.
3103 */
3104 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
6974e363
EG		 3105 if (cmd == SET_KEY)
3106 is_default_wep_key = !priv->key_mapping_key;
3107 else
ccc038ab
EG		 3108 is_default_wep_key =
3109 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3110 }
052c4b9f 3111
b481de9c 3112 switch (cmd) {
deb09c43 3113 case SET_KEY:
6974e363
EG		 3114 if (is_default_wep_key)
3115 ret = iwl_set_default_wep_key(priv, key);
deb09c43 3116 else
7480513f 3117 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 3118
e1623446 3119 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3120 break;
3121 case DISABLE_KEY:
6974e363
EG		 3122 if (is_default_wep_key)
3123 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 3124 else
3ec47732 3125 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 3126
e1623446 3127 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3128 break;
3129 default:
deb09c43 3130 ret = -EINVAL;
b481de9c
ZY		 3131 }
3132
72e15d71 3133 mutex_unlock(&priv->mutex);
e1623446 3134 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3135
deb09c43 3136 return ret;
b481de9c
ZY		 3137}
3138
5b9f8cd3 3139static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3140 struct ieee80211_vif *vif,
832f47e3
JB		 3141 enum ieee80211_ampdu_mlme_action action,
3142 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3143{
3144 struct iwl_priv *priv = hw->priv;
5c2207c6 3145 int ret;
d783b061 3146
e1623446 3147 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3148 sta->addr, tid);
d783b061
TW		 3149
3150 if (!(priv->cfg->sku & IWL_SKU_N))
3151 return -EACCES;
3152
3153 switch (action) {
3154 case IEEE80211_AMPDU_RX_START:
e1623446 3155 IWL_DEBUG_HT(priv, "start Rx\n");
619753ff 3156 return iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
d783b061 3157 case IEEE80211_AMPDU_RX_STOP:
e1623446 3158 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3159 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6
WYG		 3160 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3161 return 0;
3162 else
3163 return ret;
d783b061 3164 case IEEE80211_AMPDU_TX_START:
e1623446 3165 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3166 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3167 if (ret == 0) {
3168 priv->_agn.agg_tids_count++;
3169 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3170 priv->_agn.agg_tids_count);
3171 }
3172 return ret;
d783b061 3173 case IEEE80211_AMPDU_TX_STOP:
e1623446 3174 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3175 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3176 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3177 priv->_agn.agg_tids_count--;
3178 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3179 priv->_agn.agg_tids_count);
3180 }
5c2207c6
WYG		 3181 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3182 return 0;
3183 else
3184 return ret;
f0527971
WYG		 3185 case IEEE80211_AMPDU_TX_OPERATIONAL:
3186 /* do nothing */
3187 return -EOPNOTSUPP;
d783b061 3188 default:
e1623446 3189 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW		 3190 return -EINVAL;
3191 break;
3192 }
3193 return 0;
3194}
9f58671e 3195
6ab10ff8
JB		 3196static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3197 struct ieee80211_vif *vif,
3198 enum sta_notify_cmd cmd,
3199 struct ieee80211_sta *sta)
3200{
3201 struct iwl_priv *priv = hw->priv;
3202 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3203 int sta_id;
3204
6ab10ff8 3205 switch (cmd) {
6ab10ff8
JB		 3206 case STA_NOTIFY_SLEEP:
3207 WARN_ON(!sta_priv->client);
3208 sta_priv->asleep = true;
3209 if (atomic_read(&sta_priv->pending_frames) > 0)
3210 ieee80211_sta_block_awake(hw, sta, true);
3211 break;
3212 case STA_NOTIFY_AWAKE:
3213 WARN_ON(!sta_priv->client);
49dcc819
DH		 3214 if (!sta_priv->asleep)
3215 break;
6ab10ff8 3216 sta_priv->asleep = false;
2a87c26b 3217 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3218 if (sta_id != IWL_INVALID_STATION)
3219 iwl_sta_modify_ps_wake(priv, sta_id);
3220 break;
3221 default:
3222 break;
3223 }
3224}
3225
fe6b23dd
RC		 3226static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3227 struct ieee80211_vif *vif,
3228 struct ieee80211_sta *sta)
3229{
3230 struct iwl_priv *priv = hw->priv;
3231 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
eafdfbd3 3232 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3233 int ret;
3234 u8 sta_id;
3235
fd1af15d
JB		 3236 sta_priv->common.sta_id = IWL_INVALID_STATION;
3237
fe6b23dd
RC		 3238 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3239 sta->addr);
3240
3241 atomic_set(&sta_priv->pending_frames, 0);
3242 if (vif->type == NL80211_IFTYPE_AP)
3243 sta_priv->client = true;
3244
3245 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3246 &sta_id);
3247 if (ret) {
3248 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3249 sta->addr, ret);
3250 /* Should we return success if return code is EEXIST ? */
3251 return ret;
3252 }
3253
fd1af15d
JB		 3254 sta_priv->common.sta_id = sta_id;
3255
fe6b23dd 3256 /* Initialize rate scaling */
91dd6c27 3257 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3258 sta->addr);
3259 iwl_rs_rate_init(priv, sta, sta_id);
3260
fd1af15d 3261 return 0;
fe6b23dd
RC		 3262}
3263
b481de9c
ZY		 3264/*****************************************************************************
3265 *
3266 * sysfs attributes
3267 *
3268 *****************************************************************************/
3269
0a6857e7 3270#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 3271
3272/*
3273 * The following adds a new attribute to the sysfs representation
c3a739fa 3274 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY		 3275 * used for controlling the debug level.
3276 *
3277 * See the level definitions in iwl for details.
a562a9dd 3278 *
3d816c77
RC		 3279 * The debug_level being managed using sysfs below is a per device debug
3280 * level that is used instead of the global debug level if it (the per
3281 * device debug level) is set.
b481de9c 3282 */
8cf769c6
EK		 3283static ssize_t show_debug_level(struct device *d,
3284 struct device_attribute *attr, char *buf)
b481de9c 3285{
3d816c77
RC		 3286 struct iwl_priv *priv = dev_get_drvdata(d);
3287 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3288}
8cf769c6
EK		 3289static ssize_t store_debug_level(struct device *d,
3290 struct device_attribute *attr,
b481de9c
ZY		 3291 const char *buf, size_t count)
3292{
928841b1 3293 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW		 3294 unsigned long val;
3295 int ret;
b481de9c 3296
9257746f
TW		 3297 ret = strict_strtoul(buf, 0, &val);
3298 if (ret)
978785a3 3299 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3300 else {
3d816c77 3301 priv->debug_level = val;
20594eb0
WYG		 3302 if (iwl_alloc_traffic_mem(priv))
3303 IWL_ERR(priv,
3304 "Not enough memory to generate traffic log\n");
3305 }
b481de9c
ZY		 3306 return strnlen(buf, count);
3307}
3308
8cf769c6
EK		 3309static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3310 show_debug_level, store_debug_level);
3311
b481de9c 3312
0a6857e7 3313#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3314
b481de9c
ZY		 3315
3316static ssize_t show_temperature(struct device *d,
3317 struct device_attribute *attr, char *buf)
3318{
928841b1 3319 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3320
fee1247a 3321 if (!iwl_is_alive(priv))
b481de9c
ZY		 3322 return -EAGAIN;
3323
91dbc5bd 3324 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY		 3325}
3326
3327static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3328
b481de9c
ZY		 3329static ssize_t show_tx_power(struct device *d,
3330 struct device_attribute *attr, char *buf)
3331{
928841b1 3332 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS		 3333
3334 if (!iwl_is_ready_rf(priv))
3335 return sprintf(buf, "off\n");
3336 else
3337 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY		 3338}
3339
3340static ssize_t store_tx_power(struct device *d,
3341 struct device_attribute *attr,
3342 const char *buf, size_t count)
3343{
928841b1 3344 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW		 3345 unsigned long val;
3346 int ret;
b481de9c 3347
9257746f
TW		 3348 ret = strict_strtoul(buf, 10, &val);
3349 if (ret)
978785a3 3350 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG		 3351 else {
3352 ret = iwl_set_tx_power(priv, val, false);
3353 if (ret)
3354 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3355 ret);
3356 else
3357 ret = count;
3358 }
3359 return ret;
b481de9c
ZY		 3360}
3361
3362static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3363
01abfbb2
WYG		 3364static ssize_t show_rts_ht_protection(struct device *d,
3365 struct device_attribute *attr, char *buf)
3366{
3367 struct iwl_priv *priv = dev_get_drvdata(d);
3368
3369 return sprintf(buf, "%s\n",
3370 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3371}
3372
3373static ssize_t store_rts_ht_protection(struct device *d,
3374 struct device_attribute *attr,
3375 const char *buf, size_t count)
3376{
3377 struct iwl_priv *priv = dev_get_drvdata(d);
3378 unsigned long val;
3379 int ret;
3380
3381 ret = strict_strtoul(buf, 10, &val);
3382 if (ret)
3383 IWL_INFO(priv, "Input is not in decimal form.\n");
3384 else {
3385 if (!iwl_is_associated(priv))
3386 priv->cfg->use_rts_for_ht = val ? true : false;
3387 else
3388 IWL_ERR(priv, "Sta associated with AP - "
3389 "Change protection mechanism is not allowed\n");
3390 ret = count;
3391 }
3392 return ret;
3393}
3394
3395static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3396 show_rts_ht_protection, store_rts_ht_protection);
3397
b481de9c 3398
b481de9c
ZY		 3399/*****************************************************************************
3400 *
3401 * driver setup and teardown
3402 *
3403 *****************************************************************************/
3404
4e39317d 3405static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3406{
d21050c7 3407 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3408
3409 init_waitqueue_head(&priv->wait_command_queue);
3410
5b9f8cd3
EG		 3411 INIT_WORK(&priv->restart, iwl_bg_restart);
3412 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3413 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3414 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW		 3415 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3416 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3417
2a421b91 3418 iwl_setup_scan_deferred_work(priv);
bb8c093b 3419
4e39317d
EG		 3420 if (priv->cfg->ops->lib->setup_deferred_work)
3421 priv->cfg->ops->lib->setup_deferred_work(priv);
3422
3423 init_timer(&priv->statistics_periodic);
3424 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3425 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3426
a9e1cb6a
WYG		 3427 init_timer(&priv->ucode_trace);
3428 priv->ucode_trace.data = (unsigned long)priv;
3429 priv->ucode_trace.function = iwl_bg_ucode_trace;
3430
b74e31a9
WYG		 3431 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3432 init_timer(&priv->monitor_recover);
3433 priv->monitor_recover.data = (unsigned long)priv;
3434 priv->monitor_recover.function =
3435 priv->cfg->ops->lib->recover_from_tx_stall;
3436 }
3437
ef850d7c
MA		 3438 if (!priv->cfg->use_isr_legacy)
3439 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3440 iwl_irq_tasklet, (unsigned long)priv);
3441 else
3442 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3443 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3444}
3445
4e39317d 3446static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3447{
4e39317d
EG		 3448 if (priv->cfg->ops->lib->cancel_deferred_work)
3449 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3450
3ae6a054 3451 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3452 cancel_delayed_work(&priv->scan_check);
88be0264 3453 cancel_work_sync(&priv->start_internal_scan);
b481de9c 3454 cancel_delayed_work(&priv->alive_start);
b481de9c 3455 cancel_work_sync(&priv->beacon_update);
4e39317d 3456 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3457 del_timer_sync(&priv->ucode_trace);
b74e31a9
WYG		 3458 if (priv->cfg->ops->lib->recover_from_tx_stall)
3459 del_timer_sync(&priv->monitor_recover);
b481de9c
ZY		 3460}
3461
89f186a8
RC		 3462static void iwl_init_hw_rates(struct iwl_priv *priv,
3463 struct ieee80211_rate *rates)
3464{
3465 int i;
3466
3467 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3468 rates[i].bitrate = iwl_rates[i].ieee * 5;
3469 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3470 rates[i].hw_value_short = i;
3471 rates[i].flags = 0;
3472 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3473 /*
3474 * If CCK != 1M then set short preamble rate flag.
3475 */
3476 rates[i].flags |=
3477 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3478 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3479 }
3480 }
3481}
3482
3483static int iwl_init_drv(struct iwl_priv *priv)
3484{
3485 int ret;
3486
3487 priv->ibss_beacon = NULL;
3488
89f186a8
RC		 3489 spin_lock_init(&priv->sta_lock);
3490 spin_lock_init(&priv->hcmd_lock);
3491
3492 INIT_LIST_HEAD(&priv->free_frames);
3493
3494 mutex_init(&priv->mutex);
d2dfe6df 3495 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3496
89f186a8
RC		 3497 priv->ieee_channels = NULL;
3498 priv->ieee_rates = NULL;
3499 priv->band = IEEE80211_BAND_2GHZ;
3500
3501 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3502 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3503 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3504 priv->_agn.agg_tids_count = 0;
89f186a8 3505
8a472da4
WYG		 3506 /* initialize force reset */
3507 priv->force_reset[IWL_RF_RESET].reset_duration =
3508 IWL_DELAY_NEXT_FORCE_RF_RESET;
3509 priv->force_reset[IWL_FW_RESET].reset_duration =
3510 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 3511
3512 /* Choose which receivers/antennas to use */
3513 if (priv->cfg->ops->hcmd->set_rxon_chain)
3514 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3515
3516 iwl_init_scan_params(priv);
3517
89f186a8
RC		 3518 /* Set the tx_power_user_lmt to the lowest power level
3519 * this value will get overwritten by channel max power avg
3520 * from eeprom */
b744cb79 3521 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 3522
3523 ret = iwl_init_channel_map(priv);
3524 if (ret) {
3525 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3526 goto err;
3527 }
3528
3529 ret = iwlcore_init_geos(priv);
3530 if (ret) {
3531 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3532 goto err_free_channel_map;
3533 }
3534 iwl_init_hw_rates(priv, priv->ieee_rates);
3535
3536 return 0;
3537
3538err_free_channel_map:
3539 iwl_free_channel_map(priv);
3540err:
3541 return ret;
3542}
3543
3544static void iwl_uninit_drv(struct iwl_priv *priv)
3545{
3546 iwl_calib_free_results(priv);
3547 iwlcore_free_geos(priv);
3548 iwl_free_channel_map(priv);
811ecc99 3549 kfree(priv->scan_cmd);
89f186a8
RC		 3550}
3551
5b9f8cd3 3552static struct attribute *iwl_sysfs_entries[] = {
b481de9c 3553 &dev_attr_temperature.attr,
b481de9c 3554 &dev_attr_tx_power.attr,
01abfbb2 3555 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK		 3556#ifdef CONFIG_IWLWIFI_DEBUG
3557 &dev_attr_debug_level.attr,
3558#endif
b481de9c
ZY		 3559 NULL
3560};
3561
5b9f8cd3 3562static struct attribute_group iwl_attribute_group = {
b481de9c 3563 .name = NULL, /* put in device directory */
5b9f8cd3 3564 .attrs = iwl_sysfs_entries,
b481de9c
ZY		 3565};
3566
5b9f8cd3
EG		 3567static struct ieee80211_ops iwl_hw_ops = {
3568 .tx = iwl_mac_tx,
3569 .start = iwl_mac_start,
3570 .stop = iwl_mac_stop,
3571 .add_interface = iwl_mac_add_interface,
3572 .remove_interface = iwl_mac_remove_interface,
3573 .config = iwl_mac_config,
5b9f8cd3
EG		 3574 .configure_filter = iwl_configure_filter,
3575 .set_key = iwl_mac_set_key,
3576 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 3577 .conf_tx = iwl_mac_conf_tx,
3578 .reset_tsf = iwl_mac_reset_tsf,
3579 .bss_info_changed = iwl_bss_info_changed,
3580 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 3581 .hw_scan = iwl_mac_hw_scan,
3582 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 3583 .sta_add = iwlagn_mac_sta_add,
3584 .sta_remove = iwl_mac_sta_remove,
b481de9c
ZY		 3585};
3586
5b9f8cd3 3587static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 3588{
3589 int err = 0;
c79dd5b5 3590 struct iwl_priv *priv;
b481de9c 3591 struct ieee80211_hw *hw;
82b9a121 3592 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3593 unsigned long flags;
6cd0b1cb 3594 u16 pci_cmd;
b481de9c 3595
316c30d9
AK		 3596 /************************
3597 * 1. Allocating HW data
3598 ************************/
3599
6440adb5
CB		 3600 /* Disabling hardware scan means that mac80211 will perform scans
3601 * "the hard way", rather than using device's scan. */
1ea87396 3602 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3603 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK		 3604 dev_printk(KERN_DEBUG, &(pdev->dev),
3605 "Disabling hw_scan\n");
5b9f8cd3 3606 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 3607 }
3608
5b9f8cd3 3609 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3610 if (!hw) {
b481de9c
ZY		 3611 err = -ENOMEM;
3612 goto out;
3613 }
1d0a082d
AK		 3614 priv = hw->priv;
3615 /* At this point both hw and priv are allocated. */
3616
b481de9c
ZY		 3617 SET_IEEE80211_DEV(hw, &pdev->dev);
3618
e1623446 3619 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3620 priv->cfg = cfg;
b481de9c 3621 priv->pci_dev = pdev;
40cefda9 3622 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3623
0a6857e7 3624#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 3625 atomic_set(&priv->restrict_refcnt, 0);
3626#endif
20594eb0
WYG		 3627 if (iwl_alloc_traffic_mem(priv))
3628 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3629
316c30d9
AK		 3630 /**************************
3631 * 2. Initializing PCI bus
3632 **************************/
3633 if (pci_enable_device(pdev)) {
3634 err = -ENODEV;
3635 goto out_ieee80211_free_hw;
3636 }
3637
3638 pci_set_master(pdev);
3639
093d874c 3640 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3641 if (!err)
093d874c 3642 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3643 if (err) {
093d874c 3644 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3645 if (!err)
093d874c 3646 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3647 /* both attempts failed: */
316c30d9 3648 if (err) {
978785a3 3649 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3650 goto out_pci_disable_device;
cc2a8ea8 3651 }
316c30d9
AK		 3652 }
3653
3654 err = pci_request_regions(pdev, DRV_NAME);
3655 if (err)
3656 goto out_pci_disable_device;
3657
3658 pci_set_drvdata(pdev, priv);
3659
316c30d9
AK		 3660
3661 /***********************
3662 * 3. Read REV register
3663 ***********************/
3664 priv->hw_base = pci_iomap(pdev, 0, 0);
3665 if (!priv->hw_base) {
3666 err = -ENODEV;
3667 goto out_pci_release_regions;
3668 }
3669
e1623446 3670 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3671 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3672 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3673
731a29b7 3674 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 3675 * we should init now
3676 */
3677 spin_lock_init(&priv->reg_lock);
731a29b7 3678 spin_lock_init(&priv->lock);
4843b5a7
RC		 3679
3680 /*
3681 * stop and reset the on-board processor just in case it is in a
3682 * strange state ... like being left stranded by a primary kernel
3683 * and this is now the kdump kernel trying to start up
3684 */
3685 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3686
b661c819 3687 iwl_hw_detect(priv);
c11362c0 3688 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 3689 priv->cfg->name, priv->hw_rev);
316c30d9 3690
e7b63581
TW		 3691 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3692 * PCI Tx retries from interfering with C3 CPU state */
3693 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3694
086ed117
MA		 3695 iwl_prepare_card_hw(priv);
3696 if (!priv->hw_ready) {
3697 IWL_WARN(priv, "Failed, HW not ready\n");
3698 goto out_iounmap;
3699 }
3700
91238714
TW		 3701 /*****************
3702 * 4. Read EEPROM
3703 *****************/
316c30d9
AK		 3704 /* Read the EEPROM */
3705 err = iwl_eeprom_init(priv);
3706 if (err) {
15b1687c 3707 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 3708 goto out_iounmap;
3709 }
8614f360
TW		 3710 err = iwl_eeprom_check_version(priv);
3711 if (err)
c8f16138 3712 goto out_free_eeprom;
8614f360 3713
02883017 3714 /* extract MAC Address */
316c30d9 3715 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3716 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK		 3717 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3718
3719 /************************
3720 * 5. Setup HW constants
3721 ************************/
da154e30 3722 if (iwl_set_hw_params(priv)) {
15b1687c 3723 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3724 goto out_free_eeprom;
316c30d9
AK		 3725 }
3726
3727 /*******************
6ba87956 3728 * 6. Setup priv
316c30d9 3729 *******************/
b481de9c 3730
6ba87956 3731 err = iwl_init_drv(priv);
bf85ea4f 3732 if (err)
399f4900 3733 goto out_free_eeprom;
bf85ea4f 3734 /* At this point both hw and priv are initialized. */
316c30d9 3735
316c30d9 3736 /********************
09f9bf79 3737 * 7. Setup services
316c30d9 3738 ********************/
0359facc 3739 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3740 iwl_disable_interrupts(priv);
0359facc 3741 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3742
6cd0b1cb
HS		 3743 pci_enable_msi(priv->pci_dev);
3744
ef850d7c
MA		 3745 iwl_alloc_isr_ict(priv);
3746 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3747 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 3748 if (err) {
3749 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3750 goto out_disable_msi;
3751 }
5b9f8cd3 3752 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3753 if (err) {
15b1687c 3754 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3755 goto out_free_irq;
316c30d9
AK		 3756 }
3757
4e39317d 3758 iwl_setup_deferred_work(priv);
653fa4a0 3759 iwl_setup_rx_handlers(priv);
316c30d9 3760
158bea07
JB		 3761 /*********************************************
3762 * 8. Enable interrupts and read RFKILL state
3763 *********************************************/
6ba87956 3764
6cd0b1cb
HS		 3765 /* enable interrupts if needed: hw bug w/a */
3766 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3767 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3768 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3769 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3770 }
3771
3772 iwl_enable_interrupts(priv);
3773
6cd0b1cb
HS		 3774 /* If platform's RF_KILL switch is NOT set to KILL */
3775 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3776 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3777 else
3778 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3779
a60e77e5
JB		 3780 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3781 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3782
58d0f361 3783 iwl_power_initialize(priv);
39b73fb1 3784 iwl_tt_initialize(priv);
158bea07 3785
a15707d8 3786 init_completion(&priv->_agn.firmware_loading_complete);
562db532 3787
b08dfd04 3788 err = iwl_request_firmware(priv, true);
158bea07
JB		 3789 if (err)
3790 goto out_remove_sysfs;
3791
b481de9c
ZY		 3792 return 0;
3793
316c30d9 3794 out_remove_sysfs:
c8f16138
RC		 3795 destroy_workqueue(priv->workqueue);
3796 priv->workqueue = NULL;
5b9f8cd3 3797 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS		 3798 out_free_irq:
3799 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3800 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 3801 out_disable_msi:
3802 pci_disable_msi(priv->pci_dev);
6ba87956 3803 iwl_uninit_drv(priv);
073d3f5f
TW		 3804 out_free_eeprom:
3805 iwl_eeprom_free(priv);
b481de9c
ZY		 3806 out_iounmap:
3807 pci_iounmap(pdev, priv->hw_base);
3808 out_pci_release_regions:
316c30d9 3809 pci_set_drvdata(pdev, NULL);
623d563e 3810 pci_release_regions(pdev);
b481de9c
ZY		 3811 out_pci_disable_device:
3812 pci_disable_device(pdev);
b481de9c 3813 out_ieee80211_free_hw:
20594eb0 3814 iwl_free_traffic_mem(priv);
d7c76f4c 3815 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 3816 out:
3817 return err;
3818}
3819
5b9f8cd3 3820static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3821{
c79dd5b5 3822 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3823 unsigned long flags;
b481de9c
ZY		 3824
3825 if (!priv)
3826 return;
3827
a15707d8 3828 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 3829
e1623446 3830 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3831
67249625 3832 iwl_dbgfs_unregister(priv);
5b9f8cd3 3833 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3834
5b9f8cd3
EG		 3835 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3836 * to be called and iwl_down since we are removing the device
0b124c31
GG		 3837 * we need to set STATUS_EXIT_PENDING bit.
3838 */
3839 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 3840 if (priv->mac80211_registered) {
3841 ieee80211_unregister_hw(priv->hw);
3842 priv->mac80211_registered = 0;
0b124c31 3843 } else {
5b9f8cd3 3844 iwl_down(priv);
c4f55232
RR		 3845 }
3846
c166b25a
BC		 3847 /*
3848 * Make sure device is reset to low power before unloading driver.
3849 * This may be redundant with iwl_down(), but there are paths to
3850 * run iwl_down() without calling apm_ops.stop(), and there are
3851 * paths to avoid running iwl_down() at all before leaving driver.
3852 * This (inexpensive) call *makes sure* device is reset.
3853 */
3854 priv->cfg->ops->lib->apm_ops.stop(priv);
3855
39b73fb1
WYG		 3856 iwl_tt_exit(priv);
3857
0359facc
MA		 3858 /* make sure we flush any pending irq or
3859 * tasklet for the driver
3860 */
3861 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3862 iwl_disable_interrupts(priv);
0359facc
MA		 3863 spin_unlock_irqrestore(&priv->lock, flags);
3864
3865 iwl_synchronize_irq(priv);
3866
5b9f8cd3 3867 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 3868
3869 if (priv->rxq.bd)
54b81550 3870 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 3871 iwlagn_hw_txq_ctx_free(priv);
b481de9c 3872
073d3f5f 3873 iwl_eeprom_free(priv);
b481de9c 3874
b481de9c 3875
948c171c
MA		 3876 /*netif_stop_queue(dev); */
3877 flush_workqueue(priv->workqueue);
3878
5b9f8cd3 3879 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 3880 * priv->workqueue... so we can't take down the workqueue
3881 * until now... */
3882 destroy_workqueue(priv->workqueue);
3883 priv->workqueue = NULL;
20594eb0 3884 iwl_free_traffic_mem(priv);
b481de9c 3885
6cd0b1cb
HS		 3886 free_irq(priv->pci_dev->irq, priv);
3887 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 3888 pci_iounmap(pdev, priv->hw_base);
3889 pci_release_regions(pdev);
3890 pci_disable_device(pdev);
3891 pci_set_drvdata(pdev, NULL);
3892
6ba87956 3893 iwl_uninit_drv(priv);
b481de9c 3894
ef850d7c
MA		 3895 iwl_free_isr_ict(priv);
3896
b481de9c
ZY		 3897 if (priv->ibss_beacon)
3898 dev_kfree_skb(priv->ibss_beacon);
3899
3900 ieee80211_free_hw(priv->hw);
3901}
3902
b481de9c
ZY		 3903
3904/*****************************************************************************
3905 *
3906 * driver and module entry point
3907 *
3908 *****************************************************************************/
3909
fed9017e 3910/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 3911static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 3912#ifdef CONFIG_IWL4965
fed9017e
RR		 3913 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3914 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3915#endif /* CONFIG_IWL4965 */
5a6a256e 3916#ifdef CONFIG_IWL5000
ac592574
WYG		 3917/* 5100 Series WiFi */
3918 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3919 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3920 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3921 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3922 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3923 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3924 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3925 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3926 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3927 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3928 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3929 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3930 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3931 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3932 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3933 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3934 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3935 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3936 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3937 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3938 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3939 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3940 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3941 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3942
3943/* 5300 Series WiFi */
3944 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3945 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3946 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3947 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3948 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3949 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3950 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3951 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3952 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3953 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3954 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3955 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3956
3957/* 5350 Series WiFi/WiMax */
3958 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3959 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3960 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3961
3962/* 5150 Series Wifi/WiMax */
3963 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3964 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3965 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3966 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3967 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3968 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3969
3970 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3971 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3972 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3973 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 3974
3975/* 6x00 Series */
5953a62e
WYG		 3976 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3977 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3978 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3979 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3980 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3981 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3982 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3983 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3984 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3985 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 3986
95b13014
SZ		 3987/* 6x00 Series Gen2a */
3988 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
3989 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
3990 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
5953a62e
WYG		 3991
3992/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 3993 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3994 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3995 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3996 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 3997 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3998 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3999
77dcb6a9 4000/* 1000 Series WiFi */
4bd0914f
WYG		 4001 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4002 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4003 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4004 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4005 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4006 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4007 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4008 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4009 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4010 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4011 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4012 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 4013#endif /* CONFIG_IWL5000 */
7100e924 4014
fed9017e
RR		 4015 {0}
4016};
4017MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4018
4019static struct pci_driver iwl_driver = {
b481de9c 4020 .name = DRV_NAME,
fed9017e 4021 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4022 .probe = iwl_pci_probe,
4023 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4024#ifdef CONFIG_PM
5b9f8cd3
EG		 4025 .suspend = iwl_pci_suspend,
4026 .resume = iwl_pci_resume,
b481de9c
ZY		 4027#endif
4028};
4029
5b9f8cd3 4030static int __init iwl_init(void)
b481de9c
ZY		 4031{
4032
4033 int ret;
4034 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4035 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 4036
e227ceac 4037 ret = iwlagn_rate_control_register();
897e1cf2 4038 if (ret) {
a3139c59
SO		 4039 printk(KERN_ERR DRV_NAME
4040 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4041 return ret;
4042 }
4043
fed9017e 4044 ret = pci_register_driver(&iwl_driver);
b481de9c 4045 if (ret) {
a3139c59 4046 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4047 goto error_register;
b481de9c 4048 }
b481de9c
ZY		 4049
4050 return ret;
897e1cf2 4051
897e1cf2 4052error_register:
e227ceac 4053 iwlagn_rate_control_unregister();
897e1cf2 4054 return ret;
b481de9c
ZY		 4055}
4056
5b9f8cd3 4057static void __exit iwl_exit(void)
b481de9c 4058{
fed9017e 4059 pci_unregister_driver(&iwl_driver);
e227ceac 4060 iwlagn_rate_control_unregister();
b481de9c
ZY		 4061}
4062
5b9f8cd3
EG		 4063module_exit(iwl_exit);
4064module_init(iwl_init);
a562a9dd
RC		 4065
4066#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4067module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4068MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4069module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4070MODULE_PARM_DESC(debug, "debug output mask");
4071#endif
4072
2b068618
WYG		 4073module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4074MODULE_PARM_DESC(swcrypto50,
4075 "using crypto in software (default 0 [hardware]) (deprecated)");
4076module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4077MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4078module_param_named(queues_num50,
4079 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4080MODULE_PARM_DESC(queues_num50,
4081 "number of hw queues in 50xx series (deprecated)");
4082module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4083MODULE_PARM_DESC(queues_num, "number of hw queues.");
4084module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4085MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4086module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4087MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4088module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4089 int, S_IRUGO);
4090MODULE_PARM_DESC(amsdu_size_8K50,
4091 "enable 8K amsdu size in 50XX series (deprecated)");
4092module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4093 int, S_IRUGO);
4094MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4095module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4096MODULE_PARM_DESC(fw_restart50,
4097 "restart firmware in case of error (deprecated)");
4098module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4099MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4100module_param_named(
4101 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4102MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
dd7a2509
JB		 4103
4104module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4105 S_IRUGO);
4106MODULE_PARM_DESC(ucode_alternative,
4107 "specify ucode alternative to use from ucode file");
Linux kernel - Deliverables
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