Commit | Line | Data |
---|---|---|
b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
c96c31e4 JP |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
b481de9c ZY |
32 | #include <linux/kernel.h> |
33 | #include <linux/module.h> | |
b481de9c ZY |
34 | #include <linux/init.h> |
35 | #include <linux/pci.h> | |
1a7123cd | 36 | #include <linux/pci-aspm.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
b481de9c ZY |
38 | #include <linux/dma-mapping.h> |
39 | #include <linux/delay.h> | |
d43c36dc | 40 | #include <linux/sched.h> |
b481de9c ZY |
41 | #include <linux/skbuff.h> |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/wireless.h> | |
44 | #include <linux/firmware.h> | |
b481de9c ZY |
45 | #include <linux/etherdevice.h> |
46 | #include <linux/if_arp.h> | |
47 | ||
b481de9c ZY |
48 | #include <net/mac80211.h> |
49 | ||
50 | #include <asm/div64.h> | |
51 | ||
a3139c59 SO |
52 | #define DRV_NAME "iwlagn" |
53 | ||
6bc913bd | 54 | #include "iwl-eeprom.h" |
3e0d4cb1 | 55 | #include "iwl-dev.h" |
fee1247a | 56 | #include "iwl-core.h" |
3395f6e9 | 57 | #include "iwl-io.h" |
b481de9c | 58 | #include "iwl-helpers.h" |
6974e363 | 59 | #include "iwl-sta.h" |
0de76736 | 60 | #include "iwl-agn-calib.h" |
a1175124 | 61 | #include "iwl-agn.h" |
5ed540ae | 62 | #include "iwl-agn-led.h" |
b481de9c | 63 | |
416e1438 | 64 | |
b481de9c ZY |
65 | /****************************************************************************** |
66 | * | |
67 | * module boiler plate | |
68 | * | |
69 | ******************************************************************************/ | |
70 | ||
b481de9c ZY |
71 | /* |
72 | * module name, copyright, version, etc. | |
b481de9c | 73 | */ |
d783b061 | 74 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 75 | |
0a6857e7 | 76 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
77 | #define VD "d" |
78 | #else | |
79 | #define VD | |
80 | #endif | |
81 | ||
81963d68 | 82 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 83 | |
b481de9c ZY |
84 | |
85 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
86 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 87 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
88 | MODULE_LICENSE("GPL"); |
89 | ||
bee008b7 | 90 | static int iwlagn_ant_coupling; |
f37837c9 | 91 | static bool iwlagn_bt_ch_announce = 1; |
bee008b7 | 92 | |
5b9f8cd3 | 93 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f | 94 | { |
246ed355 | 95 | struct iwl_rxon_context *ctx; |
5da4b55f | 96 | |
246ed355 JB |
97 | if (priv->cfg->ops->hcmd->set_rxon_chain) { |
98 | for_each_context(priv, ctx) { | |
99 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
6163a373 SZ |
100 | if (ctx->active.rx_chain != ctx->staging.rx_chain) |
101 | iwlcore_commit_rxon(priv, ctx); | |
246ed355 JB |
102 | } |
103 | } | |
5da4b55f MA |
104 | } |
105 | ||
fcab423d | 106 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
107 | { |
108 | struct list_head *element; | |
109 | ||
e1623446 | 110 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
111 | priv->frames_count); |
112 | ||
113 | while (!list_empty(&priv->free_frames)) { | |
114 | element = priv->free_frames.next; | |
115 | list_del(element); | |
fcab423d | 116 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
117 | priv->frames_count--; |
118 | } | |
119 | ||
120 | if (priv->frames_count) { | |
39aadf8c | 121 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
122 | priv->frames_count); |
123 | priv->frames_count = 0; | |
124 | } | |
125 | } | |
126 | ||
fcab423d | 127 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 128 | { |
fcab423d | 129 | struct iwl_frame *frame; |
b481de9c ZY |
130 | struct list_head *element; |
131 | if (list_empty(&priv->free_frames)) { | |
132 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
133 | if (!frame) { | |
15b1687c | 134 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
135 | return NULL; |
136 | } | |
137 | ||
138 | priv->frames_count++; | |
139 | return frame; | |
140 | } | |
141 | ||
142 | element = priv->free_frames.next; | |
143 | list_del(element); | |
fcab423d | 144 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
145 | } |
146 | ||
fcab423d | 147 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
148 | { |
149 | memset(frame, 0, sizeof(*frame)); | |
150 | list_add(&frame->list, &priv->free_frames); | |
151 | } | |
152 | ||
47ff65c4 | 153 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
77834543 JB |
154 | struct ieee80211_hdr *hdr, |
155 | int left) | |
b481de9c | 156 | { |
77834543 JB |
157 | lockdep_assert_held(&priv->mutex); |
158 | ||
12e934dc | 159 | if (!priv->beacon_skb) |
b481de9c ZY |
160 | return 0; |
161 | ||
12e934dc | 162 | if (priv->beacon_skb->len > left) |
b481de9c ZY |
163 | return 0; |
164 | ||
12e934dc | 165 | memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len); |
b481de9c | 166 | |
12e934dc | 167 | return priv->beacon_skb->len; |
b481de9c ZY |
168 | } |
169 | ||
47ff65c4 DH |
170 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
171 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
77834543 JB |
172 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, |
173 | u8 *beacon, u32 frame_size) | |
47ff65c4 DH |
174 | { |
175 | u16 tim_idx; | |
176 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
177 | ||
178 | /* | |
179 | * The index is relative to frame start but we start looking at the | |
180 | * variable-length part of the beacon. | |
181 | */ | |
182 | tim_idx = mgmt->u.beacon.variable - beacon; | |
183 | ||
184 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
185 | while ((tim_idx < (frame_size - 2)) && | |
186 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
187 | tim_idx += beacon[tim_idx+1] + 2; | |
188 | ||
189 | /* If TIM field was found, set variables */ | |
190 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
191 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
192 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
193 | } else | |
194 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
195 | } | |
196 | ||
5b9f8cd3 | 197 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 198 | struct iwl_frame *frame) |
4bf64efd TW |
199 | { |
200 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
201 | u32 frame_size; |
202 | u32 rate_flags; | |
203 | u32 rate; | |
204 | /* | |
205 | * We have to set up the TX command, the TX Beacon command, and the | |
206 | * beacon contents. | |
207 | */ | |
4bf64efd | 208 | |
76d04815 JB |
209 | lockdep_assert_held(&priv->mutex); |
210 | ||
211 | if (!priv->beacon_ctx) { | |
212 | IWL_ERR(priv, "trying to build beacon w/o beacon context!\n"); | |
950094cb | 213 | return 0; |
76d04815 JB |
214 | } |
215 | ||
47ff65c4 | 216 | /* Initialize memory */ |
4bf64efd TW |
217 | tx_beacon_cmd = &frame->u.beacon; |
218 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
219 | ||
47ff65c4 | 220 | /* Set up TX beacon contents */ |
4bf64efd | 221 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 222 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
223 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
224 | return 0; | |
40bbfd4c JB |
225 | if (!frame_size) |
226 | return 0; | |
4bf64efd | 227 | |
47ff65c4 | 228 | /* Set up TX command fields */ |
4bf64efd | 229 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
76d04815 | 230 | tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id; |
47ff65c4 DH |
231 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
232 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
233 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 234 | |
47ff65c4 DH |
235 | /* Set up TX beacon command fields */ |
236 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
77834543 | 237 | frame_size); |
4bf64efd | 238 | |
47ff65c4 | 239 | /* Set up packet rate and flags */ |
76d04815 | 240 | rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx); |
0e1654fa JB |
241 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, |
242 | priv->hw_params.valid_tx_ant); | |
47ff65c4 DH |
243 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
244 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
245 | rate_flags |= RATE_MCS_CCK_MSK; | |
246 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
247 | rate_flags); | |
4bf64efd TW |
248 | |
249 | return sizeof(*tx_beacon_cmd) + frame_size; | |
250 | } | |
2295c66b JB |
251 | |
252 | int iwlagn_send_beacon_cmd(struct iwl_priv *priv) | |
b481de9c | 253 | { |
fcab423d | 254 | struct iwl_frame *frame; |
b481de9c ZY |
255 | unsigned int frame_size; |
256 | int rc; | |
b481de9c | 257 | |
fcab423d | 258 | frame = iwl_get_free_frame(priv); |
b481de9c | 259 | if (!frame) { |
15b1687c | 260 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
261 | "command.\n"); |
262 | return -ENOMEM; | |
263 | } | |
264 | ||
47ff65c4 DH |
265 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
266 | if (!frame_size) { | |
267 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
268 | iwl_free_frame(priv, frame); | |
269 | return -EINVAL; | |
270 | } | |
b481de9c | 271 | |
857485c0 | 272 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
273 | &frame->u.cmd[0]); |
274 | ||
fcab423d | 275 | iwl_free_frame(priv, frame); |
b481de9c ZY |
276 | |
277 | return rc; | |
278 | } | |
279 | ||
7aaa1d79 SO |
280 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
281 | { | |
282 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
283 | ||
284 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
285 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
286 | addr |= | |
287 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
288 | ||
289 | return addr; | |
290 | } | |
291 | ||
292 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
293 | { | |
294 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
295 | ||
296 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
297 | } | |
298 | ||
299 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
300 | dma_addr_t addr, u16 len) | |
301 | { | |
302 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
303 | u16 hi_n_len = len << 4; | |
304 | ||
305 | put_unaligned_le32(addr, &tb->lo); | |
306 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
307 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
308 | ||
309 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
310 | ||
311 | tfd->num_tbs = idx + 1; | |
312 | } | |
313 | ||
314 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
315 | { | |
316 | return tfd->num_tbs & 0x1f; | |
317 | } | |
318 | ||
319 | /** | |
320 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
321 | * @priv - driver private data | |
322 | * @txq - tx queue | |
323 | * | |
324 | * Does NOT advance any TFD circular buffer read/write indexes | |
325 | * Does NOT free the TFD itself (which is within circular buffer) | |
326 | */ | |
327 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
328 | { | |
59606ffa | 329 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
330 | struct iwl_tfd *tfd; |
331 | struct pci_dev *dev = priv->pci_dev; | |
332 | int index = txq->q.read_ptr; | |
333 | int i; | |
334 | int num_tbs; | |
335 | ||
336 | tfd = &tfd_tmp[index]; | |
337 | ||
338 | /* Sanity check on number of chunks */ | |
339 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
340 | ||
341 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
342 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
343 | /* @todo issue fatal error, it is quite serious situation */ | |
344 | return; | |
345 | } | |
346 | ||
347 | /* Unmap tx_cmd */ | |
348 | if (num_tbs) | |
349 | pci_unmap_single(dev, | |
2e724443 FT |
350 | dma_unmap_addr(&txq->meta[index], mapping), |
351 | dma_unmap_len(&txq->meta[index], len), | |
96891cee | 352 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
353 | |
354 | /* Unmap chunks, if any. */ | |
ff0d91c3 | 355 | for (i = 1; i < num_tbs; i++) |
7aaa1d79 SO |
356 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), |
357 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
358 | ||
ff0d91c3 JB |
359 | /* free SKB */ |
360 | if (txq->txb) { | |
361 | struct sk_buff *skb; | |
6f80240e | 362 | |
ff0d91c3 | 363 | skb = txq->txb[txq->q.read_ptr].skb; |
6f80240e | 364 | |
ff0d91c3 JB |
365 | /* can be called from irqs-disabled context */ |
366 | if (skb) { | |
367 | dev_kfree_skb_any(skb); | |
368 | txq->txb[txq->q.read_ptr].skb = NULL; | |
7aaa1d79 SO |
369 | } |
370 | } | |
371 | } | |
372 | ||
373 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
374 | struct iwl_tx_queue *txq, | |
375 | dma_addr_t addr, u16 len, | |
376 | u8 reset, u8 pad) | |
377 | { | |
378 | struct iwl_queue *q; | |
59606ffa | 379 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
380 | u32 num_tbs; |
381 | ||
382 | q = &txq->q; | |
59606ffa SO |
383 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
384 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
385 | |
386 | if (reset) | |
387 | memset(tfd, 0, sizeof(*tfd)); | |
388 | ||
389 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
390 | ||
391 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
392 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
393 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
394 | IWL_NUM_OF_TBS); | |
395 | return -EINVAL; | |
396 | } | |
397 | ||
398 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
399 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
400 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
401 | (unsigned long long)addr); | |
402 | ||
403 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
a8e74e27 SO |
408 | /* |
409 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
410 | * given Tx queue, and enable the DMA channel used for that queue. | |
411 | * | |
f7d046f9 | 412 | * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA |
a8e74e27 SO |
413 | * channels supported in hardware. |
414 | */ | |
415 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
416 | struct iwl_tx_queue *txq) | |
417 | { | |
a8e74e27 SO |
418 | int txq_id = txq->q.id; |
419 | ||
a8e74e27 SO |
420 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
421 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
422 | txq->q.dma_addr >> 8); | |
423 | ||
a8e74e27 SO |
424 | return 0; |
425 | } | |
426 | ||
5b9f8cd3 | 427 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 428 | { |
c79dd5b5 TW |
429 | struct iwl_priv *priv = |
430 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
431 | struct sk_buff *beacon; |
432 | ||
76d04815 JB |
433 | mutex_lock(&priv->mutex); |
434 | if (!priv->beacon_ctx) { | |
435 | IWL_ERR(priv, "updating beacon w/o beacon context!\n"); | |
436 | goto out; | |
437 | } | |
b481de9c | 438 | |
60744f62 JB |
439 | if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) { |
440 | /* | |
441 | * The ucode will send beacon notifications even in | |
442 | * IBSS mode, but we don't want to process them. But | |
443 | * we need to defer the type check to here due to | |
444 | * requiring locking around the beacon_ctx access. | |
445 | */ | |
446 | goto out; | |
447 | } | |
448 | ||
76d04815 JB |
449 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ |
450 | beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif); | |
b481de9c | 451 | if (!beacon) { |
77834543 | 452 | IWL_ERR(priv, "update beacon failed -- keeping old\n"); |
76d04815 | 453 | goto out; |
b481de9c ZY |
454 | } |
455 | ||
b481de9c | 456 | /* new beacon skb is allocated every time; dispose previous.*/ |
77834543 | 457 | dev_kfree_skb(priv->beacon_skb); |
b481de9c | 458 | |
12e934dc | 459 | priv->beacon_skb = beacon; |
b481de9c | 460 | |
2295c66b | 461 | iwlagn_send_beacon_cmd(priv); |
76d04815 JB |
462 | out: |
463 | mutex_unlock(&priv->mutex); | |
b481de9c ZY |
464 | } |
465 | ||
fbba9410 WYG |
466 | static void iwl_bg_bt_runtime_config(struct work_struct *work) |
467 | { | |
468 | struct iwl_priv *priv = | |
469 | container_of(work, struct iwl_priv, bt_runtime_config); | |
470 | ||
471 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
472 | return; | |
473 | ||
474 | /* dont send host command if rf-kill is on */ | |
475 | if (!iwl_is_ready_rf(priv)) | |
476 | return; | |
477 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
478 | } | |
479 | ||
bee008b7 WYG |
480 | static void iwl_bg_bt_full_concurrency(struct work_struct *work) |
481 | { | |
482 | struct iwl_priv *priv = | |
483 | container_of(work, struct iwl_priv, bt_full_concurrency); | |
246ed355 | 484 | struct iwl_rxon_context *ctx; |
bee008b7 | 485 | |
dc1a4068 SG |
486 | mutex_lock(&priv->mutex); |
487 | ||
bee008b7 | 488 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
dc1a4068 | 489 | goto out; |
bee008b7 WYG |
490 | |
491 | /* dont send host command if rf-kill is on */ | |
492 | if (!iwl_is_ready_rf(priv)) | |
dc1a4068 | 493 | goto out; |
bee008b7 WYG |
494 | |
495 | IWL_DEBUG_INFO(priv, "BT coex in %s mode\n", | |
496 | priv->bt_full_concurrent ? | |
497 | "full concurrency" : "3-wire"); | |
498 | ||
499 | /* | |
500 | * LQ & RXON updated cmds must be sent before BT Config cmd | |
501 | * to avoid 3-wire collisions | |
502 | */ | |
246ed355 JB |
503 | for_each_context(priv, ctx) { |
504 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
505 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
506 | iwlcore_commit_rxon(priv, ctx); | |
507 | } | |
bee008b7 WYG |
508 | |
509 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
dc1a4068 SG |
510 | out: |
511 | mutex_unlock(&priv->mutex); | |
bee008b7 WYG |
512 | } |
513 | ||
4e39317d | 514 | /** |
5b9f8cd3 | 515 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
516 | * |
517 | * This callback is provided in order to send a statistics request. | |
518 | * | |
519 | * This timer function is continually reset to execute within | |
520 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
521 | * was received. We need to ensure we receive the statistics in order | |
522 | * to update the temperature used for calibrating the TXPOWER. | |
523 | */ | |
5b9f8cd3 | 524 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
525 | { |
526 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
527 | ||
528 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
529 | return; | |
530 | ||
61780ee3 MA |
531 | /* dont send host command if rf-kill is on */ |
532 | if (!iwl_is_ready_rf(priv)) | |
533 | return; | |
534 | ||
ef8d5529 | 535 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
536 | } |
537 | ||
a9e1cb6a WYG |
538 | |
539 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
540 | u32 start_idx, u32 num_events, | |
541 | u32 mode) | |
542 | { | |
543 | u32 i; | |
544 | u32 ptr; /* SRAM byte address of log data */ | |
545 | u32 ev, time, data; /* event log data */ | |
546 | unsigned long reg_flags; | |
547 | ||
548 | if (mode == 0) | |
549 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
550 | else | |
551 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
552 | ||
553 | /* Make sure device is powered up for SRAM reads */ | |
554 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
555 | if (iwl_grab_nic_access(priv)) { | |
556 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
557 | return; | |
558 | } | |
559 | ||
560 | /* Set starting address; reads will auto-increment */ | |
561 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
562 | rmb(); | |
563 | ||
564 | /* | |
565 | * "time" is actually "data" for mode 0 (no timestamp). | |
566 | * place event id # at far right for easier visual parsing. | |
567 | */ | |
568 | for (i = 0; i < num_events; i++) { | |
569 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
570 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
571 | if (mode == 0) { | |
572 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
573 | 0, time, ev); | |
574 | } else { | |
575 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
576 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
577 | time, data, ev); | |
578 | } | |
579 | } | |
580 | /* Allow device to power down */ | |
581 | iwl_release_nic_access(priv); | |
582 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
583 | } | |
584 | ||
875295f1 | 585 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
586 | { |
587 | u32 capacity; /* event log capacity in # entries */ | |
588 | u32 base; /* SRAM byte address of event log header */ | |
589 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
590 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
591 | u32 next_entry; /* index of next entry to be written by uCode */ | |
592 | ||
d7d5783c | 593 | base = priv->device_pointers.error_event_table; |
a9e1cb6a WYG |
594 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
595 | capacity = iwl_read_targ_mem(priv, base); | |
596 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
597 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
598 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
599 | } else | |
600 | return; | |
601 | ||
602 | if (num_wraps == priv->event_log.num_wraps) { | |
603 | iwl_print_cont_event_trace(priv, | |
604 | base, priv->event_log.next_entry, | |
605 | next_entry - priv->event_log.next_entry, | |
606 | mode); | |
607 | priv->event_log.non_wraps_count++; | |
608 | } else { | |
609 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
610 | priv->event_log.wraps_more_count++; | |
611 | else | |
612 | priv->event_log.wraps_once_count++; | |
613 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
614 | num_wraps - priv->event_log.num_wraps, | |
615 | next_entry, priv->event_log.next_entry); | |
616 | if (next_entry < priv->event_log.next_entry) { | |
617 | iwl_print_cont_event_trace(priv, base, | |
618 | priv->event_log.next_entry, | |
619 | capacity - priv->event_log.next_entry, | |
620 | mode); | |
621 | ||
622 | iwl_print_cont_event_trace(priv, base, 0, | |
623 | next_entry, mode); | |
624 | } else { | |
625 | iwl_print_cont_event_trace(priv, base, | |
626 | next_entry, capacity - next_entry, | |
627 | mode); | |
628 | ||
629 | iwl_print_cont_event_trace(priv, base, 0, | |
630 | next_entry, mode); | |
631 | } | |
632 | } | |
633 | priv->event_log.num_wraps = num_wraps; | |
634 | priv->event_log.next_entry = next_entry; | |
635 | } | |
636 | ||
637 | /** | |
638 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
639 | * | |
640 | * The timer is continually set to execute every | |
641 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
642 | * this function is to perform continuous uCode event logging operation | |
643 | * if enabled | |
644 | */ | |
645 | static void iwl_bg_ucode_trace(unsigned long data) | |
646 | { | |
647 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
648 | ||
649 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
650 | return; | |
651 | ||
652 | if (priv->event_log.ucode_trace) { | |
653 | iwl_continuous_event_trace(priv); | |
654 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
655 | mod_timer(&priv->ucode_trace, | |
656 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
657 | } | |
658 | } | |
659 | ||
65550636 WYG |
660 | static void iwl_bg_tx_flush(struct work_struct *work) |
661 | { | |
662 | struct iwl_priv *priv = | |
663 | container_of(work, struct iwl_priv, tx_flush); | |
664 | ||
665 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
666 | return; | |
667 | ||
668 | /* do nothing if rf-kill is on */ | |
669 | if (!iwl_is_ready_rf(priv)) | |
670 | return; | |
671 | ||
672 | if (priv->cfg->ops->lib->txfifo_flush) { | |
673 | IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n"); | |
674 | iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL); | |
675 | } | |
676 | } | |
677 | ||
b481de9c | 678 | /** |
a55360e4 | 679 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
680 | * |
681 | * Uses the priv->rx_handlers callback function array to invoke | |
682 | * the appropriate handlers, including command responses, | |
683 | * frame-received notifications, and other notifications. | |
684 | */ | |
f945f108 | 685 | static void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 686 | { |
a55360e4 | 687 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 688 | struct iwl_rx_packet *pkt; |
a55360e4 | 689 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
690 | u32 r, i; |
691 | int reclaim; | |
692 | unsigned long flags; | |
5c0eef96 | 693 | u8 fill_rx = 0; |
d68ab680 | 694 | u32 count = 8; |
4752c93c | 695 | int total_empty; |
b481de9c | 696 | |
6440adb5 CB |
697 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
698 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 699 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
700 | i = rxq->read; |
701 | ||
702 | /* Rx interrupt, but nothing sent from uCode */ | |
703 | if (i == r) | |
e1623446 | 704 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 705 | |
4752c93c | 706 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 707 | total_empty = r - rxq->write_actual; |
4752c93c MA |
708 | if (total_empty < 0) |
709 | total_empty += RX_QUEUE_SIZE; | |
710 | ||
711 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
712 | fill_rx = 1; |
713 | ||
b481de9c | 714 | while (i != r) { |
f4989d9b JB |
715 | int len; |
716 | ||
b481de9c ZY |
717 | rxb = rxq->queue[i]; |
718 | ||
9fbab516 | 719 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
720 | * then a bug has been introduced in the queue refilling |
721 | * routines -- catch it here */ | |
722 | BUG_ON(rxb == NULL); | |
723 | ||
724 | rxq->queue[i] = NULL; | |
725 | ||
2f301227 ZY |
726 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
727 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
728 | PCI_DMA_FROMDEVICE); | |
729 | pkt = rxb_addr(rxb); | |
b481de9c | 730 | |
f4989d9b JB |
731 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
732 | len += sizeof(u32); /* account for status word */ | |
733 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
be1a71a1 | 734 | |
b481de9c ZY |
735 | /* Reclaim a command buffer only if this packet is a response |
736 | * to a (driver-originated) command. | |
737 | * If the packet (e.g. Rx frame) originated from uCode, | |
738 | * there is no command buffer to reclaim. | |
739 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
740 | * but apparently a few don't get set; catch them here. */ | |
741 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
742 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 743 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 744 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 745 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
746 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
747 | (pkt->hdr.cmd != REPLY_TX); | |
748 | ||
7194207c JB |
749 | /* |
750 | * Do the notification wait before RX handlers so | |
751 | * even if the RX handler consumes the RXB we have | |
752 | * access to it in the notification wait entry. | |
753 | */ | |
754 | if (!list_empty(&priv->_agn.notif_waits)) { | |
755 | struct iwl_notification_wait *w; | |
756 | ||
757 | spin_lock(&priv->_agn.notif_wait_lock); | |
758 | list_for_each_entry(w, &priv->_agn.notif_waits, list) { | |
759 | if (w->cmd == pkt->hdr.cmd) { | |
760 | w->triggered = true; | |
761 | if (w->fn) | |
762 | w->fn(priv, pkt); | |
763 | } | |
764 | } | |
765 | spin_unlock(&priv->_agn.notif_wait_lock); | |
766 | ||
767 | wake_up_all(&priv->_agn.notif_waitq); | |
768 | } | |
769 | ||
b481de9c ZY |
770 | /* Based on type of command response or notification, |
771 | * handle those that need handling via function in | |
5b9f8cd3 | 772 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 773 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 774 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 775 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 776 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 777 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
778 | } else { |
779 | /* No handling needed */ | |
e1623446 | 780 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
781 | "r %d i %d No handler needed for %s, 0x%02x\n", |
782 | r, i, get_cmd_string(pkt->hdr.cmd), | |
783 | pkt->hdr.cmd); | |
784 | } | |
785 | ||
29b1b268 ZY |
786 | /* |
787 | * XXX: After here, we should always check rxb->page | |
788 | * against NULL before touching it or its virtual | |
789 | * memory (pkt). Because some rx_handler might have | |
790 | * already taken or freed the pages. | |
791 | */ | |
792 | ||
b481de9c | 793 | if (reclaim) { |
2f301227 ZY |
794 | /* Invoke any callbacks, transfer the buffer to caller, |
795 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 796 | * as we reclaim the driver command queue */ |
29b1b268 | 797 | if (rxb->page) |
17b88929 | 798 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 799 | else |
39aadf8c | 800 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
801 | } |
802 | ||
7300515d ZY |
803 | /* Reuse the page if possible. For notification packets and |
804 | * SKBs that fail to Rx correctly, add them back into the | |
805 | * rx_free list for reuse later. */ | |
806 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 807 | if (rxb->page != NULL) { |
7300515d ZY |
808 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
809 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
810 | PCI_DMA_FROMDEVICE); | |
811 | list_add_tail(&rxb->list, &rxq->rx_free); | |
812 | rxq->free_count++; | |
813 | } else | |
814 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 815 | |
b481de9c | 816 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 817 | |
b481de9c | 818 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
819 | /* If there are a lot of unused frames, |
820 | * restock the Rx queue so ucode wont assert. */ | |
821 | if (fill_rx) { | |
822 | count++; | |
823 | if (count >= 8) { | |
7300515d | 824 | rxq->read = i; |
54b81550 | 825 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
826 | count = 0; |
827 | } | |
828 | } | |
b481de9c ZY |
829 | } |
830 | ||
831 | /* Backtrack one entry */ | |
7300515d | 832 | rxq->read = i; |
4752c93c | 833 | if (fill_rx) |
54b81550 | 834 | iwlagn_rx_replenish_now(priv); |
4752c93c | 835 | else |
54b81550 | 836 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 837 | } |
a55360e4 | 838 | |
0359facc MA |
839 | /* call this function to flush any scheduled tasklet */ |
840 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
841 | { | |
a96a27f9 | 842 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
843 | synchronize_irq(priv->pci_dev->irq); |
844 | tasklet_kill(&priv->irq_tasklet); | |
845 | } | |
846 | ||
ef850d7c MA |
847 | /* tasklet for iwlagn interrupt */ |
848 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
849 | { | |
850 | u32 inta = 0; | |
851 | u32 handled = 0; | |
852 | unsigned long flags; | |
8756990f | 853 | u32 i; |
ef850d7c MA |
854 | #ifdef CONFIG_IWLWIFI_DEBUG |
855 | u32 inta_mask; | |
856 | #endif | |
857 | ||
858 | spin_lock_irqsave(&priv->lock, flags); | |
859 | ||
860 | /* Ack/clear/reset pending uCode interrupts. | |
861 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
862 | */ | |
48a6be6a SZ |
863 | /* There is a hardware bug in the interrupt mask function that some |
864 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
865 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
866 | * ICT interrupt handling mechanism has another bug that might cause | |
867 | * these unmasked interrupts fail to be detected. We workaround the | |
868 | * hardware bugs here by ACKing all the possible interrupts so that | |
869 | * interrupt coalescing can still be achieved. | |
870 | */ | |
4a35ecf8 | 871 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); |
ef850d7c | 872 | |
a4c8b2a6 | 873 | inta = priv->_agn.inta; |
ef850d7c MA |
874 | |
875 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 876 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
877 | /* just for debug */ |
878 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
879 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
880 | inta, inta_mask); | |
881 | } | |
882 | #endif | |
2f301227 ZY |
883 | |
884 | spin_unlock_irqrestore(&priv->lock, flags); | |
885 | ||
a4c8b2a6 JB |
886 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
887 | priv->_agn.inta = 0; | |
ef850d7c MA |
888 | |
889 | /* Now service all interrupt bits discovered above. */ | |
890 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 891 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
892 | |
893 | /* Tell the device to stop sending interrupts */ | |
894 | iwl_disable_interrupts(priv); | |
895 | ||
896 | priv->isr_stats.hw++; | |
897 | iwl_irq_handle_error(priv); | |
898 | ||
899 | handled |= CSR_INT_BIT_HW_ERR; | |
900 | ||
ef850d7c MA |
901 | return; |
902 | } | |
903 | ||
904 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 905 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
906 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
907 | if (inta & CSR_INT_BIT_SCD) { | |
908 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
909 | "the frame/frames.\n"); | |
910 | priv->isr_stats.sch++; | |
911 | } | |
912 | ||
913 | /* Alive notification via Rx interrupt will do the real work */ | |
914 | if (inta & CSR_INT_BIT_ALIVE) { | |
915 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
916 | priv->isr_stats.alive++; | |
917 | } | |
918 | } | |
919 | #endif | |
920 | /* Safely ignore these bits for debug checks below */ | |
921 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
922 | ||
923 | /* HW RF KILL switch toggled */ | |
924 | if (inta & CSR_INT_BIT_RF_KILL) { | |
925 | int hw_rf_kill = 0; | |
926 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
927 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
928 | hw_rf_kill = 1; | |
929 | ||
4c423a2b | 930 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
931 | hw_rf_kill ? "disable radio" : "enable radio"); |
932 | ||
933 | priv->isr_stats.rfkill++; | |
934 | ||
935 | /* driver only loads ucode once setting the interface up. | |
936 | * the driver allows loading the ucode even if the radio | |
937 | * is killed. Hence update the killswitch state here. The | |
938 | * rfkill handler will care about restarting if needed. | |
939 | */ | |
940 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
941 | if (hw_rf_kill) | |
942 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
943 | else | |
944 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 945 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
946 | } |
947 | ||
948 | handled |= CSR_INT_BIT_RF_KILL; | |
949 | } | |
950 | ||
951 | /* Chip got too hot and stopped itself */ | |
952 | if (inta & CSR_INT_BIT_CT_KILL) { | |
953 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
954 | priv->isr_stats.ctkill++; | |
955 | handled |= CSR_INT_BIT_CT_KILL; | |
956 | } | |
957 | ||
958 | /* Error detected by uCode */ | |
959 | if (inta & CSR_INT_BIT_SW_ERR) { | |
960 | IWL_ERR(priv, "Microcode SW error detected. " | |
961 | " Restarting 0x%X.\n", inta); | |
962 | priv->isr_stats.sw++; | |
ef850d7c MA |
963 | iwl_irq_handle_error(priv); |
964 | handled |= CSR_INT_BIT_SW_ERR; | |
965 | } | |
966 | ||
967 | /* uCode wakes up after power-down sleep */ | |
968 | if (inta & CSR_INT_BIT_WAKEUP) { | |
969 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
970 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
971 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
972 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
973 | |
974 | priv->isr_stats.wakeup++; | |
975 | ||
976 | handled |= CSR_INT_BIT_WAKEUP; | |
977 | } | |
978 | ||
979 | /* All uCode command responses, including Tx command responses, | |
980 | * Rx "responses" (frame-received notification), and other | |
981 | * notifications from uCode come through here*/ | |
40cefda9 MA |
982 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
983 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 984 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
985 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
986 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
987 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
f7d046f9 | 988 | CSR_FH_INT_RX_MASK); |
40cefda9 MA |
989 | } |
990 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
991 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
992 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
993 | } | |
994 | /* Sending RX interrupt require many steps to be done in the | |
995 | * the device: | |
996 | * 1- write interrupt to current index in ICT table. | |
997 | * 2- dma RX frame. | |
998 | * 3- update RX shared data to indicate last write index. | |
999 | * 4- send interrupt. | |
1000 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1001 | * but the shared data changes does not reflect this; |
1002 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1003 | */ |
74ba67ed BC |
1004 | |
1005 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1006 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1007 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1008 | iwl_rx_handle(priv); |
74ba67ed BC |
1009 | |
1010 | /* | |
1011 | * Enable periodic interrupt in 8 msec only if we received | |
1012 | * real RX interrupt (instead of just periodic int), to catch | |
1013 | * any dangling Rx interrupt. If it was just the periodic | |
1014 | * interrupt, there was no dangling Rx activity, and no need | |
1015 | * to extend the periodic interrupt; one-shot is enough. | |
1016 | */ | |
40cefda9 | 1017 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1018 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1019 | CSR_INT_PERIODIC_ENA); |
1020 | ||
ef850d7c | 1021 | priv->isr_stats.rx++; |
ef850d7c MA |
1022 | } |
1023 | ||
c72cd19f | 1024 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c | 1025 | if (inta & CSR_INT_BIT_FH_TX) { |
f7d046f9 | 1026 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
c72cd19f | 1027 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1028 | priv->isr_stats.tx++; |
1029 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1030 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1031 | priv->ucode_write_complete = 1; |
1032 | wake_up_interruptible(&priv->wait_command_queue); | |
1033 | } | |
1034 | ||
1035 | if (inta & ~handled) { | |
1036 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1037 | priv->isr_stats.unhandled++; | |
1038 | } | |
1039 | ||
40cefda9 | 1040 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1041 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1042 | inta & ~priv->inta_mask); |
ef850d7c MA |
1043 | } |
1044 | ||
ef850d7c | 1045 | /* Re-enable all interrupts */ |
62e45c14 | 1046 | /* only Re-enable if disabled by irq */ |
ef850d7c MA |
1047 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) |
1048 | iwl_enable_interrupts(priv); | |
3dd823e6 DF |
1049 | /* Re-enable RF_KILL if it occurred */ |
1050 | else if (handled & CSR_INT_BIT_RF_KILL) | |
1051 | iwl_enable_rfkill_int(priv); | |
ef850d7c MA |
1052 | } |
1053 | ||
7d47618a EG |
1054 | /***************************************************************************** |
1055 | * | |
1056 | * sysfs attributes | |
1057 | * | |
1058 | *****************************************************************************/ | |
1059 | ||
1060 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1061 | ||
1062 | /* | |
1063 | * The following adds a new attribute to the sysfs representation | |
1064 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
1065 | * used for controlling the debug level. | |
1066 | * | |
1067 | * See the level definitions in iwl for details. | |
1068 | * | |
1069 | * The debug_level being managed using sysfs below is a per device debug | |
1070 | * level that is used instead of the global debug level if it (the per | |
1071 | * device debug level) is set. | |
1072 | */ | |
1073 | static ssize_t show_debug_level(struct device *d, | |
1074 | struct device_attribute *attr, char *buf) | |
1075 | { | |
1076 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1077 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
1078 | } | |
1079 | static ssize_t store_debug_level(struct device *d, | |
1080 | struct device_attribute *attr, | |
1081 | const char *buf, size_t count) | |
1082 | { | |
1083 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1084 | unsigned long val; | |
1085 | int ret; | |
1086 | ||
1087 | ret = strict_strtoul(buf, 0, &val); | |
1088 | if (ret) | |
1089 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); | |
1090 | else { | |
1091 | priv->debug_level = val; | |
1092 | if (iwl_alloc_traffic_mem(priv)) | |
1093 | IWL_ERR(priv, | |
1094 | "Not enough memory to generate traffic log\n"); | |
1095 | } | |
1096 | return strnlen(buf, count); | |
1097 | } | |
1098 | ||
1099 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
1100 | show_debug_level, store_debug_level); | |
1101 | ||
1102 | ||
1103 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
1104 | ||
1105 | ||
1106 | static ssize_t show_temperature(struct device *d, | |
1107 | struct device_attribute *attr, char *buf) | |
1108 | { | |
1109 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1110 | ||
1111 | if (!iwl_is_alive(priv)) | |
1112 | return -EAGAIN; | |
1113 | ||
1114 | return sprintf(buf, "%d\n", priv->temperature); | |
1115 | } | |
1116 | ||
1117 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
1118 | ||
1119 | static ssize_t show_tx_power(struct device *d, | |
1120 | struct device_attribute *attr, char *buf) | |
1121 | { | |
1122 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1123 | ||
1124 | if (!iwl_is_ready_rf(priv)) | |
1125 | return sprintf(buf, "off\n"); | |
1126 | else | |
1127 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
1128 | } | |
1129 | ||
1130 | static ssize_t store_tx_power(struct device *d, | |
1131 | struct device_attribute *attr, | |
1132 | const char *buf, size_t count) | |
1133 | { | |
1134 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1135 | unsigned long val; | |
1136 | int ret; | |
1137 | ||
1138 | ret = strict_strtoul(buf, 10, &val); | |
1139 | if (ret) | |
1140 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); | |
1141 | else { | |
1142 | ret = iwl_set_tx_power(priv, val, false); | |
1143 | if (ret) | |
1144 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
1145 | ret); | |
1146 | else | |
1147 | ret = count; | |
1148 | } | |
1149 | return ret; | |
1150 | } | |
1151 | ||
1152 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
1153 | ||
7d47618a EG |
1154 | static struct attribute *iwl_sysfs_entries[] = { |
1155 | &dev_attr_temperature.attr, | |
1156 | &dev_attr_tx_power.attr, | |
7d47618a EG |
1157 | #ifdef CONFIG_IWLWIFI_DEBUG |
1158 | &dev_attr_debug_level.attr, | |
1159 | #endif | |
1160 | NULL | |
1161 | }; | |
1162 | ||
1163 | static struct attribute_group iwl_attribute_group = { | |
1164 | .name = NULL, /* put in device directory */ | |
1165 | .attrs = iwl_sysfs_entries, | |
1166 | }; | |
1167 | ||
b481de9c ZY |
1168 | /****************************************************************************** |
1169 | * | |
1170 | * uCode download functions | |
1171 | * | |
1172 | ******************************************************************************/ | |
1173 | ||
5b9f8cd3 | 1174 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1175 | { |
98c92211 TW |
1176 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1177 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
98c92211 TW |
1178 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); |
1179 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
b481de9c ZY |
1180 | } |
1181 | ||
5b9f8cd3 | 1182 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1183 | { |
1184 | /* Remove all resets to allow NIC to operate */ | |
1185 | iwl_write32(priv, CSR_RESET, 0); | |
1186 | } | |
1187 | ||
dd7a2509 JB |
1188 | struct iwlagn_ucode_capabilities { |
1189 | u32 max_probe_length; | |
6a822d06 | 1190 | u32 standard_phy_calibration_size; |
3997ff39 | 1191 | u32 flags; |
dd7a2509 | 1192 | }; |
edcdf8b2 | 1193 | |
b08dfd04 | 1194 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
dd7a2509 JB |
1195 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
1196 | struct iwlagn_ucode_capabilities *capa); | |
b08dfd04 | 1197 | |
39396085 JS |
1198 | #define UCODE_EXPERIMENTAL_INDEX 100 |
1199 | #define UCODE_EXPERIMENTAL_TAG "exp" | |
1200 | ||
b08dfd04 JB |
1201 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) |
1202 | { | |
1203 | const char *name_pre = priv->cfg->fw_name_pre; | |
39396085 | 1204 | char tag[8]; |
b08dfd04 | 1205 | |
39396085 JS |
1206 | if (first) { |
1207 | #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE | |
1208 | priv->fw_index = UCODE_EXPERIMENTAL_INDEX; | |
1209 | strcpy(tag, UCODE_EXPERIMENTAL_TAG); | |
1210 | } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) { | |
1211 | #endif | |
b08dfd04 | 1212 | priv->fw_index = priv->cfg->ucode_api_max; |
39396085 JS |
1213 | sprintf(tag, "%d", priv->fw_index); |
1214 | } else { | |
b08dfd04 | 1215 | priv->fw_index--; |
39396085 JS |
1216 | sprintf(tag, "%d", priv->fw_index); |
1217 | } | |
b08dfd04 JB |
1218 | |
1219 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1220 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1221 | return -ENOENT; | |
1222 | } | |
1223 | ||
39396085 | 1224 | sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); |
b08dfd04 | 1225 | |
39396085 JS |
1226 | IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n", |
1227 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1228 | ? "EXPERIMENTAL " : "", | |
b08dfd04 JB |
1229 | priv->firmware_name); |
1230 | ||
1231 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1232 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1233 | iwl_ucode_callback); | |
1234 | } | |
1235 | ||
0e9a44dc | 1236 | struct iwlagn_firmware_pieces { |
1fc35276 JB |
1237 | const void *inst, *data, *init, *init_data; |
1238 | size_t inst_size, data_size, init_size, init_data_size; | |
0e9a44dc JB |
1239 | |
1240 | u32 build; | |
b2e640d4 JB |
1241 | |
1242 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1243 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
0e9a44dc JB |
1244 | }; |
1245 | ||
1246 | static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |
1247 | const struct firmware *ucode_raw, | |
1248 | struct iwlagn_firmware_pieces *pieces) | |
1249 | { | |
1250 | struct iwl_ucode_header *ucode = (void *)ucode_raw->data; | |
1251 | u32 api_ver, hdr_size; | |
1252 | const u8 *src; | |
1253 | ||
1254 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1255 | api_ver = IWL_UCODE_API(priv->ucode_ver); | |
1256 | ||
1257 | switch (api_ver) { | |
1258 | default: | |
f7d046f9 WYG |
1259 | hdr_size = 28; |
1260 | if (ucode_raw->size < hdr_size) { | |
1261 | IWL_ERR(priv, "File size too small!\n"); | |
1262 | return -EINVAL; | |
0e9a44dc | 1263 | } |
f7d046f9 WYG |
1264 | pieces->build = le32_to_cpu(ucode->u.v2.build); |
1265 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | |
1266 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | |
1267 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | |
1268 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | |
f7d046f9 WYG |
1269 | src = ucode->u.v2.data; |
1270 | break; | |
0e9a44dc JB |
1271 | case 0: |
1272 | case 1: | |
1273 | case 2: | |
1274 | hdr_size = 24; | |
1275 | if (ucode_raw->size < hdr_size) { | |
1276 | IWL_ERR(priv, "File size too small!\n"); | |
1277 | return -EINVAL; | |
1278 | } | |
1279 | pieces->build = 0; | |
1280 | pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size); | |
1281 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | |
1282 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | |
1283 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | |
0e9a44dc JB |
1284 | src = ucode->u.v1.data; |
1285 | break; | |
1286 | } | |
1287 | ||
1288 | /* Verify size of file vs. image size info in file's header */ | |
1289 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1290 | pieces->data_size + pieces->init_size + | |
1fc35276 | 1291 | pieces->init_data_size) { |
0e9a44dc JB |
1292 | |
1293 | IWL_ERR(priv, | |
1294 | "uCode file size %d does not match expected size\n", | |
1295 | (int)ucode_raw->size); | |
1296 | return -EINVAL; | |
1297 | } | |
1298 | ||
1299 | pieces->inst = src; | |
1300 | src += pieces->inst_size; | |
1301 | pieces->data = src; | |
1302 | src += pieces->data_size; | |
1303 | pieces->init = src; | |
1304 | src += pieces->init_size; | |
1305 | pieces->init_data = src; | |
1306 | src += pieces->init_data_size; | |
0e9a44dc JB |
1307 | |
1308 | return 0; | |
1309 | } | |
1310 | ||
dd7a2509 JB |
1311 | static int iwlagn_wanted_ucode_alternative = 1; |
1312 | ||
1313 | static int iwlagn_load_firmware(struct iwl_priv *priv, | |
1314 | const struct firmware *ucode_raw, | |
1315 | struct iwlagn_firmware_pieces *pieces, | |
1316 | struct iwlagn_ucode_capabilities *capa) | |
1317 | { | |
1318 | struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data; | |
1319 | struct iwl_ucode_tlv *tlv; | |
1320 | size_t len = ucode_raw->size; | |
1321 | const u8 *data; | |
1322 | int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp; | |
1323 | u64 alternatives; | |
ad8d8333 WYG |
1324 | u32 tlv_len; |
1325 | enum iwl_ucode_tlv_type tlv_type; | |
1326 | const u8 *tlv_data; | |
dd7a2509 | 1327 | |
ad8d8333 WYG |
1328 | if (len < sizeof(*ucode)) { |
1329 | IWL_ERR(priv, "uCode has invalid length: %zd\n", len); | |
dd7a2509 | 1330 | return -EINVAL; |
ad8d8333 | 1331 | } |
dd7a2509 | 1332 | |
ad8d8333 WYG |
1333 | if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) { |
1334 | IWL_ERR(priv, "invalid uCode magic: 0X%x\n", | |
1335 | le32_to_cpu(ucode->magic)); | |
dd7a2509 | 1336 | return -EINVAL; |
ad8d8333 | 1337 | } |
dd7a2509 JB |
1338 | |
1339 | /* | |
1340 | * Check which alternatives are present, and "downgrade" | |
1341 | * when the chosen alternative is not present, warning | |
1342 | * the user when that happens. Some files may not have | |
1343 | * any alternatives, so don't warn in that case. | |
1344 | */ | |
1345 | alternatives = le64_to_cpu(ucode->alternatives); | |
1346 | tmp = wanted_alternative; | |
1347 | if (wanted_alternative > 63) | |
1348 | wanted_alternative = 63; | |
1349 | while (wanted_alternative && !(alternatives & BIT(wanted_alternative))) | |
1350 | wanted_alternative--; | |
1351 | if (wanted_alternative && wanted_alternative != tmp) | |
1352 | IWL_WARN(priv, | |
1353 | "uCode alternative %d not available, choosing %d\n", | |
1354 | tmp, wanted_alternative); | |
1355 | ||
1356 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1357 | pieces->build = le32_to_cpu(ucode->build); | |
1358 | data = ucode->data; | |
1359 | ||
1360 | len -= sizeof(*ucode); | |
1361 | ||
704da534 | 1362 | while (len >= sizeof(*tlv)) { |
dd7a2509 | 1363 | u16 tlv_alt; |
dd7a2509 JB |
1364 | |
1365 | len -= sizeof(*tlv); | |
1366 | tlv = (void *)data; | |
1367 | ||
1368 | tlv_len = le32_to_cpu(tlv->length); | |
1369 | tlv_type = le16_to_cpu(tlv->type); | |
1370 | tlv_alt = le16_to_cpu(tlv->alternative); | |
1371 | tlv_data = tlv->data; | |
1372 | ||
ad8d8333 WYG |
1373 | if (len < tlv_len) { |
1374 | IWL_ERR(priv, "invalid TLV len: %zd/%u\n", | |
1375 | len, tlv_len); | |
dd7a2509 | 1376 | return -EINVAL; |
ad8d8333 | 1377 | } |
dd7a2509 JB |
1378 | len -= ALIGN(tlv_len, 4); |
1379 | data += sizeof(*tlv) + ALIGN(tlv_len, 4); | |
1380 | ||
1381 | /* | |
1382 | * Alternative 0 is always valid. | |
1383 | * | |
1384 | * Skip alternative TLVs that are not selected. | |
1385 | */ | |
1386 | if (tlv_alt != 0 && tlv_alt != wanted_alternative) | |
1387 | continue; | |
1388 | ||
1389 | switch (tlv_type) { | |
1390 | case IWL_UCODE_TLV_INST: | |
1391 | pieces->inst = tlv_data; | |
1392 | pieces->inst_size = tlv_len; | |
1393 | break; | |
1394 | case IWL_UCODE_TLV_DATA: | |
1395 | pieces->data = tlv_data; | |
1396 | pieces->data_size = tlv_len; | |
1397 | break; | |
1398 | case IWL_UCODE_TLV_INIT: | |
1399 | pieces->init = tlv_data; | |
1400 | pieces->init_size = tlv_len; | |
1401 | break; | |
1402 | case IWL_UCODE_TLV_INIT_DATA: | |
1403 | pieces->init_data = tlv_data; | |
1404 | pieces->init_data_size = tlv_len; | |
1405 | break; | |
1406 | case IWL_UCODE_TLV_BOOT: | |
1fc35276 | 1407 | IWL_ERR(priv, "Found unexpected BOOT ucode\n"); |
dd7a2509 JB |
1408 | break; |
1409 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | |
704da534 JB |
1410 | if (tlv_len != sizeof(u32)) |
1411 | goto invalid_tlv_len; | |
1412 | capa->max_probe_length = | |
ad8d8333 | 1413 | le32_to_cpup((__le32 *)tlv_data); |
dd7a2509 | 1414 | break; |
ece9c4ee JB |
1415 | case IWL_UCODE_TLV_PAN: |
1416 | if (tlv_len) | |
1417 | goto invalid_tlv_len; | |
3997ff39 JB |
1418 | capa->flags |= IWL_UCODE_TLV_FLAGS_PAN; |
1419 | break; | |
1420 | case IWL_UCODE_TLV_FLAGS: | |
1421 | /* must be at least one u32 */ | |
1422 | if (tlv_len < sizeof(u32)) | |
1423 | goto invalid_tlv_len; | |
1424 | /* and a proper number of u32s */ | |
1425 | if (tlv_len % sizeof(u32)) | |
1426 | goto invalid_tlv_len; | |
1427 | /* | |
1428 | * This driver only reads the first u32 as | |
1429 | * right now no more features are defined, | |
1430 | * if that changes then either the driver | |
1431 | * will not work with the new firmware, or | |
1432 | * it'll not take advantage of new features. | |
1433 | */ | |
1434 | capa->flags = le32_to_cpup((__le32 *)tlv_data); | |
ece9c4ee | 1435 | break; |
b2e640d4 | 1436 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
704da534 JB |
1437 | if (tlv_len != sizeof(u32)) |
1438 | goto invalid_tlv_len; | |
1439 | pieces->init_evtlog_ptr = | |
ad8d8333 | 1440 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1441 | break; |
1442 | case IWL_UCODE_TLV_INIT_EVTLOG_SIZE: | |
704da534 JB |
1443 | if (tlv_len != sizeof(u32)) |
1444 | goto invalid_tlv_len; | |
1445 | pieces->init_evtlog_size = | |
ad8d8333 | 1446 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1447 | break; |
1448 | case IWL_UCODE_TLV_INIT_ERRLOG_PTR: | |
704da534 JB |
1449 | if (tlv_len != sizeof(u32)) |
1450 | goto invalid_tlv_len; | |
1451 | pieces->init_errlog_ptr = | |
ad8d8333 | 1452 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1453 | break; |
1454 | case IWL_UCODE_TLV_RUNT_EVTLOG_PTR: | |
704da534 JB |
1455 | if (tlv_len != sizeof(u32)) |
1456 | goto invalid_tlv_len; | |
1457 | pieces->inst_evtlog_ptr = | |
ad8d8333 | 1458 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1459 | break; |
1460 | case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE: | |
704da534 JB |
1461 | if (tlv_len != sizeof(u32)) |
1462 | goto invalid_tlv_len; | |
1463 | pieces->inst_evtlog_size = | |
ad8d8333 | 1464 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1465 | break; |
1466 | case IWL_UCODE_TLV_RUNT_ERRLOG_PTR: | |
704da534 JB |
1467 | if (tlv_len != sizeof(u32)) |
1468 | goto invalid_tlv_len; | |
1469 | pieces->inst_errlog_ptr = | |
ad8d8333 | 1470 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 | 1471 | break; |
c8312fac WYG |
1472 | case IWL_UCODE_TLV_ENHANCE_SENS_TBL: |
1473 | if (tlv_len) | |
704da534 JB |
1474 | goto invalid_tlv_len; |
1475 | priv->enhance_sensitivity_table = true; | |
c8312fac | 1476 | break; |
6a822d06 | 1477 | case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE: |
704da534 JB |
1478 | if (tlv_len != sizeof(u32)) |
1479 | goto invalid_tlv_len; | |
1480 | capa->standard_phy_calibration_size = | |
6a822d06 WYG |
1481 | le32_to_cpup((__le32 *)tlv_data); |
1482 | break; | |
dd7a2509 | 1483 | default: |
ad8d8333 | 1484 | IWL_WARN(priv, "unknown TLV: %d\n", tlv_type); |
dd7a2509 JB |
1485 | break; |
1486 | } | |
1487 | } | |
1488 | ||
ad8d8333 WYG |
1489 | if (len) { |
1490 | IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len); | |
1491 | iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len); | |
704da534 | 1492 | return -EINVAL; |
ad8d8333 | 1493 | } |
dd7a2509 | 1494 | |
704da534 JB |
1495 | return 0; |
1496 | ||
1497 | invalid_tlv_len: | |
1498 | IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len); | |
1499 | iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len); | |
1500 | ||
1501 | return -EINVAL; | |
dd7a2509 JB |
1502 | } |
1503 | ||
b481de9c | 1504 | /** |
b08dfd04 | 1505 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1506 | * |
b08dfd04 JB |
1507 | * If loaded successfully, copies the firmware into buffers |
1508 | * for the card to fetch (via DMA). | |
b481de9c | 1509 | */ |
b08dfd04 | 1510 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1511 | { |
b08dfd04 | 1512 | struct iwl_priv *priv = context; |
cc0f555d | 1513 | struct iwl_ucode_header *ucode; |
0e9a44dc JB |
1514 | int err; |
1515 | struct iwlagn_firmware_pieces pieces; | |
a0987a8d RC |
1516 | const unsigned int api_max = priv->cfg->ucode_api_max; |
1517 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
0e9a44dc | 1518 | u32 api_ver; |
3e4de761 | 1519 | char buildstr[25]; |
0e9a44dc | 1520 | u32 build; |
dd7a2509 JB |
1521 | struct iwlagn_ucode_capabilities ucode_capa = { |
1522 | .max_probe_length = 200, | |
6a822d06 | 1523 | .standard_phy_calibration_size = |
642454cc | 1524 | IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE, |
dd7a2509 | 1525 | }; |
0e9a44dc JB |
1526 | |
1527 | memset(&pieces, 0, sizeof(pieces)); | |
b481de9c | 1528 | |
b08dfd04 | 1529 | if (!ucode_raw) { |
39396085 JS |
1530 | if (priv->fw_index <= priv->cfg->ucode_api_max) |
1531 | IWL_ERR(priv, | |
1532 | "request for firmware file '%s' failed.\n", | |
1533 | priv->firmware_name); | |
b08dfd04 | 1534 | goto try_again; |
b481de9c ZY |
1535 | } |
1536 | ||
b08dfd04 JB |
1537 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
1538 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 1539 | |
22adba2a JB |
1540 | /* Make sure that we got at least the API version number */ |
1541 | if (ucode_raw->size < 4) { | |
15b1687c | 1542 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 1543 | goto try_again; |
b481de9c ZY |
1544 | } |
1545 | ||
1546 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1547 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1548 | |
0e9a44dc JB |
1549 | if (ucode->ver) |
1550 | err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces); | |
1551 | else | |
dd7a2509 JB |
1552 | err = iwlagn_load_firmware(priv, ucode_raw, &pieces, |
1553 | &ucode_capa); | |
22adba2a | 1554 | |
0e9a44dc JB |
1555 | if (err) |
1556 | goto try_again; | |
b481de9c | 1557 | |
a0987a8d | 1558 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
0e9a44dc | 1559 | build = pieces.build; |
a0987a8d | 1560 | |
0e9a44dc JB |
1561 | /* |
1562 | * api_ver should match the api version forming part of the | |
1563 | * firmware filename ... but we don't check for that and only rely | |
1564 | * on the API version read from firmware header from here on forward | |
1565 | */ | |
65cccfb0 WYG |
1566 | /* no api version check required for experimental uCode */ |
1567 | if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) { | |
1568 | if (api_ver < api_min || api_ver > api_max) { | |
1569 | IWL_ERR(priv, | |
1570 | "Driver unable to support your firmware API. " | |
1571 | "Driver supports v%u, firmware is v%u.\n", | |
1572 | api_max, api_ver); | |
1573 | goto try_again; | |
1574 | } | |
b08dfd04 | 1575 | |
65cccfb0 WYG |
1576 | if (api_ver != api_max) |
1577 | IWL_ERR(priv, | |
1578 | "Firmware has old API version. Expected v%u, " | |
1579 | "got v%u. New firmware can be obtained " | |
1580 | "from http://www.intellinuxwireless.org.\n", | |
1581 | api_max, api_ver); | |
1582 | } | |
a0987a8d | 1583 | |
3e4de761 | 1584 | if (build) |
39396085 JS |
1585 | sprintf(buildstr, " build %u%s", build, |
1586 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1587 | ? " (EXP)" : ""); | |
3e4de761 JB |
1588 | else |
1589 | buildstr[0] = '\0'; | |
1590 | ||
1591 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n", | |
1592 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1593 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1594 | IWL_UCODE_API(priv->ucode_ver), | |
1595 | IWL_UCODE_SERIAL(priv->ucode_ver), | |
1596 | buildstr); | |
a0987a8d | 1597 | |
5ebeb5a6 RC |
1598 | snprintf(priv->hw->wiphy->fw_version, |
1599 | sizeof(priv->hw->wiphy->fw_version), | |
3e4de761 | 1600 | "%u.%u.%u.%u%s", |
5ebeb5a6 RC |
1601 | IWL_UCODE_MAJOR(priv->ucode_ver), |
1602 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1603 | IWL_UCODE_API(priv->ucode_ver), | |
3e4de761 JB |
1604 | IWL_UCODE_SERIAL(priv->ucode_ver), |
1605 | buildstr); | |
b481de9c | 1606 | |
b08dfd04 JB |
1607 | /* |
1608 | * For any of the failures below (before allocating pci memory) | |
1609 | * we will try to load a version with a smaller API -- maybe the | |
1610 | * user just got a corrupted version of the latest API. | |
1611 | */ | |
1612 | ||
0e9a44dc JB |
1613 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
1614 | priv->ucode_ver); | |
1615 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n", | |
1616 | pieces.inst_size); | |
1617 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n", | |
1618 | pieces.data_size); | |
1619 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n", | |
1620 | pieces.init_size); | |
1621 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | |
1622 | pieces.init_data_size); | |
b481de9c ZY |
1623 | |
1624 | /* Verify that uCode images will fit in card's SRAM */ | |
0e9a44dc JB |
1625 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
1626 | IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n", | |
1627 | pieces.inst_size); | |
b08dfd04 | 1628 | goto try_again; |
b481de9c ZY |
1629 | } |
1630 | ||
0e9a44dc JB |
1631 | if (pieces.data_size > priv->hw_params.max_data_size) { |
1632 | IWL_ERR(priv, "uCode data len %Zd too large to fit in\n", | |
1633 | pieces.data_size); | |
b08dfd04 | 1634 | goto try_again; |
b481de9c | 1635 | } |
0e9a44dc JB |
1636 | |
1637 | if (pieces.init_size > priv->hw_params.max_inst_size) { | |
1638 | IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n", | |
1639 | pieces.init_size); | |
b08dfd04 | 1640 | goto try_again; |
b481de9c | 1641 | } |
0e9a44dc JB |
1642 | |
1643 | if (pieces.init_data_size > priv->hw_params.max_data_size) { | |
1644 | IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n", | |
1645 | pieces.init_data_size); | |
b08dfd04 | 1646 | goto try_again; |
b481de9c | 1647 | } |
0e9a44dc | 1648 | |
b481de9c ZY |
1649 | /* Allocate ucode buffers for card's bus-master loading ... */ |
1650 | ||
1651 | /* Runtime instructions and 2 copies of data: | |
1652 | * 1) unmodified from disk | |
1653 | * 2) backup cache for save/restore during power-downs */ | |
0e9a44dc | 1654 | priv->ucode_code.len = pieces.inst_size; |
98c92211 | 1655 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c | 1656 | |
0e9a44dc | 1657 | priv->ucode_data.len = pieces.data_size; |
98c92211 | 1658 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c | 1659 | |
6009c39c | 1660 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr) |
1f304e4e ZY |
1661 | goto err_pci_alloc; |
1662 | ||
b481de9c | 1663 | /* Initialization instructions and data */ |
0e9a44dc JB |
1664 | if (pieces.init_size && pieces.init_data_size) { |
1665 | priv->ucode_init.len = pieces.init_size; | |
98c92211 | 1666 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 | 1667 | |
0e9a44dc | 1668 | priv->ucode_init_data.len = pieces.init_data_size; |
98c92211 | 1669 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1670 | |
1671 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1672 | goto err_pci_alloc; | |
1673 | } | |
b481de9c | 1674 | |
b2e640d4 JB |
1675 | /* Now that we can no longer fail, copy information */ |
1676 | ||
1677 | /* | |
1678 | * The (size - 16) / 12 formula is based on the information recorded | |
1679 | * for each event, which is of mode 1 (including timestamp) for all | |
1680 | * new microcodes that include this information. | |
1681 | */ | |
1682 | priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; | |
1683 | if (pieces.init_evtlog_size) | |
1684 | priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; | |
1685 | else | |
7cb1b088 WYG |
1686 | priv->_agn.init_evtlog_size = |
1687 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
1688 | priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; |
1689 | priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; | |
1690 | if (pieces.inst_evtlog_size) | |
1691 | priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; | |
1692 | else | |
7cb1b088 WYG |
1693 | priv->_agn.inst_evtlog_size = |
1694 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
1695 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; |
1696 | ||
3997ff39 | 1697 | if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) { |
ece9c4ee | 1698 | priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); |
c10afb6e | 1699 | priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN; |
ece9c4ee JB |
1700 | } else |
1701 | priv->sta_key_max_num = STA_KEY_MAX_NUM; | |
c10afb6e | 1702 | |
17445b8c JB |
1703 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
1704 | priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM; | |
1705 | else | |
1706 | priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM; | |
1707 | ||
3997ff39 JB |
1708 | if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_BTSTATS || |
1709 | (priv->cfg->bt_params && priv->cfg->bt_params->bt_statistics)) | |
1710 | priv->bt_statistics = true; | |
1711 | ||
b481de9c ZY |
1712 | /* Copy images into buffers for card's bus-master reads ... */ |
1713 | ||
1714 | /* Runtime instructions (first block of data in file) */ | |
0e9a44dc JB |
1715 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", |
1716 | pieces.inst_size); | |
1717 | memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size); | |
cc0f555d | 1718 | |
e1623446 | 1719 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1720 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1721 | ||
0e9a44dc JB |
1722 | /* |
1723 | * Runtime data | |
1724 | * NOTE: Copy into backup buffer will be done in iwl_up() | |
1725 | */ | |
1726 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", | |
1727 | pieces.data_size); | |
1728 | memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size); | |
0e9a44dc JB |
1729 | |
1730 | /* Initialization instructions */ | |
1731 | if (pieces.init_size) { | |
e1623446 | 1732 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
0e9a44dc JB |
1733 | pieces.init_size); |
1734 | memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size); | |
b481de9c ZY |
1735 | } |
1736 | ||
0e9a44dc JB |
1737 | /* Initialization data */ |
1738 | if (pieces.init_data_size) { | |
e1623446 | 1739 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
0e9a44dc JB |
1740 | pieces.init_data_size); |
1741 | memcpy(priv->ucode_init_data.v_addr, pieces.init_data, | |
1742 | pieces.init_data_size); | |
b481de9c ZY |
1743 | } |
1744 | ||
6a822d06 WYG |
1745 | /* |
1746 | * figure out the offset of chain noise reset and gain commands | |
1747 | * base on the size of standard phy calibration commands table size | |
1748 | */ | |
1749 | if (ucode_capa.standard_phy_calibration_size > | |
1750 | IWL_MAX_PHY_CALIBRATE_TBL_SIZE) | |
1751 | ucode_capa.standard_phy_calibration_size = | |
1752 | IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE; | |
1753 | ||
1754 | priv->_agn.phy_calib_chain_noise_reset_cmd = | |
1755 | ucode_capa.standard_phy_calibration_size; | |
1756 | priv->_agn.phy_calib_chain_noise_gain_cmd = | |
1757 | ucode_capa.standard_phy_calibration_size + 1; | |
1758 | ||
b08dfd04 JB |
1759 | /************************************************** |
1760 | * This is still part of probe() in a sense... | |
1761 | * | |
1762 | * 9. Setup and register with mac80211 and debugfs | |
1763 | **************************************************/ | |
dd7a2509 | 1764 | err = iwl_mac_setup_register(priv, &ucode_capa); |
b08dfd04 JB |
1765 | if (err) |
1766 | goto out_unbind; | |
1767 | ||
1768 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
1769 | if (err) | |
1770 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
1771 | ||
7d47618a EG |
1772 | err = sysfs_create_group(&priv->pci_dev->dev.kobj, |
1773 | &iwl_attribute_group); | |
1774 | if (err) { | |
1775 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); | |
1776 | goto out_unbind; | |
1777 | } | |
1778 | ||
b481de9c ZY |
1779 | /* We have our copies now, allow OS release its copies */ |
1780 | release_firmware(ucode_raw); | |
a15707d8 | 1781 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 JB |
1782 | return; |
1783 | ||
1784 | try_again: | |
1785 | /* try next, if any */ | |
1786 | if (iwl_request_firmware(priv, false)) | |
1787 | goto out_unbind; | |
1788 | release_firmware(ucode_raw); | |
1789 | return; | |
b481de9c ZY |
1790 | |
1791 | err_pci_alloc: | |
15b1687c | 1792 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 1793 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 | 1794 | out_unbind: |
a15707d8 | 1795 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 | 1796 | device_release_driver(&priv->pci_dev->dev); |
b481de9c | 1797 | release_firmware(ucode_raw); |
b481de9c ZY |
1798 | } |
1799 | ||
b7a79404 RC |
1800 | static const char *desc_lookup_text[] = { |
1801 | "OK", | |
1802 | "FAIL", | |
1803 | "BAD_PARAM", | |
1804 | "BAD_CHECKSUM", | |
1805 | "NMI_INTERRUPT_WDG", | |
1806 | "SYSASSERT", | |
1807 | "FATAL_ERROR", | |
1808 | "BAD_COMMAND", | |
1809 | "HW_ERROR_TUNE_LOCK", | |
1810 | "HW_ERROR_TEMPERATURE", | |
1811 | "ILLEGAL_CHAN_FREQ", | |
1812 | "VCC_NOT_STABLE", | |
1813 | "FH_ERROR", | |
1814 | "NMI_INTERRUPT_HOST", | |
1815 | "NMI_INTERRUPT_ACTION_PT", | |
1816 | "NMI_INTERRUPT_UNKNOWN", | |
1817 | "UCODE_VERSION_MISMATCH", | |
1818 | "HW_ERROR_ABS_LOCK", | |
1819 | "HW_ERROR_CAL_LOCK_FAIL", | |
1820 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1821 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1822 | "NMI_TRM_HW_ER", | |
1823 | "NMI_INTERRUPT_TRM", | |
1824 | "NMI_INTERRUPT_BREAK_POINT" | |
1825 | "DEBUG_0", | |
1826 | "DEBUG_1", | |
1827 | "DEBUG_2", | |
1828 | "DEBUG_3", | |
b7a79404 RC |
1829 | }; |
1830 | ||
4b58645c JS |
1831 | static struct { char *name; u8 num; } advanced_lookup[] = { |
1832 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
1833 | { "SYSASSERT", 0x35 }, | |
1834 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
1835 | { "BAD_COMMAND", 0x38 }, | |
1836 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
1837 | { "FATAL_ERROR", 0x3D }, | |
1838 | { "NMI_TRM_HW_ERR", 0x46 }, | |
1839 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
1840 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
1841 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
1842 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
1843 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
1844 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
1845 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
1846 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
1847 | { "ADVANCED_SYSASSERT", 0 }, | |
1848 | }; | |
1849 | ||
1850 | static const char *desc_lookup(u32 num) | |
b7a79404 | 1851 | { |
4b58645c JS |
1852 | int i; |
1853 | int max = ARRAY_SIZE(desc_lookup_text); | |
b7a79404 | 1854 | |
4b58645c JS |
1855 | if (num < max) |
1856 | return desc_lookup_text[num]; | |
b7a79404 | 1857 | |
4b58645c JS |
1858 | max = ARRAY_SIZE(advanced_lookup) - 1; |
1859 | for (i = 0; i < max; i++) { | |
1860 | if (advanced_lookup[i].num == num) | |
1861 | break;; | |
1862 | } | |
1863 | return advanced_lookup[i].name; | |
b7a79404 RC |
1864 | } |
1865 | ||
1866 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1867 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1868 | ||
1869 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1870 | { | |
1871 | u32 data2, line; | |
1872 | u32 desc, time, count, base, data1; | |
1873 | u32 blink1, blink2, ilink1, ilink2; | |
461ef382 | 1874 | u32 pc, hcmd; |
b7a79404 | 1875 | |
d7d5783c | 1876 | base = priv->device_pointers.error_event_table; |
b2e640d4 | 1877 | if (priv->ucode_type == UCODE_INIT) { |
b2e640d4 JB |
1878 | if (!base) |
1879 | base = priv->_agn.init_errlog_ptr; | |
1880 | } else { | |
b2e640d4 JB |
1881 | if (!base) |
1882 | base = priv->_agn.inst_errlog_ptr; | |
1883 | } | |
b7a79404 RC |
1884 | |
1885 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
1886 | IWL_ERR(priv, |
1887 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
1888 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
b7a79404 RC |
1889 | return; |
1890 | } | |
1891 | ||
1892 | count = iwl_read_targ_mem(priv, base); | |
1893 | ||
1894 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1895 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
1896 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1897 | priv->status, count); | |
1898 | } | |
1899 | ||
1900 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
6e6ebf4b | 1901 | priv->isr_stats.err_code = desc; |
461ef382 | 1902 | pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32)); |
b7a79404 RC |
1903 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); |
1904 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
1905 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
1906 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
1907 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
1908 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
1909 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
1910 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
461ef382 | 1911 | hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32)); |
b7a79404 | 1912 | |
be1a71a1 JB |
1913 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
1914 | blink1, blink2, ilink1, ilink2); | |
1915 | ||
87563715 | 1916 | IWL_ERR(priv, "Desc Time " |
b7a79404 | 1917 | "data1 data2 line\n"); |
87563715 | 1918 | IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", |
b7a79404 | 1919 | desc_lookup(desc), desc, time, data1, data2, line); |
461ef382 WYG |
1920 | IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
1921 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", | |
1922 | pc, blink1, blink2, ilink1, ilink2, hcmd); | |
b7a79404 RC |
1923 | } |
1924 | ||
1925 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1926 | ||
1927 | /** | |
1928 | * iwl_print_event_log - Dump error event log to syslog | |
1929 | * | |
1930 | */ | |
b03d7d0f WYG |
1931 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1932 | u32 num_events, u32 mode, | |
1933 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
1934 | { |
1935 | u32 i; | |
1936 | u32 base; /* SRAM byte address of event log header */ | |
1937 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1938 | u32 ptr; /* SRAM byte address of log data */ | |
1939 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1940 | unsigned long reg_flags; |
b7a79404 RC |
1941 | |
1942 | if (num_events == 0) | |
b03d7d0f | 1943 | return pos; |
b2e640d4 | 1944 | |
d7d5783c | 1945 | base = priv->device_pointers.log_event_table; |
b2e640d4 | 1946 | if (priv->ucode_type == UCODE_INIT) { |
b2e640d4 JB |
1947 | if (!base) |
1948 | base = priv->_agn.init_evtlog_ptr; | |
1949 | } else { | |
b2e640d4 JB |
1950 | if (!base) |
1951 | base = priv->_agn.inst_evtlog_ptr; | |
1952 | } | |
b7a79404 RC |
1953 | |
1954 | if (mode == 0) | |
1955 | event_size = 2 * sizeof(u32); | |
1956 | else | |
1957 | event_size = 3 * sizeof(u32); | |
1958 | ||
1959 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1960 | ||
e5854471 BC |
1961 | /* Make sure device is powered up for SRAM reads */ |
1962 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1963 | iwl_grab_nic_access(priv); | |
1964 | ||
1965 | /* Set starting address; reads will auto-increment */ | |
1966 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
1967 | rmb(); | |
1968 | ||
b7a79404 RC |
1969 | /* "time" is actually "data" for mode 0 (no timestamp). |
1970 | * place event id # at far right for easier visual parsing. */ | |
1971 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
1972 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
1973 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
1974 | if (mode == 0) { |
1975 | /* data, ev */ | |
b03d7d0f WYG |
1976 | if (bufsz) { |
1977 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1978 | "EVT_LOG:0x%08x:%04u\n", | |
1979 | time, ev); | |
1980 | } else { | |
1981 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1982 | time, ev); | |
1983 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
1984 | time, ev); | |
1985 | } | |
b7a79404 | 1986 | } else { |
e5854471 | 1987 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1988 | if (bufsz) { |
1989 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1990 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1991 | time, data, ev); | |
1992 | } else { | |
1993 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 1994 | time, data, ev); |
b03d7d0f WYG |
1995 | trace_iwlwifi_dev_ucode_event(priv, time, |
1996 | data, ev); | |
1997 | } | |
b7a79404 RC |
1998 | } |
1999 | } | |
e5854471 BC |
2000 | |
2001 | /* Allow device to power down */ | |
2002 | iwl_release_nic_access(priv); | |
2003 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 2004 | return pos; |
b7a79404 RC |
2005 | } |
2006 | ||
c341ddb2 WYG |
2007 | /** |
2008 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
2009 | */ | |
b03d7d0f WYG |
2010 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
2011 | u32 num_wraps, u32 next_entry, | |
2012 | u32 size, u32 mode, | |
2013 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
2014 | { |
2015 | /* | |
2016 | * display the newest DEFAULT_LOG_ENTRIES entries | |
2017 | * i.e the entries just before the next ont that uCode would fill. | |
2018 | */ | |
2019 | if (num_wraps) { | |
2020 | if (next_entry < size) { | |
b03d7d0f WYG |
2021 | pos = iwl_print_event_log(priv, |
2022 | capacity - (size - next_entry), | |
2023 | size - next_entry, mode, | |
2024 | pos, buf, bufsz); | |
2025 | pos = iwl_print_event_log(priv, 0, | |
2026 | next_entry, mode, | |
2027 | pos, buf, bufsz); | |
c341ddb2 | 2028 | } else |
b03d7d0f WYG |
2029 | pos = iwl_print_event_log(priv, next_entry - size, |
2030 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 2031 | } else { |
b03d7d0f WYG |
2032 | if (next_entry < size) { |
2033 | pos = iwl_print_event_log(priv, 0, next_entry, | |
2034 | mode, pos, buf, bufsz); | |
2035 | } else { | |
2036 | pos = iwl_print_event_log(priv, next_entry - size, | |
2037 | size, mode, pos, buf, bufsz); | |
2038 | } | |
c341ddb2 | 2039 | } |
b03d7d0f | 2040 | return pos; |
c341ddb2 WYG |
2041 | } |
2042 | ||
c341ddb2 WYG |
2043 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
2044 | ||
b03d7d0f WYG |
2045 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
2046 | char **buf, bool display) | |
b7a79404 RC |
2047 | { |
2048 | u32 base; /* SRAM byte address of event log header */ | |
2049 | u32 capacity; /* event log capacity in # entries */ | |
2050 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
2051 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
2052 | u32 next_entry; /* index of next entry to be written by uCode */ | |
2053 | u32 size; /* # entries that we'll print */ | |
b2e640d4 | 2054 | u32 logsize; |
b03d7d0f WYG |
2055 | int pos = 0; |
2056 | size_t bufsz = 0; | |
b7a79404 | 2057 | |
d7d5783c | 2058 | base = priv->device_pointers.log_event_table; |
b2e640d4 | 2059 | if (priv->ucode_type == UCODE_INIT) { |
b2e640d4 JB |
2060 | logsize = priv->_agn.init_evtlog_size; |
2061 | if (!base) | |
2062 | base = priv->_agn.init_evtlog_ptr; | |
2063 | } else { | |
b2e640d4 JB |
2064 | logsize = priv->_agn.inst_evtlog_size; |
2065 | if (!base) | |
2066 | base = priv->_agn.inst_evtlog_ptr; | |
2067 | } | |
b7a79404 RC |
2068 | |
2069 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2070 | IWL_ERR(priv, |
2071 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
2072 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
937c397e | 2073 | return -EINVAL; |
b7a79404 RC |
2074 | } |
2075 | ||
2076 | /* event log header */ | |
2077 | capacity = iwl_read_targ_mem(priv, base); | |
2078 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2079 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2080 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2081 | ||
b2e640d4 | 2082 | if (capacity > logsize) { |
84c40692 | 2083 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
b2e640d4 JB |
2084 | capacity, logsize); |
2085 | capacity = logsize; | |
84c40692 BC |
2086 | } |
2087 | ||
b2e640d4 | 2088 | if (next_entry > logsize) { |
84c40692 | 2089 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
b2e640d4 JB |
2090 | next_entry, logsize); |
2091 | next_entry = logsize; | |
84c40692 BC |
2092 | } |
2093 | ||
b7a79404 RC |
2094 | size = num_wraps ? capacity : next_entry; |
2095 | ||
2096 | /* bail out if nothing in log */ | |
2097 | if (size == 0) { | |
2098 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2099 | return pos; |
b7a79404 RC |
2100 | } |
2101 | ||
9f28ebc3 | 2102 | /* enable/disable bt channel inhibition */ |
f37837c9 WYG |
2103 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
2104 | ||
c341ddb2 | 2105 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2106 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2107 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2108 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2109 | #else | |
2110 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2111 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2112 | #endif | |
2113 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2114 | size); | |
b7a79404 | 2115 | |
c341ddb2 | 2116 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2117 | if (display) { |
2118 | if (full_log) | |
2119 | bufsz = capacity * 48; | |
2120 | else | |
2121 | bufsz = size * 48; | |
2122 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2123 | if (!*buf) | |
937c397e | 2124 | return -ENOMEM; |
b03d7d0f | 2125 | } |
c341ddb2 WYG |
2126 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2127 | /* | |
2128 | * if uCode has wrapped back to top of log, | |
2129 | * start at the oldest entry, | |
2130 | * i.e the next one that uCode would fill. | |
2131 | */ | |
2132 | if (num_wraps) | |
b03d7d0f WYG |
2133 | pos = iwl_print_event_log(priv, next_entry, |
2134 | capacity - next_entry, mode, | |
2135 | pos, buf, bufsz); | |
c341ddb2 | 2136 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2137 | pos = iwl_print_event_log(priv, 0, |
2138 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2139 | } else |
b03d7d0f WYG |
2140 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2141 | next_entry, size, mode, | |
2142 | pos, buf, bufsz); | |
c341ddb2 | 2143 | #else |
b03d7d0f WYG |
2144 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2145 | next_entry, size, mode, | |
2146 | pos, buf, bufsz); | |
b7a79404 | 2147 | #endif |
b03d7d0f | 2148 | return pos; |
c341ddb2 | 2149 | } |
b7a79404 | 2150 | |
0975cc8f WYG |
2151 | static void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
2152 | { | |
2153 | struct iwl_ct_kill_config cmd; | |
2154 | struct iwl_ct_kill_throttling_config adv_cmd; | |
2155 | unsigned long flags; | |
2156 | int ret = 0; | |
2157 | ||
2158 | spin_lock_irqsave(&priv->lock, flags); | |
2159 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
2160 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
2161 | spin_unlock_irqrestore(&priv->lock, flags); | |
2162 | priv->thermal_throttle.ct_kill_toggle = false; | |
2163 | ||
7cb1b088 | 2164 | if (priv->cfg->base_params->support_ct_kill_exit) { |
0975cc8f WYG |
2165 | adv_cmd.critical_temperature_enter = |
2166 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2167 | adv_cmd.critical_temperature_exit = | |
2168 | cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); | |
2169 | ||
2170 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2171 | sizeof(adv_cmd), &adv_cmd); | |
2172 | if (ret) | |
2173 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2174 | else | |
2175 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2176 | "succeeded, " | |
2177 | "critical temperature enter is %d," | |
2178 | "exit is %d\n", | |
2179 | priv->hw_params.ct_kill_threshold, | |
2180 | priv->hw_params.ct_kill_exit_threshold); | |
2181 | } else { | |
2182 | cmd.critical_temperature_R = | |
2183 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2184 | ||
2185 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2186 | sizeof(cmd), &cmd); | |
2187 | if (ret) | |
2188 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2189 | else | |
2190 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2191 | "succeeded, " | |
2192 | "critical temperature is %d\n", | |
2193 | priv->hw_params.ct_kill_threshold); | |
2194 | } | |
2195 | } | |
2196 | ||
6d6a1afd SZ |
2197 | static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg) |
2198 | { | |
2199 | struct iwl_calib_cfg_cmd calib_cfg_cmd; | |
2200 | struct iwl_host_cmd cmd = { | |
2201 | .id = CALIBRATION_CFG_CMD, | |
2202 | .len = sizeof(struct iwl_calib_cfg_cmd), | |
2203 | .data = &calib_cfg_cmd, | |
2204 | }; | |
2205 | ||
2206 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
2207 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
7cb1b088 | 2208 | calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg); |
6d6a1afd SZ |
2209 | |
2210 | return iwl_send_cmd(priv, &cmd); | |
2211 | } | |
2212 | ||
2213 | ||
b481de9c | 2214 | /** |
4a4a9e81 | 2215 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2216 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2217 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2218 | */ |
4a4a9e81 | 2219 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2220 | { |
57aab75a | 2221 | int ret = 0; |
246ed355 | 2222 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 2223 | |
e1623446 | 2224 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 2225 | |
b481de9c ZY |
2226 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. |
2227 | * This is a paranoid check, because we would not have gotten the | |
2228 | * "runtime" alive if code weren't properly loaded. */ | |
35b1d92d | 2229 | if (iwl_verify_ucode(priv, &priv->ucode_code)) { |
b481de9c ZY |
2230 | /* Runtime instruction load was bad; |
2231 | * take it all the way back down so we can try again */ | |
e1623446 | 2232 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2233 | goto restart; |
2234 | } | |
2235 | ||
7102762e | 2236 | ret = iwlagn_alive_notify(priv); |
57aab75a | 2237 | if (ret) { |
39aadf8c WT |
2238 | IWL_WARN(priv, |
2239 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
2240 | goto restart; |
2241 | } | |
2242 | ||
6d6a1afd | 2243 | |
5b9f8cd3 | 2244 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2245 | set_bit(STATUS_ALIVE, &priv->status); |
2246 | ||
22de94de SG |
2247 | /* Enable watchdog to monitor the driver tx queues */ |
2248 | iwl_setup_watchdog(priv); | |
b74e31a9 | 2249 | |
fee1247a | 2250 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2251 | return; |
2252 | ||
bc795df1 | 2253 | /* download priority table before any calibration request */ |
7cb1b088 WYG |
2254 | if (priv->cfg->bt_params && |
2255 | priv->cfg->bt_params->advanced_bt_coexist) { | |
f7322f8f WYG |
2256 | /* Configure Bluetooth device coexistence support */ |
2257 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
2258 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; | |
2259 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
2260 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
2261 | priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS; | |
a5901cbb | 2262 | iwlagn_send_prio_tbl(priv); |
f7322f8f WYG |
2263 | |
2264 | /* FIXME: w/a to force change uCode BT state machine */ | |
2265 | iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN, | |
2266 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2267 | iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE, | |
2268 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2269 | } | |
bc795df1 WYG |
2270 | if (priv->hw_params.calib_rt_cfg) |
2271 | iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg); | |
2272 | ||
36d6825b | 2273 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2274 | |
470ab2dd | 2275 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2276 | |
2f748dec WYG |
2277 | /* Configure Tx antenna selection based on H/W config */ |
2278 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2279 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2280 | ||
246ed355 | 2281 | if (iwl_is_associated_ctx(ctx)) { |
c1adf9fb | 2282 | struct iwl_rxon_cmd *active_rxon = |
246ed355 | 2283 | (struct iwl_rxon_cmd *)&ctx->active; |
019fb97d | 2284 | /* apply any changes in staging */ |
246ed355 | 2285 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2286 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2287 | } else { | |
d0fe478c | 2288 | struct iwl_rxon_context *tmp; |
b481de9c | 2289 | /* Initialize our rx_config data */ |
d0fe478c JB |
2290 | for_each_context(priv, tmp) |
2291 | iwl_connection_init_rx_config(priv, tmp); | |
45823531 AK |
2292 | |
2293 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 | 2294 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
b481de9c ZY |
2295 | } |
2296 | ||
73b78a22 WYG |
2297 | if (!priv->cfg->bt_params || (priv->cfg->bt_params && |
2298 | !priv->cfg->bt_params->advanced_bt_coexist)) { | |
2299 | /* | |
2300 | * default is 2-wire BT coexexistence support | |
2301 | */ | |
aeb4a2ee WYG |
2302 | priv->cfg->ops->hcmd->send_bt_config(priv); |
2303 | } | |
b481de9c | 2304 | |
4a4a9e81 TW |
2305 | iwl_reset_run_time_calib(priv); |
2306 | ||
9e2e7422 WYG |
2307 | set_bit(STATUS_READY, &priv->status); |
2308 | ||
b481de9c | 2309 | /* Configure the adapter for unassociated operation */ |
246ed355 | 2310 | iwlcore_commit_rxon(priv, ctx); |
b481de9c ZY |
2311 | |
2312 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2313 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2314 | |
e1623446 | 2315 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
5a66926a | 2316 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2317 | |
e312c24c | 2318 | iwl_power_update_mode(priv, true); |
7e246191 RC |
2319 | IWL_DEBUG_INFO(priv, "Updated power mode\n"); |
2320 | ||
c46fbefa | 2321 | |
b481de9c ZY |
2322 | return; |
2323 | ||
2324 | restart: | |
2325 | queue_work(priv->workqueue, &priv->restart); | |
2326 | } | |
2327 | ||
4e39317d | 2328 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2329 | |
5b9f8cd3 | 2330 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2331 | { |
2332 | unsigned long flags; | |
22dd2fd2 | 2333 | int exit_pending; |
b481de9c | 2334 | |
e1623446 | 2335 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2336 | |
d745d472 SG |
2337 | iwl_scan_cancel_timeout(priv, 200); |
2338 | ||
2339 | exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2340 | |
b62177a0 SG |
2341 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set |
2342 | * to prevent rearm timer */ | |
22de94de | 2343 | del_timer_sync(&priv->watchdog); |
b62177a0 | 2344 | |
dcef732c | 2345 | iwl_clear_ucode_stations(priv, NULL); |
a194e324 | 2346 | iwl_dealloc_bcast_stations(priv); |
db125c78 | 2347 | iwl_clear_driver_stations(priv); |
b481de9c | 2348 | |
a1174138 | 2349 | /* reset BT coex data */ |
da5dbb97 | 2350 | priv->bt_status = 0; |
7cb1b088 WYG |
2351 | if (priv->cfg->bt_params) |
2352 | priv->bt_traffic_load = | |
2353 | priv->cfg->bt_params->bt_init_traffic_load; | |
2354 | else | |
2355 | priv->bt_traffic_load = 0; | |
bee008b7 WYG |
2356 | priv->bt_full_concurrent = false; |
2357 | priv->bt_ci_compliance = 0; | |
a1174138 | 2358 | |
b481de9c ZY |
2359 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2360 | * exiting the module */ | |
2361 | if (!exit_pending) | |
2362 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2363 | ||
2364 | /* stop and reset the on-board processor */ | |
3395f6e9 | 2365 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2366 | |
2367 | /* tell the device to stop sending interrupts */ | |
0359facc | 2368 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2369 | iwl_disable_interrupts(priv); |
0359facc MA |
2370 | spin_unlock_irqrestore(&priv->lock, flags); |
2371 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2372 | |
2373 | if (priv->mac80211_registered) | |
2374 | ieee80211_stop_queues(priv->hw); | |
2375 | ||
5b9f8cd3 | 2376 | /* If we have not previously called iwl_init() then |
a60e77e5 | 2377 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 2378 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2379 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2380 | STATUS_RF_KILL_HW | | |
9788864e RC |
2381 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2382 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
2383 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2384 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2385 | goto exit; |
2386 | } | |
2387 | ||
6da3a13e | 2388 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2389 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2390 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2391 | STATUS_RF_KILL_HW | | |
9788864e RC |
2392 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2393 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2394 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2395 | STATUS_FW_ERROR | |
2396 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2397 | STATUS_EXIT_PENDING; | |
b481de9c | 2398 | |
ef850d7c | 2399 | /* device going down, Stop using ICT table */ |
e39fdee1 WYG |
2400 | if (priv->cfg->ops->lib->isr_ops.disable) |
2401 | priv->cfg->ops->lib->isr_ops.disable(priv); | |
b481de9c | 2402 | |
74bcdb33 | 2403 | iwlagn_txq_ctx_stop(priv); |
54b81550 | 2404 | iwlagn_rxq_stop(priv); |
b481de9c | 2405 | |
309e731a BC |
2406 | /* Power-down device's busmaster DMA clocks */ |
2407 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2408 | udelay(5); |
2409 | ||
309e731a BC |
2410 | /* Make sure (redundant) we've released our request to stay awake */ |
2411 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
2412 | ||
4d2ccdb9 | 2413 | /* Stop the device, and put it in low power state */ |
14e8e4af | 2414 | iwl_apm_stop(priv); |
4d2ccdb9 | 2415 | |
b481de9c | 2416 | exit: |
77834543 | 2417 | dev_kfree_skb(priv->beacon_skb); |
12e934dc | 2418 | priv->beacon_skb = NULL; |
b481de9c ZY |
2419 | |
2420 | /* clear out any free frames */ | |
fcab423d | 2421 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2422 | } |
2423 | ||
5b9f8cd3 | 2424 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2425 | { |
2426 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2427 | __iwl_down(priv); |
b481de9c | 2428 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2429 | |
4e39317d | 2430 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2431 | } |
2432 | ||
086ed117 MA |
2433 | #define HW_READY_TIMEOUT (50) |
2434 | ||
2435 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
2436 | { | |
2437 | int ret = 0; | |
2438 | ||
2439 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2440 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2441 | ||
2442 | /* See if we got it */ | |
2443 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2444 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2445 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2446 | HW_READY_TIMEOUT); | |
2447 | if (ret != -ETIMEDOUT) | |
2448 | priv->hw_ready = true; | |
2449 | else | |
2450 | priv->hw_ready = false; | |
2451 | ||
2452 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
2453 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
2454 | return ret; | |
2455 | } | |
2456 | ||
2457 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
2458 | { | |
2459 | int ret = 0; | |
2460 | ||
91dd6c27 | 2461 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n"); |
086ed117 | 2462 | |
3354a0f6 MA |
2463 | ret = iwl_set_hw_ready(priv); |
2464 | if (priv->hw_ready) | |
2465 | return ret; | |
2466 | ||
2467 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2468 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2469 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2470 | ||
2471 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2472 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2473 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2474 | ||
3354a0f6 | 2475 | /* HW should be ready by now, check again. */ |
086ed117 MA |
2476 | if (ret != -ETIMEDOUT) |
2477 | iwl_set_hw_ready(priv); | |
2478 | ||
2479 | return ret; | |
2480 | } | |
2481 | ||
b481de9c ZY |
2482 | #define MAX_HW_RESTARTS 5 |
2483 | ||
5b9f8cd3 | 2484 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2485 | { |
a194e324 | 2486 | struct iwl_rxon_context *ctx; |
57aab75a TW |
2487 | int i; |
2488 | int ret; | |
b481de9c ZY |
2489 | |
2490 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2491 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2492 | return -EIO; |
2493 | } | |
2494 | ||
a194e324 | 2495 | for_each_context(priv, ctx) { |
a30e3112 | 2496 | ret = iwlagn_alloc_bcast_station(priv, ctx); |
a194e324 JB |
2497 | if (ret) { |
2498 | iwl_dealloc_bcast_stations(priv); | |
2499 | return ret; | |
2500 | } | |
2501 | } | |
2c810ccd | 2502 | |
086ed117 MA |
2503 | iwl_prepare_card_hw(priv); |
2504 | ||
2505 | if (!priv->hw_ready) { | |
2506 | IWL_WARN(priv, "Exit HW not ready\n"); | |
2507 | return -EIO; | |
2508 | } | |
2509 | ||
e655b9f0 | 2510 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 2511 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 2512 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2513 | else |
e655b9f0 | 2514 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2515 | |
c1842d61 | 2516 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2517 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2518 | ||
5b9f8cd3 | 2519 | iwl_enable_interrupts(priv); |
a60e77e5 | 2520 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2521 | return 0; |
b481de9c ZY |
2522 | } |
2523 | ||
3395f6e9 | 2524 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2525 | |
74bcdb33 | 2526 | ret = iwlagn_hw_nic_init(priv); |
57aab75a | 2527 | if (ret) { |
15b1687c | 2528 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2529 | return ret; |
b481de9c ZY |
2530 | } |
2531 | ||
2532 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2533 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2534 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2535 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2536 | ||
2537 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2538 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2539 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2540 | |
2541 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2542 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2543 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c | 2544 | |
b481de9c ZY |
2545 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2546 | ||
b481de9c ZY |
2547 | /* load bootstrap state machine, |
2548 | * load bootstrap program into processor's memory, | |
2549 | * prepare to load the "initialize" uCode */ | |
7102762e | 2550 | ret = iwlagn_load_ucode(priv); |
b481de9c | 2551 | |
57aab75a | 2552 | if (ret) { |
15b1687c WT |
2553 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
2554 | ret); | |
b481de9c ZY |
2555 | continue; |
2556 | } | |
2557 | ||
2558 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 2559 | iwl_nic_start(priv); |
b481de9c | 2560 | |
e1623446 | 2561 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2562 | |
2563 | return 0; | |
2564 | } | |
2565 | ||
2566 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 2567 | __iwl_down(priv); |
64e72c3e | 2568 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2569 | |
2570 | /* tried to restart and config the device for as long as our | |
2571 | * patience could withstand */ | |
15b1687c | 2572 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2573 | return -EIO; |
2574 | } | |
2575 | ||
2576 | ||
2577 | /***************************************************************************** | |
2578 | * | |
2579 | * Workqueue callbacks | |
2580 | * | |
2581 | *****************************************************************************/ | |
2582 | ||
4a4a9e81 | 2583 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2584 | { |
c79dd5b5 TW |
2585 | struct iwl_priv *priv = |
2586 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c | 2587 | |
dc1a4068 SG |
2588 | mutex_lock(&priv->mutex); |
2589 | ||
2590 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
2591 | mutex_unlock(&priv->mutex); | |
b481de9c | 2592 | return; |
dc1a4068 | 2593 | } |
b481de9c | 2594 | |
7102762e | 2595 | iwlagn_init_alive_start(priv); |
b481de9c ZY |
2596 | mutex_unlock(&priv->mutex); |
2597 | } | |
2598 | ||
4a4a9e81 | 2599 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 2600 | { |
c79dd5b5 TW |
2601 | struct iwl_priv *priv = |
2602 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c | 2603 | |
dc1a4068 | 2604 | mutex_lock(&priv->mutex); |
b481de9c | 2605 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
dc1a4068 | 2606 | goto unlock; |
b481de9c | 2607 | |
258c44a0 | 2608 | /* enable dram interrupt */ |
e39fdee1 WYG |
2609 | if (priv->cfg->ops->lib->isr_ops.reset) |
2610 | priv->cfg->ops->lib->isr_ops.reset(priv); | |
258c44a0 | 2611 | |
4a4a9e81 | 2612 | iwl_alive_start(priv); |
dc1a4068 | 2613 | unlock: |
b481de9c ZY |
2614 | mutex_unlock(&priv->mutex); |
2615 | } | |
2616 | ||
16e727e8 EG |
2617 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2618 | { | |
2619 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2620 | run_time_calib_work); | |
2621 | ||
2622 | mutex_lock(&priv->mutex); | |
2623 | ||
2624 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2625 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2626 | mutex_unlock(&priv->mutex); | |
2627 | return; | |
2628 | } | |
2629 | ||
2630 | if (priv->start_calib) { | |
9f60e7ee | 2631 | if (iwl_bt_statistics(priv)) { |
7980fba5 WYG |
2632 | iwl_chain_noise_calibration(priv, |
2633 | (void *)&priv->_agn.statistics_bt); | |
2634 | iwl_sensitivity_calibration(priv, | |
2635 | (void *)&priv->_agn.statistics_bt); | |
2636 | } else { | |
2637 | iwl_chain_noise_calibration(priv, | |
2638 | (void *)&priv->_agn.statistics); | |
2639 | iwl_sensitivity_calibration(priv, | |
2640 | (void *)&priv->_agn.statistics); | |
2641 | } | |
16e727e8 EG |
2642 | } |
2643 | ||
2644 | mutex_unlock(&priv->mutex); | |
16e727e8 EG |
2645 | } |
2646 | ||
5b9f8cd3 | 2647 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2648 | { |
c79dd5b5 | 2649 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2650 | |
2651 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2652 | return; | |
2653 | ||
19cc1087 | 2654 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
8bd413e6 | 2655 | struct iwl_rxon_context *ctx; |
187bc4f6 | 2656 | bool bt_full_concurrent; |
bee008b7 | 2657 | u8 bt_ci_compliance; |
511b082d | 2658 | u8 bt_load; |
da5dbb97 | 2659 | u8 bt_status; |
511b082d | 2660 | |
19cc1087 | 2661 | mutex_lock(&priv->mutex); |
8bd413e6 JB |
2662 | for_each_context(priv, ctx) |
2663 | ctx->vif = NULL; | |
19cc1087 | 2664 | priv->is_open = 0; |
511b082d JB |
2665 | |
2666 | /* | |
2667 | * __iwl_down() will clear the BT status variables, | |
2668 | * which is correct, but when we restart we really | |
2669 | * want to keep them so restore them afterwards. | |
2670 | * | |
2671 | * The restart process will later pick them up and | |
2672 | * re-configure the hw when we reconfigure the BT | |
2673 | * command. | |
2674 | */ | |
bee008b7 WYG |
2675 | bt_full_concurrent = priv->bt_full_concurrent; |
2676 | bt_ci_compliance = priv->bt_ci_compliance; | |
511b082d | 2677 | bt_load = priv->bt_traffic_load; |
da5dbb97 | 2678 | bt_status = priv->bt_status; |
511b082d | 2679 | |
a1174138 | 2680 | __iwl_down(priv); |
511b082d | 2681 | |
bee008b7 WYG |
2682 | priv->bt_full_concurrent = bt_full_concurrent; |
2683 | priv->bt_ci_compliance = bt_ci_compliance; | |
511b082d | 2684 | priv->bt_traffic_load = bt_load; |
da5dbb97 | 2685 | priv->bt_status = bt_status; |
511b082d | 2686 | |
19cc1087 | 2687 | mutex_unlock(&priv->mutex); |
a1174138 | 2688 | iwl_cancel_deferred_work(priv); |
19cc1087 JB |
2689 | ieee80211_restart_hw(priv->hw); |
2690 | } else { | |
2691 | iwl_down(priv); | |
80676518 JB |
2692 | |
2693 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2694 | return; | |
2695 | ||
2696 | mutex_lock(&priv->mutex); | |
2697 | __iwl_up(priv); | |
2698 | mutex_unlock(&priv->mutex); | |
19cc1087 | 2699 | } |
b481de9c ZY |
2700 | } |
2701 | ||
5b9f8cd3 | 2702 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2703 | { |
c79dd5b5 TW |
2704 | struct iwl_priv *priv = |
2705 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2706 | |
2707 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2708 | return; | |
2709 | ||
2710 | mutex_lock(&priv->mutex); | |
54b81550 | 2711 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
2712 | mutex_unlock(&priv->mutex); |
2713 | } | |
2714 | ||
266af4c7 JB |
2715 | static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
2716 | struct ieee80211_channel *chan, | |
2717 | enum nl80211_channel_type channel_type, | |
2718 | unsigned int wait) | |
2719 | { | |
2720 | struct iwl_priv *priv = hw->priv; | |
2721 | int ret; | |
2722 | ||
2723 | /* Not supported if we don't have PAN */ | |
2724 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) { | |
2725 | ret = -EOPNOTSUPP; | |
2726 | goto free; | |
2727 | } | |
2728 | ||
2729 | /* Not supported on pre-P2P firmware */ | |
2730 | if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes & | |
2731 | BIT(NL80211_IFTYPE_P2P_CLIENT))) { | |
2732 | ret = -EOPNOTSUPP; | |
2733 | goto free; | |
2734 | } | |
2735 | ||
2736 | mutex_lock(&priv->mutex); | |
2737 | ||
2738 | if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) { | |
2739 | /* | |
2740 | * If the PAN context is free, use the normal | |
2741 | * way of doing remain-on-channel offload + TX. | |
2742 | */ | |
2743 | ret = 1; | |
2744 | goto out; | |
2745 | } | |
2746 | ||
2747 | /* TODO: queue up if scanning? */ | |
2748 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
2749 | priv->_agn.offchan_tx_skb) { | |
2750 | ret = -EBUSY; | |
2751 | goto out; | |
2752 | } | |
2753 | ||
2754 | /* | |
2755 | * max_scan_ie_len doesn't include the blank SSID or the header, | |
2756 | * so need to add that again here. | |
2757 | */ | |
2758 | if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) { | |
2759 | ret = -ENOBUFS; | |
2760 | goto out; | |
2761 | } | |
2762 | ||
2763 | priv->_agn.offchan_tx_skb = skb; | |
2764 | priv->_agn.offchan_tx_timeout = wait; | |
2765 | priv->_agn.offchan_tx_chan = chan; | |
2766 | ||
2767 | ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif, | |
2768 | IWL_SCAN_OFFCH_TX, chan->band); | |
2769 | if (ret) | |
2770 | priv->_agn.offchan_tx_skb = NULL; | |
2771 | out: | |
2772 | mutex_unlock(&priv->mutex); | |
2773 | free: | |
2774 | if (ret < 0) | |
2775 | kfree_skb(skb); | |
2776 | ||
2777 | return ret; | |
2778 | } | |
2779 | ||
2780 | static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw) | |
2781 | { | |
2782 | struct iwl_priv *priv = hw->priv; | |
2783 | int ret; | |
2784 | ||
2785 | mutex_lock(&priv->mutex); | |
2786 | ||
f8a22a2b DC |
2787 | if (!priv->_agn.offchan_tx_skb) { |
2788 | ret = -EINVAL; | |
2789 | goto unlock; | |
2790 | } | |
266af4c7 JB |
2791 | |
2792 | priv->_agn.offchan_tx_skb = NULL; | |
2793 | ||
2794 | ret = iwl_scan_cancel_timeout(priv, 200); | |
2795 | if (ret) | |
2796 | ret = -EIO; | |
f8a22a2b | 2797 | unlock: |
266af4c7 JB |
2798 | mutex_unlock(&priv->mutex); |
2799 | ||
2800 | return ret; | |
2801 | } | |
2802 | ||
b481de9c ZY |
2803 | /***************************************************************************** |
2804 | * | |
2805 | * mac80211 entry point functions | |
2806 | * | |
2807 | *****************************************************************************/ | |
2808 | ||
154b25ce | 2809 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2810 | |
f0b6e2e8 RC |
2811 | /* |
2812 | * Not a mac80211 entry point function, but it fits in with all the | |
2813 | * other mac80211 functions grouped here. | |
2814 | */ | |
dd7a2509 JB |
2815 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
2816 | struct iwlagn_ucode_capabilities *capa) | |
f0b6e2e8 RC |
2817 | { |
2818 | int ret; | |
2819 | struct ieee80211_hw *hw = priv->hw; | |
d0fe478c JB |
2820 | struct iwl_rxon_context *ctx; |
2821 | ||
f0b6e2e8 RC |
2822 | hw->rate_control_algorithm = "iwl-agn-rs"; |
2823 | ||
2824 | /* Tell mac80211 our characteristics */ | |
2825 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
f0b6e2e8 | 2826 | IEEE80211_HW_AMPDU_AGGREGATION | |
2491fa42 | 2827 | IEEE80211_HW_NEED_DTIM_PERIOD | |
6fb5511a JB |
2828 | IEEE80211_HW_SPECTRUM_MGMT | |
2829 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
f0b6e2e8 | 2830 | |
9b768832 JB |
2831 | hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF; |
2832 | ||
7cb1b088 | 2833 | if (!priv->cfg->base_params->broken_powersave) |
f0b6e2e8 RC |
2834 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | |
2835 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2836 | ||
ba37a3d0 JB |
2837 | if (priv->cfg->sku & IWL_SKU_N) |
2838 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
2839 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
2840 | ||
3997ff39 JB |
2841 | if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP) |
2842 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | |
2843 | ||
8d9698b3 | 2844 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
fd1af15d JB |
2845 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
2846 | ||
d0fe478c JB |
2847 | for_each_context(priv, ctx) { |
2848 | hw->wiphy->interface_modes |= ctx->interface_modes; | |
2849 | hw->wiphy->interface_modes |= ctx->exclusive_interface_modes; | |
2850 | } | |
f0b6e2e8 | 2851 | |
9b9190d9 JB |
2852 | hw->wiphy->max_remain_on_channel_duration = 1000; |
2853 | ||
f6c8f152 | 2854 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
274102a8 JB |
2855 | WIPHY_FLAG_DISABLE_BEACON_HINTS | |
2856 | WIPHY_FLAG_IBSS_RSN; | |
f0b6e2e8 RC |
2857 | |
2858 | /* | |
2859 | * For now, disable PS by default because it affects | |
2860 | * RX performance significantly. | |
2861 | */ | |
5be83de5 | 2862 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 2863 | |
1382c71c | 2864 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 | 2865 | /* we create the 802.11 header and a zero-length SSID element */ |
dd7a2509 | 2866 | hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2; |
f0b6e2e8 RC |
2867 | |
2868 | /* Default value; 4 EDCA QOS priorities */ | |
2869 | hw->queues = 4; | |
2870 | ||
2871 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
2872 | ||
2873 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
2874 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
2875 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2876 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
2877 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
2878 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
2879 | ||
5ed540ae WYG |
2880 | iwl_leds_init(priv); |
2881 | ||
f0b6e2e8 RC |
2882 | ret = ieee80211_register_hw(priv->hw); |
2883 | if (ret) { | |
2884 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
2885 | return ret; | |
2886 | } | |
2887 | priv->mac80211_registered = 1; | |
2888 | ||
2889 | return 0; | |
2890 | } | |
2891 | ||
2892 | ||
2dedbf58 | 2893 | static int iwlagn_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2894 | { |
c79dd5b5 | 2895 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2896 | int ret; |
b481de9c | 2897 | |
e1623446 | 2898 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2899 | |
2900 | /* we should be verifying the device is ready to be opened */ | |
2901 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2902 | ret = __iwl_up(priv); |
b481de9c | 2903 | mutex_unlock(&priv->mutex); |
5a66926a | 2904 | |
e655b9f0 | 2905 | if (ret) |
6cd0b1cb | 2906 | return ret; |
e655b9f0 | 2907 | |
c1842d61 TW |
2908 | if (iwl_is_rfkill(priv)) |
2909 | goto out; | |
2910 | ||
e1623446 | 2911 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2912 | |
fe9b6b72 | 2913 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2914 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2915 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2916 | test_bit(STATUS_READY, &priv->status), | |
2917 | UCODE_READY_TIMEOUT); | |
2918 | if (!ret) { | |
2919 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2920 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2921 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2922 | return -ETIMEDOUT; |
5a66926a | 2923 | } |
fe9b6b72 | 2924 | } |
0a078ffa | 2925 | |
5ed540ae | 2926 | iwlagn_led_enable(priv); |
e932a609 | 2927 | |
c1842d61 | 2928 | out: |
0a078ffa | 2929 | priv->is_open = 1; |
e1623446 | 2930 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2931 | return 0; |
2932 | } | |
2933 | ||
2dedbf58 | 2934 | static void iwlagn_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2935 | { |
c79dd5b5 | 2936 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2937 | |
e1623446 | 2938 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2939 | |
19cc1087 | 2940 | if (!priv->is_open) |
e655b9f0 | 2941 | return; |
e655b9f0 | 2942 | |
b481de9c | 2943 | priv->is_open = 0; |
5a66926a | 2944 | |
5b9f8cd3 | 2945 | iwl_down(priv); |
5a66926a ZY |
2946 | |
2947 | flush_workqueue(priv->workqueue); | |
6cd0b1cb | 2948 | |
554d1d02 SG |
2949 | /* User space software may expect getting rfkill changes |
2950 | * even if interface is down */ | |
6cd0b1cb | 2951 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
554d1d02 | 2952 | iwl_enable_rfkill_int(priv); |
948c171c | 2953 | |
e1623446 | 2954 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2955 | } |
2956 | ||
2dedbf58 | 2957 | static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2958 | { |
c79dd5b5 | 2959 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2960 | |
e1623446 | 2961 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2962 | |
e1623446 | 2963 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2964 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2965 | |
74bcdb33 | 2966 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
2967 | dev_kfree_skb_any(skb); |
2968 | ||
e1623446 | 2969 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
b481de9c ZY |
2970 | } |
2971 | ||
2dedbf58 JB |
2972 | static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw, |
2973 | struct ieee80211_vif *vif, | |
2974 | struct ieee80211_key_conf *keyconf, | |
2975 | struct ieee80211_sta *sta, | |
2976 | u32 iv32, u16 *phase1key) | |
ab885f8c | 2977 | { |
9f58671e | 2978 | struct iwl_priv *priv = hw->priv; |
a194e324 JB |
2979 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
2980 | ||
e1623446 | 2981 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2982 | |
a194e324 | 2983 | iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta, |
b3fbdcf4 | 2984 | iv32, phase1key); |
ab885f8c | 2985 | |
e1623446 | 2986 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2987 | } |
2988 | ||
2dedbf58 JB |
2989 | static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
2990 | struct ieee80211_vif *vif, | |
2991 | struct ieee80211_sta *sta, | |
2992 | struct ieee80211_key_conf *key) | |
b481de9c | 2993 | { |
c79dd5b5 | 2994 | struct iwl_priv *priv = hw->priv; |
a194e324 | 2995 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
c10afb6e | 2996 | struct iwl_rxon_context *ctx = vif_priv->ctx; |
42986796 WT |
2997 | int ret; |
2998 | u8 sta_id; | |
2999 | bool is_default_wep_key = false; | |
b481de9c | 3000 | |
e1623446 | 3001 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3002 | |
90e8e424 | 3003 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 3004 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3005 | return -EOPNOTSUPP; |
3006 | } | |
b481de9c | 3007 | |
274102a8 JB |
3008 | /* |
3009 | * To support IBSS RSN, don't program group keys in IBSS, the | |
3010 | * hardware will then not attempt to decrypt the frames. | |
3011 | */ | |
3012 | if (vif->type == NL80211_IFTYPE_ADHOC && | |
3013 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) | |
3014 | return -EOPNOTSUPP; | |
3015 | ||
a194e324 | 3016 | sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta); |
0af8bcae JB |
3017 | if (sta_id == IWL_INVALID_STATION) |
3018 | return -EINVAL; | |
b481de9c | 3019 | |
6974e363 | 3020 | mutex_lock(&priv->mutex); |
2a421b91 | 3021 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 | 3022 | |
a90178fa JB |
3023 | /* |
3024 | * If we are getting WEP group key and we didn't receive any key mapping | |
6974e363 EG |
3025 | * so far, we are in legacy wep mode (group key only), otherwise we are |
3026 | * in 1X mode. | |
a90178fa JB |
3027 | * In legacy wep mode, we use another host command to the uCode. |
3028 | */ | |
97359d12 JB |
3029 | if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || |
3030 | key->cipher == WLAN_CIPHER_SUITE_WEP104) && | |
54c8067a | 3031 | !sta) { |
6974e363 | 3032 | if (cmd == SET_KEY) |
c10afb6e | 3033 | is_default_wep_key = !ctx->key_mapping_keys; |
6974e363 | 3034 | else |
ccc038ab EG |
3035 | is_default_wep_key = |
3036 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 3037 | } |
052c4b9f | 3038 | |
b481de9c | 3039 | switch (cmd) { |
deb09c43 | 3040 | case SET_KEY: |
6974e363 | 3041 | if (is_default_wep_key) |
2995bafa | 3042 | ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key); |
deb09c43 | 3043 | else |
a194e324 JB |
3044 | ret = iwl_set_dynamic_key(priv, vif_priv->ctx, |
3045 | key, sta_id); | |
deb09c43 | 3046 | |
e1623446 | 3047 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
3048 | break; |
3049 | case DISABLE_KEY: | |
6974e363 | 3050 | if (is_default_wep_key) |
c10afb6e | 3051 | ret = iwl_remove_default_wep_key(priv, ctx, key); |
deb09c43 | 3052 | else |
c10afb6e | 3053 | ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id); |
deb09c43 | 3054 | |
e1623446 | 3055 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
3056 | break; |
3057 | default: | |
deb09c43 | 3058 | ret = -EINVAL; |
b481de9c ZY |
3059 | } |
3060 | ||
72e15d71 | 3061 | mutex_unlock(&priv->mutex); |
e1623446 | 3062 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3063 | |
deb09c43 | 3064 | return ret; |
b481de9c ZY |
3065 | } |
3066 | ||
2dedbf58 JB |
3067 | static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, |
3068 | struct ieee80211_vif *vif, | |
3069 | enum ieee80211_ampdu_mlme_action action, | |
3070 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, | |
3071 | u8 buf_size) | |
d783b061 TW |
3072 | { |
3073 | struct iwl_priv *priv = hw->priv; | |
4620fefa | 3074 | int ret = -EINVAL; |
7b090687 | 3075 | struct iwl_station_priv *sta_priv = (void *) sta->drv_priv; |
d783b061 | 3076 | |
e1623446 | 3077 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 3078 | sta->addr, tid); |
d783b061 TW |
3079 | |
3080 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
3081 | return -EACCES; | |
3082 | ||
4620fefa JB |
3083 | mutex_lock(&priv->mutex); |
3084 | ||
d783b061 TW |
3085 | switch (action) { |
3086 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 3087 | IWL_DEBUG_HT(priv, "start Rx\n"); |
4620fefa JB |
3088 | ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn); |
3089 | break; | |
d783b061 | 3090 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 3091 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
619753ff | 3092 | ret = iwl_sta_rx_agg_stop(priv, sta, tid); |
5c2207c6 | 3093 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa JB |
3094 | ret = 0; |
3095 | break; | |
d783b061 | 3096 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 3097 | IWL_DEBUG_HT(priv, "start Tx\n"); |
619753ff | 3098 | ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); |
d5a0ffa3 WYG |
3099 | if (ret == 0) { |
3100 | priv->_agn.agg_tids_count++; | |
3101 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3102 | priv->_agn.agg_tids_count); | |
3103 | } | |
4620fefa | 3104 | break; |
d783b061 | 3105 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 3106 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
619753ff | 3107 | ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); |
d5a0ffa3 WYG |
3108 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
3109 | priv->_agn.agg_tids_count--; | |
3110 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3111 | priv->_agn.agg_tids_count); | |
3112 | } | |
5c2207c6 | 3113 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa | 3114 | ret = 0; |
7cb1b088 WYG |
3115 | if (priv->cfg->ht_params && |
3116 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
94597ab2 JB |
3117 | struct iwl_station_priv *sta_priv = |
3118 | (void *) sta->drv_priv; | |
3119 | /* | |
3120 | * switch off RTS/CTS if it was previously enabled | |
3121 | */ | |
3122 | ||
3123 | sta_priv->lq_sta.lq.general_params.flags &= | |
3124 | ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
7e6a5886 JB |
3125 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), |
3126 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
94597ab2 | 3127 | } |
4620fefa | 3128 | break; |
f0527971 | 3129 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
c8823ec1 JB |
3130 | buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF); |
3131 | ||
3132 | iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size); | |
3133 | ||
7b090687 JB |
3134 | /* |
3135 | * If the limit is 0, then it wasn't initialised yet, | |
3136 | * use the default. We can do that since we take the | |
3137 | * minimum below, and we don't want to go above our | |
3138 | * default due to hardware restrictions. | |
3139 | */ | |
3140 | if (sta_priv->max_agg_bufsize == 0) | |
3141 | sta_priv->max_agg_bufsize = | |
3142 | LINK_QUAL_AGG_FRAME_LIMIT_DEF; | |
3143 | ||
3144 | /* | |
3145 | * Even though in theory the peer could have different | |
3146 | * aggregation reorder buffer sizes for different sessions, | |
3147 | * our ucode doesn't allow for that and has a global limit | |
3148 | * for each station. Therefore, use the minimum of all the | |
3149 | * aggregation sessions and our default value. | |
3150 | */ | |
3151 | sta_priv->max_agg_bufsize = | |
3152 | min(sta_priv->max_agg_bufsize, buf_size); | |
3153 | ||
7cb1b088 WYG |
3154 | if (priv->cfg->ht_params && |
3155 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
cfecc6b4 WYG |
3156 | /* |
3157 | * switch to RTS/CTS if it is the prefer protection | |
3158 | * method for HT traffic | |
3159 | */ | |
94597ab2 JB |
3160 | |
3161 | sta_priv->lq_sta.lq.general_params.flags |= | |
3162 | LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
cfecc6b4 | 3163 | } |
7b090687 JB |
3164 | |
3165 | sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit = | |
3166 | sta_priv->max_agg_bufsize; | |
3167 | ||
3168 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), | |
3169 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
cfecc6b4 | 3170 | ret = 0; |
d783b061 TW |
3171 | break; |
3172 | } | |
4620fefa JB |
3173 | mutex_unlock(&priv->mutex); |
3174 | ||
3175 | return ret; | |
d783b061 | 3176 | } |
9f58671e | 3177 | |
2dedbf58 JB |
3178 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
3179 | struct ieee80211_vif *vif, | |
3180 | struct ieee80211_sta *sta) | |
fe6b23dd RC |
3181 | { |
3182 | struct iwl_priv *priv = hw->priv; | |
3183 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
a194e324 | 3184 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
eafdfbd3 | 3185 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3186 | int ret; |
3187 | u8 sta_id; | |
3188 | ||
3189 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3190 | sta->addr); | |
da5ae1cf RC |
3191 | mutex_lock(&priv->mutex); |
3192 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
3193 | sta->addr); | |
3194 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
fe6b23dd RC |
3195 | |
3196 | atomic_set(&sta_priv->pending_frames, 0); | |
3197 | if (vif->type == NL80211_IFTYPE_AP) | |
3198 | sta_priv->client = true; | |
3199 | ||
a194e324 | 3200 | ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr, |
238d781d | 3201 | is_ap, sta, &sta_id); |
fe6b23dd RC |
3202 | if (ret) { |
3203 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3204 | sta->addr, ret); | |
3205 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 3206 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3207 | return ret; |
3208 | } | |
3209 | ||
fd1af15d JB |
3210 | sta_priv->common.sta_id = sta_id; |
3211 | ||
fe6b23dd | 3212 | /* Initialize rate scaling */ |
91dd6c27 | 3213 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3214 | sta->addr); |
3215 | iwl_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 3216 | mutex_unlock(&priv->mutex); |
fe6b23dd | 3217 | |
fd1af15d | 3218 | return 0; |
fe6b23dd RC |
3219 | } |
3220 | ||
2dedbf58 JB |
3221 | static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, |
3222 | struct ieee80211_channel_switch *ch_switch) | |
79d07325 WYG |
3223 | { |
3224 | struct iwl_priv *priv = hw->priv; | |
3225 | const struct iwl_channel_info *ch_info; | |
3226 | struct ieee80211_conf *conf = &hw->conf; | |
aa2dc6b5 | 3227 | struct ieee80211_channel *channel = ch_switch->channel; |
79d07325 | 3228 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
246ed355 JB |
3229 | /* |
3230 | * MULTI-FIXME | |
3231 | * When we add support for multiple interfaces, we need to | |
3232 | * revisit this. The channel switch command in the device | |
3233 | * only affects the BSS context, but what does that really | |
3234 | * mean? And what if we get a CSA on the second interface? | |
3235 | * This needs a lot of work. | |
3236 | */ | |
3237 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
79d07325 WYG |
3238 | u16 ch; |
3239 | unsigned long flags = 0; | |
3240 | ||
3241 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3242 | ||
dc1a4068 SG |
3243 | mutex_lock(&priv->mutex); |
3244 | ||
79d07325 | 3245 | if (iwl_is_rfkill(priv)) |
dc1a4068 | 3246 | goto out; |
79d07325 WYG |
3247 | |
3248 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3249 | test_bit(STATUS_SCANNING, &priv->status)) | |
dc1a4068 | 3250 | goto out; |
79d07325 | 3251 | |
246ed355 | 3252 | if (!iwl_is_associated_ctx(ctx)) |
dc1a4068 | 3253 | goto out; |
79d07325 WYG |
3254 | |
3255 | /* channel switch in progress */ | |
3256 | if (priv->switch_rxon.switch_in_progress == true) | |
dc1a4068 | 3257 | goto out; |
79d07325 | 3258 | |
79d07325 WYG |
3259 | if (priv->cfg->ops->lib->set_channel_switch) { |
3260 | ||
aa2dc6b5 | 3261 | ch = channel->hw_value; |
246ed355 | 3262 | if (le16_to_cpu(ctx->active.channel) != ch) { |
79d07325 | 3263 | ch_info = iwl_get_channel_info(priv, |
aa2dc6b5 | 3264 | channel->band, |
79d07325 WYG |
3265 | ch); |
3266 | if (!is_channel_valid(ch_info)) { | |
3267 | IWL_DEBUG_MAC80211(priv, "invalid channel\n"); | |
3268 | goto out; | |
3269 | } | |
3270 | spin_lock_irqsave(&priv->lock, flags); | |
3271 | ||
3272 | priv->current_ht_config.smps = conf->smps_mode; | |
3273 | ||
3274 | /* Configure HT40 channels */ | |
7e6a5886 JB |
3275 | ctx->ht.enabled = conf_is_ht(conf); |
3276 | if (ctx->ht.enabled) { | |
79d07325 | 3277 | if (conf_is_ht40_minus(conf)) { |
7e6a5886 | 3278 | ctx->ht.extension_chan_offset = |
79d07325 | 3279 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
7e6a5886 | 3280 | ctx->ht.is_40mhz = true; |
79d07325 | 3281 | } else if (conf_is_ht40_plus(conf)) { |
7e6a5886 | 3282 | ctx->ht.extension_chan_offset = |
79d07325 | 3283 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
7e6a5886 | 3284 | ctx->ht.is_40mhz = true; |
79d07325 | 3285 | } else { |
7e6a5886 | 3286 | ctx->ht.extension_chan_offset = |
79d07325 | 3287 | IEEE80211_HT_PARAM_CHA_SEC_NONE; |
7e6a5886 | 3288 | ctx->ht.is_40mhz = false; |
79d07325 WYG |
3289 | } |
3290 | } else | |
7e6a5886 | 3291 | ctx->ht.is_40mhz = false; |
79d07325 | 3292 | |
246ed355 JB |
3293 | if ((le16_to_cpu(ctx->staging.channel) != ch)) |
3294 | ctx->staging.flags = 0; | |
79d07325 | 3295 | |
246ed355 | 3296 | iwl_set_rxon_channel(priv, channel, ctx); |
79d07325 | 3297 | iwl_set_rxon_ht(priv, ht_conf); |
246ed355 | 3298 | iwl_set_flags_for_band(priv, ctx, channel->band, |
8bd413e6 | 3299 | ctx->vif); |
79d07325 WYG |
3300 | spin_unlock_irqrestore(&priv->lock, flags); |
3301 | ||
3302 | iwl_set_rate(priv); | |
3303 | /* | |
3304 | * at this point, staging_rxon has the | |
3305 | * configuration for channel switch | |
3306 | */ | |
3307 | if (priv->cfg->ops->lib->set_channel_switch(priv, | |
3308 | ch_switch)) | |
3309 | priv->switch_rxon.switch_in_progress = false; | |
3310 | } | |
3311 | } | |
3312 | out: | |
3313 | mutex_unlock(&priv->mutex); | |
79d07325 | 3314 | if (!priv->switch_rxon.switch_in_progress) |
8bd413e6 | 3315 | ieee80211_chswitch_done(ctx->vif, false); |
79d07325 WYG |
3316 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
3317 | } | |
3318 | ||
2dedbf58 JB |
3319 | static void iwlagn_configure_filter(struct ieee80211_hw *hw, |
3320 | unsigned int changed_flags, | |
3321 | unsigned int *total_flags, | |
3322 | u64 multicast) | |
8b8ab9d5 JB |
3323 | { |
3324 | struct iwl_priv *priv = hw->priv; | |
3325 | __le32 filter_or = 0, filter_nand = 0; | |
246ed355 | 3326 | struct iwl_rxon_context *ctx; |
8b8ab9d5 JB |
3327 | |
3328 | #define CHK(test, flag) do { \ | |
3329 | if (*total_flags & (test)) \ | |
3330 | filter_or |= (flag); \ | |
3331 | else \ | |
3332 | filter_nand |= (flag); \ | |
3333 | } while (0) | |
3334 | ||
3335 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", | |
3336 | changed_flags, *total_flags); | |
3337 | ||
3338 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
bdb84fec JB |
3339 | /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ |
3340 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); | |
8b8ab9d5 JB |
3341 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); |
3342 | ||
3343 | #undef CHK | |
3344 | ||
3345 | mutex_lock(&priv->mutex); | |
3346 | ||
246ed355 JB |
3347 | for_each_context(priv, ctx) { |
3348 | ctx->staging.filter_flags &= ~filter_nand; | |
3349 | ctx->staging.filter_flags |= filter_or; | |
749ff4ef SG |
3350 | |
3351 | /* | |
3352 | * Not committing directly because hardware can perform a scan, | |
3353 | * but we'll eventually commit the filter flags change anyway. | |
3354 | */ | |
246ed355 | 3355 | } |
8b8ab9d5 JB |
3356 | |
3357 | mutex_unlock(&priv->mutex); | |
3358 | ||
3359 | /* | |
3360 | * Receiving all multicast frames is always enabled by the | |
3361 | * default flags setup in iwl_connection_init_rx_config() | |
3362 | * since we currently do not support programming multicast | |
3363 | * filters into the device. | |
3364 | */ | |
3365 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
3366 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
3367 | } | |
3368 | ||
2dedbf58 | 3369 | static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop) |
716c74b0 WYG |
3370 | { |
3371 | struct iwl_priv *priv = hw->priv; | |
3372 | ||
3373 | mutex_lock(&priv->mutex); | |
3374 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3375 | ||
3376 | /* do not support "flush" */ | |
3377 | if (!priv->cfg->ops->lib->txfifo_flush) | |
3378 | goto done; | |
3379 | ||
3380 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
3381 | IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n"); | |
3382 | goto done; | |
3383 | } | |
3384 | if (iwl_is_rfkill(priv)) { | |
3385 | IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n"); | |
3386 | goto done; | |
3387 | } | |
3388 | ||
3389 | /* | |
3390 | * mac80211 will not push any more frames for transmit | |
3391 | * until the flush is completed | |
3392 | */ | |
3393 | if (drop) { | |
3394 | IWL_DEBUG_MAC80211(priv, "send flush command\n"); | |
3395 | if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { | |
3396 | IWL_ERR(priv, "flush request fail\n"); | |
3397 | goto done; | |
3398 | } | |
3399 | } | |
3400 | IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n"); | |
3401 | iwlagn_wait_tx_queue_empty(priv); | |
3402 | done: | |
3403 | mutex_unlock(&priv->mutex); | |
3404 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3405 | } | |
3406 | ||
9b9190d9 JB |
3407 | static void iwlagn_disable_roc(struct iwl_priv *priv) |
3408 | { | |
3409 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN]; | |
3410 | struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel); | |
3411 | ||
3412 | lockdep_assert_held(&priv->mutex); | |
3413 | ||
3414 | if (!ctx->is_active) | |
3415 | return; | |
3416 | ||
3417 | ctx->staging.dev_type = RXON_DEV_TYPE_2STA; | |
3418 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
3419 | iwl_set_rxon_channel(priv, chan, ctx); | |
3420 | iwl_set_flags_for_band(priv, ctx, chan->band, NULL); | |
3421 | ||
3422 | priv->_agn.hw_roc_channel = NULL; | |
3423 | ||
80b38fff | 3424 | iwlcore_commit_rxon(priv, ctx); |
9b9190d9 JB |
3425 | |
3426 | ctx->is_active = false; | |
3427 | } | |
3428 | ||
3429 | static void iwlagn_bg_roc_done(struct work_struct *work) | |
3430 | { | |
3431 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
3432 | _agn.hw_roc_work.work); | |
3433 | ||
3434 | mutex_lock(&priv->mutex); | |
3435 | ieee80211_remain_on_channel_expired(priv->hw); | |
3436 | iwlagn_disable_roc(priv); | |
3437 | mutex_unlock(&priv->mutex); | |
3438 | } | |
3439 | ||
3440 | static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw, | |
3441 | struct ieee80211_channel *channel, | |
3442 | enum nl80211_channel_type channel_type, | |
3443 | int duration) | |
3444 | { | |
3445 | struct iwl_priv *priv = hw->priv; | |
3446 | int err = 0; | |
3447 | ||
3448 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3449 | return -EOPNOTSUPP; | |
3450 | ||
3451 | if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes & | |
3452 | BIT(NL80211_IFTYPE_P2P_CLIENT))) | |
3453 | return -EOPNOTSUPP; | |
3454 | ||
3455 | mutex_lock(&priv->mutex); | |
3456 | ||
3457 | if (priv->contexts[IWL_RXON_CTX_PAN].is_active || | |
3458 | test_bit(STATUS_SCAN_HW, &priv->status)) { | |
3459 | err = -EBUSY; | |
3460 | goto out; | |
3461 | } | |
3462 | ||
3463 | priv->contexts[IWL_RXON_CTX_PAN].is_active = true; | |
3464 | priv->_agn.hw_roc_channel = channel; | |
3465 | priv->_agn.hw_roc_chantype = channel_type; | |
3466 | priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024); | |
80b38fff | 3467 | iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]); |
9b9190d9 JB |
3468 | queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work, |
3469 | msecs_to_jiffies(duration + 20)); | |
3470 | ||
94073919 | 3471 | msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */ |
9b9190d9 JB |
3472 | ieee80211_ready_on_channel(priv->hw); |
3473 | ||
3474 | out: | |
3475 | mutex_unlock(&priv->mutex); | |
3476 | ||
3477 | return err; | |
3478 | } | |
3479 | ||
3480 | static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw) | |
3481 | { | |
3482 | struct iwl_priv *priv = hw->priv; | |
3483 | ||
3484 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3485 | return -EOPNOTSUPP; | |
3486 | ||
3487 | cancel_delayed_work_sync(&priv->_agn.hw_roc_work); | |
3488 | ||
3489 | mutex_lock(&priv->mutex); | |
3490 | iwlagn_disable_roc(priv); | |
3491 | mutex_unlock(&priv->mutex); | |
3492 | ||
3493 | return 0; | |
3494 | } | |
3495 | ||
b481de9c ZY |
3496 | /***************************************************************************** |
3497 | * | |
3498 | * driver setup and teardown | |
3499 | * | |
3500 | *****************************************************************************/ | |
3501 | ||
4e39317d | 3502 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3503 | { |
d21050c7 | 3504 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3505 | |
3506 | init_waitqueue_head(&priv->wait_command_queue); | |
3507 | ||
5b9f8cd3 EG |
3508 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3509 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3510 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3511 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
65550636 | 3512 | INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush); |
bee008b7 | 3513 | INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency); |
fbba9410 | 3514 | INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config); |
4a4a9e81 TW |
3515 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3516 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
9b9190d9 | 3517 | INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done); |
2a421b91 | 3518 | |
2a421b91 | 3519 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3520 | |
4e39317d EG |
3521 | if (priv->cfg->ops->lib->setup_deferred_work) |
3522 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3523 | ||
3524 | init_timer(&priv->statistics_periodic); | |
3525 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3526 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3527 | |
a9e1cb6a WYG |
3528 | init_timer(&priv->ucode_trace); |
3529 | priv->ucode_trace.data = (unsigned long)priv; | |
3530 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3531 | ||
22de94de SG |
3532 | init_timer(&priv->watchdog); |
3533 | priv->watchdog.data = (unsigned long)priv; | |
3534 | priv->watchdog.function = iwl_bg_watchdog; | |
b74e31a9 | 3535 | |
d6b80618 WYG |
3536 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
3537 | iwl_irq_tasklet, (unsigned long)priv); | |
b481de9c ZY |
3538 | } |
3539 | ||
4e39317d | 3540 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3541 | { |
4e39317d EG |
3542 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3543 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3544 | |
3ae6a054 | 3545 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 3546 | cancel_delayed_work(&priv->alive_start); |
815e629b | 3547 | cancel_work_sync(&priv->run_time_calib_work); |
b481de9c | 3548 | cancel_work_sync(&priv->beacon_update); |
e7e16b90 SG |
3549 | |
3550 | iwl_cancel_scan_deferred_work(priv); | |
3551 | ||
bee008b7 | 3552 | cancel_work_sync(&priv->bt_full_concurrency); |
fbba9410 | 3553 | cancel_work_sync(&priv->bt_runtime_config); |
e7e16b90 | 3554 | |
4e39317d | 3555 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3556 | del_timer_sync(&priv->ucode_trace); |
b481de9c ZY |
3557 | } |
3558 | ||
89f186a8 RC |
3559 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3560 | struct ieee80211_rate *rates) | |
3561 | { | |
3562 | int i; | |
3563 | ||
3564 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3565 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3566 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3567 | rates[i].hw_value_short = i; | |
3568 | rates[i].flags = 0; | |
3569 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3570 | /* | |
3571 | * If CCK != 1M then set short preamble rate flag. | |
3572 | */ | |
3573 | rates[i].flags |= | |
3574 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3575 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3576 | } | |
3577 | } | |
3578 | } | |
3579 | ||
3580 | static int iwl_init_drv(struct iwl_priv *priv) | |
3581 | { | |
3582 | int ret; | |
3583 | ||
89f186a8 RC |
3584 | spin_lock_init(&priv->sta_lock); |
3585 | spin_lock_init(&priv->hcmd_lock); | |
3586 | ||
3587 | INIT_LIST_HEAD(&priv->free_frames); | |
3588 | ||
3589 | mutex_init(&priv->mutex); | |
3590 | ||
89f186a8 RC |
3591 | priv->ieee_channels = NULL; |
3592 | priv->ieee_rates = NULL; | |
3593 | priv->band = IEEE80211_BAND_2GHZ; | |
3594 | ||
3595 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3596 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3597 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 3598 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 3599 | |
8a472da4 WYG |
3600 | /* initialize force reset */ |
3601 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3602 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3603 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3604 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 | 3605 | |
410f2bb3 SG |
3606 | priv->rx_statistics_jiffies = jiffies; |
3607 | ||
89f186a8 RC |
3608 | /* Choose which receivers/antennas to use */ |
3609 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 JB |
3610 | priv->cfg->ops->hcmd->set_rxon_chain(priv, |
3611 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
89f186a8 RC |
3612 | |
3613 | iwl_init_scan_params(priv); | |
3614 | ||
22bf59a0 | 3615 | /* init bt coex */ |
7cb1b088 WYG |
3616 | if (priv->cfg->bt_params && |
3617 | priv->cfg->bt_params->advanced_bt_coexist) { | |
b6e116e8 WYG |
3618 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; |
3619 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
3620 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
22bf59a0 WYG |
3621 | priv->bt_on_thresh = BT_ON_THRESHOLD_DEF; |
3622 | priv->bt_duration = BT_DURATION_LIMIT_DEF; | |
3623 | priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF; | |
22bf59a0 WYG |
3624 | } |
3625 | ||
89f186a8 RC |
3626 | /* Set the tx_power_user_lmt to the lowest power level |
3627 | * this value will get overwritten by channel max power avg | |
3628 | * from eeprom */ | |
b744cb79 | 3629 | priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
a25a66ac | 3630 | priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
89f186a8 RC |
3631 | |
3632 | ret = iwl_init_channel_map(priv); | |
3633 | if (ret) { | |
3634 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3635 | goto err; | |
3636 | } | |
3637 | ||
3638 | ret = iwlcore_init_geos(priv); | |
3639 | if (ret) { | |
3640 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3641 | goto err_free_channel_map; | |
3642 | } | |
3643 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
3644 | ||
3645 | return 0; | |
3646 | ||
3647 | err_free_channel_map: | |
3648 | iwl_free_channel_map(priv); | |
3649 | err: | |
3650 | return ret; | |
3651 | } | |
3652 | ||
3653 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
3654 | { | |
3655 | iwl_calib_free_results(priv); | |
3656 | iwlcore_free_geos(priv); | |
3657 | iwl_free_channel_map(priv); | |
811ecc99 | 3658 | kfree(priv->scan_cmd); |
89f186a8 RC |
3659 | } |
3660 | ||
dc21b545 | 3661 | struct ieee80211_ops iwlagn_hw_ops = { |
2295c66b JB |
3662 | .tx = iwlagn_mac_tx, |
3663 | .start = iwlagn_mac_start, | |
3664 | .stop = iwlagn_mac_stop, | |
5b9f8cd3 EG |
3665 | .add_interface = iwl_mac_add_interface, |
3666 | .remove_interface = iwl_mac_remove_interface, | |
d4daaea6 | 3667 | .change_interface = iwl_mac_change_interface, |
2295c66b | 3668 | .config = iwlagn_mac_config, |
8b8ab9d5 | 3669 | .configure_filter = iwlagn_configure_filter, |
2295c66b JB |
3670 | .set_key = iwlagn_mac_set_key, |
3671 | .update_tkip_key = iwlagn_mac_update_tkip_key, | |
5b9f8cd3 | 3672 | .conf_tx = iwl_mac_conf_tx, |
2295c66b JB |
3673 | .bss_info_changed = iwlagn_bss_info_changed, |
3674 | .ampdu_action = iwlagn_mac_ampdu_action, | |
6ab10ff8 | 3675 | .hw_scan = iwl_mac_hw_scan, |
2295c66b | 3676 | .sta_notify = iwlagn_mac_sta_notify, |
fe6b23dd RC |
3677 | .sta_add = iwlagn_mac_sta_add, |
3678 | .sta_remove = iwl_mac_sta_remove, | |
2295c66b JB |
3679 | .channel_switch = iwlagn_mac_channel_switch, |
3680 | .flush = iwlagn_mac_flush, | |
a85d7cca | 3681 | .tx_last_beacon = iwl_mac_tx_last_beacon, |
9b9190d9 JB |
3682 | .remain_on_channel = iwl_mac_remain_on_channel, |
3683 | .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel, | |
266af4c7 JB |
3684 | .offchannel_tx = iwl_mac_offchannel_tx, |
3685 | .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait, | |
b481de9c ZY |
3686 | }; |
3687 | ||
e98a1302 | 3688 | static u32 iwl_hw_detect(struct iwl_priv *priv) |
3867fe04 | 3689 | { |
c2974a1d JB |
3690 | u8 rev_id; |
3691 | ||
3692 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id); | |
3693 | IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id); | |
e98a1302 | 3694 | return _iwl_read32(priv, CSR_HW_REV); |
3867fe04 WYG |
3695 | } |
3696 | ||
07d4f1ad WYG |
3697 | static int iwl_set_hw_params(struct iwl_priv *priv) |
3698 | { | |
3699 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; | |
3700 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
3701 | if (priv->cfg->mod_params->amsdu_size_8K) | |
3702 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K); | |
3703 | else | |
3704 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K); | |
3705 | ||
3706 | priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; | |
3707 | ||
3708 | if (priv->cfg->mod_params->disable_11n) | |
3709 | priv->cfg->sku &= ~IWL_SKU_N; | |
3710 | ||
3711 | /* Device-specific setup */ | |
3712 | return priv->cfg->ops->lib->set_hw_params(priv); | |
3713 | } | |
3714 | ||
e72f368b JB |
3715 | static const u8 iwlagn_bss_ac_to_fifo[] = { |
3716 | IWL_TX_FIFO_VO, | |
3717 | IWL_TX_FIFO_VI, | |
3718 | IWL_TX_FIFO_BE, | |
3719 | IWL_TX_FIFO_BK, | |
3720 | }; | |
3721 | ||
3722 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
3723 | 0, 1, 2, 3, | |
3724 | }; | |
3725 | ||
3726 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
3727 | IWL_TX_FIFO_VO_IPAN, | |
3728 | IWL_TX_FIFO_VI_IPAN, | |
3729 | IWL_TX_FIFO_BE_IPAN, | |
3730 | IWL_TX_FIFO_BK_IPAN, | |
3731 | }; | |
3732 | ||
3733 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
3734 | 7, 6, 5, 4, | |
3735 | }; | |
3736 | ||
5b9f8cd3 | 3737 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c | 3738 | { |
246ed355 | 3739 | int err = 0, i; |
c79dd5b5 | 3740 | struct iwl_priv *priv; |
b481de9c | 3741 | struct ieee80211_hw *hw; |
82b9a121 | 3742 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 3743 | unsigned long flags; |
c6fa17ed | 3744 | u16 pci_cmd, num_mac; |
e98a1302 | 3745 | u32 hw_rev; |
b481de9c | 3746 | |
316c30d9 AK |
3747 | /************************ |
3748 | * 1. Allocating HW data | |
3749 | ************************/ | |
3750 | ||
dc21b545 | 3751 | hw = iwl_alloc_all(cfg); |
1d0a082d | 3752 | if (!hw) { |
b481de9c ZY |
3753 | err = -ENOMEM; |
3754 | goto out; | |
3755 | } | |
1d0a082d AK |
3756 | priv = hw->priv; |
3757 | /* At this point both hw and priv are allocated. */ | |
3758 | ||
246ed355 JB |
3759 | /* |
3760 | * The default context is always valid, | |
3761 | * more may be discovered when firmware | |
3762 | * is loaded. | |
3763 | */ | |
3764 | priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); | |
3765 | ||
3766 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) | |
3767 | priv->contexts[i].ctxid = i; | |
3768 | ||
763cc3bf JB |
3769 | priv->contexts[IWL_RXON_CTX_BSS].always_active = true; |
3770 | priv->contexts[IWL_RXON_CTX_BSS].is_active = true; | |
8f2d3d2a JB |
3771 | priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; |
3772 | priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; | |
3773 | priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
8dfdb9d5 | 3774 | priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; |
2995bafa | 3775 | priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID; |
c10afb6e | 3776 | priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY; |
e72f368b JB |
3777 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo; |
3778 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue; | |
d0fe478c JB |
3779 | priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes = |
3780 | BIT(NL80211_IFTYPE_ADHOC); | |
3781 | priv->contexts[IWL_RXON_CTX_BSS].interface_modes = | |
3782 | BIT(NL80211_IFTYPE_STATION); | |
2295c66b | 3783 | priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP; |
d0fe478c JB |
3784 | priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS; |
3785 | priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS; | |
3786 | priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS; | |
ece9c4ee JB |
3787 | |
3788 | priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON; | |
3789 | priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING; | |
3790 | priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC; | |
3791 | priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM; | |
3792 | priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN; | |
3793 | priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY; | |
3794 | priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID; | |
3795 | priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION; | |
e72f368b JB |
3796 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo; |
3797 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue; | |
3798 | priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE; | |
d0fe478c JB |
3799 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes = |
3800 | BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP); | |
f35c0c56 WYG |
3801 | #ifdef CONFIG_IWL_P2P |
3802 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes |= | |
3803 | BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO); | |
3804 | #endif | |
d0fe478c JB |
3805 | priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP; |
3806 | priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA; | |
3807 | priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P; | |
ece9c4ee JB |
3808 | |
3809 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | |
8f2d3d2a | 3810 | |
b481de9c ZY |
3811 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3812 | ||
e1623446 | 3813 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 3814 | priv->cfg = cfg; |
b481de9c | 3815 | priv->pci_dev = pdev; |
40cefda9 | 3816 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 3817 | |
bee008b7 WYG |
3818 | /* is antenna coupling more than 35dB ? */ |
3819 | priv->bt_ant_couple_ok = | |
3820 | (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ? | |
3821 | true : false; | |
3822 | ||
9f28ebc3 | 3823 | /* enable/disable bt channel inhibition */ |
f37837c9 | 3824 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
9f28ebc3 WYG |
3825 | IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n", |
3826 | (priv->bt_ch_announce) ? "On" : "Off"); | |
f37837c9 | 3827 | |
20594eb0 WYG |
3828 | if (iwl_alloc_traffic_mem(priv)) |
3829 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3830 | |
316c30d9 AK |
3831 | /************************** |
3832 | * 2. Initializing PCI bus | |
3833 | **************************/ | |
1a7123cd JL |
3834 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
3835 | PCIE_LINK_STATE_CLKPM); | |
3836 | ||
316c30d9 AK |
3837 | if (pci_enable_device(pdev)) { |
3838 | err = -ENODEV; | |
3839 | goto out_ieee80211_free_hw; | |
3840 | } | |
3841 | ||
3842 | pci_set_master(pdev); | |
3843 | ||
093d874c | 3844 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 3845 | if (!err) |
093d874c | 3846 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 3847 | if (err) { |
093d874c | 3848 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3849 | if (!err) |
093d874c | 3850 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3851 | /* both attempts failed: */ |
316c30d9 | 3852 | if (err) { |
978785a3 | 3853 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 3854 | goto out_pci_disable_device; |
cc2a8ea8 | 3855 | } |
316c30d9 AK |
3856 | } |
3857 | ||
3858 | err = pci_request_regions(pdev, DRV_NAME); | |
3859 | if (err) | |
3860 | goto out_pci_disable_device; | |
3861 | ||
3862 | pci_set_drvdata(pdev, priv); | |
3863 | ||
316c30d9 AK |
3864 | |
3865 | /*********************** | |
3866 | * 3. Read REV register | |
3867 | ***********************/ | |
3868 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3869 | if (!priv->hw_base) { | |
3870 | err = -ENODEV; | |
3871 | goto out_pci_release_regions; | |
3872 | } | |
3873 | ||
e1623446 | 3874 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3875 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3876 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3877 | |
731a29b7 | 3878 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
3879 | * we should init now |
3880 | */ | |
3881 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 3882 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
3883 | |
3884 | /* | |
3885 | * stop and reset the on-board processor just in case it is in a | |
3886 | * strange state ... like being left stranded by a primary kernel | |
3887 | * and this is now the kdump kernel trying to start up | |
3888 | */ | |
3889 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
3890 | ||
e98a1302 | 3891 | hw_rev = iwl_hw_detect(priv); |
c11362c0 | 3892 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
e98a1302 | 3893 | priv->cfg->name, hw_rev); |
316c30d9 | 3894 | |
e7b63581 TW |
3895 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3896 | * PCI Tx retries from interfering with C3 CPU state */ | |
3897 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3898 | ||
086ed117 MA |
3899 | iwl_prepare_card_hw(priv); |
3900 | if (!priv->hw_ready) { | |
3901 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
3902 | goto out_iounmap; | |
3903 | } | |
3904 | ||
91238714 TW |
3905 | /***************** |
3906 | * 4. Read EEPROM | |
3907 | *****************/ | |
316c30d9 | 3908 | /* Read the EEPROM */ |
e98a1302 | 3909 | err = iwl_eeprom_init(priv, hw_rev); |
316c30d9 | 3910 | if (err) { |
15b1687c | 3911 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3912 | goto out_iounmap; |
3913 | } | |
8614f360 TW |
3914 | err = iwl_eeprom_check_version(priv); |
3915 | if (err) | |
c8f16138 | 3916 | goto out_free_eeprom; |
8614f360 | 3917 | |
21a5b3c6 WYG |
3918 | err = iwl_eeprom_check_sku(priv); |
3919 | if (err) | |
3920 | goto out_free_eeprom; | |
3921 | ||
02883017 | 3922 | /* extract MAC Address */ |
c6fa17ed WYG |
3923 | iwl_eeprom_get_mac(priv, priv->addresses[0].addr); |
3924 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr); | |
3925 | priv->hw->wiphy->addresses = priv->addresses; | |
3926 | priv->hw->wiphy->n_addresses = 1; | |
3927 | num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS); | |
3928 | if (num_mac > 1) { | |
3929 | memcpy(priv->addresses[1].addr, priv->addresses[0].addr, | |
3930 | ETH_ALEN); | |
3931 | priv->addresses[1].addr[5]++; | |
3932 | priv->hw->wiphy->n_addresses++; | |
3933 | } | |
316c30d9 AK |
3934 | |
3935 | /************************ | |
3936 | * 5. Setup HW constants | |
3937 | ************************/ | |
da154e30 | 3938 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3939 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3940 | goto out_free_eeprom; |
316c30d9 AK |
3941 | } |
3942 | ||
3943 | /******************* | |
6ba87956 | 3944 | * 6. Setup priv |
316c30d9 | 3945 | *******************/ |
b481de9c | 3946 | |
6ba87956 | 3947 | err = iwl_init_drv(priv); |
bf85ea4f | 3948 | if (err) |
399f4900 | 3949 | goto out_free_eeprom; |
bf85ea4f | 3950 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3951 | |
316c30d9 | 3952 | /******************** |
09f9bf79 | 3953 | * 7. Setup services |
316c30d9 | 3954 | ********************/ |
0359facc | 3955 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3956 | iwl_disable_interrupts(priv); |
0359facc | 3957 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3958 | |
6cd0b1cb HS |
3959 | pci_enable_msi(priv->pci_dev); |
3960 | ||
e39fdee1 WYG |
3961 | if (priv->cfg->ops->lib->isr_ops.alloc) |
3962 | priv->cfg->ops->lib->isr_ops.alloc(priv); | |
3963 | ||
3964 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr, | |
ef850d7c | 3965 | IRQF_SHARED, DRV_NAME, priv); |
6cd0b1cb HS |
3966 | if (err) { |
3967 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3968 | goto out_disable_msi; | |
3969 | } | |
316c30d9 | 3970 | |
4e39317d | 3971 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3972 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3973 | |
158bea07 JB |
3974 | /********************************************* |
3975 | * 8. Enable interrupts and read RFKILL state | |
3976 | *********************************************/ | |
6ba87956 | 3977 | |
554d1d02 | 3978 | /* enable rfkill interrupt: hw bug w/a */ |
6cd0b1cb HS |
3979 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); |
3980 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3981 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3982 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3983 | } | |
3984 | ||
554d1d02 | 3985 | iwl_enable_rfkill_int(priv); |
6cd0b1cb | 3986 | |
6cd0b1cb HS |
3987 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3988 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3989 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3990 | else | |
3991 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3992 | |
a60e77e5 JB |
3993 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3994 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3995 | |
58d0f361 | 3996 | iwl_power_initialize(priv); |
39b73fb1 | 3997 | iwl_tt_initialize(priv); |
158bea07 | 3998 | |
a15707d8 | 3999 | init_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4000 | |
b08dfd04 | 4001 | err = iwl_request_firmware(priv, true); |
158bea07 | 4002 | if (err) |
7d47618a | 4003 | goto out_destroy_workqueue; |
158bea07 | 4004 | |
b481de9c ZY |
4005 | return 0; |
4006 | ||
7d47618a | 4007 | out_destroy_workqueue: |
c8f16138 RC |
4008 | destroy_workqueue(priv->workqueue); |
4009 | priv->workqueue = NULL; | |
795cc0ad | 4010 | free_irq(priv->pci_dev->irq, priv); |
e39fdee1 WYG |
4011 | if (priv->cfg->ops->lib->isr_ops.free) |
4012 | priv->cfg->ops->lib->isr_ops.free(priv); | |
6cd0b1cb HS |
4013 | out_disable_msi: |
4014 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 4015 | iwl_uninit_drv(priv); |
073d3f5f TW |
4016 | out_free_eeprom: |
4017 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4018 | out_iounmap: |
4019 | pci_iounmap(pdev, priv->hw_base); | |
4020 | out_pci_release_regions: | |
316c30d9 | 4021 | pci_set_drvdata(pdev, NULL); |
623d563e | 4022 | pci_release_regions(pdev); |
b481de9c ZY |
4023 | out_pci_disable_device: |
4024 | pci_disable_device(pdev); | |
b481de9c | 4025 | out_ieee80211_free_hw: |
20594eb0 | 4026 | iwl_free_traffic_mem(priv); |
d7c76f4c | 4027 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
4028 | out: |
4029 | return err; | |
4030 | } | |
4031 | ||
5b9f8cd3 | 4032 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 4033 | { |
c79dd5b5 | 4034 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4035 | unsigned long flags; |
b481de9c ZY |
4036 | |
4037 | if (!priv) | |
4038 | return; | |
4039 | ||
a15707d8 | 4040 | wait_for_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4041 | |
e1623446 | 4042 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4043 | |
67249625 | 4044 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 4045 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 4046 | |
5b9f8cd3 EG |
4047 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
4048 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
4049 | * we need to set STATUS_EXIT_PENDING bit. |
4050 | */ | |
4051 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5ed540ae WYG |
4052 | |
4053 | iwl_leds_exit(priv); | |
4054 | ||
c4f55232 RR |
4055 | if (priv->mac80211_registered) { |
4056 | ieee80211_unregister_hw(priv->hw); | |
4057 | priv->mac80211_registered = 0; | |
0b124c31 | 4058 | } else { |
5b9f8cd3 | 4059 | iwl_down(priv); |
c4f55232 RR |
4060 | } |
4061 | ||
c166b25a BC |
4062 | /* |
4063 | * Make sure device is reset to low power before unloading driver. | |
4064 | * This may be redundant with iwl_down(), but there are paths to | |
4065 | * run iwl_down() without calling apm_ops.stop(), and there are | |
4066 | * paths to avoid running iwl_down() at all before leaving driver. | |
4067 | * This (inexpensive) call *makes sure* device is reset. | |
4068 | */ | |
14e8e4af | 4069 | iwl_apm_stop(priv); |
c166b25a | 4070 | |
39b73fb1 WYG |
4071 | iwl_tt_exit(priv); |
4072 | ||
0359facc MA |
4073 | /* make sure we flush any pending irq or |
4074 | * tasklet for the driver | |
4075 | */ | |
4076 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 4077 | iwl_disable_interrupts(priv); |
0359facc MA |
4078 | spin_unlock_irqrestore(&priv->lock, flags); |
4079 | ||
4080 | iwl_synchronize_irq(priv); | |
4081 | ||
5b9f8cd3 | 4082 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
4083 | |
4084 | if (priv->rxq.bd) | |
54b81550 | 4085 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 4086 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 4087 | |
073d3f5f | 4088 | iwl_eeprom_free(priv); |
b481de9c | 4089 | |
b481de9c | 4090 | |
948c171c MA |
4091 | /*netif_stop_queue(dev); */ |
4092 | flush_workqueue(priv->workqueue); | |
4093 | ||
5b9f8cd3 | 4094 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
4095 | * priv->workqueue... so we can't take down the workqueue |
4096 | * until now... */ | |
4097 | destroy_workqueue(priv->workqueue); | |
4098 | priv->workqueue = NULL; | |
20594eb0 | 4099 | iwl_free_traffic_mem(priv); |
b481de9c | 4100 | |
6cd0b1cb HS |
4101 | free_irq(priv->pci_dev->irq, priv); |
4102 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
4103 | pci_iounmap(pdev, priv->hw_base); |
4104 | pci_release_regions(pdev); | |
4105 | pci_disable_device(pdev); | |
4106 | pci_set_drvdata(pdev, NULL); | |
4107 | ||
6ba87956 | 4108 | iwl_uninit_drv(priv); |
b481de9c | 4109 | |
e39fdee1 WYG |
4110 | if (priv->cfg->ops->lib->isr_ops.free) |
4111 | priv->cfg->ops->lib->isr_ops.free(priv); | |
ef850d7c | 4112 | |
77834543 | 4113 | dev_kfree_skb(priv->beacon_skb); |
b481de9c ZY |
4114 | |
4115 | ieee80211_free_hw(priv->hw); | |
4116 | } | |
4117 | ||
b481de9c ZY |
4118 | |
4119 | /***************************************************************************** | |
4120 | * | |
4121 | * driver and module entry point | |
4122 | * | |
4123 | *****************************************************************************/ | |
4124 | ||
fed9017e | 4125 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 4126 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
ac592574 WYG |
4127 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ |
4128 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4129 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
4130 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4131 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4132 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4133 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
4134 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4135 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
4136 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4137 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
4138 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4139 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4140 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4141 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
4142 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4143 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
4144 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4145 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
4146 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4147 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4148 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4149 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
4150 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4151 | ||
4152 | /* 5300 Series WiFi */ | |
4153 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
4154 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4155 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
4156 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4157 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
4158 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4159 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
4160 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4161 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
4162 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4163 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
4164 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4165 | ||
4166 | /* 5350 Series WiFi/WiMax */ | |
4167 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
4168 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
4169 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
4170 | ||
4171 | /* 5150 Series Wifi/WiMax */ | |
4172 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
4173 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4174 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
4175 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
4176 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
4177 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4178 | ||
4179 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
4180 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4181 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
4182 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
4183 | |
4184 | /* 6x00 Series */ | |
5953a62e WYG |
4185 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
4186 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
4187 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
4188 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
4189 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
4190 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
4191 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
4192 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
4193 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
4194 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
4b3e8062 | 4195 | |
003ea981 | 4196 | /* 6x05 Series */ |
8b3ee296 WYG |
4197 | {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)}, |
4198 | {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)}, | |
4199 | {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)}, | |
4200 | {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)}, | |
4201 | {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)}, | |
4202 | {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)}, | |
4203 | {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)}, | |
1808972f | 4204 | |
003ea981 | 4205 | /* 6x30 Series */ |
8b3ee296 WYG |
4206 | {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)}, |
4207 | {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)}, | |
4208 | {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)}, | |
4209 | {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)}, | |
4210 | {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)}, | |
4211 | {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)}, | |
4212 | {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)}, | |
4213 | {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)}, | |
4214 | {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)}, | |
4215 | {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)}, | |
4216 | {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)}, | |
4217 | {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)}, | |
4218 | {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)}, | |
4219 | {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)}, | |
4220 | {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)}, | |
4221 | {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)}, | |
5953a62e WYG |
4222 | |
4223 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
4224 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
4225 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
4226 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
4227 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
4228 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
4229 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
4230 | ||
003ea981 | 4231 | /* 6150 WiFi/WiMax Series */ |
8b3ee296 WYG |
4232 | {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)}, |
4233 | {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)}, | |
4234 | {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)}, | |
4235 | {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)}, | |
4236 | {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)}, | |
4237 | {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)}, | |
03264339 | 4238 | |
77dcb6a9 | 4239 | /* 1000 Series WiFi */ |
4bd0914f WYG |
4240 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
4241 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
4242 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
4243 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
4244 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
4245 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
4246 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
4247 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
4248 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
4249 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
4250 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
4251 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
1de19ecc | 4252 | |
58a39090 | 4253 | /* 100 Series WiFi */ |
1de19ecc | 4254 | {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)}, |
2a21ff44 | 4255 | {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)}, |
1de19ecc | 4256 | {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)}, |
2a21ff44 | 4257 | {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)}, |
1de19ecc | 4258 | {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)}, |
2a21ff44 | 4259 | {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)}, |
58a39090 WYG |
4260 | |
4261 | /* 130 Series WiFi */ | |
4262 | {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)}, | |
4263 | {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)}, | |
4264 | {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)}, | |
4265 | {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)}, | |
4266 | {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)}, | |
4267 | {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)}, | |
4268 | ||
04b8e751 WYG |
4269 | /* 2x00 Series */ |
4270 | {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)}, | |
4271 | {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)}, | |
4272 | {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)}, | |
4273 | {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)}, | |
4274 | {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)}, | |
4275 | {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)}, | |
4276 | ||
4277 | /* 2x30 Series */ | |
4278 | {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)}, | |
4279 | {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)}, | |
4280 | {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)}, | |
4281 | {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)}, | |
4282 | {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)}, | |
4283 | {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)}, | |
4284 | ||
4285 | /* 6x35 Series */ | |
4286 | {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)}, | |
4287 | {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)}, | |
4288 | {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)}, | |
4289 | {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)}, | |
4290 | {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)}, | |
4291 | {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)}, | |
4292 | {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)}, | |
4293 | {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)}, | |
4294 | {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)}, | |
4295 | ||
4296 | /* 200 Series */ | |
4297 | {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)}, | |
4298 | {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)}, | |
4299 | {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)}, | |
4300 | {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)}, | |
4301 | {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)}, | |
4302 | {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)}, | |
4303 | ||
4304 | /* 230 Series */ | |
4305 | {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)}, | |
4306 | {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)}, | |
4307 | {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)}, | |
4308 | {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)}, | |
4309 | {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)}, | |
4310 | {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)}, | |
4311 | ||
fed9017e RR |
4312 | {0} |
4313 | }; | |
4314 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
4315 | ||
4316 | static struct pci_driver iwl_driver = { | |
b481de9c | 4317 | .name = DRV_NAME, |
fed9017e | 4318 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
4319 | .probe = iwl_pci_probe, |
4320 | .remove = __devexit_p(iwl_pci_remove), | |
f60dc013 | 4321 | .driver.pm = IWL_PM_OPS, |
b481de9c ZY |
4322 | }; |
4323 | ||
5b9f8cd3 | 4324 | static int __init iwl_init(void) |
b481de9c ZY |
4325 | { |
4326 | ||
4327 | int ret; | |
c96c31e4 JP |
4328 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); |
4329 | pr_info(DRV_COPYRIGHT "\n"); | |
897e1cf2 | 4330 | |
e227ceac | 4331 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 4332 | if (ret) { |
c96c31e4 | 4333 | pr_err("Unable to register rate control algorithm: %d\n", ret); |
897e1cf2 RC |
4334 | return ret; |
4335 | } | |
4336 | ||
fed9017e | 4337 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 4338 | if (ret) { |
c96c31e4 | 4339 | pr_err("Unable to initialize PCI module\n"); |
897e1cf2 | 4340 | goto error_register; |
b481de9c | 4341 | } |
b481de9c ZY |
4342 | |
4343 | return ret; | |
897e1cf2 | 4344 | |
897e1cf2 | 4345 | error_register: |
e227ceac | 4346 | iwlagn_rate_control_unregister(); |
897e1cf2 | 4347 | return ret; |
b481de9c ZY |
4348 | } |
4349 | ||
5b9f8cd3 | 4350 | static void __exit iwl_exit(void) |
b481de9c | 4351 | { |
fed9017e | 4352 | pci_unregister_driver(&iwl_driver); |
e227ceac | 4353 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
4354 | } |
4355 | ||
5b9f8cd3 EG |
4356 | module_exit(iwl_exit); |
4357 | module_init(iwl_init); | |
a562a9dd RC |
4358 | |
4359 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 4360 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
4361 | MODULE_PARM_DESC(debug, "debug output mask"); |
4362 | #endif | |
4363 | ||
2b068618 WYG |
4364 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); |
4365 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
2b068618 WYG |
4366 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); |
4367 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
2b068618 WYG |
4368 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); |
4369 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
2b068618 WYG |
4370 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, |
4371 | int, S_IRUGO); | |
4372 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
2b068618 WYG |
4373 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); |
4374 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
dd7a2509 JB |
4375 | |
4376 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | |
4377 | S_IRUGO); | |
4378 | MODULE_PARM_DESC(ucode_alternative, | |
4379 | "specify ucode alternative to use from ucode file"); | |
bee008b7 WYG |
4380 | |
4381 | module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO); | |
4382 | MODULE_PARM_DESC(antenna_coupling, | |
4383 | "specify antenna coupling in dB (defualt: 0 dB)"); | |
f37837c9 | 4384 | |
9f28ebc3 WYG |
4385 | module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO); |
4386 | MODULE_PARM_DESC(bt_ch_inhibition, | |
4387 | "Disable BT channel inhibition (default: enable)"); | |
b7977ffa SG |
4388 | |
4389 | module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO); | |
4390 | MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])"); | |
4391 | ||
4392 | module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO); | |
4393 | MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])"); |