Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
d43c36dc | 36 | #include <linux/sched.h> |
b481de9c ZY |
37 | #include <linux/skbuff.h> |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
b481de9c ZY |
44 | #include <net/mac80211.h> |
45 | ||
46 | #include <asm/div64.h> | |
47 | ||
a3139c59 SO |
48 | #define DRV_NAME "iwlagn" |
49 | ||
6bc913bd | 50 | #include "iwl-eeprom.h" |
3e0d4cb1 | 51 | #include "iwl-dev.h" |
fee1247a | 52 | #include "iwl-core.h" |
3395f6e9 | 53 | #include "iwl-io.h" |
b481de9c | 54 | #include "iwl-helpers.h" |
6974e363 | 55 | #include "iwl-sta.h" |
f0832f13 | 56 | #include "iwl-calib.h" |
a1175124 | 57 | #include "iwl-agn.h" |
b481de9c | 58 | |
416e1438 | 59 | |
b481de9c ZY |
60 | /****************************************************************************** |
61 | * | |
62 | * module boiler plate | |
63 | * | |
64 | ******************************************************************************/ | |
65 | ||
b481de9c ZY |
66 | /* |
67 | * module name, copyright, version, etc. | |
b481de9c | 68 | */ |
d783b061 | 69 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 70 | |
0a6857e7 | 71 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
72 | #define VD "d" |
73 | #else | |
74 | #define VD | |
75 | #endif | |
76 | ||
81963d68 | 77 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 78 | |
b481de9c ZY |
79 | |
80 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
81 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 82 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 83 | MODULE_LICENSE("GPL"); |
4fc22b21 | 84 | MODULE_ALIAS("iwl4965"); |
b481de9c | 85 | |
b481de9c | 86 | /** |
5b9f8cd3 | 87 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 88 | * |
01ebd063 | 89 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
90 | * the active_rxon structure is updated with the new data. This |
91 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
92 | * a HW tune is required based on the RXON structure changes. | |
93 | */ | |
e0158e61 | 94 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
95 | { |
96 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 97 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
98 | int ret; |
99 | bool new_assoc = | |
100 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 101 | |
fee1247a | 102 | if (!iwl_is_alive(priv)) |
43d59b32 | 103 | return -EBUSY; |
b481de9c ZY |
104 | |
105 | /* always get timestamp with Rx frame */ | |
106 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
107 | ||
8ccde88a | 108 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 109 | if (ret) { |
15b1687c | 110 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
111 | return -EINVAL; |
112 | } | |
113 | ||
0924e519 WYG |
114 | /* |
115 | * receive commit_rxon request | |
116 | * abort any previous channel switch if still in process | |
117 | */ | |
118 | if (priv->switch_rxon.switch_in_progress && | |
119 | (priv->switch_rxon.channel != priv->staging_rxon.channel)) { | |
120 | IWL_DEBUG_11H(priv, "abort channel switch on %d\n", | |
121 | le16_to_cpu(priv->switch_rxon.channel)); | |
122 | priv->switch_rxon.switch_in_progress = false; | |
123 | } | |
124 | ||
b481de9c | 125 | /* If we don't need to send a full RXON, we can use |
5b9f8cd3 | 126 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 127 | * and other flags for the current radio configuration. */ |
54559703 | 128 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
129 | ret = iwl_send_rxon_assoc(priv); |
130 | if (ret) { | |
15b1687c | 131 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 132 | return ret; |
b481de9c ZY |
133 | } |
134 | ||
135 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
a643565e | 136 | iwl_print_rx_config_cmd(priv); |
b481de9c ZY |
137 | return 0; |
138 | } | |
139 | ||
b481de9c ZY |
140 | /* If we are currently associated and the new config requires |
141 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
142 | * we must clear the associated from the active configuration | |
143 | * before we apply the new config */ | |
43d59b32 | 144 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 145 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
146 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
147 | ||
43d59b32 | 148 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 149 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
150 | &priv->active_rxon); |
151 | ||
152 | /* If the mask clearing failed then we set | |
153 | * active_rxon back to what it was previously */ | |
43d59b32 | 154 | if (ret) { |
b481de9c | 155 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 156 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 157 | return ret; |
b481de9c | 158 | } |
7e246191 RC |
159 | iwl_clear_ucode_stations(priv, false); |
160 | iwl_restore_stations(priv); | |
b481de9c ZY |
161 | } |
162 | ||
e1623446 | 163 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
164 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
165 | "* channel = %d\n" | |
e174961c | 166 | "* bssid = %pM\n", |
43d59b32 | 167 | (new_assoc ? "" : "out"), |
b481de9c | 168 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 169 | priv->staging_rxon.bssid_addr); |
b481de9c | 170 | |
90e8e424 | 171 | iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
172 | |
173 | /* Apply the new configuration | |
7e246191 RC |
174 | * RXON unassoc clears the station table in uCode so restoration of |
175 | * stations is needed after it (the RXON command) completes | |
43d59b32 EG |
176 | */ |
177 | if (!new_assoc) { | |
178 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 179 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 180 | if (ret) { |
15b1687c | 181 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
182 | return ret; |
183 | } | |
7e246191 | 184 | IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON. \n"); |
43d59b32 | 185 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); |
7e246191 RC |
186 | iwl_clear_ucode_stations(priv, false); |
187 | iwl_restore_stations(priv); | |
b481de9c ZY |
188 | } |
189 | ||
19cc1087 | 190 | priv->start_calib = 0; |
9185159d | 191 | if (new_assoc) { |
47eef9bd WYG |
192 | /* |
193 | * allow CTS-to-self if possible for new association. | |
194 | * this is relevant only for 5000 series and up, | |
195 | * but will not damage 4965 | |
196 | */ | |
197 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
198 | ||
43d59b32 EG |
199 | /* Apply the new configuration |
200 | * RXON assoc doesn't clear the station table in uCode, | |
201 | */ | |
202 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
203 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
204 | if (ret) { | |
15b1687c | 205 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
206 | return ret; |
207 | } | |
208 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c | 209 | } |
a643565e | 210 | iwl_print_rx_config_cmd(priv); |
b481de9c | 211 | |
36da7d70 ZY |
212 | iwl_init_sensitivity(priv); |
213 | ||
214 | /* If we issue a new RXON command which required a tune then we must | |
215 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
216 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
217 | if (ret) { | |
15b1687c | 218 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
219 | return ret; |
220 | } | |
221 | ||
b481de9c ZY |
222 | return 0; |
223 | } | |
224 | ||
5b9f8cd3 | 225 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
226 | { |
227 | ||
45823531 AK |
228 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
229 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 230 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
231 | } |
232 | ||
fcab423d | 233 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
234 | { |
235 | struct list_head *element; | |
236 | ||
e1623446 | 237 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
238 | priv->frames_count); |
239 | ||
240 | while (!list_empty(&priv->free_frames)) { | |
241 | element = priv->free_frames.next; | |
242 | list_del(element); | |
fcab423d | 243 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
244 | priv->frames_count--; |
245 | } | |
246 | ||
247 | if (priv->frames_count) { | |
39aadf8c | 248 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
249 | priv->frames_count); |
250 | priv->frames_count = 0; | |
251 | } | |
252 | } | |
253 | ||
fcab423d | 254 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 255 | { |
fcab423d | 256 | struct iwl_frame *frame; |
b481de9c ZY |
257 | struct list_head *element; |
258 | if (list_empty(&priv->free_frames)) { | |
259 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
260 | if (!frame) { | |
15b1687c | 261 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
262 | return NULL; |
263 | } | |
264 | ||
265 | priv->frames_count++; | |
266 | return frame; | |
267 | } | |
268 | ||
269 | element = priv->free_frames.next; | |
270 | list_del(element); | |
fcab423d | 271 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
272 | } |
273 | ||
fcab423d | 274 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
275 | { |
276 | memset(frame, 0, sizeof(*frame)); | |
277 | list_add(&frame->list, &priv->free_frames); | |
278 | } | |
279 | ||
47ff65c4 | 280 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
4bf64efd | 281 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 282 | int left) |
b481de9c | 283 | { |
3109ece1 | 284 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
285 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
286 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
287 | return 0; |
288 | ||
289 | if (priv->ibss_beacon->len > left) | |
290 | return 0; | |
291 | ||
292 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
293 | ||
294 | return priv->ibss_beacon->len; | |
295 | } | |
296 | ||
47ff65c4 DH |
297 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
298 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
299 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, | |
300 | u8 *beacon, u32 frame_size) | |
301 | { | |
302 | u16 tim_idx; | |
303 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
304 | ||
305 | /* | |
306 | * The index is relative to frame start but we start looking at the | |
307 | * variable-length part of the beacon. | |
308 | */ | |
309 | tim_idx = mgmt->u.beacon.variable - beacon; | |
310 | ||
311 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
312 | while ((tim_idx < (frame_size - 2)) && | |
313 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
314 | tim_idx += beacon[tim_idx+1] + 2; | |
315 | ||
316 | /* If TIM field was found, set variables */ | |
317 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
318 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
319 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
320 | } else | |
321 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
322 | } | |
323 | ||
5b9f8cd3 | 324 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 325 | struct iwl_frame *frame) |
4bf64efd TW |
326 | { |
327 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
328 | u32 frame_size; |
329 | u32 rate_flags; | |
330 | u32 rate; | |
331 | /* | |
332 | * We have to set up the TX command, the TX Beacon command, and the | |
333 | * beacon contents. | |
334 | */ | |
4bf64efd | 335 | |
47ff65c4 | 336 | /* Initialize memory */ |
4bf64efd TW |
337 | tx_beacon_cmd = &frame->u.beacon; |
338 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
339 | ||
47ff65c4 | 340 | /* Set up TX beacon contents */ |
4bf64efd | 341 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 342 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
343 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
344 | return 0; | |
4bf64efd | 345 | |
47ff65c4 | 346 | /* Set up TX command fields */ |
4bf64efd | 347 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
47ff65c4 DH |
348 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; |
349 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
350 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
351 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 352 | |
47ff65c4 DH |
353 | /* Set up TX beacon command fields */ |
354 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
355 | frame_size); | |
4bf64efd | 356 | |
47ff65c4 DH |
357 | /* Set up packet rate and flags */ |
358 | rate = iwl_rate_get_lowest_plcp(priv); | |
359 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); | |
360 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
361 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
362 | rate_flags |= RATE_MCS_CCK_MSK; | |
363 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
364 | rate_flags); | |
4bf64efd TW |
365 | |
366 | return sizeof(*tx_beacon_cmd) + frame_size; | |
367 | } | |
5b9f8cd3 | 368 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 369 | { |
fcab423d | 370 | struct iwl_frame *frame; |
b481de9c ZY |
371 | unsigned int frame_size; |
372 | int rc; | |
b481de9c | 373 | |
fcab423d | 374 | frame = iwl_get_free_frame(priv); |
b481de9c | 375 | if (!frame) { |
15b1687c | 376 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
377 | "command.\n"); |
378 | return -ENOMEM; | |
379 | } | |
380 | ||
47ff65c4 DH |
381 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
382 | if (!frame_size) { | |
383 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
384 | iwl_free_frame(priv, frame); | |
385 | return -EINVAL; | |
386 | } | |
b481de9c | 387 | |
857485c0 | 388 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
389 | &frame->u.cmd[0]); |
390 | ||
fcab423d | 391 | iwl_free_frame(priv, frame); |
b481de9c ZY |
392 | |
393 | return rc; | |
394 | } | |
395 | ||
7aaa1d79 SO |
396 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
397 | { | |
398 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
399 | ||
400 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
401 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
402 | addr |= | |
403 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
404 | ||
405 | return addr; | |
406 | } | |
407 | ||
408 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
409 | { | |
410 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
411 | ||
412 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
413 | } | |
414 | ||
415 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
416 | dma_addr_t addr, u16 len) | |
417 | { | |
418 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
419 | u16 hi_n_len = len << 4; | |
420 | ||
421 | put_unaligned_le32(addr, &tb->lo); | |
422 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
423 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
424 | ||
425 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
426 | ||
427 | tfd->num_tbs = idx + 1; | |
428 | } | |
429 | ||
430 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
431 | { | |
432 | return tfd->num_tbs & 0x1f; | |
433 | } | |
434 | ||
435 | /** | |
436 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
437 | * @priv - driver private data | |
438 | * @txq - tx queue | |
439 | * | |
440 | * Does NOT advance any TFD circular buffer read/write indexes | |
441 | * Does NOT free the TFD itself (which is within circular buffer) | |
442 | */ | |
443 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
444 | { | |
59606ffa | 445 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
446 | struct iwl_tfd *tfd; |
447 | struct pci_dev *dev = priv->pci_dev; | |
448 | int index = txq->q.read_ptr; | |
449 | int i; | |
450 | int num_tbs; | |
451 | ||
452 | tfd = &tfd_tmp[index]; | |
453 | ||
454 | /* Sanity check on number of chunks */ | |
455 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
456 | ||
457 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
458 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
459 | /* @todo issue fatal error, it is quite serious situation */ | |
460 | return; | |
461 | } | |
462 | ||
463 | /* Unmap tx_cmd */ | |
464 | if (num_tbs) | |
465 | pci_unmap_single(dev, | |
c2acea8e JB |
466 | pci_unmap_addr(&txq->meta[index], mapping), |
467 | pci_unmap_len(&txq->meta[index], len), | |
96891cee | 468 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
469 | |
470 | /* Unmap chunks, if any. */ | |
471 | for (i = 1; i < num_tbs; i++) { | |
472 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
473 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
474 | ||
475 | if (txq->txb) { | |
476 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
477 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
478 | } | |
479 | } | |
480 | } | |
481 | ||
482 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
483 | struct iwl_tx_queue *txq, | |
484 | dma_addr_t addr, u16 len, | |
485 | u8 reset, u8 pad) | |
486 | { | |
487 | struct iwl_queue *q; | |
59606ffa | 488 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
489 | u32 num_tbs; |
490 | ||
491 | q = &txq->q; | |
59606ffa SO |
492 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
493 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
494 | |
495 | if (reset) | |
496 | memset(tfd, 0, sizeof(*tfd)); | |
497 | ||
498 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
499 | ||
500 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
501 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
502 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
503 | IWL_NUM_OF_TBS); | |
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
508 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
509 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
510 | (unsigned long long)addr); | |
511 | ||
512 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
a8e74e27 SO |
517 | /* |
518 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
519 | * given Tx queue, and enable the DMA channel used for that queue. | |
520 | * | |
521 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
522 | * channels supported in hardware. | |
523 | */ | |
524 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
525 | struct iwl_tx_queue *txq) | |
526 | { | |
a8e74e27 SO |
527 | int txq_id = txq->q.id; |
528 | ||
a8e74e27 SO |
529 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
530 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
531 | txq->q.dma_addr >> 8); | |
532 | ||
a8e74e27 SO |
533 | return 0; |
534 | } | |
535 | ||
b481de9c ZY |
536 | /****************************************************************************** |
537 | * | |
538 | * Generic RX handler implementations | |
539 | * | |
540 | ******************************************************************************/ | |
885ba202 TW |
541 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
542 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 543 | { |
2f301227 | 544 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
885ba202 | 545 | struct iwl_alive_resp *palive; |
b481de9c ZY |
546 | struct delayed_work *pwork; |
547 | ||
548 | palive = &pkt->u.alive_frame; | |
549 | ||
e1623446 | 550 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
551 | "0x%01X 0x%01X\n", |
552 | palive->is_valid, palive->ver_type, | |
553 | palive->ver_subtype); | |
554 | ||
555 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 556 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
557 | memcpy(&priv->card_alive_init, |
558 | &pkt->u.alive_frame, | |
885ba202 | 559 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
560 | pwork = &priv->init_alive_start; |
561 | } else { | |
e1623446 | 562 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 563 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 564 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
565 | pwork = &priv->alive_start; |
566 | } | |
567 | ||
568 | /* We delay the ALIVE response by 5ms to | |
569 | * give the HW RF Kill time to activate... */ | |
570 | if (palive->is_valid == UCODE_VALID_OK) | |
571 | queue_delayed_work(priv->workqueue, pwork, | |
572 | msecs_to_jiffies(5)); | |
573 | else | |
39aadf8c | 574 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
575 | } |
576 | ||
5b9f8cd3 | 577 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 578 | { |
c79dd5b5 TW |
579 | struct iwl_priv *priv = |
580 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
581 | struct sk_buff *beacon; |
582 | ||
583 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 584 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
585 | |
586 | if (!beacon) { | |
15b1687c | 587 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
588 | return; |
589 | } | |
590 | ||
591 | mutex_lock(&priv->mutex); | |
592 | /* new beacon skb is allocated every time; dispose previous.*/ | |
593 | if (priv->ibss_beacon) | |
594 | dev_kfree_skb(priv->ibss_beacon); | |
595 | ||
596 | priv->ibss_beacon = beacon; | |
597 | mutex_unlock(&priv->mutex); | |
598 | ||
5b9f8cd3 | 599 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
600 | } |
601 | ||
4e39317d | 602 | /** |
5b9f8cd3 | 603 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
604 | * |
605 | * This callback is provided in order to send a statistics request. | |
606 | * | |
607 | * This timer function is continually reset to execute within | |
608 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
609 | * was received. We need to ensure we receive the statistics in order | |
610 | * to update the temperature used for calibrating the TXPOWER. | |
611 | */ | |
5b9f8cd3 | 612 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
613 | { |
614 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
615 | ||
616 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
617 | return; | |
618 | ||
61780ee3 MA |
619 | /* dont send host command if rf-kill is on */ |
620 | if (!iwl_is_ready_rf(priv)) | |
621 | return; | |
622 | ||
ef8d5529 | 623 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
624 | } |
625 | ||
a9e1cb6a WYG |
626 | |
627 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
628 | u32 start_idx, u32 num_events, | |
629 | u32 mode) | |
630 | { | |
631 | u32 i; | |
632 | u32 ptr; /* SRAM byte address of log data */ | |
633 | u32 ev, time, data; /* event log data */ | |
634 | unsigned long reg_flags; | |
635 | ||
636 | if (mode == 0) | |
637 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
638 | else | |
639 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
640 | ||
641 | /* Make sure device is powered up for SRAM reads */ | |
642 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
643 | if (iwl_grab_nic_access(priv)) { | |
644 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
645 | return; | |
646 | } | |
647 | ||
648 | /* Set starting address; reads will auto-increment */ | |
649 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
650 | rmb(); | |
651 | ||
652 | /* | |
653 | * "time" is actually "data" for mode 0 (no timestamp). | |
654 | * place event id # at far right for easier visual parsing. | |
655 | */ | |
656 | for (i = 0; i < num_events; i++) { | |
657 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
658 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
659 | if (mode == 0) { | |
660 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
661 | 0, time, ev); | |
662 | } else { | |
663 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
664 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
665 | time, data, ev); | |
666 | } | |
667 | } | |
668 | /* Allow device to power down */ | |
669 | iwl_release_nic_access(priv); | |
670 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
671 | } | |
672 | ||
875295f1 | 673 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
674 | { |
675 | u32 capacity; /* event log capacity in # entries */ | |
676 | u32 base; /* SRAM byte address of event log header */ | |
677 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
678 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
679 | u32 next_entry; /* index of next entry to be written by uCode */ | |
680 | ||
681 | if (priv->ucode_type == UCODE_INIT) | |
682 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
683 | else | |
684 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
685 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
686 | capacity = iwl_read_targ_mem(priv, base); | |
687 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
688 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
689 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
690 | } else | |
691 | return; | |
692 | ||
693 | if (num_wraps == priv->event_log.num_wraps) { | |
694 | iwl_print_cont_event_trace(priv, | |
695 | base, priv->event_log.next_entry, | |
696 | next_entry - priv->event_log.next_entry, | |
697 | mode); | |
698 | priv->event_log.non_wraps_count++; | |
699 | } else { | |
700 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
701 | priv->event_log.wraps_more_count++; | |
702 | else | |
703 | priv->event_log.wraps_once_count++; | |
704 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
705 | num_wraps - priv->event_log.num_wraps, | |
706 | next_entry, priv->event_log.next_entry); | |
707 | if (next_entry < priv->event_log.next_entry) { | |
708 | iwl_print_cont_event_trace(priv, base, | |
709 | priv->event_log.next_entry, | |
710 | capacity - priv->event_log.next_entry, | |
711 | mode); | |
712 | ||
713 | iwl_print_cont_event_trace(priv, base, 0, | |
714 | next_entry, mode); | |
715 | } else { | |
716 | iwl_print_cont_event_trace(priv, base, | |
717 | next_entry, capacity - next_entry, | |
718 | mode); | |
719 | ||
720 | iwl_print_cont_event_trace(priv, base, 0, | |
721 | next_entry, mode); | |
722 | } | |
723 | } | |
724 | priv->event_log.num_wraps = num_wraps; | |
725 | priv->event_log.next_entry = next_entry; | |
726 | } | |
727 | ||
728 | /** | |
729 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
730 | * | |
731 | * The timer is continually set to execute every | |
732 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
733 | * this function is to perform continuous uCode event logging operation | |
734 | * if enabled | |
735 | */ | |
736 | static void iwl_bg_ucode_trace(unsigned long data) | |
737 | { | |
738 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
739 | ||
740 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
741 | return; | |
742 | ||
743 | if (priv->event_log.ucode_trace) { | |
744 | iwl_continuous_event_trace(priv); | |
745 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
746 | mod_timer(&priv->ucode_trace, | |
747 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
748 | } | |
749 | } | |
750 | ||
5b9f8cd3 | 751 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 752 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 753 | { |
0a6857e7 | 754 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 755 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
2aa6ab86 TW |
756 | struct iwl4965_beacon_notif *beacon = |
757 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 758 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 759 | |
e1623446 | 760 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 761 | "tsf %d %d rate %d\n", |
25a6572c | 762 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
763 | beacon->beacon_notify_hdr.failure_frame, |
764 | le32_to_cpu(beacon->ibss_mgr_status), | |
765 | le32_to_cpu(beacon->high_tsf), | |
766 | le32_to_cpu(beacon->low_tsf), rate); | |
767 | #endif | |
768 | ||
05c914fe | 769 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
770 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
771 | queue_work(priv->workqueue, &priv->beacon_update); | |
772 | } | |
773 | ||
b481de9c ZY |
774 | /* Handle notification from uCode that card's power state is changing |
775 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 776 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 777 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 778 | { |
2f301227 | 779 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
780 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
781 | unsigned long status = priv->status; | |
782 | ||
3a41bbd5 | 783 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n", |
b481de9c | 784 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
3a41bbd5 WYG |
785 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", |
786 | (flags & CT_CARD_DISABLED) ? | |
787 | "Reached" : "Not reached"); | |
b481de9c ZY |
788 | |
789 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3a41bbd5 | 790 | CT_CARD_DISABLED)) { |
b481de9c | 791 | |
3395f6e9 | 792 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
793 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
794 | ||
a8b50a0a MA |
795 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
796 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
797 | |
798 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 799 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 800 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 801 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 802 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 803 | } |
3a41bbd5 | 804 | if (flags & CT_CARD_DISABLED) |
39b73fb1 | 805 | iwl_tt_enter_ct_kill(priv); |
b481de9c | 806 | } |
3a41bbd5 | 807 | if (!(flags & CT_CARD_DISABLED)) |
39b73fb1 | 808 | iwl_tt_exit_ct_kill(priv); |
b481de9c ZY |
809 | |
810 | if (flags & HW_CARD_DISABLED) | |
811 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
812 | else | |
813 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
814 | ||
815 | ||
b481de9c | 816 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 817 | iwl_scan_cancel(priv); |
b481de9c ZY |
818 | |
819 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
820 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
821 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
822 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
823 | else |
824 | wake_up_interruptible(&priv->wait_command_queue); | |
825 | } | |
826 | ||
5b9f8cd3 | 827 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 828 | { |
e2e3c57b | 829 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 830 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
831 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
832 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
833 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
834 | } else { | |
835 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
836 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
837 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
838 | } | |
839 | ||
a8b50a0a | 840 | return 0; |
e2e3c57b TW |
841 | } |
842 | ||
b481de9c | 843 | /** |
5b9f8cd3 | 844 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
845 | * |
846 | * Setup the RX handlers for each of the reply types sent from the uCode | |
847 | * to the host. | |
848 | * | |
849 | * This function chains into the hardware specific files for them to setup | |
850 | * any hardware specific handlers as well. | |
851 | */ | |
653fa4a0 | 852 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 853 | { |
885ba202 | 854 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
855 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
856 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
81963d68 RC |
857 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
858 | iwl_rx_spectrum_measure_notif; | |
5b9f8cd3 | 859 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 860 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
861 | iwl_rx_pm_debug_statistics_notif; |
862 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 863 | |
9fbab516 BC |
864 | /* |
865 | * The same handler is used for both the REPLY to a discrete | |
866 | * statistics request from the host as well as for the periodic | |
867 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 868 | */ |
ef8d5529 | 869 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics; |
8f91aecb | 870 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; |
2a421b91 TW |
871 | |
872 | iwl_setup_rx_scan_handlers(priv); | |
873 | ||
37a44211 | 874 | /* status change handler */ |
5b9f8cd3 | 875 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 876 | |
c1354754 TW |
877 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
878 | iwl_rx_missed_beacon_notif; | |
37a44211 | 879 | /* Rx handlers */ |
8d801080 WYG |
880 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy; |
881 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx; | |
653fa4a0 | 882 | /* block ack */ |
74bcdb33 | 883 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba; |
9fbab516 | 884 | /* Set up hardware specific Rx handlers */ |
d4789efe | 885 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
886 | } |
887 | ||
b481de9c | 888 | /** |
a55360e4 | 889 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
890 | * |
891 | * Uses the priv->rx_handlers callback function array to invoke | |
892 | * the appropriate handlers, including command responses, | |
893 | * frame-received notifications, and other notifications. | |
894 | */ | |
a55360e4 | 895 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 896 | { |
a55360e4 | 897 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 898 | struct iwl_rx_packet *pkt; |
a55360e4 | 899 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
900 | u32 r, i; |
901 | int reclaim; | |
902 | unsigned long flags; | |
5c0eef96 | 903 | u8 fill_rx = 0; |
d68ab680 | 904 | u32 count = 8; |
4752c93c | 905 | int total_empty; |
b481de9c | 906 | |
6440adb5 CB |
907 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
908 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 909 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
910 | i = rxq->read; |
911 | ||
912 | /* Rx interrupt, but nothing sent from uCode */ | |
913 | if (i == r) | |
e1623446 | 914 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 915 | |
4752c93c | 916 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 917 | total_empty = r - rxq->write_actual; |
4752c93c MA |
918 | if (total_empty < 0) |
919 | total_empty += RX_QUEUE_SIZE; | |
920 | ||
921 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
922 | fill_rx = 1; |
923 | ||
b481de9c ZY |
924 | while (i != r) { |
925 | rxb = rxq->queue[i]; | |
926 | ||
9fbab516 | 927 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
928 | * then a bug has been introduced in the queue refilling |
929 | * routines -- catch it here */ | |
930 | BUG_ON(rxb == NULL); | |
931 | ||
932 | rxq->queue[i] = NULL; | |
933 | ||
2f301227 ZY |
934 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
935 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
936 | PCI_DMA_FROMDEVICE); | |
937 | pkt = rxb_addr(rxb); | |
b481de9c | 938 | |
be1a71a1 JB |
939 | trace_iwlwifi_dev_rx(priv, pkt, |
940 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
941 | ||
b481de9c ZY |
942 | /* Reclaim a command buffer only if this packet is a response |
943 | * to a (driver-originated) command. | |
944 | * If the packet (e.g. Rx frame) originated from uCode, | |
945 | * there is no command buffer to reclaim. | |
946 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
947 | * but apparently a few don't get set; catch them here. */ | |
948 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
949 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 950 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 951 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 952 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
953 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
954 | (pkt->hdr.cmd != REPLY_TX); | |
955 | ||
956 | /* Based on type of command response or notification, | |
957 | * handle those that need handling via function in | |
5b9f8cd3 | 958 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 959 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 960 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 961 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 962 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 963 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
964 | } else { |
965 | /* No handling needed */ | |
e1623446 | 966 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
967 | "r %d i %d No handler needed for %s, 0x%02x\n", |
968 | r, i, get_cmd_string(pkt->hdr.cmd), | |
969 | pkt->hdr.cmd); | |
970 | } | |
971 | ||
29b1b268 ZY |
972 | /* |
973 | * XXX: After here, we should always check rxb->page | |
974 | * against NULL before touching it or its virtual | |
975 | * memory (pkt). Because some rx_handler might have | |
976 | * already taken or freed the pages. | |
977 | */ | |
978 | ||
b481de9c | 979 | if (reclaim) { |
2f301227 ZY |
980 | /* Invoke any callbacks, transfer the buffer to caller, |
981 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 982 | * as we reclaim the driver command queue */ |
29b1b268 | 983 | if (rxb->page) |
17b88929 | 984 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 985 | else |
39aadf8c | 986 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
987 | } |
988 | ||
7300515d ZY |
989 | /* Reuse the page if possible. For notification packets and |
990 | * SKBs that fail to Rx correctly, add them back into the | |
991 | * rx_free list for reuse later. */ | |
992 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 993 | if (rxb->page != NULL) { |
7300515d ZY |
994 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
995 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
996 | PCI_DMA_FROMDEVICE); | |
997 | list_add_tail(&rxb->list, &rxq->rx_free); | |
998 | rxq->free_count++; | |
999 | } else | |
1000 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1001 | |
b481de9c | 1002 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1003 | |
b481de9c | 1004 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1005 | /* If there are a lot of unused frames, |
1006 | * restock the Rx queue so ucode wont assert. */ | |
1007 | if (fill_rx) { | |
1008 | count++; | |
1009 | if (count >= 8) { | |
7300515d | 1010 | rxq->read = i; |
54b81550 | 1011 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
1012 | count = 0; |
1013 | } | |
1014 | } | |
b481de9c ZY |
1015 | } |
1016 | ||
1017 | /* Backtrack one entry */ | |
7300515d | 1018 | rxq->read = i; |
4752c93c | 1019 | if (fill_rx) |
54b81550 | 1020 | iwlagn_rx_replenish_now(priv); |
4752c93c | 1021 | else |
54b81550 | 1022 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 1023 | } |
a55360e4 | 1024 | |
0359facc MA |
1025 | /* call this function to flush any scheduled tasklet */ |
1026 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
1027 | { | |
a96a27f9 | 1028 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1029 | synchronize_irq(priv->pci_dev->irq); |
1030 | tasklet_kill(&priv->irq_tasklet); | |
1031 | } | |
1032 | ||
ef850d7c | 1033 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
1034 | { |
1035 | u32 inta, handled = 0; | |
1036 | u32 inta_fh; | |
1037 | unsigned long flags; | |
c2e61da2 | 1038 | u32 i; |
0a6857e7 | 1039 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1040 | u32 inta_mask; |
1041 | #endif | |
1042 | ||
1043 | spin_lock_irqsave(&priv->lock, flags); | |
1044 | ||
1045 | /* Ack/clear/reset pending uCode interrupts. | |
1046 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1047 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1048 | inta = iwl_read32(priv, CSR_INT); |
1049 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1050 | |
1051 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1052 | * Any new interrupts that happen after this, either while we're | |
1053 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1054 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1055 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1056 | |
0a6857e7 | 1057 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1058 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1059 | /* just for debug */ |
3395f6e9 | 1060 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1061 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1062 | inta, inta_mask, inta_fh); |
1063 | } | |
1064 | #endif | |
1065 | ||
2f301227 ZY |
1066 | spin_unlock_irqrestore(&priv->lock, flags); |
1067 | ||
b481de9c ZY |
1068 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1069 | * atomic, make sure that inta covers all the interrupts that | |
1070 | * we've discovered, even if FH interrupt came in just after | |
1071 | * reading CSR_INT. */ | |
6f83eaa1 | 1072 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1073 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1074 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1075 | inta |= CSR_INT_BIT_FH_TX; |
1076 | ||
1077 | /* Now service all interrupt bits discovered above. */ | |
1078 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1079 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1080 | |
1081 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1082 | iwl_disable_interrupts(priv); |
b481de9c | 1083 | |
a83b9141 | 1084 | priv->isr_stats.hw++; |
5b9f8cd3 | 1085 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1086 | |
1087 | handled |= CSR_INT_BIT_HW_ERR; | |
1088 | ||
b481de9c ZY |
1089 | return; |
1090 | } | |
1091 | ||
0a6857e7 | 1092 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1093 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1094 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1095 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1096 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1097 | "the frame/frames.\n"); |
a83b9141 WYG |
1098 | priv->isr_stats.sch++; |
1099 | } | |
b481de9c ZY |
1100 | |
1101 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1102 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1103 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1104 | priv->isr_stats.alive++; |
1105 | } | |
b481de9c ZY |
1106 | } |
1107 | #endif | |
1108 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1109 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1110 | |
9fbab516 | 1111 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1112 | if (inta & CSR_INT_BIT_RF_KILL) { |
1113 | int hw_rf_kill = 0; | |
3395f6e9 | 1114 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1115 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1116 | hw_rf_kill = 1; | |
1117 | ||
4c423a2b | 1118 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1119 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1120 | |
a83b9141 WYG |
1121 | priv->isr_stats.rfkill++; |
1122 | ||
a9efa652 | 1123 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1124 | * the driver allows loading the ucode even if the radio |
1125 | * is killed. Hence update the killswitch state here. The | |
1126 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1127 | */ |
6cd0b1cb HS |
1128 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1129 | if (hw_rf_kill) | |
1130 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1131 | else | |
1132 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1133 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 1134 | } |
b481de9c ZY |
1135 | |
1136 | handled |= CSR_INT_BIT_RF_KILL; | |
1137 | } | |
1138 | ||
9fbab516 | 1139 | /* Chip got too hot and stopped itself */ |
b481de9c | 1140 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1141 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1142 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1143 | handled |= CSR_INT_BIT_CT_KILL; |
1144 | } | |
1145 | ||
1146 | /* Error detected by uCode */ | |
1147 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1148 | IWL_ERR(priv, "Microcode SW error detected. " |
1149 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
1150 | priv->isr_stats.sw++; |
1151 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 1152 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1153 | handled |= CSR_INT_BIT_SW_ERR; |
1154 | } | |
1155 | ||
c2e61da2 BC |
1156 | /* |
1157 | * uCode wakes up after power-down sleep. | |
1158 | * Tell device about any new tx or host commands enqueued, | |
1159 | * and about any Rx buffers made available while asleep. | |
1160 | */ | |
b481de9c | 1161 | if (inta & CSR_INT_BIT_WAKEUP) { |
e1623446 | 1162 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1163 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
c2e61da2 BC |
1164 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1165 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
a83b9141 | 1166 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1167 | handled |= CSR_INT_BIT_WAKEUP; |
1168 | } | |
1169 | ||
1170 | /* All uCode command responses, including Tx command responses, | |
1171 | * Rx "responses" (frame-received notification), and other | |
1172 | * notifications from uCode come through here*/ | |
1173 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1174 | iwl_rx_handle(priv); |
a83b9141 | 1175 | priv->isr_stats.rx++; |
b481de9c ZY |
1176 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1177 | } | |
1178 | ||
c72cd19f | 1179 | /* This "Tx" DMA channel is used only for loading uCode */ |
b481de9c | 1180 | if (inta & CSR_INT_BIT_FH_TX) { |
c72cd19f | 1181 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
a83b9141 | 1182 | priv->isr_stats.tx++; |
b481de9c | 1183 | handled |= CSR_INT_BIT_FH_TX; |
c72cd19f | 1184 | /* Wake up uCode load routine, now that load is complete */ |
dbb983b7 RR |
1185 | priv->ucode_write_complete = 1; |
1186 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1187 | } |
1188 | ||
a83b9141 | 1189 | if (inta & ~handled) { |
15b1687c | 1190 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1191 | priv->isr_stats.unhandled++; |
1192 | } | |
b481de9c | 1193 | |
40cefda9 | 1194 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1195 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1196 | inta & ~priv->inta_mask); |
39aadf8c | 1197 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1198 | } |
1199 | ||
1200 | /* Re-enable all interrupts */ | |
0359facc MA |
1201 | /* only Re-enable if diabled by irq */ |
1202 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1203 | iwl_enable_interrupts(priv); |
b481de9c | 1204 | |
0a6857e7 | 1205 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1206 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1207 | inta = iwl_read32(priv, CSR_INT); |
1208 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1209 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1210 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1211 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1212 | } | |
1213 | #endif | |
b481de9c ZY |
1214 | } |
1215 | ||
ef850d7c MA |
1216 | /* tasklet for iwlagn interrupt */ |
1217 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1218 | { | |
1219 | u32 inta = 0; | |
1220 | u32 handled = 0; | |
1221 | unsigned long flags; | |
8756990f | 1222 | u32 i; |
ef850d7c MA |
1223 | #ifdef CONFIG_IWLWIFI_DEBUG |
1224 | u32 inta_mask; | |
1225 | #endif | |
1226 | ||
1227 | spin_lock_irqsave(&priv->lock, flags); | |
1228 | ||
1229 | /* Ack/clear/reset pending uCode interrupts. | |
1230 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1231 | */ | |
a4c8b2a6 | 1232 | iwl_write32(priv, CSR_INT, priv->_agn.inta); |
ef850d7c | 1233 | |
a4c8b2a6 | 1234 | inta = priv->_agn.inta; |
ef850d7c MA |
1235 | |
1236 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1237 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1238 | /* just for debug */ |
1239 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1240 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1241 | inta, inta_mask); | |
1242 | } | |
1243 | #endif | |
2f301227 ZY |
1244 | |
1245 | spin_unlock_irqrestore(&priv->lock, flags); | |
1246 | ||
a4c8b2a6 JB |
1247 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
1248 | priv->_agn.inta = 0; | |
ef850d7c MA |
1249 | |
1250 | /* Now service all interrupt bits discovered above. */ | |
1251 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1252 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1253 | |
1254 | /* Tell the device to stop sending interrupts */ | |
1255 | iwl_disable_interrupts(priv); | |
1256 | ||
1257 | priv->isr_stats.hw++; | |
1258 | iwl_irq_handle_error(priv); | |
1259 | ||
1260 | handled |= CSR_INT_BIT_HW_ERR; | |
1261 | ||
ef850d7c MA |
1262 | return; |
1263 | } | |
1264 | ||
1265 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1266 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1267 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1268 | if (inta & CSR_INT_BIT_SCD) { | |
1269 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1270 | "the frame/frames.\n"); | |
1271 | priv->isr_stats.sch++; | |
1272 | } | |
1273 | ||
1274 | /* Alive notification via Rx interrupt will do the real work */ | |
1275 | if (inta & CSR_INT_BIT_ALIVE) { | |
1276 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1277 | priv->isr_stats.alive++; | |
1278 | } | |
1279 | } | |
1280 | #endif | |
1281 | /* Safely ignore these bits for debug checks below */ | |
1282 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1283 | ||
1284 | /* HW RF KILL switch toggled */ | |
1285 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1286 | int hw_rf_kill = 0; | |
1287 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1288 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1289 | hw_rf_kill = 1; | |
1290 | ||
4c423a2b | 1291 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1292 | hw_rf_kill ? "disable radio" : "enable radio"); |
1293 | ||
1294 | priv->isr_stats.rfkill++; | |
1295 | ||
1296 | /* driver only loads ucode once setting the interface up. | |
1297 | * the driver allows loading the ucode even if the radio | |
1298 | * is killed. Hence update the killswitch state here. The | |
1299 | * rfkill handler will care about restarting if needed. | |
1300 | */ | |
1301 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1302 | if (hw_rf_kill) | |
1303 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1304 | else | |
1305 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1306 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1307 | } |
1308 | ||
1309 | handled |= CSR_INT_BIT_RF_KILL; | |
1310 | } | |
1311 | ||
1312 | /* Chip got too hot and stopped itself */ | |
1313 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1314 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1315 | priv->isr_stats.ctkill++; | |
1316 | handled |= CSR_INT_BIT_CT_KILL; | |
1317 | } | |
1318 | ||
1319 | /* Error detected by uCode */ | |
1320 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1321 | IWL_ERR(priv, "Microcode SW error detected. " | |
1322 | " Restarting 0x%X.\n", inta); | |
1323 | priv->isr_stats.sw++; | |
1324 | priv->isr_stats.sw_err = inta; | |
1325 | iwl_irq_handle_error(priv); | |
1326 | handled |= CSR_INT_BIT_SW_ERR; | |
1327 | } | |
1328 | ||
1329 | /* uCode wakes up after power-down sleep */ | |
1330 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1331 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1332 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
1333 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1334 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
1335 | |
1336 | priv->isr_stats.wakeup++; | |
1337 | ||
1338 | handled |= CSR_INT_BIT_WAKEUP; | |
1339 | } | |
1340 | ||
1341 | /* All uCode command responses, including Tx command responses, | |
1342 | * Rx "responses" (frame-received notification), and other | |
1343 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1344 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1345 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1346 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1347 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1348 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1349 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1350 | CSR49_FH_INT_RX_MASK); | |
1351 | } | |
1352 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1353 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1354 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1355 | } | |
1356 | /* Sending RX interrupt require many steps to be done in the | |
1357 | * the device: | |
1358 | * 1- write interrupt to current index in ICT table. | |
1359 | * 2- dma RX frame. | |
1360 | * 3- update RX shared data to indicate last write index. | |
1361 | * 4- send interrupt. | |
1362 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1363 | * but the shared data changes does not reflect this; |
1364 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1365 | */ |
74ba67ed BC |
1366 | |
1367 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1368 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1369 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1370 | iwl_rx_handle(priv); |
74ba67ed BC |
1371 | |
1372 | /* | |
1373 | * Enable periodic interrupt in 8 msec only if we received | |
1374 | * real RX interrupt (instead of just periodic int), to catch | |
1375 | * any dangling Rx interrupt. If it was just the periodic | |
1376 | * interrupt, there was no dangling Rx activity, and no need | |
1377 | * to extend the periodic interrupt; one-shot is enough. | |
1378 | */ | |
40cefda9 | 1379 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1380 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1381 | CSR_INT_PERIODIC_ENA); |
1382 | ||
ef850d7c | 1383 | priv->isr_stats.rx++; |
ef850d7c MA |
1384 | } |
1385 | ||
c72cd19f | 1386 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c MA |
1387 | if (inta & CSR_INT_BIT_FH_TX) { |
1388 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
c72cd19f | 1389 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1390 | priv->isr_stats.tx++; |
1391 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1392 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1393 | priv->ucode_write_complete = 1; |
1394 | wake_up_interruptible(&priv->wait_command_queue); | |
1395 | } | |
1396 | ||
1397 | if (inta & ~handled) { | |
1398 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1399 | priv->isr_stats.unhandled++; | |
1400 | } | |
1401 | ||
40cefda9 | 1402 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1403 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1404 | inta & ~priv->inta_mask); |
ef850d7c MA |
1405 | } |
1406 | ||
ef850d7c MA |
1407 | /* Re-enable all interrupts */ |
1408 | /* only Re-enable if diabled by irq */ | |
1409 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1410 | iwl_enable_interrupts(priv); | |
ef850d7c MA |
1411 | } |
1412 | ||
872c8ddc WYG |
1413 | /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */ |
1414 | #define ACK_CNT_RATIO (50) | |
1415 | #define BA_TIMEOUT_CNT (5) | |
1416 | #define BA_TIMEOUT_MAX (16) | |
1417 | ||
1418 | /** | |
1419 | * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries. | |
1420 | * | |
1421 | * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding | |
1422 | * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal | |
1423 | * operation state. | |
1424 | */ | |
1425 | bool iwl_good_ack_health(struct iwl_priv *priv, | |
1426 | struct iwl_rx_packet *pkt) | |
1427 | { | |
1428 | bool rc = true; | |
1429 | int actual_ack_cnt_delta, expected_ack_cnt_delta; | |
1430 | int ba_timeout_delta; | |
1431 | ||
1432 | actual_ack_cnt_delta = | |
1433 | le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) - | |
1434 | le32_to_cpu(priv->statistics.tx.actual_ack_cnt); | |
1435 | expected_ack_cnt_delta = | |
1436 | le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) - | |
1437 | le32_to_cpu(priv->statistics.tx.expected_ack_cnt); | |
1438 | ba_timeout_delta = | |
1439 | le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) - | |
1440 | le32_to_cpu(priv->statistics.tx.agg.ba_timeout); | |
1441 | if ((priv->_agn.agg_tids_count > 0) && | |
1442 | (expected_ack_cnt_delta > 0) && | |
1443 | (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta) | |
1444 | < ACK_CNT_RATIO) && | |
1445 | (ba_timeout_delta > BA_TIMEOUT_CNT)) { | |
1446 | IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d," | |
1447 | " expected_ack_cnt = %d\n", | |
1448 | actual_ack_cnt_delta, expected_ack_cnt_delta); | |
1449 | ||
1450 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1451 | IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n", | |
1452 | priv->delta_statistics.tx.rx_detected_cnt); | |
1453 | IWL_DEBUG_RADIO(priv, | |
1454 | "ack_or_ba_timeout_collision delta = %d\n", | |
1455 | priv->delta_statistics.tx. | |
1456 | ack_or_ba_timeout_collision); | |
1457 | #endif | |
1458 | IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n", | |
1459 | ba_timeout_delta); | |
1460 | if (!actual_ack_cnt_delta && | |
1461 | (ba_timeout_delta >= BA_TIMEOUT_MAX)) | |
1462 | rc = false; | |
1463 | } | |
1464 | return rc; | |
1465 | } | |
1466 | ||
a83b9141 | 1467 | |
b481de9c ZY |
1468 | /****************************************************************************** |
1469 | * | |
1470 | * uCode download functions | |
1471 | * | |
1472 | ******************************************************************************/ | |
1473 | ||
5b9f8cd3 | 1474 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1475 | { |
98c92211 TW |
1476 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1477 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1478 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1479 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1480 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1481 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1482 | } |
1483 | ||
5b9f8cd3 | 1484 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1485 | { |
1486 | /* Remove all resets to allow NIC to operate */ | |
1487 | iwl_write32(priv, CSR_RESET, 0); | |
1488 | } | |
1489 | ||
1490 | ||
b08dfd04 JB |
1491 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
1492 | static int iwl_mac_setup_register(struct iwl_priv *priv); | |
1493 | ||
1494 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) | |
1495 | { | |
1496 | const char *name_pre = priv->cfg->fw_name_pre; | |
1497 | ||
1498 | if (first) | |
1499 | priv->fw_index = priv->cfg->ucode_api_max; | |
1500 | else | |
1501 | priv->fw_index--; | |
1502 | ||
1503 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1504 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1505 | return -ENOENT; | |
1506 | } | |
1507 | ||
1508 | sprintf(priv->firmware_name, "%s%d%s", | |
1509 | name_pre, priv->fw_index, ".ucode"); | |
1510 | ||
1511 | IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n", | |
1512 | priv->firmware_name); | |
1513 | ||
1514 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1515 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1516 | iwl_ucode_callback); | |
1517 | } | |
1518 | ||
b481de9c | 1519 | /** |
b08dfd04 | 1520 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1521 | * |
b08dfd04 JB |
1522 | * If loaded successfully, copies the firmware into buffers |
1523 | * for the card to fetch (via DMA). | |
b481de9c | 1524 | */ |
b08dfd04 | 1525 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1526 | { |
b08dfd04 | 1527 | struct iwl_priv *priv = context; |
cc0f555d | 1528 | struct iwl_ucode_header *ucode; |
a0987a8d RC |
1529 | const unsigned int api_max = priv->cfg->ucode_api_max; |
1530 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
b481de9c ZY |
1531 | u8 *src; |
1532 | size_t len; | |
cc0f555d JS |
1533 | u32 api_ver, build; |
1534 | u32 inst_size, data_size, init_size, init_data_size, boot_size; | |
b08dfd04 | 1535 | int err; |
abdc2d62 | 1536 | u16 eeprom_ver; |
b481de9c | 1537 | |
b08dfd04 JB |
1538 | if (!ucode_raw) { |
1539 | IWL_ERR(priv, "request for firmware file '%s' failed.\n", | |
1540 | priv->firmware_name); | |
1541 | goto try_again; | |
b481de9c ZY |
1542 | } |
1543 | ||
b08dfd04 JB |
1544 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
1545 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 1546 | |
cc0f555d JS |
1547 | /* Make sure that we got at least the v1 header! */ |
1548 | if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { | |
15b1687c | 1549 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 1550 | goto try_again; |
b481de9c ZY |
1551 | } |
1552 | ||
1553 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1554 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1555 | |
c02b3acd | 1556 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1557 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
cc0f555d JS |
1558 | build = priv->cfg->ops->ucode->get_build(ucode, api_ver); |
1559 | inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver); | |
1560 | data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver); | |
1561 | init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver); | |
1562 | init_data_size = | |
1563 | priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver); | |
1564 | boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver); | |
1565 | src = priv->cfg->ops->ucode->get_data(ucode, api_ver); | |
b481de9c | 1566 | |
a0987a8d RC |
1567 | /* api_ver should match the api version forming part of the |
1568 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 1569 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
1570 | |
1571 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1572 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1573 | "Driver supports v%u, firmware is v%u.\n", |
1574 | api_max, api_ver); | |
b08dfd04 | 1575 | goto try_again; |
a0987a8d | 1576 | } |
b08dfd04 | 1577 | |
a0987a8d | 1578 | if (api_ver != api_max) |
978785a3 | 1579 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1580 | "got v%u. New firmware can be obtained " |
1581 | "from http://www.intellinuxwireless.org.\n", | |
1582 | api_max, api_ver); | |
1583 | ||
978785a3 TW |
1584 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1585 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1586 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1587 | IWL_UCODE_API(priv->ucode_ver), | |
1588 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d | 1589 | |
5ebeb5a6 RC |
1590 | snprintf(priv->hw->wiphy->fw_version, |
1591 | sizeof(priv->hw->wiphy->fw_version), | |
1592 | "%u.%u.%u.%u", | |
1593 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1594 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1595 | IWL_UCODE_API(priv->ucode_ver), | |
1596 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
1597 | ||
cc0f555d JS |
1598 | if (build) |
1599 | IWL_DEBUG_INFO(priv, "Build %u\n", build); | |
1600 | ||
abdc2d62 JS |
1601 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); |
1602 | IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n", | |
1603 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) | |
1604 | ? "OTP" : "EEPROM", eeprom_ver); | |
1605 | ||
e1623446 | 1606 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 1607 | priv->ucode_ver); |
e1623446 | 1608 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
b481de9c | 1609 | inst_size); |
e1623446 | 1610 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", |
b481de9c | 1611 | data_size); |
e1623446 | 1612 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", |
b481de9c | 1613 | init_size); |
e1623446 | 1614 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", |
b481de9c | 1615 | init_data_size); |
e1623446 | 1616 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", |
b481de9c ZY |
1617 | boot_size); |
1618 | ||
b08dfd04 JB |
1619 | /* |
1620 | * For any of the failures below (before allocating pci memory) | |
1621 | * we will try to load a version with a smaller API -- maybe the | |
1622 | * user just got a corrupted version of the latest API. | |
1623 | */ | |
1624 | ||
b481de9c | 1625 | /* Verify size of file vs. image size info in file's header */ |
cc0f555d JS |
1626 | if (ucode_raw->size != |
1627 | priv->cfg->ops->ucode->get_header_size(api_ver) + | |
b481de9c ZY |
1628 | inst_size + data_size + init_size + |
1629 | init_data_size + boot_size) { | |
1630 | ||
cc0f555d JS |
1631 | IWL_DEBUG_INFO(priv, |
1632 | "uCode file size %d does not match expected size\n", | |
1633 | (int)ucode_raw->size); | |
b08dfd04 | 1634 | goto try_again; |
b481de9c ZY |
1635 | } |
1636 | ||
1637 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1638 | if (inst_size > priv->hw_params.max_inst_size) { |
e1623446 | 1639 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 | 1640 | inst_size); |
b08dfd04 | 1641 | goto try_again; |
b481de9c ZY |
1642 | } |
1643 | ||
099b40b7 | 1644 | if (data_size > priv->hw_params.max_data_size) { |
e1623446 | 1645 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 | 1646 | data_size); |
b08dfd04 | 1647 | goto try_again; |
b481de9c | 1648 | } |
099b40b7 | 1649 | if (init_size > priv->hw_params.max_inst_size) { |
e1623446 TW |
1650 | IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", |
1651 | init_size); | |
b08dfd04 | 1652 | goto try_again; |
b481de9c | 1653 | } |
099b40b7 | 1654 | if (init_data_size > priv->hw_params.max_data_size) { |
e1623446 | 1655 | IWL_INFO(priv, "uCode init data len %d too large to fit in\n", |
90e759d1 | 1656 | init_data_size); |
b08dfd04 | 1657 | goto try_again; |
b481de9c | 1658 | } |
099b40b7 | 1659 | if (boot_size > priv->hw_params.max_bsm_size) { |
e1623446 TW |
1660 | IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", |
1661 | boot_size); | |
b08dfd04 | 1662 | goto try_again; |
b481de9c ZY |
1663 | } |
1664 | ||
1665 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1666 | ||
1667 | /* Runtime instructions and 2 copies of data: | |
1668 | * 1) unmodified from disk | |
1669 | * 2) backup cache for save/restore during power-downs */ | |
1670 | priv->ucode_code.len = inst_size; | |
98c92211 | 1671 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1672 | |
1673 | priv->ucode_data.len = data_size; | |
98c92211 | 1674 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1675 | |
1676 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1677 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1678 | |
1f304e4e ZY |
1679 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1680 | !priv->ucode_data_backup.v_addr) | |
1681 | goto err_pci_alloc; | |
1682 | ||
b481de9c | 1683 | /* Initialization instructions and data */ |
90e759d1 TW |
1684 | if (init_size && init_data_size) { |
1685 | priv->ucode_init.len = init_size; | |
98c92211 | 1686 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1687 | |
1688 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1689 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1690 | |
1691 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1692 | goto err_pci_alloc; | |
1693 | } | |
b481de9c ZY |
1694 | |
1695 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1696 | if (boot_size) { |
1697 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1698 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1699 | |
90e759d1 TW |
1700 | if (!priv->ucode_boot.v_addr) |
1701 | goto err_pci_alloc; | |
1702 | } | |
b481de9c ZY |
1703 | |
1704 | /* Copy images into buffers for card's bus-master reads ... */ | |
1705 | ||
1706 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 1707 | len = inst_size; |
e1623446 | 1708 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c | 1709 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
1710 | src += len; |
1711 | ||
e1623446 | 1712 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1713 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1714 | ||
1715 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1716 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
cc0f555d | 1717 | len = data_size; |
e1623446 | 1718 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1719 | memcpy(priv->ucode_data.v_addr, src, len); |
1720 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 1721 | src += len; |
b481de9c ZY |
1722 | |
1723 | /* Initialization instructions (3rd block) */ | |
1724 | if (init_size) { | |
cc0f555d | 1725 | len = init_size; |
e1623446 | 1726 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
90e759d1 | 1727 | len); |
b481de9c | 1728 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 1729 | src += len; |
b481de9c ZY |
1730 | } |
1731 | ||
1732 | /* Initialization data (4th block) */ | |
1733 | if (init_data_size) { | |
cc0f555d | 1734 | len = init_data_size; |
e1623446 | 1735 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
90e759d1 | 1736 | len); |
b481de9c | 1737 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 1738 | src += len; |
b481de9c ZY |
1739 | } |
1740 | ||
1741 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 1742 | len = boot_size; |
e1623446 | 1743 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1744 | memcpy(priv->ucode_boot.v_addr, src, len); |
1745 | ||
b08dfd04 JB |
1746 | /************************************************** |
1747 | * This is still part of probe() in a sense... | |
1748 | * | |
1749 | * 9. Setup and register with mac80211 and debugfs | |
1750 | **************************************************/ | |
1751 | err = iwl_mac_setup_register(priv); | |
1752 | if (err) | |
1753 | goto out_unbind; | |
1754 | ||
1755 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
1756 | if (err) | |
1757 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
1758 | ||
b481de9c ZY |
1759 | /* We have our copies now, allow OS release its copies */ |
1760 | release_firmware(ucode_raw); | |
b08dfd04 JB |
1761 | return; |
1762 | ||
1763 | try_again: | |
1764 | /* try next, if any */ | |
1765 | if (iwl_request_firmware(priv, false)) | |
1766 | goto out_unbind; | |
1767 | release_firmware(ucode_raw); | |
1768 | return; | |
b481de9c ZY |
1769 | |
1770 | err_pci_alloc: | |
15b1687c | 1771 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 1772 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 JB |
1773 | out_unbind: |
1774 | device_release_driver(&priv->pci_dev->dev); | |
b481de9c | 1775 | release_firmware(ucode_raw); |
b481de9c ZY |
1776 | } |
1777 | ||
b7a79404 RC |
1778 | static const char *desc_lookup_text[] = { |
1779 | "OK", | |
1780 | "FAIL", | |
1781 | "BAD_PARAM", | |
1782 | "BAD_CHECKSUM", | |
1783 | "NMI_INTERRUPT_WDG", | |
1784 | "SYSASSERT", | |
1785 | "FATAL_ERROR", | |
1786 | "BAD_COMMAND", | |
1787 | "HW_ERROR_TUNE_LOCK", | |
1788 | "HW_ERROR_TEMPERATURE", | |
1789 | "ILLEGAL_CHAN_FREQ", | |
1790 | "VCC_NOT_STABLE", | |
1791 | "FH_ERROR", | |
1792 | "NMI_INTERRUPT_HOST", | |
1793 | "NMI_INTERRUPT_ACTION_PT", | |
1794 | "NMI_INTERRUPT_UNKNOWN", | |
1795 | "UCODE_VERSION_MISMATCH", | |
1796 | "HW_ERROR_ABS_LOCK", | |
1797 | "HW_ERROR_CAL_LOCK_FAIL", | |
1798 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1799 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1800 | "NMI_TRM_HW_ER", | |
1801 | "NMI_INTERRUPT_TRM", | |
1802 | "NMI_INTERRUPT_BREAK_POINT" | |
1803 | "DEBUG_0", | |
1804 | "DEBUG_1", | |
1805 | "DEBUG_2", | |
1806 | "DEBUG_3", | |
a7fce6ee | 1807 | "ADVANCED SYSASSERT" |
b7a79404 RC |
1808 | }; |
1809 | ||
1810 | static const char *desc_lookup(int i) | |
1811 | { | |
1812 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | |
1813 | ||
1814 | if (i < 0 || i > max) | |
1815 | i = max; | |
1816 | ||
1817 | return desc_lookup_text[i]; | |
1818 | } | |
1819 | ||
1820 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1821 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1822 | ||
1823 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1824 | { | |
1825 | u32 data2, line; | |
1826 | u32 desc, time, count, base, data1; | |
1827 | u32 blink1, blink2, ilink1, ilink2; | |
1828 | ||
1829 | if (priv->ucode_type == UCODE_INIT) | |
1830 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
1831 | else | |
1832 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1833 | ||
1834 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
1835 | IWL_ERR(priv, |
1836 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
1837 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
b7a79404 RC |
1838 | return; |
1839 | } | |
1840 | ||
1841 | count = iwl_read_targ_mem(priv, base); | |
1842 | ||
1843 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1844 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
1845 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1846 | priv->status, count); | |
1847 | } | |
1848 | ||
1849 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
1850 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
1851 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
1852 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
1853 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
1854 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
1855 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
1856 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
1857 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
1858 | ||
be1a71a1 JB |
1859 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
1860 | blink1, blink2, ilink1, ilink2); | |
1861 | ||
b7a79404 RC |
1862 | IWL_ERR(priv, "Desc Time " |
1863 | "data1 data2 line\n"); | |
1864 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | |
1865 | desc_lookup(desc), desc, time, data1, data2, line); | |
1866 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); | |
1867 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
1868 | ilink1, ilink2); | |
1869 | ||
1870 | } | |
1871 | ||
1872 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1873 | ||
1874 | /** | |
1875 | * iwl_print_event_log - Dump error event log to syslog | |
1876 | * | |
1877 | */ | |
b03d7d0f WYG |
1878 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1879 | u32 num_events, u32 mode, | |
1880 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
1881 | { |
1882 | u32 i; | |
1883 | u32 base; /* SRAM byte address of event log header */ | |
1884 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1885 | u32 ptr; /* SRAM byte address of log data */ | |
1886 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1887 | unsigned long reg_flags; |
b7a79404 RC |
1888 | |
1889 | if (num_events == 0) | |
b03d7d0f | 1890 | return pos; |
b7a79404 RC |
1891 | if (priv->ucode_type == UCODE_INIT) |
1892 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1893 | else | |
1894 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1895 | ||
1896 | if (mode == 0) | |
1897 | event_size = 2 * sizeof(u32); | |
1898 | else | |
1899 | event_size = 3 * sizeof(u32); | |
1900 | ||
1901 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1902 | ||
e5854471 BC |
1903 | /* Make sure device is powered up for SRAM reads */ |
1904 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1905 | iwl_grab_nic_access(priv); | |
1906 | ||
1907 | /* Set starting address; reads will auto-increment */ | |
1908 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
1909 | rmb(); | |
1910 | ||
b7a79404 RC |
1911 | /* "time" is actually "data" for mode 0 (no timestamp). |
1912 | * place event id # at far right for easier visual parsing. */ | |
1913 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
1914 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
1915 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
1916 | if (mode == 0) { |
1917 | /* data, ev */ | |
b03d7d0f WYG |
1918 | if (bufsz) { |
1919 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1920 | "EVT_LOG:0x%08x:%04u\n", | |
1921 | time, ev); | |
1922 | } else { | |
1923 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1924 | time, ev); | |
1925 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
1926 | time, ev); | |
1927 | } | |
b7a79404 | 1928 | } else { |
e5854471 | 1929 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1930 | if (bufsz) { |
1931 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1932 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1933 | time, data, ev); | |
1934 | } else { | |
1935 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 1936 | time, data, ev); |
b03d7d0f WYG |
1937 | trace_iwlwifi_dev_ucode_event(priv, time, |
1938 | data, ev); | |
1939 | } | |
b7a79404 RC |
1940 | } |
1941 | } | |
e5854471 BC |
1942 | |
1943 | /* Allow device to power down */ | |
1944 | iwl_release_nic_access(priv); | |
1945 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 1946 | return pos; |
b7a79404 RC |
1947 | } |
1948 | ||
c341ddb2 WYG |
1949 | /** |
1950 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
1951 | */ | |
b03d7d0f WYG |
1952 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
1953 | u32 num_wraps, u32 next_entry, | |
1954 | u32 size, u32 mode, | |
1955 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
1956 | { |
1957 | /* | |
1958 | * display the newest DEFAULT_LOG_ENTRIES entries | |
1959 | * i.e the entries just before the next ont that uCode would fill. | |
1960 | */ | |
1961 | if (num_wraps) { | |
1962 | if (next_entry < size) { | |
b03d7d0f WYG |
1963 | pos = iwl_print_event_log(priv, |
1964 | capacity - (size - next_entry), | |
1965 | size - next_entry, mode, | |
1966 | pos, buf, bufsz); | |
1967 | pos = iwl_print_event_log(priv, 0, | |
1968 | next_entry, mode, | |
1969 | pos, buf, bufsz); | |
c341ddb2 | 1970 | } else |
b03d7d0f WYG |
1971 | pos = iwl_print_event_log(priv, next_entry - size, |
1972 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 1973 | } else { |
b03d7d0f WYG |
1974 | if (next_entry < size) { |
1975 | pos = iwl_print_event_log(priv, 0, next_entry, | |
1976 | mode, pos, buf, bufsz); | |
1977 | } else { | |
1978 | pos = iwl_print_event_log(priv, next_entry - size, | |
1979 | size, mode, pos, buf, bufsz); | |
1980 | } | |
c341ddb2 | 1981 | } |
b03d7d0f | 1982 | return pos; |
c341ddb2 WYG |
1983 | } |
1984 | ||
84c40692 BC |
1985 | /* For sanity check only. Actual size is determined by uCode, typ. 512 */ |
1986 | #define MAX_EVENT_LOG_SIZE (512) | |
1987 | ||
c341ddb2 WYG |
1988 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
1989 | ||
b03d7d0f WYG |
1990 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
1991 | char **buf, bool display) | |
b7a79404 RC |
1992 | { |
1993 | u32 base; /* SRAM byte address of event log header */ | |
1994 | u32 capacity; /* event log capacity in # entries */ | |
1995 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1996 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1997 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1998 | u32 size; /* # entries that we'll print */ | |
b03d7d0f WYG |
1999 | int pos = 0; |
2000 | size_t bufsz = 0; | |
b7a79404 RC |
2001 | |
2002 | if (priv->ucode_type == UCODE_INIT) | |
2003 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
2004 | else | |
2005 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
2006 | ||
2007 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2008 | IWL_ERR(priv, |
2009 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
2010 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
937c397e | 2011 | return -EINVAL; |
b7a79404 RC |
2012 | } |
2013 | ||
2014 | /* event log header */ | |
2015 | capacity = iwl_read_targ_mem(priv, base); | |
2016 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2017 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2018 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2019 | ||
84c40692 BC |
2020 | if (capacity > MAX_EVENT_LOG_SIZE) { |
2021 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", | |
2022 | capacity, MAX_EVENT_LOG_SIZE); | |
2023 | capacity = MAX_EVENT_LOG_SIZE; | |
2024 | } | |
2025 | ||
2026 | if (next_entry > MAX_EVENT_LOG_SIZE) { | |
2027 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", | |
2028 | next_entry, MAX_EVENT_LOG_SIZE); | |
2029 | next_entry = MAX_EVENT_LOG_SIZE; | |
2030 | } | |
2031 | ||
b7a79404 RC |
2032 | size = num_wraps ? capacity : next_entry; |
2033 | ||
2034 | /* bail out if nothing in log */ | |
2035 | if (size == 0) { | |
2036 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2037 | return pos; |
b7a79404 RC |
2038 | } |
2039 | ||
c341ddb2 | 2040 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2041 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2042 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2043 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2044 | #else | |
2045 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2046 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2047 | #endif | |
2048 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2049 | size); | |
b7a79404 | 2050 | |
c341ddb2 | 2051 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2052 | if (display) { |
2053 | if (full_log) | |
2054 | bufsz = capacity * 48; | |
2055 | else | |
2056 | bufsz = size * 48; | |
2057 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2058 | if (!*buf) | |
937c397e | 2059 | return -ENOMEM; |
b03d7d0f | 2060 | } |
c341ddb2 WYG |
2061 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2062 | /* | |
2063 | * if uCode has wrapped back to top of log, | |
2064 | * start at the oldest entry, | |
2065 | * i.e the next one that uCode would fill. | |
2066 | */ | |
2067 | if (num_wraps) | |
b03d7d0f WYG |
2068 | pos = iwl_print_event_log(priv, next_entry, |
2069 | capacity - next_entry, mode, | |
2070 | pos, buf, bufsz); | |
c341ddb2 | 2071 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2072 | pos = iwl_print_event_log(priv, 0, |
2073 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2074 | } else |
b03d7d0f WYG |
2075 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2076 | next_entry, size, mode, | |
2077 | pos, buf, bufsz); | |
c341ddb2 | 2078 | #else |
b03d7d0f WYG |
2079 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2080 | next_entry, size, mode, | |
2081 | pos, buf, bufsz); | |
b7a79404 | 2082 | #endif |
b03d7d0f | 2083 | return pos; |
c341ddb2 | 2084 | } |
b7a79404 | 2085 | |
b481de9c | 2086 | /** |
4a4a9e81 | 2087 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2088 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2089 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2090 | */ |
4a4a9e81 | 2091 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2092 | { |
57aab75a | 2093 | int ret = 0; |
b481de9c | 2094 | |
e1623446 | 2095 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2096 | |
2097 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2098 | /* We had an error bringing up the hardware, so take it | |
2099 | * all the way back down so we can try again */ | |
e1623446 | 2100 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2101 | goto restart; |
2102 | } | |
2103 | ||
2104 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2105 | * This is a paranoid check, because we would not have gotten the | |
2106 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 2107 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
2108 | /* Runtime instruction load was bad; |
2109 | * take it all the way back down so we can try again */ | |
e1623446 | 2110 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2111 | goto restart; |
2112 | } | |
2113 | ||
57aab75a TW |
2114 | ret = priv->cfg->ops->lib->alive_notify(priv); |
2115 | if (ret) { | |
39aadf8c WT |
2116 | IWL_WARN(priv, |
2117 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
2118 | goto restart; |
2119 | } | |
2120 | ||
5b9f8cd3 | 2121 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2122 | set_bit(STATUS_ALIVE, &priv->status); |
2123 | ||
b74e31a9 WYG |
2124 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
2125 | /* Enable timer to monitor the driver queues */ | |
2126 | mod_timer(&priv->monitor_recover, | |
2127 | jiffies + | |
2128 | msecs_to_jiffies(priv->cfg->monitor_recover_period)); | |
2129 | } | |
2130 | ||
fee1247a | 2131 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2132 | return; |
2133 | ||
36d6825b | 2134 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2135 | |
470ab2dd | 2136 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2137 | |
2f748dec WYG |
2138 | /* Configure Tx antenna selection based on H/W config */ |
2139 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2140 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2141 | ||
3109ece1 | 2142 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
2143 | struct iwl_rxon_cmd *active_rxon = |
2144 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
2145 | /* apply any changes in staging */ |
2146 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
2147 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2148 | } else { | |
2149 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 2150 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
45823531 AK |
2151 | |
2152 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2153 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2154 | ||
b481de9c ZY |
2155 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
2156 | } | |
2157 | ||
9fbab516 | 2158 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 2159 | iwl_send_bt_config(priv); |
b481de9c | 2160 | |
4a4a9e81 TW |
2161 | iwl_reset_run_time_calib(priv); |
2162 | ||
b481de9c | 2163 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 2164 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2165 | |
2166 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2167 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2168 | |
e932a609 | 2169 | iwl_leds_init(priv); |
fe00b5a5 | 2170 | |
e1623446 | 2171 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2172 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2173 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2174 | |
e312c24c | 2175 | iwl_power_update_mode(priv, true); |
7e246191 RC |
2176 | IWL_DEBUG_INFO(priv, "Updated power mode\n"); |
2177 | ||
c46fbefa | 2178 | |
b481de9c ZY |
2179 | return; |
2180 | ||
2181 | restart: | |
2182 | queue_work(priv->workqueue, &priv->restart); | |
2183 | } | |
2184 | ||
4e39317d | 2185 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2186 | |
5b9f8cd3 | 2187 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2188 | { |
2189 | unsigned long flags; | |
2190 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2191 | |
e1623446 | 2192 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2193 | |
b481de9c ZY |
2194 | if (!exit_pending) |
2195 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2196 | ||
7e246191 | 2197 | iwl_clear_ucode_stations(priv, true); |
b481de9c ZY |
2198 | |
2199 | /* Unblock any waiting calls */ | |
2200 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2201 | ||
b481de9c ZY |
2202 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2203 | * exiting the module */ | |
2204 | if (!exit_pending) | |
2205 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2206 | ||
2207 | /* stop and reset the on-board processor */ | |
3395f6e9 | 2208 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2209 | |
2210 | /* tell the device to stop sending interrupts */ | |
0359facc | 2211 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2212 | iwl_disable_interrupts(priv); |
0359facc MA |
2213 | spin_unlock_irqrestore(&priv->lock, flags); |
2214 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2215 | |
2216 | if (priv->mac80211_registered) | |
2217 | ieee80211_stop_queues(priv->hw); | |
2218 | ||
5b9f8cd3 | 2219 | /* If we have not previously called iwl_init() then |
a60e77e5 | 2220 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 2221 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2222 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2223 | STATUS_RF_KILL_HW | | |
9788864e RC |
2224 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2225 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
2226 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2227 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2228 | goto exit; |
2229 | } | |
2230 | ||
6da3a13e | 2231 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2232 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2233 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2234 | STATUS_RF_KILL_HW | | |
9788864e RC |
2235 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2236 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2237 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2238 | STATUS_FW_ERROR | |
2239 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2240 | STATUS_EXIT_PENDING; | |
b481de9c | 2241 | |
ef850d7c MA |
2242 | /* device going down, Stop using ICT table */ |
2243 | iwl_disable_ict(priv); | |
b481de9c | 2244 | |
74bcdb33 | 2245 | iwlagn_txq_ctx_stop(priv); |
54b81550 | 2246 | iwlagn_rxq_stop(priv); |
b481de9c | 2247 | |
309e731a BC |
2248 | /* Power-down device's busmaster DMA clocks */ |
2249 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2250 | udelay(5); |
2251 | ||
309e731a BC |
2252 | /* Make sure (redundant) we've released our request to stay awake */ |
2253 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
2254 | ||
4d2ccdb9 BC |
2255 | /* Stop the device, and put it in low power state */ |
2256 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
2257 | ||
b481de9c | 2258 | exit: |
885ba202 | 2259 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2260 | |
2261 | if (priv->ibss_beacon) | |
2262 | dev_kfree_skb(priv->ibss_beacon); | |
2263 | priv->ibss_beacon = NULL; | |
2264 | ||
2265 | /* clear out any free frames */ | |
fcab423d | 2266 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2267 | } |
2268 | ||
5b9f8cd3 | 2269 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2270 | { |
2271 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2272 | __iwl_down(priv); |
b481de9c | 2273 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2274 | |
4e39317d | 2275 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2276 | } |
2277 | ||
086ed117 MA |
2278 | #define HW_READY_TIMEOUT (50) |
2279 | ||
2280 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
2281 | { | |
2282 | int ret = 0; | |
2283 | ||
2284 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2285 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2286 | ||
2287 | /* See if we got it */ | |
2288 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2289 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2290 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2291 | HW_READY_TIMEOUT); | |
2292 | if (ret != -ETIMEDOUT) | |
2293 | priv->hw_ready = true; | |
2294 | else | |
2295 | priv->hw_ready = false; | |
2296 | ||
2297 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
2298 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
2299 | return ret; | |
2300 | } | |
2301 | ||
2302 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
2303 | { | |
2304 | int ret = 0; | |
2305 | ||
2306 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n"); | |
2307 | ||
3354a0f6 MA |
2308 | ret = iwl_set_hw_ready(priv); |
2309 | if (priv->hw_ready) | |
2310 | return ret; | |
2311 | ||
2312 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2313 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2314 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2315 | ||
2316 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2317 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2318 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2319 | ||
3354a0f6 | 2320 | /* HW should be ready by now, check again. */ |
086ed117 MA |
2321 | if (ret != -ETIMEDOUT) |
2322 | iwl_set_hw_ready(priv); | |
2323 | ||
2324 | return ret; | |
2325 | } | |
2326 | ||
b481de9c ZY |
2327 | #define MAX_HW_RESTARTS 5 |
2328 | ||
5b9f8cd3 | 2329 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2330 | { |
57aab75a TW |
2331 | int i; |
2332 | int ret; | |
b481de9c ZY |
2333 | |
2334 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2335 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2336 | return -EIO; |
2337 | } | |
2338 | ||
e903fbd4 | 2339 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2340 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
2341 | return -EIO; |
2342 | } | |
2343 | ||
086ed117 MA |
2344 | iwl_prepare_card_hw(priv); |
2345 | ||
2346 | if (!priv->hw_ready) { | |
2347 | IWL_WARN(priv, "Exit HW not ready\n"); | |
2348 | return -EIO; | |
2349 | } | |
2350 | ||
e655b9f0 | 2351 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 2352 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 2353 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2354 | else |
e655b9f0 | 2355 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2356 | |
c1842d61 | 2357 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2358 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2359 | ||
5b9f8cd3 | 2360 | iwl_enable_interrupts(priv); |
a60e77e5 | 2361 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2362 | return 0; |
b481de9c ZY |
2363 | } |
2364 | ||
3395f6e9 | 2365 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2366 | |
74bcdb33 | 2367 | ret = iwlagn_hw_nic_init(priv); |
57aab75a | 2368 | if (ret) { |
15b1687c | 2369 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2370 | return ret; |
b481de9c ZY |
2371 | } |
2372 | ||
2373 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2374 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2375 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2376 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2377 | ||
2378 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2379 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2380 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2381 | |
2382 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2383 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2384 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2385 | |
2386 | /* Copy original ucode data image from disk into backup cache. | |
2387 | * This will be used to initialize the on-board processor's | |
2388 | * data SRAM for a clean start when the runtime program first loads. */ | |
2389 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2390 | priv->ucode_data.len); |
b481de9c | 2391 | |
b481de9c ZY |
2392 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2393 | ||
b481de9c ZY |
2394 | /* load bootstrap state machine, |
2395 | * load bootstrap program into processor's memory, | |
2396 | * prepare to load the "initialize" uCode */ | |
57aab75a | 2397 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 2398 | |
57aab75a | 2399 | if (ret) { |
15b1687c WT |
2400 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
2401 | ret); | |
b481de9c ZY |
2402 | continue; |
2403 | } | |
2404 | ||
2405 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 2406 | iwl_nic_start(priv); |
b481de9c | 2407 | |
e1623446 | 2408 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2409 | |
2410 | return 0; | |
2411 | } | |
2412 | ||
2413 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 2414 | __iwl_down(priv); |
64e72c3e | 2415 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2416 | |
2417 | /* tried to restart and config the device for as long as our | |
2418 | * patience could withstand */ | |
15b1687c | 2419 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2420 | return -EIO; |
2421 | } | |
2422 | ||
2423 | ||
2424 | /***************************************************************************** | |
2425 | * | |
2426 | * Workqueue callbacks | |
2427 | * | |
2428 | *****************************************************************************/ | |
2429 | ||
4a4a9e81 | 2430 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2431 | { |
c79dd5b5 TW |
2432 | struct iwl_priv *priv = |
2433 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2434 | |
2435 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2436 | return; | |
2437 | ||
2438 | mutex_lock(&priv->mutex); | |
f3ccc08c | 2439 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
2440 | mutex_unlock(&priv->mutex); |
2441 | } | |
2442 | ||
4a4a9e81 | 2443 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 2444 | { |
c79dd5b5 TW |
2445 | struct iwl_priv *priv = |
2446 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2447 | |
2448 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2449 | return; | |
2450 | ||
258c44a0 MA |
2451 | /* enable dram interrupt */ |
2452 | iwl_reset_ict(priv); | |
2453 | ||
b481de9c | 2454 | mutex_lock(&priv->mutex); |
4a4a9e81 | 2455 | iwl_alive_start(priv); |
b481de9c ZY |
2456 | mutex_unlock(&priv->mutex); |
2457 | } | |
2458 | ||
16e727e8 EG |
2459 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2460 | { | |
2461 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2462 | run_time_calib_work); | |
2463 | ||
2464 | mutex_lock(&priv->mutex); | |
2465 | ||
2466 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2467 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2468 | mutex_unlock(&priv->mutex); | |
2469 | return; | |
2470 | } | |
2471 | ||
2472 | if (priv->start_calib) { | |
2473 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
2474 | ||
2475 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
2476 | } | |
2477 | ||
2478 | mutex_unlock(&priv->mutex); | |
2479 | return; | |
2480 | } | |
2481 | ||
5b9f8cd3 | 2482 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2483 | { |
c79dd5b5 | 2484 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2485 | |
2486 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2487 | return; | |
2488 | ||
19cc1087 JB |
2489 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2490 | mutex_lock(&priv->mutex); | |
2491 | priv->vif = NULL; | |
2492 | priv->is_open = 0; | |
2493 | mutex_unlock(&priv->mutex); | |
2494 | iwl_down(priv); | |
2495 | ieee80211_restart_hw(priv->hw); | |
2496 | } else { | |
2497 | iwl_down(priv); | |
80676518 JB |
2498 | |
2499 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2500 | return; | |
2501 | ||
2502 | mutex_lock(&priv->mutex); | |
2503 | __iwl_up(priv); | |
2504 | mutex_unlock(&priv->mutex); | |
19cc1087 | 2505 | } |
b481de9c ZY |
2506 | } |
2507 | ||
5b9f8cd3 | 2508 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2509 | { |
c79dd5b5 TW |
2510 | struct iwl_priv *priv = |
2511 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2512 | |
2513 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2514 | return; | |
2515 | ||
2516 | mutex_lock(&priv->mutex); | |
54b81550 | 2517 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
2518 | mutex_unlock(&priv->mutex); |
2519 | } | |
2520 | ||
7878a5a4 MA |
2521 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
2522 | ||
5bbe233b | 2523 | void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 2524 | { |
b481de9c | 2525 | struct ieee80211_conf *conf = NULL; |
857485c0 | 2526 | int ret = 0; |
b481de9c | 2527 | |
05c914fe | 2528 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 2529 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
2530 | return; |
2531 | } | |
2532 | ||
b481de9c ZY |
2533 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
2534 | return; | |
2535 | ||
b481de9c | 2536 | |
508e32e1 | 2537 | if (!priv->vif || !priv->is_open) |
948c171c | 2538 | return; |
508e32e1 | 2539 | |
2a421b91 | 2540 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2541 | |
b481de9c ZY |
2542 | conf = ieee80211_get_hw_conf(priv->hw); |
2543 | ||
2544 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2545 | iwlcore_commit_rxon(priv); |
b481de9c | 2546 | |
3195c1f3 | 2547 | iwl_setup_rxon_timing(priv); |
857485c0 | 2548 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2549 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2550 | if (ret) |
39aadf8c | 2551 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2552 | "Attempting to continue.\n"); |
2553 | ||
2554 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2555 | ||
42eb7c64 | 2556 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2557 | |
45823531 AK |
2558 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2559 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2560 | ||
b481de9c ZY |
2561 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
2562 | ||
e1623446 | 2563 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
2564 | priv->assoc_id, priv->beacon_int); |
2565 | ||
2566 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2567 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2568 | else | |
2569 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2570 | ||
2571 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2572 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2573 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2574 | else | |
2575 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2576 | ||
05c914fe | 2577 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2578 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2579 | ||
2580 | } | |
2581 | ||
e0158e61 | 2582 | iwlcore_commit_rxon(priv); |
b481de9c | 2583 | |
fe6b23dd RC |
2584 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
2585 | priv->assoc_id, priv->active_rxon.bssid_addr); | |
2586 | ||
b481de9c | 2587 | switch (priv->iw_mode) { |
05c914fe | 2588 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2589 | break; |
2590 | ||
05c914fe | 2591 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 2592 | |
c46fbefa AK |
2593 | /* assume default assoc id */ |
2594 | priv->assoc_id = 1; | |
b481de9c | 2595 | |
fe6b23dd | 2596 | iwl_add_local_station(priv, priv->bssid, true); |
5b9f8cd3 | 2597 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2598 | |
2599 | break; | |
2600 | ||
2601 | default: | |
15b1687c | 2602 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 2603 | __func__, priv->iw_mode); |
b481de9c ZY |
2604 | break; |
2605 | } | |
2606 | ||
04816448 GE |
2607 | /* the chain noise calibration will enabled PM upon completion |
2608 | * If chain noise has already been run, then we need to enable | |
2609 | * power management here */ | |
2610 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
e312c24c | 2611 | iwl_power_update_mode(priv, false); |
c90a74ba EG |
2612 | |
2613 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2614 | iwl_chain_noise_reset(priv); | |
2615 | priv->start_calib = 1; | |
2616 | ||
508e32e1 RC |
2617 | } |
2618 | ||
b481de9c ZY |
2619 | /***************************************************************************** |
2620 | * | |
2621 | * mac80211 entry point functions | |
2622 | * | |
2623 | *****************************************************************************/ | |
2624 | ||
154b25ce | 2625 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2626 | |
f0b6e2e8 RC |
2627 | /* |
2628 | * Not a mac80211 entry point function, but it fits in with all the | |
2629 | * other mac80211 functions grouped here. | |
2630 | */ | |
158bea07 | 2631 | static int iwl_mac_setup_register(struct iwl_priv *priv) |
f0b6e2e8 RC |
2632 | { |
2633 | int ret; | |
2634 | struct ieee80211_hw *hw = priv->hw; | |
2635 | hw->rate_control_algorithm = "iwl-agn-rs"; | |
2636 | ||
2637 | /* Tell mac80211 our characteristics */ | |
2638 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
2639 | IEEE80211_HW_NOISE_DBM | | |
2640 | IEEE80211_HW_AMPDU_AGGREGATION | | |
2641 | IEEE80211_HW_SPECTRUM_MGMT; | |
2642 | ||
2643 | if (!priv->cfg->broken_powersave) | |
2644 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
2645 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2646 | ||
ba37a3d0 JB |
2647 | if (priv->cfg->sku & IWL_SKU_N) |
2648 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
2649 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
2650 | ||
8d9698b3 | 2651 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
f0b6e2e8 RC |
2652 | hw->wiphy->interface_modes = |
2653 | BIT(NL80211_IFTYPE_STATION) | | |
2654 | BIT(NL80211_IFTYPE_ADHOC); | |
2655 | ||
5be83de5 JB |
2656 | hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY | |
2657 | WIPHY_FLAG_DISABLE_BEACON_HINTS; | |
f0b6e2e8 RC |
2658 | |
2659 | /* | |
2660 | * For now, disable PS by default because it affects | |
2661 | * RX performance significantly. | |
2662 | */ | |
5be83de5 | 2663 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 2664 | |
21b2d8bd | 2665 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX + 1; |
f0b6e2e8 RC |
2666 | /* we create the 802.11 header and a zero-length SSID element */ |
2667 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
2668 | ||
2669 | /* Default value; 4 EDCA QOS priorities */ | |
2670 | hw->queues = 4; | |
2671 | ||
2672 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
2673 | ||
2674 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
2675 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
2676 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2677 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
2678 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
2679 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
2680 | ||
2681 | ret = ieee80211_register_hw(priv->hw); | |
2682 | if (ret) { | |
2683 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
2684 | return ret; | |
2685 | } | |
2686 | priv->mac80211_registered = 1; | |
2687 | ||
2688 | return 0; | |
2689 | } | |
2690 | ||
2691 | ||
5b9f8cd3 | 2692 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2693 | { |
c79dd5b5 | 2694 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2695 | int ret; |
b481de9c | 2696 | |
e1623446 | 2697 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2698 | |
2699 | /* we should be verifying the device is ready to be opened */ | |
2700 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2701 | ret = __iwl_up(priv); |
b481de9c | 2702 | mutex_unlock(&priv->mutex); |
5a66926a | 2703 | |
e655b9f0 | 2704 | if (ret) |
6cd0b1cb | 2705 | return ret; |
e655b9f0 | 2706 | |
c1842d61 TW |
2707 | if (iwl_is_rfkill(priv)) |
2708 | goto out; | |
2709 | ||
e1623446 | 2710 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2711 | |
fe9b6b72 | 2712 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2713 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2714 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2715 | test_bit(STATUS_READY, &priv->status), | |
2716 | UCODE_READY_TIMEOUT); | |
2717 | if (!ret) { | |
2718 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2719 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2720 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2721 | return -ETIMEDOUT; |
5a66926a | 2722 | } |
fe9b6b72 | 2723 | } |
0a078ffa | 2724 | |
e932a609 JB |
2725 | iwl_led_start(priv); |
2726 | ||
c1842d61 | 2727 | out: |
0a078ffa | 2728 | priv->is_open = 1; |
e1623446 | 2729 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2730 | return 0; |
2731 | } | |
2732 | ||
5b9f8cd3 | 2733 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2734 | { |
c79dd5b5 | 2735 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2736 | |
e1623446 | 2737 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2738 | |
19cc1087 | 2739 | if (!priv->is_open) |
e655b9f0 | 2740 | return; |
e655b9f0 | 2741 | |
b481de9c | 2742 | priv->is_open = 0; |
5a66926a | 2743 | |
5bddf549 | 2744 | if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) { |
e655b9f0 ZY |
2745 | /* stop mac, cancel any scan request and clear |
2746 | * RXON_FILTER_ASSOC_MSK BIT | |
2747 | */ | |
5a66926a | 2748 | mutex_lock(&priv->mutex); |
2a421b91 | 2749 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2750 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2751 | } |
2752 | ||
5b9f8cd3 | 2753 | iwl_down(priv); |
5a66926a ZY |
2754 | |
2755 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2756 | |
2757 | /* enable interrupts again in order to receive rfkill changes */ | |
2758 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2759 | iwl_enable_interrupts(priv); | |
948c171c | 2760 | |
e1623446 | 2761 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2762 | } |
2763 | ||
5b9f8cd3 | 2764 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2765 | { |
c79dd5b5 | 2766 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2767 | |
e1623446 | 2768 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2769 | |
e1623446 | 2770 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2771 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2772 | |
74bcdb33 | 2773 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
2774 | dev_kfree_skb_any(skb); |
2775 | ||
e1623446 | 2776 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 2777 | return NETDEV_TX_OK; |
b481de9c ZY |
2778 | } |
2779 | ||
60690a6a | 2780 | void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2781 | { |
857485c0 | 2782 | int ret = 0; |
b481de9c | 2783 | |
d986bcd1 | 2784 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2785 | return; |
2786 | ||
2787 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2788 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2789 | |
2790 | /* RXON - unassoc (to set timing command) */ | |
2791 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2792 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2793 | |
2794 | /* RXON Timing */ | |
3195c1f3 | 2795 | iwl_setup_rxon_timing(priv); |
857485c0 | 2796 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2797 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2798 | if (ret) |
39aadf8c | 2799 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2800 | "Attempting to continue.\n"); |
2801 | ||
f513dfff DH |
2802 | /* AP has all antennas */ |
2803 | priv->chain_noise_data.active_chains = | |
2804 | priv->hw_params.valid_rx_ant; | |
2805 | iwl_set_rxon_ht(priv, &priv->current_ht_config); | |
45823531 AK |
2806 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2807 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2808 | |
2809 | /* FIXME: what should be the assoc_id for AP? */ | |
2810 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2811 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2812 | priv->staging_rxon.flags |= | |
2813 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2814 | else | |
2815 | priv->staging_rxon.flags &= | |
2816 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2817 | ||
2818 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2819 | if (priv->assoc_capability & | |
2820 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2821 | priv->staging_rxon.flags |= | |
2822 | RXON_FLG_SHORT_SLOT_MSK; | |
2823 | else | |
2824 | priv->staging_rxon.flags &= | |
2825 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2826 | ||
05c914fe | 2827 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2828 | priv->staging_rxon.flags &= |
2829 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2830 | } | |
2831 | /* restore RXON assoc */ | |
2832 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2833 | iwlcore_commit_rxon(priv); |
9a9ca65f | 2834 | iwl_add_bcast_station(priv); |
e1493deb | 2835 | } |
5b9f8cd3 | 2836 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2837 | |
2838 | /* FIXME - we need to add code here to detect a totally new | |
2839 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2840 | * clear sta table, add BCAST sta... */ | |
2841 | } | |
2842 | ||
5b9f8cd3 | 2843 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
b3fbdcf4 JB |
2844 | struct ieee80211_vif *vif, |
2845 | struct ieee80211_key_conf *keyconf, | |
2846 | struct ieee80211_sta *sta, | |
2847 | u32 iv32, u16 *phase1key) | |
ab885f8c | 2848 | { |
ab885f8c | 2849 | |
9f58671e | 2850 | struct iwl_priv *priv = hw->priv; |
e1623446 | 2851 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2852 | |
b3fbdcf4 JB |
2853 | iwl_update_tkip_key(priv, keyconf, |
2854 | sta ? sta->addr : iwl_bcast_addr, | |
2855 | iv32, phase1key); | |
ab885f8c | 2856 | |
e1623446 | 2857 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2858 | } |
2859 | ||
5b9f8cd3 | 2860 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2861 | struct ieee80211_vif *vif, |
2862 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2863 | struct ieee80211_key_conf *key) |
2864 | { | |
c79dd5b5 | 2865 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2866 | const u8 *addr; |
2867 | int ret; | |
2868 | u8 sta_id; | |
2869 | bool is_default_wep_key = false; | |
b481de9c | 2870 | |
e1623446 | 2871 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2872 | |
90e8e424 | 2873 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 2874 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2875 | return -EOPNOTSUPP; |
2876 | } | |
42986796 | 2877 | addr = sta ? sta->addr : iwl_bcast_addr; |
c587de0b | 2878 | sta_id = iwl_find_station(priv, addr); |
6974e363 | 2879 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 2880 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
e174961c | 2881 | addr); |
6974e363 | 2882 | return -EINVAL; |
b481de9c | 2883 | |
deb09c43 | 2884 | } |
b481de9c | 2885 | |
6974e363 | 2886 | mutex_lock(&priv->mutex); |
2a421b91 | 2887 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2888 | |
2889 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2890 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2891 | * in 1X mode. | |
2892 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2893 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2894 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2895 | if (cmd == SET_KEY) |
2896 | is_default_wep_key = !priv->key_mapping_key; | |
2897 | else | |
ccc038ab EG |
2898 | is_default_wep_key = |
2899 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2900 | } |
052c4b9f | 2901 | |
b481de9c | 2902 | switch (cmd) { |
deb09c43 | 2903 | case SET_KEY: |
6974e363 EG |
2904 | if (is_default_wep_key) |
2905 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2906 | else |
7480513f | 2907 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 2908 | |
e1623446 | 2909 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2910 | break; |
2911 | case DISABLE_KEY: | |
6974e363 EG |
2912 | if (is_default_wep_key) |
2913 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2914 | else |
3ec47732 | 2915 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 2916 | |
e1623446 | 2917 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2918 | break; |
2919 | default: | |
deb09c43 | 2920 | ret = -EINVAL; |
b481de9c ZY |
2921 | } |
2922 | ||
72e15d71 | 2923 | mutex_unlock(&priv->mutex); |
e1623446 | 2924 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2925 | |
deb09c43 | 2926 | return ret; |
b481de9c ZY |
2927 | } |
2928 | ||
5b9f8cd3 | 2929 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2930 | struct ieee80211_vif *vif, |
d783b061 | 2931 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2932 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2933 | { |
2934 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 2935 | int ret; |
d783b061 | 2936 | |
e1623446 | 2937 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2938 | sta->addr, tid); |
d783b061 TW |
2939 | |
2940 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2941 | return -EACCES; | |
2942 | ||
2943 | switch (action) { | |
2944 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2945 | IWL_DEBUG_HT(priv, "start Rx\n"); |
9f58671e | 2946 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 | 2947 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2948 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
5c2207c6 WYG |
2949 | ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
2950 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2951 | return 0; | |
2952 | else | |
2953 | return ret; | |
d783b061 | 2954 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2955 | IWL_DEBUG_HT(priv, "start Tx\n"); |
74bcdb33 | 2956 | ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn); |
d5a0ffa3 WYG |
2957 | if (ret == 0) { |
2958 | priv->_agn.agg_tids_count++; | |
2959 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
2960 | priv->_agn.agg_tids_count); | |
2961 | } | |
2962 | return ret; | |
d783b061 | 2963 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2964 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
74bcdb33 | 2965 | ret = iwlagn_tx_agg_stop(priv, sta->addr, tid); |
d5a0ffa3 WYG |
2966 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
2967 | priv->_agn.agg_tids_count--; | |
2968 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
2969 | priv->_agn.agg_tids_count); | |
2970 | } | |
5c2207c6 WYG |
2971 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
2972 | return 0; | |
2973 | else | |
2974 | return ret; | |
f0527971 WYG |
2975 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
2976 | /* do nothing */ | |
2977 | return -EOPNOTSUPP; | |
d783b061 | 2978 | default: |
e1623446 | 2979 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
2980 | return -EINVAL; |
2981 | break; | |
2982 | } | |
2983 | return 0; | |
2984 | } | |
9f58671e | 2985 | |
5b9f8cd3 | 2986 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2987 | struct ieee80211_low_level_stats *stats) |
2988 | { | |
bf403db8 EK |
2989 | struct iwl_priv *priv = hw->priv; |
2990 | ||
2991 | priv = hw->priv; | |
e1623446 TW |
2992 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
2993 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
b481de9c ZY |
2994 | |
2995 | return 0; | |
2996 | } | |
2997 | ||
6ab10ff8 JB |
2998 | static void iwl_mac_sta_notify(struct ieee80211_hw *hw, |
2999 | struct ieee80211_vif *vif, | |
3000 | enum sta_notify_cmd cmd, | |
3001 | struct ieee80211_sta *sta) | |
3002 | { | |
3003 | struct iwl_priv *priv = hw->priv; | |
3004 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
3005 | int sta_id; | |
3006 | ||
6ab10ff8 | 3007 | switch (cmd) { |
6ab10ff8 JB |
3008 | case STA_NOTIFY_SLEEP: |
3009 | WARN_ON(!sta_priv->client); | |
3010 | sta_priv->asleep = true; | |
3011 | if (atomic_read(&sta_priv->pending_frames) > 0) | |
3012 | ieee80211_sta_block_awake(hw, sta, true); | |
3013 | break; | |
3014 | case STA_NOTIFY_AWAKE: | |
3015 | WARN_ON(!sta_priv->client); | |
49dcc819 DH |
3016 | if (!sta_priv->asleep) |
3017 | break; | |
6ab10ff8 JB |
3018 | sta_priv->asleep = false; |
3019 | sta_id = iwl_find_station(priv, sta->addr); | |
3020 | if (sta_id != IWL_INVALID_STATION) | |
3021 | iwl_sta_modify_ps_wake(priv, sta_id); | |
3022 | break; | |
3023 | default: | |
3024 | break; | |
3025 | } | |
3026 | } | |
3027 | ||
fe6b23dd RC |
3028 | /** |
3029 | * iwl_restore_wepkeys - Restore WEP keys to device | |
3030 | */ | |
3031 | static void iwl_restore_wepkeys(struct iwl_priv *priv) | |
3032 | { | |
3033 | mutex_lock(&priv->mutex); | |
3034 | if (priv->iw_mode == NL80211_IFTYPE_STATION && | |
3035 | priv->default_wep_key && | |
3036 | iwl_send_static_wepkey_cmd(priv, 0)) | |
3037 | IWL_ERR(priv, "Could not send WEP static key\n"); | |
3038 | mutex_unlock(&priv->mutex); | |
3039 | } | |
3040 | ||
3041 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, | |
3042 | struct ieee80211_vif *vif, | |
3043 | struct ieee80211_sta *sta) | |
3044 | { | |
3045 | struct iwl_priv *priv = hw->priv; | |
3046 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
3047 | bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION; | |
3048 | int ret; | |
3049 | u8 sta_id; | |
3050 | ||
3051 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3052 | sta->addr); | |
3053 | ||
3054 | atomic_set(&sta_priv->pending_frames, 0); | |
3055 | if (vif->type == NL80211_IFTYPE_AP) | |
3056 | sta_priv->client = true; | |
3057 | ||
3058 | ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap, | |
3059 | &sta_id); | |
3060 | if (ret) { | |
3061 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3062 | sta->addr, ret); | |
3063 | /* Should we return success if return code is EEXIST ? */ | |
3064 | return ret; | |
3065 | } | |
3066 | ||
3067 | iwl_restore_wepkeys(priv); | |
3068 | ||
3069 | /* Initialize rate scaling */ | |
3070 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM \n", | |
3071 | sta->addr); | |
3072 | iwl_rs_rate_init(priv, sta, sta_id); | |
3073 | ||
3074 | return ret; | |
3075 | } | |
3076 | ||
b481de9c ZY |
3077 | /***************************************************************************** |
3078 | * | |
3079 | * sysfs attributes | |
3080 | * | |
3081 | *****************************************************************************/ | |
3082 | ||
0a6857e7 | 3083 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3084 | |
3085 | /* | |
3086 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 3087 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
3088 | * used for controlling the debug level. |
3089 | * | |
3090 | * See the level definitions in iwl for details. | |
a562a9dd | 3091 | * |
3d816c77 RC |
3092 | * The debug_level being managed using sysfs below is a per device debug |
3093 | * level that is used instead of the global debug level if it (the per | |
3094 | * device debug level) is set. | |
b481de9c | 3095 | */ |
8cf769c6 EK |
3096 | static ssize_t show_debug_level(struct device *d, |
3097 | struct device_attribute *attr, char *buf) | |
b481de9c | 3098 | { |
3d816c77 RC |
3099 | struct iwl_priv *priv = dev_get_drvdata(d); |
3100 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 3101 | } |
8cf769c6 EK |
3102 | static ssize_t store_debug_level(struct device *d, |
3103 | struct device_attribute *attr, | |
b481de9c ZY |
3104 | const char *buf, size_t count) |
3105 | { | |
928841b1 | 3106 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3107 | unsigned long val; |
3108 | int ret; | |
b481de9c | 3109 | |
9257746f TW |
3110 | ret = strict_strtoul(buf, 0, &val); |
3111 | if (ret) | |
978785a3 | 3112 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 3113 | else { |
3d816c77 | 3114 | priv->debug_level = val; |
20594eb0 WYG |
3115 | if (iwl_alloc_traffic_mem(priv)) |
3116 | IWL_ERR(priv, | |
3117 | "Not enough memory to generate traffic log\n"); | |
3118 | } | |
b481de9c ZY |
3119 | return strnlen(buf, count); |
3120 | } | |
3121 | ||
8cf769c6 EK |
3122 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3123 | show_debug_level, store_debug_level); | |
3124 | ||
b481de9c | 3125 | |
0a6857e7 | 3126 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3127 | |
b481de9c ZY |
3128 | |
3129 | static ssize_t show_temperature(struct device *d, | |
3130 | struct device_attribute *attr, char *buf) | |
3131 | { | |
928841b1 | 3132 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3133 | |
fee1247a | 3134 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3135 | return -EAGAIN; |
3136 | ||
91dbc5bd | 3137 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
3138 | } |
3139 | ||
3140 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3141 | ||
b481de9c ZY |
3142 | static ssize_t show_tx_power(struct device *d, |
3143 | struct device_attribute *attr, char *buf) | |
3144 | { | |
928841b1 | 3145 | struct iwl_priv *priv = dev_get_drvdata(d); |
91f39e8e JS |
3146 | |
3147 | if (!iwl_is_ready_rf(priv)) | |
3148 | return sprintf(buf, "off\n"); | |
3149 | else | |
3150 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
3151 | } |
3152 | ||
3153 | static ssize_t store_tx_power(struct device *d, | |
3154 | struct device_attribute *attr, | |
3155 | const char *buf, size_t count) | |
3156 | { | |
928841b1 | 3157 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3158 | unsigned long val; |
3159 | int ret; | |
b481de9c | 3160 | |
9257746f TW |
3161 | ret = strict_strtoul(buf, 10, &val); |
3162 | if (ret) | |
978785a3 | 3163 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
5eadd94b WYG |
3164 | else { |
3165 | ret = iwl_set_tx_power(priv, val, false); | |
3166 | if (ret) | |
3167 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
3168 | ret); | |
3169 | else | |
3170 | ret = count; | |
3171 | } | |
3172 | return ret; | |
b481de9c ZY |
3173 | } |
3174 | ||
3175 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3176 | ||
b481de9c ZY |
3177 | static ssize_t show_statistics(struct device *d, |
3178 | struct device_attribute *attr, char *buf) | |
3179 | { | |
c79dd5b5 | 3180 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 3181 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 3182 | u32 len = 0, ofs = 0; |
3ac7f146 | 3183 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
3184 | int rc = 0; |
3185 | ||
fee1247a | 3186 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3187 | return -EAGAIN; |
3188 | ||
3189 | mutex_lock(&priv->mutex); | |
ef8d5529 | 3190 | rc = iwl_send_statistics_request(priv, CMD_SYNC, false); |
b481de9c ZY |
3191 | mutex_unlock(&priv->mutex); |
3192 | ||
3193 | if (rc) { | |
3194 | len = sprintf(buf, | |
3195 | "Error sending statistics request: 0x%08X\n", rc); | |
3196 | return len; | |
3197 | } | |
3198 | ||
3199 | while (size && (PAGE_SIZE - len)) { | |
3200 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3201 | PAGE_SIZE - len, 1); | |
3202 | len = strlen(buf); | |
3203 | if (PAGE_SIZE - len) | |
3204 | buf[len++] = '\n'; | |
3205 | ||
3206 | ofs += 16; | |
3207 | size -= min(size, 16U); | |
3208 | } | |
3209 | ||
3210 | return len; | |
3211 | } | |
3212 | ||
3213 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
3214 | ||
01abfbb2 WYG |
3215 | static ssize_t show_rts_ht_protection(struct device *d, |
3216 | struct device_attribute *attr, char *buf) | |
3217 | { | |
3218 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3219 | ||
3220 | return sprintf(buf, "%s\n", | |
3221 | priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self"); | |
3222 | } | |
3223 | ||
3224 | static ssize_t store_rts_ht_protection(struct device *d, | |
3225 | struct device_attribute *attr, | |
3226 | const char *buf, size_t count) | |
3227 | { | |
3228 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3229 | unsigned long val; | |
3230 | int ret; | |
3231 | ||
3232 | ret = strict_strtoul(buf, 10, &val); | |
3233 | if (ret) | |
3234 | IWL_INFO(priv, "Input is not in decimal form.\n"); | |
3235 | else { | |
3236 | if (!iwl_is_associated(priv)) | |
3237 | priv->cfg->use_rts_for_ht = val ? true : false; | |
3238 | else | |
3239 | IWL_ERR(priv, "Sta associated with AP - " | |
3240 | "Change protection mechanism is not allowed\n"); | |
3241 | ret = count; | |
3242 | } | |
3243 | return ret; | |
3244 | } | |
3245 | ||
3246 | static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO, | |
3247 | show_rts_ht_protection, store_rts_ht_protection); | |
3248 | ||
b481de9c | 3249 | |
b481de9c ZY |
3250 | /***************************************************************************** |
3251 | * | |
3252 | * driver setup and teardown | |
3253 | * | |
3254 | *****************************************************************************/ | |
3255 | ||
4e39317d | 3256 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3257 | { |
d21050c7 | 3258 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3259 | |
3260 | init_waitqueue_head(&priv->wait_command_queue); | |
3261 | ||
5b9f8cd3 EG |
3262 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3263 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3264 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3265 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
3266 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3267 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 3268 | |
2a421b91 | 3269 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3270 | |
4e39317d EG |
3271 | if (priv->cfg->ops->lib->setup_deferred_work) |
3272 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3273 | ||
3274 | init_timer(&priv->statistics_periodic); | |
3275 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3276 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3277 | |
a9e1cb6a WYG |
3278 | init_timer(&priv->ucode_trace); |
3279 | priv->ucode_trace.data = (unsigned long)priv; | |
3280 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3281 | ||
b74e31a9 WYG |
3282 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
3283 | init_timer(&priv->monitor_recover); | |
3284 | priv->monitor_recover.data = (unsigned long)priv; | |
3285 | priv->monitor_recover.function = | |
3286 | priv->cfg->ops->lib->recover_from_tx_stall; | |
3287 | } | |
3288 | ||
ef850d7c MA |
3289 | if (!priv->cfg->use_isr_legacy) |
3290 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3291 | iwl_irq_tasklet, (unsigned long)priv); | |
3292 | else | |
3293 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3294 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
3295 | } |
3296 | ||
4e39317d | 3297 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3298 | { |
4e39317d EG |
3299 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3300 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3301 | |
3ae6a054 | 3302 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
3303 | cancel_delayed_work(&priv->scan_check); |
3304 | cancel_delayed_work(&priv->alive_start); | |
b481de9c | 3305 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 3306 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3307 | del_timer_sync(&priv->ucode_trace); |
b74e31a9 WYG |
3308 | if (priv->cfg->ops->lib->recover_from_tx_stall) |
3309 | del_timer_sync(&priv->monitor_recover); | |
b481de9c ZY |
3310 | } |
3311 | ||
89f186a8 RC |
3312 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3313 | struct ieee80211_rate *rates) | |
3314 | { | |
3315 | int i; | |
3316 | ||
3317 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3318 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3319 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3320 | rates[i].hw_value_short = i; | |
3321 | rates[i].flags = 0; | |
3322 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3323 | /* | |
3324 | * If CCK != 1M then set short preamble rate flag. | |
3325 | */ | |
3326 | rates[i].flags |= | |
3327 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3328 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3329 | } | |
3330 | } | |
3331 | } | |
3332 | ||
3333 | static int iwl_init_drv(struct iwl_priv *priv) | |
3334 | { | |
3335 | int ret; | |
3336 | ||
3337 | priv->ibss_beacon = NULL; | |
3338 | ||
89f186a8 RC |
3339 | spin_lock_init(&priv->sta_lock); |
3340 | spin_lock_init(&priv->hcmd_lock); | |
3341 | ||
3342 | INIT_LIST_HEAD(&priv->free_frames); | |
3343 | ||
3344 | mutex_init(&priv->mutex); | |
d2dfe6df | 3345 | mutex_init(&priv->sync_cmd_mutex); |
89f186a8 | 3346 | |
89f186a8 RC |
3347 | priv->ieee_channels = NULL; |
3348 | priv->ieee_rates = NULL; | |
3349 | priv->band = IEEE80211_BAND_2GHZ; | |
3350 | ||
3351 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3352 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3353 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 3354 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 3355 | |
8a472da4 WYG |
3356 | /* initialize force reset */ |
3357 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3358 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3359 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3360 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 RC |
3361 | |
3362 | /* Choose which receivers/antennas to use */ | |
3363 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
3364 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
3365 | ||
3366 | iwl_init_scan_params(priv); | |
3367 | ||
89f186a8 RC |
3368 | /* Set the tx_power_user_lmt to the lowest power level |
3369 | * this value will get overwritten by channel max power avg | |
3370 | * from eeprom */ | |
3371 | priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN; | |
3372 | ||
3373 | ret = iwl_init_channel_map(priv); | |
3374 | if (ret) { | |
3375 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3376 | goto err; | |
3377 | } | |
3378 | ||
3379 | ret = iwlcore_init_geos(priv); | |
3380 | if (ret) { | |
3381 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3382 | goto err_free_channel_map; | |
3383 | } | |
3384 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
3385 | ||
3386 | return 0; | |
3387 | ||
3388 | err_free_channel_map: | |
3389 | iwl_free_channel_map(priv); | |
3390 | err: | |
3391 | return ret; | |
3392 | } | |
3393 | ||
3394 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
3395 | { | |
3396 | iwl_calib_free_results(priv); | |
3397 | iwlcore_free_geos(priv); | |
3398 | iwl_free_channel_map(priv); | |
3399 | kfree(priv->scan); | |
3400 | } | |
3401 | ||
5b9f8cd3 | 3402 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c | 3403 | &dev_attr_statistics.attr, |
b481de9c | 3404 | &dev_attr_temperature.attr, |
b481de9c | 3405 | &dev_attr_tx_power.attr, |
01abfbb2 | 3406 | &dev_attr_rts_ht_protection.attr, |
8cf769c6 EK |
3407 | #ifdef CONFIG_IWLWIFI_DEBUG |
3408 | &dev_attr_debug_level.attr, | |
3409 | #endif | |
b481de9c ZY |
3410 | NULL |
3411 | }; | |
3412 | ||
5b9f8cd3 | 3413 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 3414 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 3415 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
3416 | }; |
3417 | ||
5b9f8cd3 EG |
3418 | static struct ieee80211_ops iwl_hw_ops = { |
3419 | .tx = iwl_mac_tx, | |
3420 | .start = iwl_mac_start, | |
3421 | .stop = iwl_mac_stop, | |
3422 | .add_interface = iwl_mac_add_interface, | |
3423 | .remove_interface = iwl_mac_remove_interface, | |
3424 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
3425 | .configure_filter = iwl_configure_filter, |
3426 | .set_key = iwl_mac_set_key, | |
3427 | .update_tkip_key = iwl_mac_update_tkip_key, | |
3428 | .get_stats = iwl_mac_get_stats, | |
5b9f8cd3 EG |
3429 | .conf_tx = iwl_mac_conf_tx, |
3430 | .reset_tsf = iwl_mac_reset_tsf, | |
3431 | .bss_info_changed = iwl_bss_info_changed, | |
3432 | .ampdu_action = iwl_mac_ampdu_action, | |
6ab10ff8 JB |
3433 | .hw_scan = iwl_mac_hw_scan, |
3434 | .sta_notify = iwl_mac_sta_notify, | |
fe6b23dd RC |
3435 | .sta_add = iwlagn_mac_sta_add, |
3436 | .sta_remove = iwl_mac_sta_remove, | |
b481de9c ZY |
3437 | }; |
3438 | ||
5b9f8cd3 | 3439 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3440 | { |
3441 | int err = 0; | |
c79dd5b5 | 3442 | struct iwl_priv *priv; |
b481de9c | 3443 | struct ieee80211_hw *hw; |
82b9a121 | 3444 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 3445 | unsigned long flags; |
6cd0b1cb | 3446 | u16 pci_cmd; |
b481de9c | 3447 | |
316c30d9 AK |
3448 | /************************ |
3449 | * 1. Allocating HW data | |
3450 | ************************/ | |
3451 | ||
6440adb5 CB |
3452 | /* Disabling hardware scan means that mac80211 will perform scans |
3453 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 3454 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 3455 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
3456 | dev_printk(KERN_DEBUG, &(pdev->dev), |
3457 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 3458 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
3459 | } |
3460 | ||
5b9f8cd3 | 3461 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 3462 | if (!hw) { |
b481de9c ZY |
3463 | err = -ENOMEM; |
3464 | goto out; | |
3465 | } | |
1d0a082d AK |
3466 | priv = hw->priv; |
3467 | /* At this point both hw and priv are allocated. */ | |
3468 | ||
b481de9c ZY |
3469 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3470 | ||
e1623446 | 3471 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 3472 | priv->cfg = cfg; |
b481de9c | 3473 | priv->pci_dev = pdev; |
40cefda9 | 3474 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 3475 | |
0a6857e7 | 3476 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3477 | atomic_set(&priv->restrict_refcnt, 0); |
3478 | #endif | |
20594eb0 WYG |
3479 | if (iwl_alloc_traffic_mem(priv)) |
3480 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3481 | |
316c30d9 AK |
3482 | /************************** |
3483 | * 2. Initializing PCI bus | |
3484 | **************************/ | |
3485 | if (pci_enable_device(pdev)) { | |
3486 | err = -ENODEV; | |
3487 | goto out_ieee80211_free_hw; | |
3488 | } | |
3489 | ||
3490 | pci_set_master(pdev); | |
3491 | ||
093d874c | 3492 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 3493 | if (!err) |
093d874c | 3494 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 3495 | if (err) { |
093d874c | 3496 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3497 | if (!err) |
093d874c | 3498 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3499 | /* both attempts failed: */ |
316c30d9 | 3500 | if (err) { |
978785a3 | 3501 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 3502 | goto out_pci_disable_device; |
cc2a8ea8 | 3503 | } |
316c30d9 AK |
3504 | } |
3505 | ||
3506 | err = pci_request_regions(pdev, DRV_NAME); | |
3507 | if (err) | |
3508 | goto out_pci_disable_device; | |
3509 | ||
3510 | pci_set_drvdata(pdev, priv); | |
3511 | ||
316c30d9 AK |
3512 | |
3513 | /*********************** | |
3514 | * 3. Read REV register | |
3515 | ***********************/ | |
3516 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3517 | if (!priv->hw_base) { | |
3518 | err = -ENODEV; | |
3519 | goto out_pci_release_regions; | |
3520 | } | |
3521 | ||
e1623446 | 3522 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3523 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3524 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3525 | |
731a29b7 | 3526 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
3527 | * we should init now |
3528 | */ | |
3529 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 3530 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
3531 | |
3532 | /* | |
3533 | * stop and reset the on-board processor just in case it is in a | |
3534 | * strange state ... like being left stranded by a primary kernel | |
3535 | * and this is now the kdump kernel trying to start up | |
3536 | */ | |
3537 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
3538 | ||
b661c819 | 3539 | iwl_hw_detect(priv); |
c11362c0 | 3540 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
b661c819 | 3541 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 3542 | |
e7b63581 TW |
3543 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3544 | * PCI Tx retries from interfering with C3 CPU state */ | |
3545 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3546 | ||
086ed117 MA |
3547 | iwl_prepare_card_hw(priv); |
3548 | if (!priv->hw_ready) { | |
3549 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
3550 | goto out_iounmap; | |
3551 | } | |
3552 | ||
91238714 TW |
3553 | /***************** |
3554 | * 4. Read EEPROM | |
3555 | *****************/ | |
316c30d9 AK |
3556 | /* Read the EEPROM */ |
3557 | err = iwl_eeprom_init(priv); | |
3558 | if (err) { | |
15b1687c | 3559 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3560 | goto out_iounmap; |
3561 | } | |
8614f360 TW |
3562 | err = iwl_eeprom_check_version(priv); |
3563 | if (err) | |
c8f16138 | 3564 | goto out_free_eeprom; |
8614f360 | 3565 | |
02883017 | 3566 | /* extract MAC Address */ |
316c30d9 | 3567 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 3568 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
3569 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
3570 | ||
3571 | /************************ | |
3572 | * 5. Setup HW constants | |
3573 | ************************/ | |
da154e30 | 3574 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3575 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3576 | goto out_free_eeprom; |
316c30d9 AK |
3577 | } |
3578 | ||
3579 | /******************* | |
6ba87956 | 3580 | * 6. Setup priv |
316c30d9 | 3581 | *******************/ |
b481de9c | 3582 | |
6ba87956 | 3583 | err = iwl_init_drv(priv); |
bf85ea4f | 3584 | if (err) |
399f4900 | 3585 | goto out_free_eeprom; |
bf85ea4f | 3586 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3587 | |
316c30d9 | 3588 | /******************** |
09f9bf79 | 3589 | * 7. Setup services |
316c30d9 | 3590 | ********************/ |
0359facc | 3591 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3592 | iwl_disable_interrupts(priv); |
0359facc | 3593 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3594 | |
6cd0b1cb HS |
3595 | pci_enable_msi(priv->pci_dev); |
3596 | ||
ef850d7c MA |
3597 | iwl_alloc_isr_ict(priv); |
3598 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
3599 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
3600 | if (err) { |
3601 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3602 | goto out_disable_msi; | |
3603 | } | |
5b9f8cd3 | 3604 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 3605 | if (err) { |
15b1687c | 3606 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 3607 | goto out_free_irq; |
316c30d9 AK |
3608 | } |
3609 | ||
4e39317d | 3610 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3611 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3612 | |
158bea07 JB |
3613 | /********************************************* |
3614 | * 8. Enable interrupts and read RFKILL state | |
3615 | *********************************************/ | |
6ba87956 | 3616 | |
6cd0b1cb HS |
3617 | /* enable interrupts if needed: hw bug w/a */ |
3618 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
3619 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3620 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3621 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3622 | } | |
3623 | ||
3624 | iwl_enable_interrupts(priv); | |
3625 | ||
6cd0b1cb HS |
3626 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3627 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3628 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3629 | else | |
3630 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3631 | |
a60e77e5 JB |
3632 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3633 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3634 | |
58d0f361 | 3635 | iwl_power_initialize(priv); |
39b73fb1 | 3636 | iwl_tt_initialize(priv); |
158bea07 | 3637 | |
b08dfd04 | 3638 | err = iwl_request_firmware(priv, true); |
158bea07 JB |
3639 | if (err) |
3640 | goto out_remove_sysfs; | |
3641 | ||
b481de9c ZY |
3642 | return 0; |
3643 | ||
316c30d9 | 3644 | out_remove_sysfs: |
c8f16138 RC |
3645 | destroy_workqueue(priv->workqueue); |
3646 | priv->workqueue = NULL; | |
5b9f8cd3 | 3647 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
3648 | out_free_irq: |
3649 | free_irq(priv->pci_dev->irq, priv); | |
ef850d7c | 3650 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
3651 | out_disable_msi: |
3652 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 3653 | iwl_uninit_drv(priv); |
073d3f5f TW |
3654 | out_free_eeprom: |
3655 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3656 | out_iounmap: |
3657 | pci_iounmap(pdev, priv->hw_base); | |
3658 | out_pci_release_regions: | |
316c30d9 | 3659 | pci_set_drvdata(pdev, NULL); |
623d563e | 3660 | pci_release_regions(pdev); |
b481de9c ZY |
3661 | out_pci_disable_device: |
3662 | pci_disable_device(pdev); | |
b481de9c | 3663 | out_ieee80211_free_hw: |
20594eb0 | 3664 | iwl_free_traffic_mem(priv); |
d7c76f4c | 3665 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
3666 | out: |
3667 | return err; | |
3668 | } | |
3669 | ||
5b9f8cd3 | 3670 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3671 | { |
c79dd5b5 | 3672 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3673 | unsigned long flags; |
b481de9c ZY |
3674 | |
3675 | if (!priv) | |
3676 | return; | |
3677 | ||
e1623446 | 3678 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3679 | |
67249625 | 3680 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3681 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3682 | |
5b9f8cd3 EG |
3683 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3684 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3685 | * we need to set STATUS_EXIT_PENDING bit. |
3686 | */ | |
3687 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
3688 | if (priv->mac80211_registered) { |
3689 | ieee80211_unregister_hw(priv->hw); | |
3690 | priv->mac80211_registered = 0; | |
0b124c31 | 3691 | } else { |
5b9f8cd3 | 3692 | iwl_down(priv); |
c4f55232 RR |
3693 | } |
3694 | ||
c166b25a BC |
3695 | /* |
3696 | * Make sure device is reset to low power before unloading driver. | |
3697 | * This may be redundant with iwl_down(), but there are paths to | |
3698 | * run iwl_down() without calling apm_ops.stop(), and there are | |
3699 | * paths to avoid running iwl_down() at all before leaving driver. | |
3700 | * This (inexpensive) call *makes sure* device is reset. | |
3701 | */ | |
3702 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
3703 | ||
39b73fb1 WYG |
3704 | iwl_tt_exit(priv); |
3705 | ||
0359facc MA |
3706 | /* make sure we flush any pending irq or |
3707 | * tasklet for the driver | |
3708 | */ | |
3709 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3710 | iwl_disable_interrupts(priv); |
0359facc MA |
3711 | spin_unlock_irqrestore(&priv->lock, flags); |
3712 | ||
3713 | iwl_synchronize_irq(priv); | |
3714 | ||
5b9f8cd3 | 3715 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3716 | |
3717 | if (priv->rxq.bd) | |
54b81550 | 3718 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 3719 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 3720 | |
073d3f5f | 3721 | iwl_eeprom_free(priv); |
b481de9c | 3722 | |
b481de9c | 3723 | |
948c171c MA |
3724 | /*netif_stop_queue(dev); */ |
3725 | flush_workqueue(priv->workqueue); | |
3726 | ||
5b9f8cd3 | 3727 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3728 | * priv->workqueue... so we can't take down the workqueue |
3729 | * until now... */ | |
3730 | destroy_workqueue(priv->workqueue); | |
3731 | priv->workqueue = NULL; | |
20594eb0 | 3732 | iwl_free_traffic_mem(priv); |
b481de9c | 3733 | |
6cd0b1cb HS |
3734 | free_irq(priv->pci_dev->irq, priv); |
3735 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3736 | pci_iounmap(pdev, priv->hw_base); |
3737 | pci_release_regions(pdev); | |
3738 | pci_disable_device(pdev); | |
3739 | pci_set_drvdata(pdev, NULL); | |
3740 | ||
6ba87956 | 3741 | iwl_uninit_drv(priv); |
b481de9c | 3742 | |
ef850d7c MA |
3743 | iwl_free_isr_ict(priv); |
3744 | ||
b481de9c ZY |
3745 | if (priv->ibss_beacon) |
3746 | dev_kfree_skb(priv->ibss_beacon); | |
3747 | ||
3748 | ieee80211_free_hw(priv->hw); | |
3749 | } | |
3750 | ||
b481de9c ZY |
3751 | |
3752 | /***************************************************************************** | |
3753 | * | |
3754 | * driver and module entry point | |
3755 | * | |
3756 | *****************************************************************************/ | |
3757 | ||
fed9017e | 3758 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 3759 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
4fc22b21 | 3760 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3761 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3762 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3763 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3764 | #ifdef CONFIG_IWL5000 |
ac592574 WYG |
3765 | /* 5100 Series WiFi */ |
3766 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ | |
3767 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3768 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
3769 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3770 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3771 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3772 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
3773 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3774 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
3775 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3776 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
3777 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3778 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3779 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3780 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
3781 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3782 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
3783 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3784 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
3785 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3786 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3787 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3788 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
3789 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3790 | ||
3791 | /* 5300 Series WiFi */ | |
3792 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
3793 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3794 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
3795 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3796 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
3797 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3798 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
3799 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3800 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
3801 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3802 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
3803 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3804 | ||
3805 | /* 5350 Series WiFi/WiMax */ | |
3806 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
3807 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
3808 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
3809 | ||
3810 | /* 5150 Series Wifi/WiMax */ | |
3811 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
3812 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
3813 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
3814 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
3815 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
3816 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
3817 | ||
3818 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
3819 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
3820 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
3821 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
3822 | |
3823 | /* 6x00 Series */ | |
5953a62e WYG |
3824 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
3825 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
3826 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
3827 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
3828 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
3829 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
3830 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
3831 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
3832 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
3833 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
0b5af201 | 3834 | {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000i_g2_2agn_cfg)}, |
5953a62e WYG |
3835 | |
3836 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
3837 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
3838 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
3839 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
3840 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
3841 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
3842 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
3843 | ||
77dcb6a9 | 3844 | /* 1000 Series WiFi */ |
4bd0914f WYG |
3845 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
3846 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
3847 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
3848 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
3849 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
3850 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
3851 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
3852 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
3853 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
3854 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
3855 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
3856 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
5a6a256e | 3857 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 3858 | |
fed9017e RR |
3859 | {0} |
3860 | }; | |
3861 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
3862 | ||
3863 | static struct pci_driver iwl_driver = { | |
b481de9c | 3864 | .name = DRV_NAME, |
fed9017e | 3865 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
3866 | .probe = iwl_pci_probe, |
3867 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 3868 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
3869 | .suspend = iwl_pci_suspend, |
3870 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3871 | #endif |
3872 | }; | |
3873 | ||
5b9f8cd3 | 3874 | static int __init iwl_init(void) |
b481de9c ZY |
3875 | { |
3876 | ||
3877 | int ret; | |
3878 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3879 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3880 | |
e227ceac | 3881 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3882 | if (ret) { |
a3139c59 SO |
3883 | printk(KERN_ERR DRV_NAME |
3884 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3885 | return ret; |
3886 | } | |
3887 | ||
fed9017e | 3888 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3889 | if (ret) { |
a3139c59 | 3890 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3891 | goto error_register; |
b481de9c | 3892 | } |
b481de9c ZY |
3893 | |
3894 | return ret; | |
897e1cf2 | 3895 | |
897e1cf2 | 3896 | error_register: |
e227ceac | 3897 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3898 | return ret; |
b481de9c ZY |
3899 | } |
3900 | ||
5b9f8cd3 | 3901 | static void __exit iwl_exit(void) |
b481de9c | 3902 | { |
fed9017e | 3903 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3904 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3905 | } |
3906 | ||
5b9f8cd3 EG |
3907 | module_exit(iwl_exit); |
3908 | module_init(iwl_init); | |
a562a9dd RC |
3909 | |
3910 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 3911 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 3912 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 3913 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
3914 | MODULE_PARM_DESC(debug, "debug output mask"); |
3915 | #endif | |
3916 | ||
2b068618 WYG |
3917 | module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO); |
3918 | MODULE_PARM_DESC(swcrypto50, | |
3919 | "using crypto in software (default 0 [hardware]) (deprecated)"); | |
3920 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); | |
3921 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
3922 | module_param_named(queues_num50, | |
3923 | iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
3924 | MODULE_PARM_DESC(queues_num50, | |
3925 | "number of hw queues in 50xx series (deprecated)"); | |
3926 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
3927 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
3928 | module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
3929 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)"); | |
3930 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
3931 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
3932 | module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K, | |
3933 | int, S_IRUGO); | |
3934 | MODULE_PARM_DESC(amsdu_size_8K50, | |
3935 | "enable 8K amsdu size in 50XX series (deprecated)"); | |
3936 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, | |
3937 | int, S_IRUGO); | |
3938 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
3939 | module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
3940 | MODULE_PARM_DESC(fw_restart50, | |
3941 | "restart firmware in case of error (deprecated)"); | |
3942 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
3943 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
3944 | module_param_named( | |
3945 | disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO); | |
3946 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |