iwlwifi: more code clean up for agn devices
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
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44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO
48#define DRV_NAME "iwlagn"
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
f0832f13 56#include "iwl-calib.h"
a1175124 57#include "iwl-agn.h"
b481de9c 58
416e1438 59
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60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
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66/*
67 * module name, copyright, version, etc.
b481de9c 68 */
d783b061 69#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 70
0a6857e7 71#ifdef CONFIG_IWLWIFI_DEBUG
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72#define VD "d"
73#else
74#define VD
75#endif
76
81963d68 77#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 78
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79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_VERSION(DRV_VERSION);
a7b75207 82MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 83MODULE_LICENSE("GPL");
4fc22b21 84MODULE_ALIAS("iwl4965");
b481de9c 85
b481de9c 86/**
5b9f8cd3 87 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 88 *
01ebd063 89 * The RXON command in staging_rxon is committed to the hardware and
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90 * the active_rxon structure is updated with the new data. This
91 * function correctly transitions out of the RXON_ASSOC_MSK state if
92 * a HW tune is required based on the RXON structure changes.
93 */
e0158e61 94int iwl_commit_rxon(struct iwl_priv *priv)
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95{
96 /* cast away the const for active_rxon in this function */
c1adf9fb 97 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
98 int ret;
99 bool new_assoc =
100 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 101
fee1247a 102 if (!iwl_is_alive(priv))
43d59b32 103 return -EBUSY;
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104
105 /* always get timestamp with Rx frame */
106 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
107
8ccde88a 108 ret = iwl_check_rxon_cmd(priv);
43d59b32 109 if (ret) {
15b1687c 110 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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111 return -EINVAL;
112 }
113
0924e519
WYG
114 /*
115 * receive commit_rxon request
116 * abort any previous channel switch if still in process
117 */
118 if (priv->switch_rxon.switch_in_progress &&
119 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
120 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
121 le16_to_cpu(priv->switch_rxon.channel));
122 priv->switch_rxon.switch_in_progress = false;
123 }
124
b481de9c 125 /* If we don't need to send a full RXON, we can use
5b9f8cd3 126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 127 * and other flags for the current radio configuration. */
54559703 128 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
15b1687c 131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 132 return ret;
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133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 136 iwl_print_rx_config_cmd(priv);
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137 return 0;
138 }
139
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140 /* If we are currently associated and the new config requires
141 * an RXON_ASSOC and the new config wants the associated mask enabled,
142 * we must clear the associated from the active configuration
143 * before we apply the new config */
43d59b32 144 if (iwl_is_associated(priv) && new_assoc) {
e1623446 145 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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146 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
147
43d59b32 148 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 149 sizeof(struct iwl_rxon_cmd),
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150 &priv->active_rxon);
151
152 /* If the mask clearing failed then we set
153 * active_rxon back to what it was previously */
43d59b32 154 if (ret) {
b481de9c 155 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 156 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 157 return ret;
b481de9c 158 }
7e246191
RC
159 iwl_clear_ucode_stations(priv, false);
160 iwl_restore_stations(priv);
335348b1
JB
161 ret = iwl_restore_default_wep_keys(priv);
162 if (ret) {
163 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
164 return ret;
165 }
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166 }
167
e1623446 168 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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169 "* with%s RXON_FILTER_ASSOC_MSK\n"
170 "* channel = %d\n"
e174961c 171 "* bssid = %pM\n",
43d59b32 172 (new_assoc ? "" : "out"),
b481de9c 173 le16_to_cpu(priv->staging_rxon.channel),
e174961c 174 priv->staging_rxon.bssid_addr);
b481de9c 175
90e8e424 176 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
177
178 /* Apply the new configuration
7e246191
RC
179 * RXON unassoc clears the station table in uCode so restoration of
180 * stations is needed after it (the RXON command) completes
43d59b32
EG
181 */
182 if (!new_assoc) {
183 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 184 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 185 if (ret) {
15b1687c 186 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
187 return ret;
188 }
91dd6c27 189 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
43d59b32 190 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
7e246191
RC
191 iwl_clear_ucode_stations(priv, false);
192 iwl_restore_stations(priv);
335348b1
JB
193 ret = iwl_restore_default_wep_keys(priv);
194 if (ret) {
195 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
196 return ret;
197 }
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198 }
199
19cc1087 200 priv->start_calib = 0;
9185159d 201 if (new_assoc) {
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202 /*
203 * allow CTS-to-self if possible for new association.
204 * this is relevant only for 5000 series and up,
205 * but will not damage 4965
206 */
207 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
208
43d59b32
EG
209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
211 */
212 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
213 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
214 if (ret) {
15b1687c 215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
216 return ret;
217 }
218 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 219 }
a643565e 220 iwl_print_rx_config_cmd(priv);
b481de9c 221
36da7d70
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222 iwl_init_sensitivity(priv);
223
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227 if (ret) {
15b1687c 228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY
229 return ret;
230 }
231
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232 return 0;
233}
234
5b9f8cd3 235void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
236{
237
45823531
AK
238 if (priv->cfg->ops->hcmd->set_rxon_chain)
239 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 240 iwlcore_commit_rxon(priv);
5da4b55f
MA
241}
242
fcab423d 243static void iwl_clear_free_frames(struct iwl_priv *priv)
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244{
245 struct list_head *element;
246
e1623446 247 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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248 priv->frames_count);
249
250 while (!list_empty(&priv->free_frames)) {
251 element = priv->free_frames.next;
252 list_del(element);
fcab423d 253 kfree(list_entry(element, struct iwl_frame, list));
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254 priv->frames_count--;
255 }
256
257 if (priv->frames_count) {
39aadf8c 258 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
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259 priv->frames_count);
260 priv->frames_count = 0;
261 }
262}
263
fcab423d 264static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 265{
fcab423d 266 struct iwl_frame *frame;
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267 struct list_head *element;
268 if (list_empty(&priv->free_frames)) {
269 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
270 if (!frame) {
15b1687c 271 IWL_ERR(priv, "Could not allocate frame!\n");
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272 return NULL;
273 }
274
275 priv->frames_count++;
276 return frame;
277 }
278
279 element = priv->free_frames.next;
280 list_del(element);
fcab423d 281 return list_entry(element, struct iwl_frame, list);
b481de9c
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282}
283
fcab423d 284static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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285{
286 memset(frame, 0, sizeof(*frame));
287 list_add(&frame->list, &priv->free_frames);
288}
289
47ff65c4 290static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 291 struct ieee80211_hdr *hdr,
73ec1cc2 292 int left)
b481de9c 293{
3109ece1 294 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
295 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
296 (priv->iw_mode != NL80211_IFTYPE_AP)))
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297 return 0;
298
299 if (priv->ibss_beacon->len > left)
300 return 0;
301
302 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
303
304 return priv->ibss_beacon->len;
305}
306
47ff65c4
DH
307/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
308static void iwl_set_beacon_tim(struct iwl_priv *priv,
309 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
310 u8 *beacon, u32 frame_size)
311{
312 u16 tim_idx;
313 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
314
315 /*
316 * The index is relative to frame start but we start looking at the
317 * variable-length part of the beacon.
318 */
319 tim_idx = mgmt->u.beacon.variable - beacon;
320
321 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
322 while ((tim_idx < (frame_size - 2)) &&
323 (beacon[tim_idx] != WLAN_EID_TIM))
324 tim_idx += beacon[tim_idx+1] + 2;
325
326 /* If TIM field was found, set variables */
327 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
328 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
329 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
330 } else
331 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
332}
333
5b9f8cd3 334static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 335 struct iwl_frame *frame)
4bf64efd
TW
336{
337 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH
338 u32 frame_size;
339 u32 rate_flags;
340 u32 rate;
341 /*
342 * We have to set up the TX command, the TX Beacon command, and the
343 * beacon contents.
344 */
4bf64efd 345
47ff65c4 346 /* Initialize memory */
4bf64efd
TW
347 tx_beacon_cmd = &frame->u.beacon;
348 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
349
47ff65c4 350 /* Set up TX beacon contents */
4bf64efd 351 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 352 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH
353 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
354 return 0;
4bf64efd 355
47ff65c4 356 /* Set up TX command fields */
4bf64efd 357 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH
358 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
359 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
360 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
361 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 362
47ff65c4
DH
363 /* Set up TX beacon command fields */
364 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
365 frame_size);
4bf64efd 366
47ff65c4
DH
367 /* Set up packet rate and flags */
368 rate = iwl_rate_get_lowest_plcp(priv);
369 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
370 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
371 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
372 rate_flags |= RATE_MCS_CCK_MSK;
373 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
374 rate_flags);
4bf64efd
TW
375
376 return sizeof(*tx_beacon_cmd) + frame_size;
377}
5b9f8cd3 378static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 379{
fcab423d 380 struct iwl_frame *frame;
b481de9c
ZY
381 unsigned int frame_size;
382 int rc;
b481de9c 383
fcab423d 384 frame = iwl_get_free_frame(priv);
b481de9c 385 if (!frame) {
15b1687c 386 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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387 "command.\n");
388 return -ENOMEM;
389 }
390
47ff65c4
DH
391 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
392 if (!frame_size) {
393 IWL_ERR(priv, "Error configuring the beacon command\n");
394 iwl_free_frame(priv, frame);
395 return -EINVAL;
396 }
b481de9c 397
857485c0 398 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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399 &frame->u.cmd[0]);
400
fcab423d 401 iwl_free_frame(priv, frame);
b481de9c
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402
403 return rc;
404}
405
7aaa1d79
SO
406static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
407{
408 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
409
410 dma_addr_t addr = get_unaligned_le32(&tb->lo);
411 if (sizeof(dma_addr_t) > sizeof(u32))
412 addr |=
413 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
414
415 return addr;
416}
417
418static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
419{
420 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
421
422 return le16_to_cpu(tb->hi_n_len) >> 4;
423}
424
425static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
426 dma_addr_t addr, u16 len)
427{
428 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
429 u16 hi_n_len = len << 4;
430
431 put_unaligned_le32(addr, &tb->lo);
432 if (sizeof(dma_addr_t) > sizeof(u32))
433 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
434
435 tb->hi_n_len = cpu_to_le16(hi_n_len);
436
437 tfd->num_tbs = idx + 1;
438}
439
440static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
441{
442 return tfd->num_tbs & 0x1f;
443}
444
445/**
446 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
447 * @priv - driver private data
448 * @txq - tx queue
449 *
450 * Does NOT advance any TFD circular buffer read/write indexes
451 * Does NOT free the TFD itself (which is within circular buffer)
452 */
453void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
454{
59606ffa 455 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
456 struct iwl_tfd *tfd;
457 struct pci_dev *dev = priv->pci_dev;
458 int index = txq->q.read_ptr;
459 int i;
460 int num_tbs;
461
462 tfd = &tfd_tmp[index];
463
464 /* Sanity check on number of chunks */
465 num_tbs = iwl_tfd_get_num_tbs(tfd);
466
467 if (num_tbs >= IWL_NUM_OF_TBS) {
468 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
469 /* @todo issue fatal error, it is quite serious situation */
470 return;
471 }
472
473 /* Unmap tx_cmd */
474 if (num_tbs)
475 pci_unmap_single(dev,
c2acea8e
JB
476 pci_unmap_addr(&txq->meta[index], mapping),
477 pci_unmap_len(&txq->meta[index], len),
96891cee 478 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
479
480 /* Unmap chunks, if any. */
481 for (i = 1; i < num_tbs; i++) {
482 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
483 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
484
485 if (txq->txb) {
486 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
487 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
488 }
489 }
490}
491
492int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
493 struct iwl_tx_queue *txq,
494 dma_addr_t addr, u16 len,
495 u8 reset, u8 pad)
496{
497 struct iwl_queue *q;
59606ffa 498 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
499 u32 num_tbs;
500
501 q = &txq->q;
59606ffa
SO
502 tfd_tmp = (struct iwl_tfd *)txq->tfds;
503 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
504
505 if (reset)
506 memset(tfd, 0, sizeof(*tfd));
507
508 num_tbs = iwl_tfd_get_num_tbs(tfd);
509
510 /* Each TFD can point to a maximum 20 Tx buffers */
511 if (num_tbs >= IWL_NUM_OF_TBS) {
512 IWL_ERR(priv, "Error can not send more than %d chunks\n",
513 IWL_NUM_OF_TBS);
514 return -EINVAL;
515 }
516
517 BUG_ON(addr & ~DMA_BIT_MASK(36));
518 if (unlikely(addr & ~IWL_TX_DMA_MASK))
519 IWL_ERR(priv, "Unaligned address = %llx\n",
520 (unsigned long long)addr);
521
522 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
523
524 return 0;
525}
526
a8e74e27
SO
527/*
528 * Tell nic where to find circular buffer of Tx Frame Descriptors for
529 * given Tx queue, and enable the DMA channel used for that queue.
530 *
531 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
532 * channels supported in hardware.
533 */
534int iwl_hw_tx_queue_init(struct iwl_priv *priv,
535 struct iwl_tx_queue *txq)
536{
a8e74e27
SO
537 int txq_id = txq->q.id;
538
a8e74e27
SO
539 /* Circular buffer (TFD queue in DRAM) physical base address */
540 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
541 txq->q.dma_addr >> 8);
542
a8e74e27
SO
543 return 0;
544}
545
b481de9c
ZY
546/******************************************************************************
547 *
548 * Generic RX handler implementations
549 *
550 ******************************************************************************/
885ba202
TW
551static void iwl_rx_reply_alive(struct iwl_priv *priv,
552 struct iwl_rx_mem_buffer *rxb)
b481de9c 553{
2f301227 554 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 555 struct iwl_alive_resp *palive;
b481de9c
ZY
556 struct delayed_work *pwork;
557
558 palive = &pkt->u.alive_frame;
559
e1623446 560 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
561 "0x%01X 0x%01X\n",
562 palive->is_valid, palive->ver_type,
563 palive->ver_subtype);
564
565 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 566 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
567 memcpy(&priv->card_alive_init,
568 &pkt->u.alive_frame,
885ba202 569 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
570 pwork = &priv->init_alive_start;
571 } else {
e1623446 572 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 573 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 574 sizeof(struct iwl_alive_resp));
b481de9c
ZY
575 pwork = &priv->alive_start;
576 }
577
578 /* We delay the ALIVE response by 5ms to
579 * give the HW RF Kill time to activate... */
580 if (palive->is_valid == UCODE_VALID_OK)
581 queue_delayed_work(priv->workqueue, pwork,
582 msecs_to_jiffies(5));
583 else
39aadf8c 584 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
585}
586
5b9f8cd3 587static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 588{
c79dd5b5
TW
589 struct iwl_priv *priv =
590 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
591 struct sk_buff *beacon;
592
593 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 594 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
595
596 if (!beacon) {
15b1687c 597 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
598 return;
599 }
600
601 mutex_lock(&priv->mutex);
602 /* new beacon skb is allocated every time; dispose previous.*/
603 if (priv->ibss_beacon)
604 dev_kfree_skb(priv->ibss_beacon);
605
606 priv->ibss_beacon = beacon;
607 mutex_unlock(&priv->mutex);
608
5b9f8cd3 609 iwl_send_beacon_cmd(priv);
b481de9c
ZY
610}
611
4e39317d 612/**
5b9f8cd3 613 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
614 *
615 * This callback is provided in order to send a statistics request.
616 *
617 * This timer function is continually reset to execute within
618 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
619 * was received. We need to ensure we receive the statistics in order
620 * to update the temperature used for calibrating the TXPOWER.
621 */
5b9f8cd3 622static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
623{
624 struct iwl_priv *priv = (struct iwl_priv *)data;
625
626 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
627 return;
628
61780ee3
MA
629 /* dont send host command if rf-kill is on */
630 if (!iwl_is_ready_rf(priv))
631 return;
632
ef8d5529 633 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
634}
635
a9e1cb6a
WYG
636
637static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
638 u32 start_idx, u32 num_events,
639 u32 mode)
640{
641 u32 i;
642 u32 ptr; /* SRAM byte address of log data */
643 u32 ev, time, data; /* event log data */
644 unsigned long reg_flags;
645
646 if (mode == 0)
647 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
648 else
649 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
650
651 /* Make sure device is powered up for SRAM reads */
652 spin_lock_irqsave(&priv->reg_lock, reg_flags);
653 if (iwl_grab_nic_access(priv)) {
654 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
655 return;
656 }
657
658 /* Set starting address; reads will auto-increment */
659 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
660 rmb();
661
662 /*
663 * "time" is actually "data" for mode 0 (no timestamp).
664 * place event id # at far right for easier visual parsing.
665 */
666 for (i = 0; i < num_events; i++) {
667 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
668 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
669 if (mode == 0) {
670 trace_iwlwifi_dev_ucode_cont_event(priv,
671 0, time, ev);
672 } else {
673 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
674 trace_iwlwifi_dev_ucode_cont_event(priv,
675 time, data, ev);
676 }
677 }
678 /* Allow device to power down */
679 iwl_release_nic_access(priv);
680 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
681}
682
875295f1 683static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG
684{
685 u32 capacity; /* event log capacity in # entries */
686 u32 base; /* SRAM byte address of event log header */
687 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
688 u32 num_wraps; /* # times uCode wrapped to top of log */
689 u32 next_entry; /* index of next entry to be written by uCode */
690
691 if (priv->ucode_type == UCODE_INIT)
692 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
693 else
694 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
695 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
696 capacity = iwl_read_targ_mem(priv, base);
697 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
698 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
699 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
700 } else
701 return;
702
703 if (num_wraps == priv->event_log.num_wraps) {
704 iwl_print_cont_event_trace(priv,
705 base, priv->event_log.next_entry,
706 next_entry - priv->event_log.next_entry,
707 mode);
708 priv->event_log.non_wraps_count++;
709 } else {
710 if ((num_wraps - priv->event_log.num_wraps) > 1)
711 priv->event_log.wraps_more_count++;
712 else
713 priv->event_log.wraps_once_count++;
714 trace_iwlwifi_dev_ucode_wrap_event(priv,
715 num_wraps - priv->event_log.num_wraps,
716 next_entry, priv->event_log.next_entry);
717 if (next_entry < priv->event_log.next_entry) {
718 iwl_print_cont_event_trace(priv, base,
719 priv->event_log.next_entry,
720 capacity - priv->event_log.next_entry,
721 mode);
722
723 iwl_print_cont_event_trace(priv, base, 0,
724 next_entry, mode);
725 } else {
726 iwl_print_cont_event_trace(priv, base,
727 next_entry, capacity - next_entry,
728 mode);
729
730 iwl_print_cont_event_trace(priv, base, 0,
731 next_entry, mode);
732 }
733 }
734 priv->event_log.num_wraps = num_wraps;
735 priv->event_log.next_entry = next_entry;
736}
737
738/**
739 * iwl_bg_ucode_trace - Timer callback to log ucode event
740 *
741 * The timer is continually set to execute every
742 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
743 * this function is to perform continuous uCode event logging operation
744 * if enabled
745 */
746static void iwl_bg_ucode_trace(unsigned long data)
747{
748 struct iwl_priv *priv = (struct iwl_priv *)data;
749
750 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
751 return;
752
753 if (priv->event_log.ucode_trace) {
754 iwl_continuous_event_trace(priv);
755 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
756 mod_timer(&priv->ucode_trace,
757 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
758 }
759}
760
5b9f8cd3 761static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 762 struct iwl_rx_mem_buffer *rxb)
b481de9c 763{
0a6857e7 764#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 765 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
766 struct iwl4965_beacon_notif *beacon =
767 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 768 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 769
e1623446 770 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 771 "tsf %d %d rate %d\n",
25a6572c 772 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
773 beacon->beacon_notify_hdr.failure_frame,
774 le32_to_cpu(beacon->ibss_mgr_status),
775 le32_to_cpu(beacon->high_tsf),
776 le32_to_cpu(beacon->low_tsf), rate);
777#endif
778
05c914fe 779 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
780 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
781 queue_work(priv->workqueue, &priv->beacon_update);
782}
783
b481de9c
ZY
784/* Handle notification from uCode that card's power state is changing
785 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 786static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 787 struct iwl_rx_mem_buffer *rxb)
b481de9c 788{
2f301227 789 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
790 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
791 unsigned long status = priv->status;
792
3a41bbd5 793 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 794 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG
795 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
796 (flags & CT_CARD_DISABLED) ?
797 "Reached" : "Not reached");
b481de9c
ZY
798
799 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 800 CT_CARD_DISABLED)) {
b481de9c 801
3395f6e9 802 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
803 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
804
a8b50a0a
MA
805 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
806 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
807
808 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 809 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 810 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 811 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 812 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 813 }
3a41bbd5 814 if (flags & CT_CARD_DISABLED)
39b73fb1 815 iwl_tt_enter_ct_kill(priv);
b481de9c 816 }
3a41bbd5 817 if (!(flags & CT_CARD_DISABLED))
39b73fb1 818 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
819
820 if (flags & HW_CARD_DISABLED)
821 set_bit(STATUS_RF_KILL_HW, &priv->status);
822 else
823 clear_bit(STATUS_RF_KILL_HW, &priv->status);
824
825
b481de9c 826 if (!(flags & RXON_CARD_DISABLED))
2a421b91 827 iwl_scan_cancel(priv);
b481de9c
ZY
828
829 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
830 test_bit(STATUS_RF_KILL_HW, &priv->status)))
831 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
832 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
833 else
834 wake_up_interruptible(&priv->wait_command_queue);
835}
836
5b9f8cd3 837int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 838{
e2e3c57b 839 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 840 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
841 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
842 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
843 ~APMG_PS_CTRL_MSK_PWR_SRC);
844 } else {
845 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
846 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
847 ~APMG_PS_CTRL_MSK_PWR_SRC);
848 }
849
a8b50a0a 850 return 0;
e2e3c57b
TW
851}
852
b481de9c 853/**
5b9f8cd3 854 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
855 *
856 * Setup the RX handlers for each of the reply types sent from the uCode
857 * to the host.
858 *
859 * This function chains into the hardware specific files for them to setup
860 * any hardware specific handlers as well.
861 */
653fa4a0 862static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 863{
885ba202 864 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
865 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
866 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
867 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
868 iwl_rx_spectrum_measure_notif;
5b9f8cd3 869 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 870 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
871 iwl_rx_pm_debug_statistics_notif;
872 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 873
9fbab516
BC
874 /*
875 * The same handler is used for both the REPLY to a discrete
876 * statistics request from the host as well as for the periodic
877 * statistics notifications (after received beacons) from the uCode.
b481de9c 878 */
ef8d5529 879 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 880 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW
881
882 iwl_setup_rx_scan_handlers(priv);
883
37a44211 884 /* status change handler */
5b9f8cd3 885 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 886
c1354754
TW
887 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
888 iwl_rx_missed_beacon_notif;
37a44211 889 /* Rx handlers */
8d801080
WYG
890 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
891 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 892 /* block ack */
74bcdb33 893 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 894 /* Set up hardware specific Rx handlers */
d4789efe 895 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
896}
897
b481de9c 898/**
a55360e4 899 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
900 *
901 * Uses the priv->rx_handlers callback function array to invoke
902 * the appropriate handlers, including command responses,
903 * frame-received notifications, and other notifications.
904 */
a55360e4 905void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 906{
a55360e4 907 struct iwl_rx_mem_buffer *rxb;
db11d634 908 struct iwl_rx_packet *pkt;
a55360e4 909 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
910 u32 r, i;
911 int reclaim;
912 unsigned long flags;
5c0eef96 913 u8 fill_rx = 0;
d68ab680 914 u32 count = 8;
4752c93c 915 int total_empty;
b481de9c 916
6440adb5
CB
917 /* uCode's read index (stored in shared DRAM) indicates the last Rx
918 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 919 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
920 i = rxq->read;
921
922 /* Rx interrupt, but nothing sent from uCode */
923 if (i == r)
e1623446 924 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 925
4752c93c 926 /* calculate total frames need to be restock after handling RX */
7300515d 927 total_empty = r - rxq->write_actual;
4752c93c
MA
928 if (total_empty < 0)
929 total_empty += RX_QUEUE_SIZE;
930
931 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
932 fill_rx = 1;
933
b481de9c
ZY
934 while (i != r) {
935 rxb = rxq->queue[i];
936
9fbab516 937 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
938 * then a bug has been introduced in the queue refilling
939 * routines -- catch it here */
940 BUG_ON(rxb == NULL);
941
942 rxq->queue[i] = NULL;
943
2f301227
ZY
944 pci_unmap_page(priv->pci_dev, rxb->page_dma,
945 PAGE_SIZE << priv->hw_params.rx_page_order,
946 PCI_DMA_FROMDEVICE);
947 pkt = rxb_addr(rxb);
b481de9c 948
be1a71a1
JB
949 trace_iwlwifi_dev_rx(priv, pkt,
950 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
951
b481de9c
ZY
952 /* Reclaim a command buffer only if this packet is a response
953 * to a (driver-originated) command.
954 * If the packet (e.g. Rx frame) originated from uCode,
955 * there is no command buffer to reclaim.
956 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
957 * but apparently a few don't get set; catch them here. */
958 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
959 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 960 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 961 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 962 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
963 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
964 (pkt->hdr.cmd != REPLY_TX);
965
966 /* Based on type of command response or notification,
967 * handle those that need handling via function in
5b9f8cd3 968 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 969 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 970 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 971 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 972 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 973 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
974 } else {
975 /* No handling needed */
e1623446 976 IWL_DEBUG_RX(priv,
b481de9c
ZY
977 "r %d i %d No handler needed for %s, 0x%02x\n",
978 r, i, get_cmd_string(pkt->hdr.cmd),
979 pkt->hdr.cmd);
980 }
981
29b1b268
ZY
982 /*
983 * XXX: After here, we should always check rxb->page
984 * against NULL before touching it or its virtual
985 * memory (pkt). Because some rx_handler might have
986 * already taken or freed the pages.
987 */
988
b481de9c 989 if (reclaim) {
2f301227
ZY
990 /* Invoke any callbacks, transfer the buffer to caller,
991 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 992 * as we reclaim the driver command queue */
29b1b268 993 if (rxb->page)
17b88929 994 iwl_tx_cmd_complete(priv, rxb);
b481de9c 995 else
39aadf8c 996 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
997 }
998
7300515d
ZY
999 /* Reuse the page if possible. For notification packets and
1000 * SKBs that fail to Rx correctly, add them back into the
1001 * rx_free list for reuse later. */
1002 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1003 if (rxb->page != NULL) {
7300515d
ZY
1004 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1005 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1006 PCI_DMA_FROMDEVICE);
1007 list_add_tail(&rxb->list, &rxq->rx_free);
1008 rxq->free_count++;
1009 } else
1010 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1011
b481de9c 1012 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1013
b481de9c 1014 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1015 /* If there are a lot of unused frames,
1016 * restock the Rx queue so ucode wont assert. */
1017 if (fill_rx) {
1018 count++;
1019 if (count >= 8) {
7300515d 1020 rxq->read = i;
54b81550 1021 iwlagn_rx_replenish_now(priv);
5c0eef96
MA
1022 count = 0;
1023 }
1024 }
b481de9c
ZY
1025 }
1026
1027 /* Backtrack one entry */
7300515d 1028 rxq->read = i;
4752c93c 1029 if (fill_rx)
54b81550 1030 iwlagn_rx_replenish_now(priv);
4752c93c 1031 else
54b81550 1032 iwlagn_rx_queue_restock(priv);
a55360e4 1033}
a55360e4 1034
0359facc
MA
1035/* call this function to flush any scheduled tasklet */
1036static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1037{
a96a27f9 1038 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1039 synchronize_irq(priv->pci_dev->irq);
1040 tasklet_kill(&priv->irq_tasklet);
1041}
1042
ef850d7c 1043static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
1044{
1045 u32 inta, handled = 0;
1046 u32 inta_fh;
1047 unsigned long flags;
c2e61da2 1048 u32 i;
0a6857e7 1049#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1050 u32 inta_mask;
1051#endif
1052
1053 spin_lock_irqsave(&priv->lock, flags);
1054
1055 /* Ack/clear/reset pending uCode interrupts.
1056 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1057 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
1058 inta = iwl_read32(priv, CSR_INT);
1059 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1060
1061 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1062 * Any new interrupts that happen after this, either while we're
1063 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
1064 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1065 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1066
0a6857e7 1067#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1068 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1069 /* just for debug */
3395f6e9 1070 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1071 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1072 inta, inta_mask, inta_fh);
1073 }
1074#endif
1075
2f301227
ZY
1076 spin_unlock_irqrestore(&priv->lock, flags);
1077
b481de9c
ZY
1078 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1079 * atomic, make sure that inta covers all the interrupts that
1080 * we've discovered, even if FH interrupt came in just after
1081 * reading CSR_INT. */
6f83eaa1 1082 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1083 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1084 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
1085 inta |= CSR_INT_BIT_FH_TX;
1086
1087 /* Now service all interrupt bits discovered above. */
1088 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1089 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1090
1091 /* Tell the device to stop sending interrupts */
5b9f8cd3 1092 iwl_disable_interrupts(priv);
b481de9c 1093
a83b9141 1094 priv->isr_stats.hw++;
5b9f8cd3 1095 iwl_irq_handle_error(priv);
b481de9c
ZY
1096
1097 handled |= CSR_INT_BIT_HW_ERR;
1098
b481de9c
ZY
1099 return;
1100 }
1101
0a6857e7 1102#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1103 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1104 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1105 if (inta & CSR_INT_BIT_SCD) {
e1623446 1106 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1107 "the frame/frames.\n");
a83b9141
WYG
1108 priv->isr_stats.sch++;
1109 }
b481de9c
ZY
1110
1111 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1112 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1113 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
1114 priv->isr_stats.alive++;
1115 }
b481de9c
ZY
1116 }
1117#endif
1118 /* Safely ignore these bits for debug checks below */
25c03d8e 1119 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1120
9fbab516 1121 /* HW RF KILL switch toggled */
b481de9c
ZY
1122 if (inta & CSR_INT_BIT_RF_KILL) {
1123 int hw_rf_kill = 0;
3395f6e9 1124 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1125 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1126 hw_rf_kill = 1;
1127
4c423a2b 1128 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1129 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1130
a83b9141
WYG
1131 priv->isr_stats.rfkill++;
1132
a9efa652 1133 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1134 * the driver allows loading the ucode even if the radio
1135 * is killed. Hence update the killswitch state here. The
1136 * rfkill handler will care about restarting if needed.
a9efa652 1137 */
6cd0b1cb
HS
1138 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1139 if (hw_rf_kill)
1140 set_bit(STATUS_RF_KILL_HW, &priv->status);
1141 else
1142 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1143 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1144 }
b481de9c
ZY
1145
1146 handled |= CSR_INT_BIT_RF_KILL;
1147 }
1148
9fbab516 1149 /* Chip got too hot and stopped itself */
b481de9c 1150 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1151 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1152 priv->isr_stats.ctkill++;
b481de9c
ZY
1153 handled |= CSR_INT_BIT_CT_KILL;
1154 }
1155
1156 /* Error detected by uCode */
1157 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1158 IWL_ERR(priv, "Microcode SW error detected. "
1159 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1160 priv->isr_stats.sw++;
1161 priv->isr_stats.sw_err = inta;
5b9f8cd3 1162 iwl_irq_handle_error(priv);
b481de9c
ZY
1163 handled |= CSR_INT_BIT_SW_ERR;
1164 }
1165
c2e61da2
BC
1166 /*
1167 * uCode wakes up after power-down sleep.
1168 * Tell device about any new tx or host commands enqueued,
1169 * and about any Rx buffers made available while asleep.
1170 */
b481de9c 1171 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1172 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1173 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1174 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1175 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1176 priv->isr_stats.wakeup++;
b481de9c
ZY
1177 handled |= CSR_INT_BIT_WAKEUP;
1178 }
1179
1180 /* All uCode command responses, including Tx command responses,
1181 * Rx "responses" (frame-received notification), and other
1182 * notifications from uCode come through here*/
1183 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1184 iwl_rx_handle(priv);
a83b9141 1185 priv->isr_stats.rx++;
b481de9c
ZY
1186 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1187 }
1188
c72cd19f 1189 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1190 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1191 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1192 priv->isr_stats.tx++;
b481de9c 1193 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1194 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1195 priv->ucode_write_complete = 1;
1196 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1197 }
1198
a83b9141 1199 if (inta & ~handled) {
15b1687c 1200 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1201 priv->isr_stats.unhandled++;
1202 }
b481de9c 1203
40cefda9 1204 if (inta & ~(priv->inta_mask)) {
39aadf8c 1205 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1206 inta & ~priv->inta_mask);
39aadf8c 1207 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1208 }
1209
1210 /* Re-enable all interrupts */
0359facc
MA
1211 /* only Re-enable if diabled by irq */
1212 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1213 iwl_enable_interrupts(priv);
b481de9c 1214
0a6857e7 1215#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1216 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1217 inta = iwl_read32(priv, CSR_INT);
1218 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1219 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1220 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1221 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1222 }
1223#endif
b481de9c
ZY
1224}
1225
ef850d7c
MA
1226/* tasklet for iwlagn interrupt */
1227static void iwl_irq_tasklet(struct iwl_priv *priv)
1228{
1229 u32 inta = 0;
1230 u32 handled = 0;
1231 unsigned long flags;
8756990f 1232 u32 i;
ef850d7c
MA
1233#ifdef CONFIG_IWLWIFI_DEBUG
1234 u32 inta_mask;
1235#endif
1236
1237 spin_lock_irqsave(&priv->lock, flags);
1238
1239 /* Ack/clear/reset pending uCode interrupts.
1240 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1241 */
48a6be6a
SZ
1242 /* There is a hardware bug in the interrupt mask function that some
1243 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1244 * they are disabled in the CSR_INT_MASK register. Furthermore the
1245 * ICT interrupt handling mechanism has another bug that might cause
1246 * these unmasked interrupts fail to be detected. We workaround the
1247 * hardware bugs here by ACKing all the possible interrupts so that
1248 * interrupt coalescing can still be achieved.
1249 */
0f2df9ea 1250 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1251
a4c8b2a6 1252 inta = priv->_agn.inta;
ef850d7c
MA
1253
1254#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1255 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1256 /* just for debug */
1257 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1258 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1259 inta, inta_mask);
1260 }
1261#endif
2f301227
ZY
1262
1263 spin_unlock_irqrestore(&priv->lock, flags);
1264
a4c8b2a6
JB
1265 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1266 priv->_agn.inta = 0;
ef850d7c
MA
1267
1268 /* Now service all interrupt bits discovered above. */
1269 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1270 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1271
1272 /* Tell the device to stop sending interrupts */
1273 iwl_disable_interrupts(priv);
1274
1275 priv->isr_stats.hw++;
1276 iwl_irq_handle_error(priv);
1277
1278 handled |= CSR_INT_BIT_HW_ERR;
1279
ef850d7c
MA
1280 return;
1281 }
1282
1283#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1284 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1285 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1286 if (inta & CSR_INT_BIT_SCD) {
1287 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1288 "the frame/frames.\n");
1289 priv->isr_stats.sch++;
1290 }
1291
1292 /* Alive notification via Rx interrupt will do the real work */
1293 if (inta & CSR_INT_BIT_ALIVE) {
1294 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1295 priv->isr_stats.alive++;
1296 }
1297 }
1298#endif
1299 /* Safely ignore these bits for debug checks below */
1300 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1301
1302 /* HW RF KILL switch toggled */
1303 if (inta & CSR_INT_BIT_RF_KILL) {
1304 int hw_rf_kill = 0;
1305 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1306 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1307 hw_rf_kill = 1;
1308
4c423a2b 1309 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1310 hw_rf_kill ? "disable radio" : "enable radio");
1311
1312 priv->isr_stats.rfkill++;
1313
1314 /* driver only loads ucode once setting the interface up.
1315 * the driver allows loading the ucode even if the radio
1316 * is killed. Hence update the killswitch state here. The
1317 * rfkill handler will care about restarting if needed.
1318 */
1319 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1320 if (hw_rf_kill)
1321 set_bit(STATUS_RF_KILL_HW, &priv->status);
1322 else
1323 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1324 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1325 }
1326
1327 handled |= CSR_INT_BIT_RF_KILL;
1328 }
1329
1330 /* Chip got too hot and stopped itself */
1331 if (inta & CSR_INT_BIT_CT_KILL) {
1332 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1333 priv->isr_stats.ctkill++;
1334 handled |= CSR_INT_BIT_CT_KILL;
1335 }
1336
1337 /* Error detected by uCode */
1338 if (inta & CSR_INT_BIT_SW_ERR) {
1339 IWL_ERR(priv, "Microcode SW error detected. "
1340 " Restarting 0x%X.\n", inta);
1341 priv->isr_stats.sw++;
1342 priv->isr_stats.sw_err = inta;
1343 iwl_irq_handle_error(priv);
1344 handled |= CSR_INT_BIT_SW_ERR;
1345 }
1346
1347 /* uCode wakes up after power-down sleep */
1348 if (inta & CSR_INT_BIT_WAKEUP) {
1349 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1350 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
1351 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1352 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
1353
1354 priv->isr_stats.wakeup++;
1355
1356 handled |= CSR_INT_BIT_WAKEUP;
1357 }
1358
1359 /* All uCode command responses, including Tx command responses,
1360 * Rx "responses" (frame-received notification), and other
1361 * notifications from uCode come through here*/
40cefda9
MA
1362 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1363 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1364 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1365 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1366 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1367 iwl_write32(priv, CSR_FH_INT_STATUS,
1368 CSR49_FH_INT_RX_MASK);
1369 }
1370 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1371 handled |= CSR_INT_BIT_RX_PERIODIC;
1372 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1373 }
1374 /* Sending RX interrupt require many steps to be done in the
1375 * the device:
1376 * 1- write interrupt to current index in ICT table.
1377 * 2- dma RX frame.
1378 * 3- update RX shared data to indicate last write index.
1379 * 4- send interrupt.
1380 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
1381 * but the shared data changes does not reflect this;
1382 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1383 */
74ba67ed
BC
1384
1385 /* Disable periodic interrupt; we use it as just a one-shot. */
1386 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1387 CSR_INT_PERIODIC_DIS);
ef850d7c 1388 iwl_rx_handle(priv);
74ba67ed
BC
1389
1390 /*
1391 * Enable periodic interrupt in 8 msec only if we received
1392 * real RX interrupt (instead of just periodic int), to catch
1393 * any dangling Rx interrupt. If it was just the periodic
1394 * interrupt, there was no dangling Rx activity, and no need
1395 * to extend the periodic interrupt; one-shot is enough.
1396 */
40cefda9 1397 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1398 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
1399 CSR_INT_PERIODIC_ENA);
1400
ef850d7c 1401 priv->isr_stats.rx++;
ef850d7c
MA
1402 }
1403
c72cd19f 1404 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1405 if (inta & CSR_INT_BIT_FH_TX) {
1406 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1407 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1408 priv->isr_stats.tx++;
1409 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1410 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1411 priv->ucode_write_complete = 1;
1412 wake_up_interruptible(&priv->wait_command_queue);
1413 }
1414
1415 if (inta & ~handled) {
1416 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1417 priv->isr_stats.unhandled++;
1418 }
1419
40cefda9 1420 if (inta & ~(priv->inta_mask)) {
ef850d7c 1421 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1422 inta & ~priv->inta_mask);
ef850d7c
MA
1423 }
1424
ef850d7c
MA
1425 /* Re-enable all interrupts */
1426 /* only Re-enable if diabled by irq */
1427 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1428 iwl_enable_interrupts(priv);
ef850d7c
MA
1429}
1430
872c8ddc
WYG
1431/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1432#define ACK_CNT_RATIO (50)
1433#define BA_TIMEOUT_CNT (5)
1434#define BA_TIMEOUT_MAX (16)
1435
1436/**
1437 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1438 *
1439 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1440 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1441 * operation state.
1442 */
1443bool iwl_good_ack_health(struct iwl_priv *priv,
1444 struct iwl_rx_packet *pkt)
1445{
1446 bool rc = true;
1447 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1448 int ba_timeout_delta;
1449
1450 actual_ack_cnt_delta =
1451 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1452 le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
1453 expected_ack_cnt_delta =
1454 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1455 le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
1456 ba_timeout_delta =
1457 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1458 le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
1459 if ((priv->_agn.agg_tids_count > 0) &&
1460 (expected_ack_cnt_delta > 0) &&
1461 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1462 < ACK_CNT_RATIO) &&
1463 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1464 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1465 " expected_ack_cnt = %d\n",
1466 actual_ack_cnt_delta, expected_ack_cnt_delta);
1467
1468#ifdef CONFIG_IWLWIFI_DEBUG
1469 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1470 priv->delta_statistics.tx.rx_detected_cnt);
1471 IWL_DEBUG_RADIO(priv,
1472 "ack_or_ba_timeout_collision delta = %d\n",
1473 priv->delta_statistics.tx.
1474 ack_or_ba_timeout_collision);
1475#endif
1476 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1477 ba_timeout_delta);
1478 if (!actual_ack_cnt_delta &&
1479 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1480 rc = false;
1481 }
1482 return rc;
1483}
1484
a83b9141 1485
b481de9c
ZY
1486/******************************************************************************
1487 *
1488 * uCode download functions
1489 *
1490 ******************************************************************************/
1491
5b9f8cd3 1492static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1493{
98c92211
TW
1494 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1495 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1496 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1497 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1498 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1499 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1500}
1501
5b9f8cd3 1502static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1503{
1504 /* Remove all resets to allow NIC to operate */
1505 iwl_write32(priv, CSR_RESET, 0);
1506}
1507
1508
b08dfd04
JB
1509static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1510static int iwl_mac_setup_register(struct iwl_priv *priv);
1511
1512static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1513{
1514 const char *name_pre = priv->cfg->fw_name_pre;
1515
1516 if (first)
1517 priv->fw_index = priv->cfg->ucode_api_max;
1518 else
1519 priv->fw_index--;
1520
1521 if (priv->fw_index < priv->cfg->ucode_api_min) {
1522 IWL_ERR(priv, "no suitable firmware found!\n");
1523 return -ENOENT;
1524 }
1525
1526 sprintf(priv->firmware_name, "%s%d%s",
1527 name_pre, priv->fw_index, ".ucode");
1528
1529 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1530 priv->firmware_name);
1531
1532 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1533 &priv->pci_dev->dev, GFP_KERNEL, priv,
1534 iwl_ucode_callback);
1535}
1536
b481de9c 1537/**
b08dfd04 1538 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1539 *
b08dfd04
JB
1540 * If loaded successfully, copies the firmware into buffers
1541 * for the card to fetch (via DMA).
b481de9c 1542 */
b08dfd04 1543static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1544{
b08dfd04 1545 struct iwl_priv *priv = context;
cc0f555d 1546 struct iwl_ucode_header *ucode;
a0987a8d
RC
1547 const unsigned int api_max = priv->cfg->ucode_api_max;
1548 const unsigned int api_min = priv->cfg->ucode_api_min;
b481de9c
ZY
1549 u8 *src;
1550 size_t len;
cc0f555d
JS
1551 u32 api_ver, build;
1552 u32 inst_size, data_size, init_size, init_data_size, boot_size;
b08dfd04 1553 int err;
abdc2d62 1554 u16 eeprom_ver;
b481de9c 1555
b08dfd04
JB
1556 if (!ucode_raw) {
1557 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1558 priv->firmware_name);
1559 goto try_again;
b481de9c
ZY
1560 }
1561
b08dfd04
JB
1562 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1563 priv->firmware_name, ucode_raw->size);
b481de9c 1564
cc0f555d
JS
1565 /* Make sure that we got at least the v1 header! */
1566 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1567 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1568 goto try_again;
b481de9c
ZY
1569 }
1570
1571 /* Data from ucode file: header followed by uCode images */
cc0f555d 1572 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1573
c02b3acd 1574 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1575 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1576 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1577 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1578 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1579 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1580 init_data_size =
1581 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1582 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1583 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1584
a0987a8d
RC
1585 /* api_ver should match the api version forming part of the
1586 * firmware filename ... but we don't check for that and only rely
877d0310 1587 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1588
1589 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1590 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1591 "Driver supports v%u, firmware is v%u.\n",
1592 api_max, api_ver);
b08dfd04 1593 goto try_again;
a0987a8d 1594 }
b08dfd04 1595
a0987a8d 1596 if (api_ver != api_max)
978785a3 1597 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1598 "got v%u. New firmware can be obtained "
1599 "from http://www.intellinuxwireless.org.\n",
1600 api_max, api_ver);
1601
978785a3
TW
1602 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1603 IWL_UCODE_MAJOR(priv->ucode_ver),
1604 IWL_UCODE_MINOR(priv->ucode_ver),
1605 IWL_UCODE_API(priv->ucode_ver),
1606 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1607
5ebeb5a6
RC
1608 snprintf(priv->hw->wiphy->fw_version,
1609 sizeof(priv->hw->wiphy->fw_version),
1610 "%u.%u.%u.%u",
1611 IWL_UCODE_MAJOR(priv->ucode_ver),
1612 IWL_UCODE_MINOR(priv->ucode_ver),
1613 IWL_UCODE_API(priv->ucode_ver),
1614 IWL_UCODE_SERIAL(priv->ucode_ver));
1615
cc0f555d
JS
1616 if (build)
1617 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1618
abdc2d62
JS
1619 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1620 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1621 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1622 ? "OTP" : "EEPROM", eeprom_ver);
1623
e1623446 1624 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1625 priv->ucode_ver);
e1623446 1626 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1627 inst_size);
e1623446 1628 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1629 data_size);
e1623446 1630 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1631 init_size);
e1623446 1632 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1633 init_data_size);
e1623446 1634 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1635 boot_size);
1636
b08dfd04
JB
1637 /*
1638 * For any of the failures below (before allocating pci memory)
1639 * we will try to load a version with a smaller API -- maybe the
1640 * user just got a corrupted version of the latest API.
1641 */
1642
b481de9c 1643 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1644 if (ucode_raw->size !=
1645 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1646 inst_size + data_size + init_size +
1647 init_data_size + boot_size) {
1648
cc0f555d
JS
1649 IWL_DEBUG_INFO(priv,
1650 "uCode file size %d does not match expected size\n",
1651 (int)ucode_raw->size);
b08dfd04 1652 goto try_again;
b481de9c
ZY
1653 }
1654
1655 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1656 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1657 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1 1658 inst_size);
b08dfd04 1659 goto try_again;
b481de9c
ZY
1660 }
1661
099b40b7 1662 if (data_size > priv->hw_params.max_data_size) {
e1623446 1663 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1 1664 data_size);
b08dfd04 1665 goto try_again;
b481de9c 1666 }
099b40b7 1667 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1668 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1669 init_size);
b08dfd04 1670 goto try_again;
b481de9c 1671 }
099b40b7 1672 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1673 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1 1674 init_data_size);
b08dfd04 1675 goto try_again;
b481de9c 1676 }
099b40b7 1677 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1678 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1679 boot_size);
b08dfd04 1680 goto try_again;
b481de9c
ZY
1681 }
1682
1683 /* Allocate ucode buffers for card's bus-master loading ... */
1684
1685 /* Runtime instructions and 2 copies of data:
1686 * 1) unmodified from disk
1687 * 2) backup cache for save/restore during power-downs */
1688 priv->ucode_code.len = inst_size;
98c92211 1689 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1690
1691 priv->ucode_data.len = data_size;
98c92211 1692 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1693
1694 priv->ucode_data_backup.len = data_size;
98c92211 1695 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1696
1f304e4e
ZY
1697 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1698 !priv->ucode_data_backup.v_addr)
1699 goto err_pci_alloc;
1700
b481de9c 1701 /* Initialization instructions and data */
90e759d1
TW
1702 if (init_size && init_data_size) {
1703 priv->ucode_init.len = init_size;
98c92211 1704 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1705
1706 priv->ucode_init_data.len = init_data_size;
98c92211 1707 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1708
1709 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1710 goto err_pci_alloc;
1711 }
b481de9c
ZY
1712
1713 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1714 if (boot_size) {
1715 priv->ucode_boot.len = boot_size;
98c92211 1716 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1717
90e759d1
TW
1718 if (!priv->ucode_boot.v_addr)
1719 goto err_pci_alloc;
1720 }
b481de9c
ZY
1721
1722 /* Copy images into buffers for card's bus-master reads ... */
1723
1724 /* Runtime instructions (first block of data in file) */
cc0f555d 1725 len = inst_size;
e1623446 1726 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1727 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1728 src += len;
1729
e1623446 1730 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1731 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1732
1733 /* Runtime data (2nd block)
5b9f8cd3 1734 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1735 len = data_size;
e1623446 1736 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1737 memcpy(priv->ucode_data.v_addr, src, len);
1738 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1739 src += len;
b481de9c
ZY
1740
1741 /* Initialization instructions (3rd block) */
1742 if (init_size) {
cc0f555d 1743 len = init_size;
e1623446 1744 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1745 len);
b481de9c 1746 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1747 src += len;
b481de9c
ZY
1748 }
1749
1750 /* Initialization data (4th block) */
1751 if (init_data_size) {
cc0f555d 1752 len = init_data_size;
e1623446 1753 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1754 len);
b481de9c 1755 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1756 src += len;
b481de9c
ZY
1757 }
1758
1759 /* Bootstrap instructions (5th block) */
cc0f555d 1760 len = boot_size;
e1623446 1761 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1762 memcpy(priv->ucode_boot.v_addr, src, len);
1763
b08dfd04
JB
1764 /**************************************************
1765 * This is still part of probe() in a sense...
1766 *
1767 * 9. Setup and register with mac80211 and debugfs
1768 **************************************************/
1769 err = iwl_mac_setup_register(priv);
1770 if (err)
1771 goto out_unbind;
1772
1773 err = iwl_dbgfs_register(priv, DRV_NAME);
1774 if (err)
1775 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1776
b481de9c
ZY
1777 /* We have our copies now, allow OS release its copies */
1778 release_firmware(ucode_raw);
b08dfd04
JB
1779 return;
1780
1781 try_again:
1782 /* try next, if any */
1783 if (iwl_request_firmware(priv, false))
1784 goto out_unbind;
1785 release_firmware(ucode_raw);
1786 return;
b481de9c
ZY
1787
1788 err_pci_alloc:
15b1687c 1789 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 1790 iwl_dealloc_ucode_pci(priv);
b08dfd04
JB
1791 out_unbind:
1792 device_release_driver(&priv->pci_dev->dev);
b481de9c 1793 release_firmware(ucode_raw);
b481de9c
ZY
1794}
1795
b7a79404
RC
1796static const char *desc_lookup_text[] = {
1797 "OK",
1798 "FAIL",
1799 "BAD_PARAM",
1800 "BAD_CHECKSUM",
1801 "NMI_INTERRUPT_WDG",
1802 "SYSASSERT",
1803 "FATAL_ERROR",
1804 "BAD_COMMAND",
1805 "HW_ERROR_TUNE_LOCK",
1806 "HW_ERROR_TEMPERATURE",
1807 "ILLEGAL_CHAN_FREQ",
1808 "VCC_NOT_STABLE",
1809 "FH_ERROR",
1810 "NMI_INTERRUPT_HOST",
1811 "NMI_INTERRUPT_ACTION_PT",
1812 "NMI_INTERRUPT_UNKNOWN",
1813 "UCODE_VERSION_MISMATCH",
1814 "HW_ERROR_ABS_LOCK",
1815 "HW_ERROR_CAL_LOCK_FAIL",
1816 "NMI_INTERRUPT_INST_ACTION_PT",
1817 "NMI_INTERRUPT_DATA_ACTION_PT",
1818 "NMI_TRM_HW_ER",
1819 "NMI_INTERRUPT_TRM",
1820 "NMI_INTERRUPT_BREAK_POINT"
1821 "DEBUG_0",
1822 "DEBUG_1",
1823 "DEBUG_2",
1824 "DEBUG_3",
a7fce6ee 1825 "ADVANCED SYSASSERT"
b7a79404
RC
1826};
1827
1828static const char *desc_lookup(int i)
1829{
1830 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1831
1832 if (i < 0 || i > max)
1833 i = max;
1834
1835 return desc_lookup_text[i];
1836}
1837
1838#define ERROR_START_OFFSET (1 * sizeof(u32))
1839#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1840
1841void iwl_dump_nic_error_log(struct iwl_priv *priv)
1842{
1843 u32 data2, line;
1844 u32 desc, time, count, base, data1;
1845 u32 blink1, blink2, ilink1, ilink2;
461ef382 1846 u32 pc, hcmd;
b7a79404
RC
1847
1848 if (priv->ucode_type == UCODE_INIT)
1849 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1850 else
1851 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1852
1853 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1854 IWL_ERR(priv,
1855 "Not valid error log pointer 0x%08X for %s uCode\n",
1856 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC
1857 return;
1858 }
1859
1860 count = iwl_read_targ_mem(priv, base);
1861
1862 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1863 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1864 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1865 priv->status, count);
1866 }
1867
1868 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 1869 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC
1870 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1871 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1872 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1873 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1874 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1875 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1876 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1877 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 1878 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 1879
be1a71a1
JB
1880 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1881 blink1, blink2, ilink1, ilink2);
1882
b7a79404
RC
1883 IWL_ERR(priv, "Desc Time "
1884 "data1 data2 line\n");
1885 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1886 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG
1887 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1888 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1889 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC
1890}
1891
1892#define EVENT_START_OFFSET (4 * sizeof(u32))
1893
1894/**
1895 * iwl_print_event_log - Dump error event log to syslog
1896 *
1897 */
b03d7d0f
WYG
1898static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1899 u32 num_events, u32 mode,
1900 int pos, char **buf, size_t bufsz)
b7a79404
RC
1901{
1902 u32 i;
1903 u32 base; /* SRAM byte address of event log header */
1904 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1905 u32 ptr; /* SRAM byte address of log data */
1906 u32 ev, time, data; /* event log data */
e5854471 1907 unsigned long reg_flags;
b7a79404
RC
1908
1909 if (num_events == 0)
b03d7d0f 1910 return pos;
b7a79404
RC
1911 if (priv->ucode_type == UCODE_INIT)
1912 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1913 else
1914 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1915
1916 if (mode == 0)
1917 event_size = 2 * sizeof(u32);
1918 else
1919 event_size = 3 * sizeof(u32);
1920
1921 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1922
e5854471
BC
1923 /* Make sure device is powered up for SRAM reads */
1924 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1925 iwl_grab_nic_access(priv);
1926
1927 /* Set starting address; reads will auto-increment */
1928 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1929 rmb();
1930
b7a79404
RC
1931 /* "time" is actually "data" for mode 0 (no timestamp).
1932 * place event id # at far right for easier visual parsing. */
1933 for (i = 0; i < num_events; i++) {
e5854471
BC
1934 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1935 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1936 if (mode == 0) {
1937 /* data, ev */
b03d7d0f
WYG
1938 if (bufsz) {
1939 pos += scnprintf(*buf + pos, bufsz - pos,
1940 "EVT_LOG:0x%08x:%04u\n",
1941 time, ev);
1942 } else {
1943 trace_iwlwifi_dev_ucode_event(priv, 0,
1944 time, ev);
1945 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1946 time, ev);
1947 }
b7a79404 1948 } else {
e5854471 1949 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1950 if (bufsz) {
1951 pos += scnprintf(*buf + pos, bufsz - pos,
1952 "EVT_LOGT:%010u:0x%08x:%04u\n",
1953 time, data, ev);
1954 } else {
1955 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 1956 time, data, ev);
b03d7d0f
WYG
1957 trace_iwlwifi_dev_ucode_event(priv, time,
1958 data, ev);
1959 }
b7a79404
RC
1960 }
1961 }
e5854471
BC
1962
1963 /* Allow device to power down */
1964 iwl_release_nic_access(priv);
1965 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1966 return pos;
b7a79404
RC
1967}
1968
c341ddb2
WYG
1969/**
1970 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1971 */
b03d7d0f
WYG
1972static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1973 u32 num_wraps, u32 next_entry,
1974 u32 size, u32 mode,
1975 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1976{
1977 /*
1978 * display the newest DEFAULT_LOG_ENTRIES entries
1979 * i.e the entries just before the next ont that uCode would fill.
1980 */
1981 if (num_wraps) {
1982 if (next_entry < size) {
b03d7d0f
WYG
1983 pos = iwl_print_event_log(priv,
1984 capacity - (size - next_entry),
1985 size - next_entry, mode,
1986 pos, buf, bufsz);
1987 pos = iwl_print_event_log(priv, 0,
1988 next_entry, mode,
1989 pos, buf, bufsz);
c341ddb2 1990 } else
b03d7d0f
WYG
1991 pos = iwl_print_event_log(priv, next_entry - size,
1992 size, mode, pos, buf, bufsz);
c341ddb2 1993 } else {
b03d7d0f
WYG
1994 if (next_entry < size) {
1995 pos = iwl_print_event_log(priv, 0, next_entry,
1996 mode, pos, buf, bufsz);
1997 } else {
1998 pos = iwl_print_event_log(priv, next_entry - size,
1999 size, mode, pos, buf, bufsz);
2000 }
c341ddb2 2001 }
b03d7d0f 2002 return pos;
c341ddb2
WYG
2003}
2004
c341ddb2
WYG
2005#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2006
b03d7d0f
WYG
2007int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2008 char **buf, bool display)
b7a79404
RC
2009{
2010 u32 base; /* SRAM byte address of event log header */
2011 u32 capacity; /* event log capacity in # entries */
2012 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2013 u32 num_wraps; /* # times uCode wrapped to top of log */
2014 u32 next_entry; /* index of next entry to be written by uCode */
2015 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
2016 int pos = 0;
2017 size_t bufsz = 0;
b7a79404
RC
2018
2019 if (priv->ucode_type == UCODE_INIT)
2020 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2021 else
2022 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2023
2024 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
2025 IWL_ERR(priv,
2026 "Invalid event log pointer 0x%08X for %s uCode\n",
2027 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2028 return -EINVAL;
b7a79404
RC
2029 }
2030
2031 /* event log header */
2032 capacity = iwl_read_targ_mem(priv, base);
2033 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2034 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2035 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2036
678b385d 2037 if (capacity > priv->cfg->max_event_log_size) {
84c40692 2038 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
678b385d
WYG
2039 capacity, priv->cfg->max_event_log_size);
2040 capacity = priv->cfg->max_event_log_size;
84c40692
BC
2041 }
2042
678b385d 2043 if (next_entry > priv->cfg->max_event_log_size) {
84c40692 2044 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
678b385d
WYG
2045 next_entry, priv->cfg->max_event_log_size);
2046 next_entry = priv->cfg->max_event_log_size;
84c40692
BC
2047 }
2048
b7a79404
RC
2049 size = num_wraps ? capacity : next_entry;
2050
2051 /* bail out if nothing in log */
2052 if (size == 0) {
2053 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2054 return pos;
b7a79404
RC
2055 }
2056
c341ddb2 2057#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2058 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
2059 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2060 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2061#else
2062 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2063 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2064#endif
2065 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2066 size);
b7a79404 2067
c341ddb2 2068#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
2069 if (display) {
2070 if (full_log)
2071 bufsz = capacity * 48;
2072 else
2073 bufsz = size * 48;
2074 *buf = kmalloc(bufsz, GFP_KERNEL);
2075 if (!*buf)
937c397e 2076 return -ENOMEM;
b03d7d0f 2077 }
c341ddb2
WYG
2078 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2079 /*
2080 * if uCode has wrapped back to top of log,
2081 * start at the oldest entry,
2082 * i.e the next one that uCode would fill.
2083 */
2084 if (num_wraps)
b03d7d0f
WYG
2085 pos = iwl_print_event_log(priv, next_entry,
2086 capacity - next_entry, mode,
2087 pos, buf, bufsz);
c341ddb2 2088 /* (then/else) start at top of log */
b03d7d0f
WYG
2089 pos = iwl_print_event_log(priv, 0,
2090 next_entry, mode, pos, buf, bufsz);
c341ddb2 2091 } else
b03d7d0f
WYG
2092 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2093 next_entry, size, mode,
2094 pos, buf, bufsz);
c341ddb2 2095#else
b03d7d0f
WYG
2096 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2097 next_entry, size, mode,
2098 pos, buf, bufsz);
b7a79404 2099#endif
b03d7d0f 2100 return pos;
c341ddb2 2101}
b7a79404 2102
b481de9c 2103/**
4a4a9e81 2104 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2105 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2106 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2107 */
4a4a9e81 2108static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2109{
57aab75a 2110 int ret = 0;
b481de9c 2111
e1623446 2112 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2113
2114 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2115 /* We had an error bringing up the hardware, so take it
2116 * all the way back down so we can try again */
e1623446 2117 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2118 goto restart;
2119 }
2120
2121 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2122 * This is a paranoid check, because we would not have gotten the
2123 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2124 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
2125 /* Runtime instruction load was bad;
2126 * take it all the way back down so we can try again */
e1623446 2127 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2128 goto restart;
2129 }
2130
57aab75a
TW
2131 ret = priv->cfg->ops->lib->alive_notify(priv);
2132 if (ret) {
39aadf8c
WT
2133 IWL_WARN(priv,
2134 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
2135 goto restart;
2136 }
2137
5b9f8cd3 2138 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
2139 set_bit(STATUS_ALIVE, &priv->status);
2140
b74e31a9
WYG
2141 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2142 /* Enable timer to monitor the driver queues */
2143 mod_timer(&priv->monitor_recover,
2144 jiffies +
2145 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2146 }
2147
fee1247a 2148 if (iwl_is_rfkill(priv))
b481de9c
ZY
2149 return;
2150
36d6825b 2151 ieee80211_wake_queues(priv->hw);
b481de9c 2152
470ab2dd 2153 priv->active_rate = IWL_RATES_MASK;
b481de9c 2154
2f748dec
WYG
2155 /* Configure Tx antenna selection based on H/W config */
2156 if (priv->cfg->ops->hcmd->set_tx_ant)
2157 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2158
3109ece1 2159 if (iwl_is_associated(priv)) {
c1adf9fb
GG
2160 struct iwl_rxon_cmd *active_rxon =
2161 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
2162 /* apply any changes in staging */
2163 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2164 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2165 } else {
2166 /* Initialize our rx_config data */
5b9f8cd3 2167 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
2168
2169 if (priv->cfg->ops->hcmd->set_rxon_chain)
2170 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2171
b481de9c
ZY
2172 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2173 }
2174
9fbab516 2175 /* Configure Bluetooth device coexistence support */
5b9f8cd3 2176 iwl_send_bt_config(priv);
b481de9c 2177
4a4a9e81
TW
2178 iwl_reset_run_time_calib(priv);
2179
b481de9c 2180 /* Configure the adapter for unassociated operation */
e0158e61 2181 iwlcore_commit_rxon(priv);
b481de9c
ZY
2182
2183 /* At this point, the NIC is initialized and operational */
47f4a587 2184 iwl_rf_kill_ct_config(priv);
5a66926a 2185
e932a609 2186 iwl_leds_init(priv);
fe00b5a5 2187
e1623446 2188 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2189 set_bit(STATUS_READY, &priv->status);
5a66926a 2190 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2191
e312c24c 2192 iwl_power_update_mode(priv, true);
7e246191
RC
2193 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2194
c46fbefa 2195
b481de9c
ZY
2196 return;
2197
2198 restart:
2199 queue_work(priv->workqueue, &priv->restart);
2200}
2201
4e39317d 2202static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2203
5b9f8cd3 2204static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2205{
2206 unsigned long flags;
2207 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2208
e1623446 2209 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2210
b481de9c
ZY
2211 if (!exit_pending)
2212 set_bit(STATUS_EXIT_PENDING, &priv->status);
2213
7e246191 2214 iwl_clear_ucode_stations(priv, true);
b481de9c
ZY
2215
2216 /* Unblock any waiting calls */
2217 wake_up_interruptible_all(&priv->wait_command_queue);
2218
b481de9c
ZY
2219 /* Wipe out the EXIT_PENDING status bit if we are not actually
2220 * exiting the module */
2221 if (!exit_pending)
2222 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2223
2224 /* stop and reset the on-board processor */
3395f6e9 2225 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2226
2227 /* tell the device to stop sending interrupts */
0359facc 2228 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2229 iwl_disable_interrupts(priv);
0359facc
MA
2230 spin_unlock_irqrestore(&priv->lock, flags);
2231 iwl_synchronize_irq(priv);
b481de9c
ZY
2232
2233 if (priv->mac80211_registered)
2234 ieee80211_stop_queues(priv->hw);
2235
5b9f8cd3 2236 /* If we have not previously called iwl_init() then
a60e77e5 2237 * clear all bits but the RF Kill bit and return */
fee1247a 2238 if (!iwl_is_init(priv)) {
b481de9c
ZY
2239 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2240 STATUS_RF_KILL_HW |
9788864e
RC
2241 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2242 STATUS_GEO_CONFIGURED |
052ec3f1
MA
2243 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2244 STATUS_EXIT_PENDING;
b481de9c
ZY
2245 goto exit;
2246 }
2247
6da3a13e 2248 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2249 * bit and continue taking the NIC down. */
b481de9c
ZY
2250 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2251 STATUS_RF_KILL_HW |
9788864e
RC
2252 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2253 STATUS_GEO_CONFIGURED |
b481de9c 2254 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
2255 STATUS_FW_ERROR |
2256 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2257 STATUS_EXIT_PENDING;
b481de9c 2258
ef850d7c
MA
2259 /* device going down, Stop using ICT table */
2260 iwl_disable_ict(priv);
b481de9c 2261
74bcdb33 2262 iwlagn_txq_ctx_stop(priv);
54b81550 2263 iwlagn_rxq_stop(priv);
b481de9c 2264
309e731a
BC
2265 /* Power-down device's busmaster DMA clocks */
2266 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2267 udelay(5);
2268
309e731a
BC
2269 /* Make sure (redundant) we've released our request to stay awake */
2270 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2271
4d2ccdb9
BC
2272 /* Stop the device, and put it in low power state */
2273 priv->cfg->ops->lib->apm_ops.stop(priv);
2274
b481de9c 2275 exit:
885ba202 2276 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2277
2278 if (priv->ibss_beacon)
2279 dev_kfree_skb(priv->ibss_beacon);
2280 priv->ibss_beacon = NULL;
2281
2282 /* clear out any free frames */
fcab423d 2283 iwl_clear_free_frames(priv);
b481de9c
ZY
2284}
2285
5b9f8cd3 2286static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2287{
2288 mutex_lock(&priv->mutex);
5b9f8cd3 2289 __iwl_down(priv);
b481de9c 2290 mutex_unlock(&priv->mutex);
b24d22b1 2291
4e39317d 2292 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2293}
2294
086ed117
MA
2295#define HW_READY_TIMEOUT (50)
2296
2297static int iwl_set_hw_ready(struct iwl_priv *priv)
2298{
2299 int ret = 0;
2300
2301 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2302 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2303
2304 /* See if we got it */
2305 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2306 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2307 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2308 HW_READY_TIMEOUT);
2309 if (ret != -ETIMEDOUT)
2310 priv->hw_ready = true;
2311 else
2312 priv->hw_ready = false;
2313
2314 IWL_DEBUG_INFO(priv, "hardware %s\n",
2315 (priv->hw_ready == 1) ? "ready" : "not ready");
2316 return ret;
2317}
2318
2319static int iwl_prepare_card_hw(struct iwl_priv *priv)
2320{
2321 int ret = 0;
2322
91dd6c27 2323 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2324
3354a0f6
MA
2325 ret = iwl_set_hw_ready(priv);
2326 if (priv->hw_ready)
2327 return ret;
2328
2329 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2330 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2331 CSR_HW_IF_CONFIG_REG_PREPARE);
2332
2333 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2334 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2335 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2336
3354a0f6 2337 /* HW should be ready by now, check again. */
086ed117
MA
2338 if (ret != -ETIMEDOUT)
2339 iwl_set_hw_ready(priv);
2340
2341 return ret;
2342}
2343
b481de9c
ZY
2344#define MAX_HW_RESTARTS 5
2345
5b9f8cd3 2346static int __iwl_up(struct iwl_priv *priv)
b481de9c 2347{
57aab75a
TW
2348 int i;
2349 int ret;
b481de9c
ZY
2350
2351 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2352 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2353 return -EIO;
2354 }
2355
e903fbd4 2356 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2357 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2358 return -EIO;
2359 }
2360
086ed117
MA
2361 iwl_prepare_card_hw(priv);
2362
2363 if (!priv->hw_ready) {
2364 IWL_WARN(priv, "Exit HW not ready\n");
2365 return -EIO;
2366 }
2367
e655b9f0 2368 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2369 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2370 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2371 else
e655b9f0 2372 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2373
c1842d61 2374 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2375 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2376
5b9f8cd3 2377 iwl_enable_interrupts(priv);
a60e77e5 2378 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2379 return 0;
b481de9c
ZY
2380 }
2381
3395f6e9 2382 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2383
74bcdb33 2384 ret = iwlagn_hw_nic_init(priv);
57aab75a 2385 if (ret) {
15b1687c 2386 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2387 return ret;
b481de9c
ZY
2388 }
2389
2390 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2391 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2392 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2393 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2394
2395 /* clear (again), then enable host interrupts */
3395f6e9 2396 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2397 iwl_enable_interrupts(priv);
b481de9c
ZY
2398
2399 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2400 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2401 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2402
2403 /* Copy original ucode data image from disk into backup cache.
2404 * This will be used to initialize the on-board processor's
2405 * data SRAM for a clean start when the runtime program first loads. */
2406 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2407 priv->ucode_data.len);
b481de9c 2408
b481de9c
ZY
2409 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2410
b481de9c
ZY
2411 /* load bootstrap state machine,
2412 * load bootstrap program into processor's memory,
2413 * prepare to load the "initialize" uCode */
57aab75a 2414 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2415
57aab75a 2416 if (ret) {
15b1687c
WT
2417 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2418 ret);
b481de9c
ZY
2419 continue;
2420 }
2421
2422 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2423 iwl_nic_start(priv);
b481de9c 2424
e1623446 2425 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2426
2427 return 0;
2428 }
2429
2430 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2431 __iwl_down(priv);
64e72c3e 2432 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2433
2434 /* tried to restart and config the device for as long as our
2435 * patience could withstand */
15b1687c 2436 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2437 return -EIO;
2438}
2439
2440
2441/*****************************************************************************
2442 *
2443 * Workqueue callbacks
2444 *
2445 *****************************************************************************/
2446
4a4a9e81 2447static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2448{
c79dd5b5
TW
2449 struct iwl_priv *priv =
2450 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2451
2452 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2453 return;
2454
2455 mutex_lock(&priv->mutex);
f3ccc08c 2456 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2457 mutex_unlock(&priv->mutex);
2458}
2459
4a4a9e81 2460static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2461{
c79dd5b5
TW
2462 struct iwl_priv *priv =
2463 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2464
2465 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2466 return;
2467
258c44a0
MA
2468 /* enable dram interrupt */
2469 iwl_reset_ict(priv);
2470
b481de9c 2471 mutex_lock(&priv->mutex);
4a4a9e81 2472 iwl_alive_start(priv);
b481de9c
ZY
2473 mutex_unlock(&priv->mutex);
2474}
2475
16e727e8
EG
2476static void iwl_bg_run_time_calib_work(struct work_struct *work)
2477{
2478 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2479 run_time_calib_work);
2480
2481 mutex_lock(&priv->mutex);
2482
2483 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2484 test_bit(STATUS_SCANNING, &priv->status)) {
2485 mutex_unlock(&priv->mutex);
2486 return;
2487 }
2488
2489 if (priv->start_calib) {
2490 iwl_chain_noise_calibration(priv, &priv->statistics);
2491
2492 iwl_sensitivity_calibration(priv, &priv->statistics);
2493 }
2494
2495 mutex_unlock(&priv->mutex);
2496 return;
2497}
2498
5b9f8cd3 2499static void iwl_bg_restart(struct work_struct *data)
b481de9c 2500{
c79dd5b5 2501 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2502
2503 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2504 return;
2505
19cc1087
JB
2506 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2507 mutex_lock(&priv->mutex);
2508 priv->vif = NULL;
2509 priv->is_open = 0;
2510 mutex_unlock(&priv->mutex);
2511 iwl_down(priv);
2512 ieee80211_restart_hw(priv->hw);
2513 } else {
2514 iwl_down(priv);
80676518
JB
2515
2516 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2517 return;
2518
2519 mutex_lock(&priv->mutex);
2520 __iwl_up(priv);
2521 mutex_unlock(&priv->mutex);
19cc1087 2522 }
b481de9c
ZY
2523}
2524
5b9f8cd3 2525static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2526{
c79dd5b5
TW
2527 struct iwl_priv *priv =
2528 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2529
2530 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2531 return;
2532
2533 mutex_lock(&priv->mutex);
54b81550 2534 iwlagn_rx_replenish(priv);
b481de9c
ZY
2535 mutex_unlock(&priv->mutex);
2536}
2537
7878a5a4
MA
2538#define IWL_DELAY_NEXT_SCAN (HZ*2)
2539
5bbe233b 2540void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2541{
b481de9c 2542 struct ieee80211_conf *conf = NULL;
857485c0 2543 int ret = 0;
b481de9c 2544
05c914fe 2545 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2546 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2547 return;
2548 }
2549
b481de9c
ZY
2550 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2551 return;
2552
b481de9c 2553
508e32e1 2554 if (!priv->vif || !priv->is_open)
948c171c 2555 return;
508e32e1 2556
2a421b91 2557 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2558
b481de9c
ZY
2559 conf = ieee80211_get_hw_conf(priv->hw);
2560
2561 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2562 iwlcore_commit_rxon(priv);
b481de9c 2563
3195c1f3 2564 iwl_setup_rxon_timing(priv);
857485c0 2565 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2566 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2567 if (ret)
39aadf8c 2568 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2569 "Attempting to continue.\n");
2570
2571 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2572
42eb7c64 2573 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2574
45823531
AK
2575 if (priv->cfg->ops->hcmd->set_rxon_chain)
2576 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2577
b481de9c
ZY
2578 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2579
e1623446 2580 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2581 priv->assoc_id, priv->beacon_int);
2582
2583 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2584 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2585 else
2586 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2587
2588 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2589 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2590 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2591 else
2592 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2593
05c914fe 2594 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2595 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2596
2597 }
2598
e0158e61 2599 iwlcore_commit_rxon(priv);
b481de9c 2600
fe6b23dd
RC
2601 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2602 priv->assoc_id, priv->active_rxon.bssid_addr);
2603
b481de9c 2604 switch (priv->iw_mode) {
05c914fe 2605 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2606 break;
2607
05c914fe 2608 case NL80211_IFTYPE_ADHOC:
b481de9c 2609
c46fbefa
AK
2610 /* assume default assoc id */
2611 priv->assoc_id = 1;
b481de9c 2612
fe6b23dd 2613 iwl_add_local_station(priv, priv->bssid, true);
5b9f8cd3 2614 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2615
2616 break;
2617
2618 default:
15b1687c 2619 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2620 __func__, priv->iw_mode);
b481de9c
ZY
2621 break;
2622 }
2623
04816448
GE
2624 /* the chain noise calibration will enabled PM upon completion
2625 * If chain noise has already been run, then we need to enable
2626 * power management here */
2627 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2628 iwl_power_update_mode(priv, false);
c90a74ba
EG
2629
2630 /* Enable Rx differential gain and sensitivity calibrations */
2631 iwl_chain_noise_reset(priv);
2632 priv->start_calib = 1;
2633
508e32e1
RC
2634}
2635
b481de9c
ZY
2636/*****************************************************************************
2637 *
2638 * mac80211 entry point functions
2639 *
2640 *****************************************************************************/
2641
154b25ce 2642#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2643
f0b6e2e8
RC
2644/*
2645 * Not a mac80211 entry point function, but it fits in with all the
2646 * other mac80211 functions grouped here.
2647 */
158bea07 2648static int iwl_mac_setup_register(struct iwl_priv *priv)
f0b6e2e8
RC
2649{
2650 int ret;
2651 struct ieee80211_hw *hw = priv->hw;
2652 hw->rate_control_algorithm = "iwl-agn-rs";
2653
2654 /* Tell mac80211 our characteristics */
2655 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2656 IEEE80211_HW_NOISE_DBM |
2657 IEEE80211_HW_AMPDU_AGGREGATION |
2658 IEEE80211_HW_SPECTRUM_MGMT;
2659
2660 if (!priv->cfg->broken_powersave)
2661 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2662 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2663
ba37a3d0
JB
2664 if (priv->cfg->sku & IWL_SKU_N)
2665 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2666 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2667
8d9698b3 2668 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2669 hw->wiphy->interface_modes =
2670 BIT(NL80211_IFTYPE_STATION) |
2671 BIT(NL80211_IFTYPE_ADHOC);
2672
f6c8f152 2673 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 2674 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC
2675
2676 /*
2677 * For now, disable PS by default because it affects
2678 * RX performance significantly.
2679 */
5be83de5 2680 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 2681
1382c71c 2682 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8
RC
2683 /* we create the 802.11 header and a zero-length SSID element */
2684 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2685
2686 /* Default value; 4 EDCA QOS priorities */
2687 hw->queues = 4;
2688
2689 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2690
2691 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2692 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2693 &priv->bands[IEEE80211_BAND_2GHZ];
2694 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2695 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2696 &priv->bands[IEEE80211_BAND_5GHZ];
2697
2698 ret = ieee80211_register_hw(priv->hw);
2699 if (ret) {
2700 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2701 return ret;
2702 }
2703 priv->mac80211_registered = 1;
2704
2705 return 0;
2706}
2707
2708
5b9f8cd3 2709static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2710{
c79dd5b5 2711 struct iwl_priv *priv = hw->priv;
5a66926a 2712 int ret;
b481de9c 2713
e1623446 2714 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2715
2716 /* we should be verifying the device is ready to be opened */
2717 mutex_lock(&priv->mutex);
5b9f8cd3 2718 ret = __iwl_up(priv);
b481de9c 2719 mutex_unlock(&priv->mutex);
5a66926a 2720
e655b9f0 2721 if (ret)
6cd0b1cb 2722 return ret;
e655b9f0 2723
c1842d61
TW
2724 if (iwl_is_rfkill(priv))
2725 goto out;
2726
e1623446 2727 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2728
fe9b6b72 2729 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2730 * mac80211 will not be run successfully. */
154b25ce
EG
2731 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2732 test_bit(STATUS_READY, &priv->status),
2733 UCODE_READY_TIMEOUT);
2734 if (!ret) {
2735 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2736 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2737 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2738 return -ETIMEDOUT;
5a66926a 2739 }
fe9b6b72 2740 }
0a078ffa 2741
e932a609
JB
2742 iwl_led_start(priv);
2743
c1842d61 2744out:
0a078ffa 2745 priv->is_open = 1;
e1623446 2746 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2747 return 0;
2748}
2749
5b9f8cd3 2750static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2751{
c79dd5b5 2752 struct iwl_priv *priv = hw->priv;
b481de9c 2753
e1623446 2754 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2755
19cc1087 2756 if (!priv->is_open)
e655b9f0 2757 return;
e655b9f0 2758
b481de9c 2759 priv->is_open = 0;
5a66926a 2760
5bddf549 2761 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2762 /* stop mac, cancel any scan request and clear
2763 * RXON_FILTER_ASSOC_MSK BIT
2764 */
5a66926a 2765 mutex_lock(&priv->mutex);
2a421b91 2766 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2767 mutex_unlock(&priv->mutex);
fde3571f
MA
2768 }
2769
5b9f8cd3 2770 iwl_down(priv);
5a66926a
ZY
2771
2772 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2773
2774 /* enable interrupts again in order to receive rfkill changes */
2775 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2776 iwl_enable_interrupts(priv);
948c171c 2777
e1623446 2778 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2779}
2780
5b9f8cd3 2781static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2782{
c79dd5b5 2783 struct iwl_priv *priv = hw->priv;
b481de9c 2784
e1623446 2785 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2786
e1623446 2787 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2788 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2789
74bcdb33 2790 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY
2791 dev_kfree_skb_any(skb);
2792
e1623446 2793 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2794 return NETDEV_TX_OK;
b481de9c
ZY
2795}
2796
60690a6a 2797void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2798{
857485c0 2799 int ret = 0;
b481de9c 2800
d986bcd1 2801 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2802 return;
2803
2804 /* The following should be done only at AP bring up */
3195c1f3 2805 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2806
2807 /* RXON - unassoc (to set timing command) */
2808 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2809 iwlcore_commit_rxon(priv);
b481de9c
ZY
2810
2811 /* RXON Timing */
3195c1f3 2812 iwl_setup_rxon_timing(priv);
857485c0 2813 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2814 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2815 if (ret)
39aadf8c 2816 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2817 "Attempting to continue.\n");
2818
f513dfff
DH
2819 /* AP has all antennas */
2820 priv->chain_noise_data.active_chains =
2821 priv->hw_params.valid_rx_ant;
2822 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK
2823 if (priv->cfg->ops->hcmd->set_rxon_chain)
2824 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2825
2826 /* FIXME: what should be the assoc_id for AP? */
2827 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2828 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2829 priv->staging_rxon.flags |=
2830 RXON_FLG_SHORT_PREAMBLE_MSK;
2831 else
2832 priv->staging_rxon.flags &=
2833 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2834
2835 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2836 if (priv->assoc_capability &
2837 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2838 priv->staging_rxon.flags |=
2839 RXON_FLG_SHORT_SLOT_MSK;
2840 else
2841 priv->staging_rxon.flags &=
2842 ~RXON_FLG_SHORT_SLOT_MSK;
2843
05c914fe 2844 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2845 priv->staging_rxon.flags &=
2846 ~RXON_FLG_SHORT_SLOT_MSK;
2847 }
2848 /* restore RXON assoc */
2849 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2850 iwlcore_commit_rxon(priv);
9a9ca65f 2851 iwl_add_bcast_station(priv);
e1493deb 2852 }
5b9f8cd3 2853 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2854
2855 /* FIXME - we need to add code here to detect a totally new
2856 * configuration, reset the AP, unassoc, rxon timing, assoc,
2857 * clear sta table, add BCAST sta... */
2858}
2859
5b9f8cd3 2860static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB
2861 struct ieee80211_vif *vif,
2862 struct ieee80211_key_conf *keyconf,
2863 struct ieee80211_sta *sta,
2864 u32 iv32, u16 *phase1key)
ab885f8c 2865{
ab885f8c 2866
9f58671e 2867 struct iwl_priv *priv = hw->priv;
e1623446 2868 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2869
b3fbdcf4
JB
2870 iwl_update_tkip_key(priv, keyconf,
2871 sta ? sta->addr : iwl_bcast_addr,
2872 iv32, phase1key);
ab885f8c 2873
e1623446 2874 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2875}
2876
5b9f8cd3 2877static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2878 struct ieee80211_vif *vif,
2879 struct ieee80211_sta *sta,
b481de9c
ZY
2880 struct ieee80211_key_conf *key)
2881{
c79dd5b5 2882 struct iwl_priv *priv = hw->priv;
42986796
WT
2883 const u8 *addr;
2884 int ret;
2885 u8 sta_id;
2886 bool is_default_wep_key = false;
b481de9c 2887
e1623446 2888 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2889
90e8e424 2890 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2891 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2892 return -EOPNOTSUPP;
2893 }
42986796 2894 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2895 sta_id = iwl_find_station(priv, addr);
6974e363 2896 if (sta_id == IWL_INVALID_STATION) {
e1623446 2897 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2898 addr);
6974e363 2899 return -EINVAL;
b481de9c 2900
deb09c43 2901 }
b481de9c 2902
6974e363 2903 mutex_lock(&priv->mutex);
2a421b91 2904 iwl_scan_cancel_timeout(priv, 100);
6974e363 2905
a90178fa
JB
2906 /*
2907 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG
2908 * so far, we are in legacy wep mode (group key only), otherwise we are
2909 * in 1X mode.
a90178fa
JB
2910 * In legacy wep mode, we use another host command to the uCode.
2911 */
2912 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
6974e363
EG
2913 if (cmd == SET_KEY)
2914 is_default_wep_key = !priv->key_mapping_key;
2915 else
ccc038ab
EG
2916 is_default_wep_key =
2917 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2918 }
052c4b9f 2919
b481de9c 2920 switch (cmd) {
deb09c43 2921 case SET_KEY:
6974e363
EG
2922 if (is_default_wep_key)
2923 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2924 else
7480513f 2925 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2926
e1623446 2927 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2928 break;
2929 case DISABLE_KEY:
6974e363
EG
2930 if (is_default_wep_key)
2931 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2932 else
3ec47732 2933 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2934
e1623446 2935 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2936 break;
2937 default:
deb09c43 2938 ret = -EINVAL;
b481de9c
ZY
2939 }
2940
72e15d71 2941 mutex_unlock(&priv->mutex);
e1623446 2942 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2943
deb09c43 2944 return ret;
b481de9c
ZY
2945}
2946
5b9f8cd3 2947static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2948 struct ieee80211_vif *vif,
d783b061 2949 enum ieee80211_ampdu_mlme_action action,
17741cdc 2950 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2951{
2952 struct iwl_priv *priv = hw->priv;
5c2207c6 2953 int ret;
d783b061 2954
e1623446 2955 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2956 sta->addr, tid);
d783b061
TW
2957
2958 if (!(priv->cfg->sku & IWL_SKU_N))
2959 return -EACCES;
2960
2961 switch (action) {
2962 case IEEE80211_AMPDU_RX_START:
e1623446 2963 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2964 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2965 case IEEE80211_AMPDU_RX_STOP:
e1623446 2966 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2967 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2968 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2969 return 0;
2970 else
2971 return ret;
d783b061 2972 case IEEE80211_AMPDU_TX_START:
e1623446 2973 IWL_DEBUG_HT(priv, "start Tx\n");
74bcdb33 2974 ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn);
d5a0ffa3
WYG
2975 if (ret == 0) {
2976 priv->_agn.agg_tids_count++;
2977 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2978 priv->_agn.agg_tids_count);
2979 }
2980 return ret;
d783b061 2981 case IEEE80211_AMPDU_TX_STOP:
e1623446 2982 IWL_DEBUG_HT(priv, "stop Tx\n");
74bcdb33 2983 ret = iwlagn_tx_agg_stop(priv, sta->addr, tid);
d5a0ffa3
WYG
2984 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2985 priv->_agn.agg_tids_count--;
2986 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2987 priv->_agn.agg_tids_count);
2988 }
5c2207c6
WYG
2989 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2990 return 0;
2991 else
2992 return ret;
f0527971
WYG
2993 case IEEE80211_AMPDU_TX_OPERATIONAL:
2994 /* do nothing */
2995 return -EOPNOTSUPP;
d783b061 2996 default:
e1623446 2997 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2998 return -EINVAL;
2999 break;
3000 }
3001 return 0;
3002}
9f58671e 3003
5b9f8cd3 3004static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
3005 struct ieee80211_low_level_stats *stats)
3006{
bf403db8
EK
3007 struct iwl_priv *priv = hw->priv;
3008
3009 priv = hw->priv;
e1623446
TW
3010 IWL_DEBUG_MAC80211(priv, "enter\n");
3011 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3012
3013 return 0;
3014}
3015
6ab10ff8
JB
3016static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3017 struct ieee80211_vif *vif,
3018 enum sta_notify_cmd cmd,
3019 struct ieee80211_sta *sta)
3020{
3021 struct iwl_priv *priv = hw->priv;
3022 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3023 int sta_id;
3024
6ab10ff8 3025 switch (cmd) {
6ab10ff8
JB
3026 case STA_NOTIFY_SLEEP:
3027 WARN_ON(!sta_priv->client);
3028 sta_priv->asleep = true;
3029 if (atomic_read(&sta_priv->pending_frames) > 0)
3030 ieee80211_sta_block_awake(hw, sta, true);
3031 break;
3032 case STA_NOTIFY_AWAKE:
3033 WARN_ON(!sta_priv->client);
49dcc819
DH
3034 if (!sta_priv->asleep)
3035 break;
6ab10ff8
JB
3036 sta_priv->asleep = false;
3037 sta_id = iwl_find_station(priv, sta->addr);
3038 if (sta_id != IWL_INVALID_STATION)
3039 iwl_sta_modify_ps_wake(priv, sta_id);
3040 break;
3041 default:
3042 break;
3043 }
3044}
3045
fe6b23dd
RC
3046static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3047 struct ieee80211_vif *vif,
3048 struct ieee80211_sta *sta)
3049{
3050 struct iwl_priv *priv = hw->priv;
3051 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3052 bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
3053 int ret;
3054 u8 sta_id;
3055
3056 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3057 sta->addr);
3058
3059 atomic_set(&sta_priv->pending_frames, 0);
3060 if (vif->type == NL80211_IFTYPE_AP)
3061 sta_priv->client = true;
3062
3063 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3064 &sta_id);
3065 if (ret) {
3066 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3067 sta->addr, ret);
3068 /* Should we return success if return code is EEXIST ? */
3069 return ret;
3070 }
3071
fe6b23dd 3072 /* Initialize rate scaling */
91dd6c27 3073 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC
3074 sta->addr);
3075 iwl_rs_rate_init(priv, sta, sta_id);
3076
3077 return ret;
3078}
3079
b481de9c
ZY
3080/*****************************************************************************
3081 *
3082 * sysfs attributes
3083 *
3084 *****************************************************************************/
3085
0a6857e7 3086#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3087
3088/*
3089 * The following adds a new attribute to the sysfs representation
c3a739fa 3090 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
3091 * used for controlling the debug level.
3092 *
3093 * See the level definitions in iwl for details.
a562a9dd 3094 *
3d816c77
RC
3095 * The debug_level being managed using sysfs below is a per device debug
3096 * level that is used instead of the global debug level if it (the per
3097 * device debug level) is set.
b481de9c 3098 */
8cf769c6
EK
3099static ssize_t show_debug_level(struct device *d,
3100 struct device_attribute *attr, char *buf)
b481de9c 3101{
3d816c77
RC
3102 struct iwl_priv *priv = dev_get_drvdata(d);
3103 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3104}
8cf769c6
EK
3105static ssize_t store_debug_level(struct device *d,
3106 struct device_attribute *attr,
b481de9c
ZY
3107 const char *buf, size_t count)
3108{
928841b1 3109 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3110 unsigned long val;
3111 int ret;
b481de9c 3112
9257746f
TW
3113 ret = strict_strtoul(buf, 0, &val);
3114 if (ret)
978785a3 3115 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3116 else {
3d816c77 3117 priv->debug_level = val;
20594eb0
WYG
3118 if (iwl_alloc_traffic_mem(priv))
3119 IWL_ERR(priv,
3120 "Not enough memory to generate traffic log\n");
3121 }
b481de9c
ZY
3122 return strnlen(buf, count);
3123}
3124
8cf769c6
EK
3125static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3126 show_debug_level, store_debug_level);
3127
b481de9c 3128
0a6857e7 3129#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3130
b481de9c
ZY
3131
3132static ssize_t show_temperature(struct device *d,
3133 struct device_attribute *attr, char *buf)
3134{
928841b1 3135 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3136
fee1247a 3137 if (!iwl_is_alive(priv))
b481de9c
ZY
3138 return -EAGAIN;
3139
91dbc5bd 3140 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
3141}
3142
3143static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3144
b481de9c
ZY
3145static ssize_t show_tx_power(struct device *d,
3146 struct device_attribute *attr, char *buf)
3147{
928841b1 3148 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
3149
3150 if (!iwl_is_ready_rf(priv))
3151 return sprintf(buf, "off\n");
3152 else
3153 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3154}
3155
3156static ssize_t store_tx_power(struct device *d,
3157 struct device_attribute *attr,
3158 const char *buf, size_t count)
3159{
928841b1 3160 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
3161 unsigned long val;
3162 int ret;
b481de9c 3163
9257746f
TW
3164 ret = strict_strtoul(buf, 10, &val);
3165 if (ret)
978785a3 3166 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
3167 else {
3168 ret = iwl_set_tx_power(priv, val, false);
3169 if (ret)
3170 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3171 ret);
3172 else
3173 ret = count;
3174 }
3175 return ret;
b481de9c
ZY
3176}
3177
3178static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3179
01abfbb2
WYG
3180static ssize_t show_rts_ht_protection(struct device *d,
3181 struct device_attribute *attr, char *buf)
3182{
3183 struct iwl_priv *priv = dev_get_drvdata(d);
3184
3185 return sprintf(buf, "%s\n",
3186 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3187}
3188
3189static ssize_t store_rts_ht_protection(struct device *d,
3190 struct device_attribute *attr,
3191 const char *buf, size_t count)
3192{
3193 struct iwl_priv *priv = dev_get_drvdata(d);
3194 unsigned long val;
3195 int ret;
3196
3197 ret = strict_strtoul(buf, 10, &val);
3198 if (ret)
3199 IWL_INFO(priv, "Input is not in decimal form.\n");
3200 else {
3201 if (!iwl_is_associated(priv))
3202 priv->cfg->use_rts_for_ht = val ? true : false;
3203 else
3204 IWL_ERR(priv, "Sta associated with AP - "
3205 "Change protection mechanism is not allowed\n");
3206 ret = count;
3207 }
3208 return ret;
3209}
3210
3211static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3212 show_rts_ht_protection, store_rts_ht_protection);
3213
b481de9c 3214
b481de9c
ZY
3215/*****************************************************************************
3216 *
3217 * driver setup and teardown
3218 *
3219 *****************************************************************************/
3220
4e39317d 3221static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3222{
d21050c7 3223 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3224
3225 init_waitqueue_head(&priv->wait_command_queue);
3226
5b9f8cd3
EG
3227 INIT_WORK(&priv->restart, iwl_bg_restart);
3228 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3229 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3230 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
3231 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3232 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3233
2a421b91 3234 iwl_setup_scan_deferred_work(priv);
bb8c093b 3235
4e39317d
EG
3236 if (priv->cfg->ops->lib->setup_deferred_work)
3237 priv->cfg->ops->lib->setup_deferred_work(priv);
3238
3239 init_timer(&priv->statistics_periodic);
3240 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3241 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3242
a9e1cb6a
WYG
3243 init_timer(&priv->ucode_trace);
3244 priv->ucode_trace.data = (unsigned long)priv;
3245 priv->ucode_trace.function = iwl_bg_ucode_trace;
3246
b74e31a9
WYG
3247 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3248 init_timer(&priv->monitor_recover);
3249 priv->monitor_recover.data = (unsigned long)priv;
3250 priv->monitor_recover.function =
3251 priv->cfg->ops->lib->recover_from_tx_stall;
3252 }
3253
ef850d7c
MA
3254 if (!priv->cfg->use_isr_legacy)
3255 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3256 iwl_irq_tasklet, (unsigned long)priv);
3257 else
3258 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3259 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
3260}
3261
4e39317d 3262static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3263{
4e39317d
EG
3264 if (priv->cfg->ops->lib->cancel_deferred_work)
3265 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3266
3ae6a054 3267 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3268 cancel_delayed_work(&priv->scan_check);
88be0264 3269 cancel_work_sync(&priv->start_internal_scan);
b481de9c 3270 cancel_delayed_work(&priv->alive_start);
b481de9c 3271 cancel_work_sync(&priv->beacon_update);
4e39317d 3272 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3273 del_timer_sync(&priv->ucode_trace);
b74e31a9
WYG
3274 if (priv->cfg->ops->lib->recover_from_tx_stall)
3275 del_timer_sync(&priv->monitor_recover);
b481de9c
ZY
3276}
3277
89f186a8
RC
3278static void iwl_init_hw_rates(struct iwl_priv *priv,
3279 struct ieee80211_rate *rates)
3280{
3281 int i;
3282
3283 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3284 rates[i].bitrate = iwl_rates[i].ieee * 5;
3285 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3286 rates[i].hw_value_short = i;
3287 rates[i].flags = 0;
3288 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3289 /*
3290 * If CCK != 1M then set short preamble rate flag.
3291 */
3292 rates[i].flags |=
3293 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3294 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3295 }
3296 }
3297}
3298
3299static int iwl_init_drv(struct iwl_priv *priv)
3300{
3301 int ret;
3302
3303 priv->ibss_beacon = NULL;
3304
89f186a8
RC
3305 spin_lock_init(&priv->sta_lock);
3306 spin_lock_init(&priv->hcmd_lock);
3307
3308 INIT_LIST_HEAD(&priv->free_frames);
3309
3310 mutex_init(&priv->mutex);
d2dfe6df 3311 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3312
89f186a8
RC
3313 priv->ieee_channels = NULL;
3314 priv->ieee_rates = NULL;
3315 priv->band = IEEE80211_BAND_2GHZ;
3316
3317 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3318 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3319 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3320 priv->_agn.agg_tids_count = 0;
89f186a8 3321
8a472da4
WYG
3322 /* initialize force reset */
3323 priv->force_reset[IWL_RF_RESET].reset_duration =
3324 IWL_DELAY_NEXT_FORCE_RF_RESET;
3325 priv->force_reset[IWL_FW_RESET].reset_duration =
3326 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC
3327
3328 /* Choose which receivers/antennas to use */
3329 if (priv->cfg->ops->hcmd->set_rxon_chain)
3330 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3331
3332 iwl_init_scan_params(priv);
3333
89f186a8
RC
3334 /* Set the tx_power_user_lmt to the lowest power level
3335 * this value will get overwritten by channel max power avg
3336 * from eeprom */
b744cb79 3337 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC
3338
3339 ret = iwl_init_channel_map(priv);
3340 if (ret) {
3341 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3342 goto err;
3343 }
3344
3345 ret = iwlcore_init_geos(priv);
3346 if (ret) {
3347 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3348 goto err_free_channel_map;
3349 }
3350 iwl_init_hw_rates(priv, priv->ieee_rates);
3351
3352 return 0;
3353
3354err_free_channel_map:
3355 iwl_free_channel_map(priv);
3356err:
3357 return ret;
3358}
3359
3360static void iwl_uninit_drv(struct iwl_priv *priv)
3361{
3362 iwl_calib_free_results(priv);
3363 iwlcore_free_geos(priv);
3364 iwl_free_channel_map(priv);
811ecc99 3365 kfree(priv->scan_cmd);
89f186a8
RC
3366}
3367
5b9f8cd3 3368static struct attribute *iwl_sysfs_entries[] = {
b481de9c 3369 &dev_attr_temperature.attr,
b481de9c 3370 &dev_attr_tx_power.attr,
01abfbb2 3371 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3372#ifdef CONFIG_IWLWIFI_DEBUG
3373 &dev_attr_debug_level.attr,
3374#endif
b481de9c
ZY
3375 NULL
3376};
3377
5b9f8cd3 3378static struct attribute_group iwl_attribute_group = {
b481de9c 3379 .name = NULL, /* put in device directory */
5b9f8cd3 3380 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3381};
3382
5b9f8cd3
EG
3383static struct ieee80211_ops iwl_hw_ops = {
3384 .tx = iwl_mac_tx,
3385 .start = iwl_mac_start,
3386 .stop = iwl_mac_stop,
3387 .add_interface = iwl_mac_add_interface,
3388 .remove_interface = iwl_mac_remove_interface,
3389 .config = iwl_mac_config,
5b9f8cd3
EG
3390 .configure_filter = iwl_configure_filter,
3391 .set_key = iwl_mac_set_key,
3392 .update_tkip_key = iwl_mac_update_tkip_key,
3393 .get_stats = iwl_mac_get_stats,
5b9f8cd3
EG
3394 .conf_tx = iwl_mac_conf_tx,
3395 .reset_tsf = iwl_mac_reset_tsf,
3396 .bss_info_changed = iwl_bss_info_changed,
3397 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB
3398 .hw_scan = iwl_mac_hw_scan,
3399 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC
3400 .sta_add = iwlagn_mac_sta_add,
3401 .sta_remove = iwl_mac_sta_remove,
b481de9c
ZY
3402};
3403
5b9f8cd3 3404static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3405{
3406 int err = 0;
c79dd5b5 3407 struct iwl_priv *priv;
b481de9c 3408 struct ieee80211_hw *hw;
82b9a121 3409 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3410 unsigned long flags;
6cd0b1cb 3411 u16 pci_cmd;
b481de9c 3412
316c30d9
AK
3413 /************************
3414 * 1. Allocating HW data
3415 ************************/
3416
6440adb5
CB
3417 /* Disabling hardware scan means that mac80211 will perform scans
3418 * "the hard way", rather than using device's scan. */
1ea87396 3419 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3420 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3421 dev_printk(KERN_DEBUG, &(pdev->dev),
3422 "Disabling hw_scan\n");
5b9f8cd3 3423 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3424 }
3425
5b9f8cd3 3426 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3427 if (!hw) {
b481de9c
ZY
3428 err = -ENOMEM;
3429 goto out;
3430 }
1d0a082d
AK
3431 priv = hw->priv;
3432 /* At this point both hw and priv are allocated. */
3433
b481de9c
ZY
3434 SET_IEEE80211_DEV(hw, &pdev->dev);
3435
e1623446 3436 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3437 priv->cfg = cfg;
b481de9c 3438 priv->pci_dev = pdev;
40cefda9 3439 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3440
0a6857e7 3441#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3442 atomic_set(&priv->restrict_refcnt, 0);
3443#endif
20594eb0
WYG
3444 if (iwl_alloc_traffic_mem(priv))
3445 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3446
316c30d9
AK
3447 /**************************
3448 * 2. Initializing PCI bus
3449 **************************/
3450 if (pci_enable_device(pdev)) {
3451 err = -ENODEV;
3452 goto out_ieee80211_free_hw;
3453 }
3454
3455 pci_set_master(pdev);
3456
093d874c 3457 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3458 if (!err)
093d874c 3459 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3460 if (err) {
093d874c 3461 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3462 if (!err)
093d874c 3463 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3464 /* both attempts failed: */
316c30d9 3465 if (err) {
978785a3 3466 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3467 goto out_pci_disable_device;
cc2a8ea8 3468 }
316c30d9
AK
3469 }
3470
3471 err = pci_request_regions(pdev, DRV_NAME);
3472 if (err)
3473 goto out_pci_disable_device;
3474
3475 pci_set_drvdata(pdev, priv);
3476
316c30d9
AK
3477
3478 /***********************
3479 * 3. Read REV register
3480 ***********************/
3481 priv->hw_base = pci_iomap(pdev, 0, 0);
3482 if (!priv->hw_base) {
3483 err = -ENODEV;
3484 goto out_pci_release_regions;
3485 }
3486
e1623446 3487 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3488 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3489 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3490
731a29b7 3491 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
3492 * we should init now
3493 */
3494 spin_lock_init(&priv->reg_lock);
731a29b7 3495 spin_lock_init(&priv->lock);
4843b5a7
RC
3496
3497 /*
3498 * stop and reset the on-board processor just in case it is in a
3499 * strange state ... like being left stranded by a primary kernel
3500 * and this is now the kdump kernel trying to start up
3501 */
3502 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3503
b661c819 3504 iwl_hw_detect(priv);
c11362c0 3505 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 3506 priv->cfg->name, priv->hw_rev);
316c30d9 3507
e7b63581
TW
3508 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3509 * PCI Tx retries from interfering with C3 CPU state */
3510 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3511
086ed117
MA
3512 iwl_prepare_card_hw(priv);
3513 if (!priv->hw_ready) {
3514 IWL_WARN(priv, "Failed, HW not ready\n");
3515 goto out_iounmap;
3516 }
3517
91238714
TW
3518 /*****************
3519 * 4. Read EEPROM
3520 *****************/
316c30d9
AK
3521 /* Read the EEPROM */
3522 err = iwl_eeprom_init(priv);
3523 if (err) {
15b1687c 3524 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3525 goto out_iounmap;
3526 }
8614f360
TW
3527 err = iwl_eeprom_check_version(priv);
3528 if (err)
c8f16138 3529 goto out_free_eeprom;
8614f360 3530
02883017 3531 /* extract MAC Address */
316c30d9 3532 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3533 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3534 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3535
3536 /************************
3537 * 5. Setup HW constants
3538 ************************/
da154e30 3539 if (iwl_set_hw_params(priv)) {
15b1687c 3540 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3541 goto out_free_eeprom;
316c30d9
AK
3542 }
3543
3544 /*******************
6ba87956 3545 * 6. Setup priv
316c30d9 3546 *******************/
b481de9c 3547
6ba87956 3548 err = iwl_init_drv(priv);
bf85ea4f 3549 if (err)
399f4900 3550 goto out_free_eeprom;
bf85ea4f 3551 /* At this point both hw and priv are initialized. */
316c30d9 3552
316c30d9 3553 /********************
09f9bf79 3554 * 7. Setup services
316c30d9 3555 ********************/
0359facc 3556 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3557 iwl_disable_interrupts(priv);
0359facc 3558 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3559
6cd0b1cb
HS
3560 pci_enable_msi(priv->pci_dev);
3561
ef850d7c
MA
3562 iwl_alloc_isr_ict(priv);
3563 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3564 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3565 if (err) {
3566 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3567 goto out_disable_msi;
3568 }
5b9f8cd3 3569 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3570 if (err) {
15b1687c 3571 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3572 goto out_free_irq;
316c30d9
AK
3573 }
3574
4e39317d 3575 iwl_setup_deferred_work(priv);
653fa4a0 3576 iwl_setup_rx_handlers(priv);
316c30d9 3577
158bea07
JB
3578 /*********************************************
3579 * 8. Enable interrupts and read RFKILL state
3580 *********************************************/
6ba87956 3581
6cd0b1cb
HS
3582 /* enable interrupts if needed: hw bug w/a */
3583 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3584 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3585 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3586 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3587 }
3588
3589 iwl_enable_interrupts(priv);
3590
6cd0b1cb
HS
3591 /* If platform's RF_KILL switch is NOT set to KILL */
3592 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3593 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3594 else
3595 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3596
a60e77e5
JB
3597 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3598 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3599
58d0f361 3600 iwl_power_initialize(priv);
39b73fb1 3601 iwl_tt_initialize(priv);
158bea07 3602
b08dfd04 3603 err = iwl_request_firmware(priv, true);
158bea07
JB
3604 if (err)
3605 goto out_remove_sysfs;
3606
b481de9c
ZY
3607 return 0;
3608
316c30d9 3609 out_remove_sysfs:
c8f16138
RC
3610 destroy_workqueue(priv->workqueue);
3611 priv->workqueue = NULL;
5b9f8cd3 3612 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3613 out_free_irq:
3614 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3615 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3616 out_disable_msi:
3617 pci_disable_msi(priv->pci_dev);
6ba87956 3618 iwl_uninit_drv(priv);
073d3f5f
TW
3619 out_free_eeprom:
3620 iwl_eeprom_free(priv);
b481de9c
ZY
3621 out_iounmap:
3622 pci_iounmap(pdev, priv->hw_base);
3623 out_pci_release_regions:
316c30d9 3624 pci_set_drvdata(pdev, NULL);
623d563e 3625 pci_release_regions(pdev);
b481de9c
ZY
3626 out_pci_disable_device:
3627 pci_disable_device(pdev);
b481de9c 3628 out_ieee80211_free_hw:
20594eb0 3629 iwl_free_traffic_mem(priv);
d7c76f4c 3630 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3631 out:
3632 return err;
3633}
3634
5b9f8cd3 3635static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3636{
c79dd5b5 3637 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3638 unsigned long flags;
b481de9c
ZY
3639
3640 if (!priv)
3641 return;
3642
e1623446 3643 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3644
67249625 3645 iwl_dbgfs_unregister(priv);
5b9f8cd3 3646 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3647
5b9f8cd3
EG
3648 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3649 * to be called and iwl_down since we are removing the device
0b124c31
GG
3650 * we need to set STATUS_EXIT_PENDING bit.
3651 */
3652 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3653 if (priv->mac80211_registered) {
3654 ieee80211_unregister_hw(priv->hw);
3655 priv->mac80211_registered = 0;
0b124c31 3656 } else {
5b9f8cd3 3657 iwl_down(priv);
c4f55232
RR
3658 }
3659
c166b25a
BC
3660 /*
3661 * Make sure device is reset to low power before unloading driver.
3662 * This may be redundant with iwl_down(), but there are paths to
3663 * run iwl_down() without calling apm_ops.stop(), and there are
3664 * paths to avoid running iwl_down() at all before leaving driver.
3665 * This (inexpensive) call *makes sure* device is reset.
3666 */
3667 priv->cfg->ops->lib->apm_ops.stop(priv);
3668
39b73fb1
WYG
3669 iwl_tt_exit(priv);
3670
0359facc
MA
3671 /* make sure we flush any pending irq or
3672 * tasklet for the driver
3673 */
3674 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3675 iwl_disable_interrupts(priv);
0359facc
MA
3676 spin_unlock_irqrestore(&priv->lock, flags);
3677
3678 iwl_synchronize_irq(priv);
3679
5b9f8cd3 3680 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3681
3682 if (priv->rxq.bd)
54b81550 3683 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 3684 iwlagn_hw_txq_ctx_free(priv);
b481de9c 3685
073d3f5f 3686 iwl_eeprom_free(priv);
b481de9c 3687
b481de9c 3688
948c171c
MA
3689 /*netif_stop_queue(dev); */
3690 flush_workqueue(priv->workqueue);
3691
5b9f8cd3 3692 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3693 * priv->workqueue... so we can't take down the workqueue
3694 * until now... */
3695 destroy_workqueue(priv->workqueue);
3696 priv->workqueue = NULL;
20594eb0 3697 iwl_free_traffic_mem(priv);
b481de9c 3698
6cd0b1cb
HS
3699 free_irq(priv->pci_dev->irq, priv);
3700 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3701 pci_iounmap(pdev, priv->hw_base);
3702 pci_release_regions(pdev);
3703 pci_disable_device(pdev);
3704 pci_set_drvdata(pdev, NULL);
3705
6ba87956 3706 iwl_uninit_drv(priv);
b481de9c 3707
ef850d7c
MA
3708 iwl_free_isr_ict(priv);
3709
b481de9c
ZY
3710 if (priv->ibss_beacon)
3711 dev_kfree_skb(priv->ibss_beacon);
3712
3713 ieee80211_free_hw(priv->hw);
3714}
3715
b481de9c
ZY
3716
3717/*****************************************************************************
3718 *
3719 * driver and module entry point
3720 *
3721 *****************************************************************************/
3722
fed9017e 3723/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 3724static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 3725#ifdef CONFIG_IWL4965
fed9017e
RR
3726 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3727 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3728#endif /* CONFIG_IWL4965 */
5a6a256e 3729#ifdef CONFIG_IWL5000
ac592574
WYG
3730/* 5100 Series WiFi */
3731 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3732 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3733 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3734 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3735 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3736 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3737 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3738 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3739 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3740 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3741 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3742 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3743 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3744 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3745 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3746 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3747 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3748 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3749 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3750 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3751 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3752 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3753 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3754 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3755
3756/* 5300 Series WiFi */
3757 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3758 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3759 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3760 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3761 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3762 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3763 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3764 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3765 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3766 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3767 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3768 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3769
3770/* 5350 Series WiFi/WiMax */
3771 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3772 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3773 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3774
3775/* 5150 Series Wifi/WiMax */
3776 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3777 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3778 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3779 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3780 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3781 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3782
3783 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3784 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3785 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3786 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG
3787
3788/* 6x00 Series */
5953a62e
WYG
3789 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3790 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3791 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3792 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3793 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3794 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3795 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3796 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3797 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3798 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062
SZ
3799
3800/* 6x00 Series Gen2 */
33e6f816
WYG
3801 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2_2agn_cfg)},
3802 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2_2agn_cfg)},
3803 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2_2agn_cfg)},
3804 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2_2agn_cfg)},
5953a62e
WYG
3805
3806/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3807 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3808 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3809 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3810 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3811 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3812 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3813
77dcb6a9 3814/* 1000 Series WiFi */
4bd0914f
WYG
3815 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3816 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3817 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3818 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3819 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3820 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3821 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3822 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3823 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3824 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3825 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3826 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3827#endif /* CONFIG_IWL5000 */
7100e924 3828
fed9017e
RR
3829 {0}
3830};
3831MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3832
3833static struct pci_driver iwl_driver = {
b481de9c 3834 .name = DRV_NAME,
fed9017e 3835 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3836 .probe = iwl_pci_probe,
3837 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3838#ifdef CONFIG_PM
5b9f8cd3
EG
3839 .suspend = iwl_pci_suspend,
3840 .resume = iwl_pci_resume,
b481de9c
ZY
3841#endif
3842};
3843
5b9f8cd3 3844static int __init iwl_init(void)
b481de9c
ZY
3845{
3846
3847 int ret;
3848 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3849 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3850
e227ceac 3851 ret = iwlagn_rate_control_register();
897e1cf2 3852 if (ret) {
a3139c59
SO
3853 printk(KERN_ERR DRV_NAME
3854 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3855 return ret;
3856 }
3857
fed9017e 3858 ret = pci_register_driver(&iwl_driver);
b481de9c 3859 if (ret) {
a3139c59 3860 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3861 goto error_register;
b481de9c 3862 }
b481de9c
ZY
3863
3864 return ret;
897e1cf2 3865
897e1cf2 3866error_register:
e227ceac 3867 iwlagn_rate_control_unregister();
897e1cf2 3868 return ret;
b481de9c
ZY
3869}
3870
5b9f8cd3 3871static void __exit iwl_exit(void)
b481de9c 3872{
fed9017e 3873 pci_unregister_driver(&iwl_driver);
e227ceac 3874 iwlagn_rate_control_unregister();
b481de9c
ZY
3875}
3876
5b9f8cd3
EG
3877module_exit(iwl_exit);
3878module_init(iwl_init);
a562a9dd
RC
3879
3880#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3881module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3882MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3883module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3884MODULE_PARM_DESC(debug, "debug output mask");
3885#endif
3886
2b068618
WYG
3887module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
3888MODULE_PARM_DESC(swcrypto50,
3889 "using crypto in software (default 0 [hardware]) (deprecated)");
3890module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
3891MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
3892module_param_named(queues_num50,
3893 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3894MODULE_PARM_DESC(queues_num50,
3895 "number of hw queues in 50xx series (deprecated)");
3896module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3897MODULE_PARM_DESC(queues_num, "number of hw queues.");
3898module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3899MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
3900module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3901MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
3902module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
3903 int, S_IRUGO);
3904MODULE_PARM_DESC(amsdu_size_8K50,
3905 "enable 8K amsdu size in 50XX series (deprecated)");
3906module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
3907 int, S_IRUGO);
3908MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3909module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3910MODULE_PARM_DESC(fw_restart50,
3911 "restart firmware in case of error (deprecated)");
3912module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3913MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3914module_param_named(
3915 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
3916MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
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