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iwlwifi: Fix null pointer referencing in iwl_dbgfs_rx_queue_read.
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
5a0e3ad6 34#include <linux/slab.h>
b481de9c
ZY		 35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
d43c36dc 37#include <linux/sched.h>
b481de9c
ZY		 38#include <linux/skbuff.h>
39#include <linux/netdevice.h>
40#include <linux/wireless.h>
41#include <linux/firmware.h>
b481de9c
ZY		 42#include <linux/etherdevice.h>
43#include <linux/if_arp.h>
44
b481de9c
ZY		 45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO		 49#define DRV_NAME "iwlagn"
50
6bc913bd 51#include "iwl-eeprom.h"
3e0d4cb1 52#include "iwl-dev.h"
fee1247a 53#include "iwl-core.h"
3395f6e9 54#include "iwl-io.h"
b481de9c 55#include "iwl-helpers.h"
6974e363 56#include "iwl-sta.h"
f0832f13 57#include "iwl-calib.h"
a1175124 58#include "iwl-agn.h"
b481de9c 59
416e1438 60
b481de9c
ZY		 61/******************************************************************************
62 *
63 * module boiler plate
64 *
65 ******************************************************************************/
66
b481de9c
ZY		 67/*
68 * module name, copyright, version, etc.
b481de9c 69 */
d783b061 70#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 71
0a6857e7 72#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 73#define VD "d"
74#else
75#define VD
76#endif
77
81963d68 78#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 79
b481de9c
ZY		 80
81MODULE_DESCRIPTION(DRV_DESCRIPTION);
82MODULE_VERSION(DRV_VERSION);
a7b75207 83MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 84MODULE_LICENSE("GPL");
4fc22b21 85MODULE_ALIAS("iwl4965");
b481de9c 86
b481de9c 87/**
5b9f8cd3 88 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 89 *
01ebd063 90 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 91 * the active_rxon structure is updated with the new data. This
92 * function correctly transitions out of the RXON_ASSOC_MSK state if
93 * a HW tune is required based on the RXON structure changes.
94 */
e0158e61 95int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 96{
97 /* cast away the const for active_rxon in this function */
c1adf9fb 98 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG		 99 int ret;
100 bool new_assoc =
101 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 102
fee1247a 103 if (!iwl_is_alive(priv))
43d59b32 104 return -EBUSY;
b481de9c
ZY		 105
106 /* always get timestamp with Rx frame */
107 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
108
8ccde88a 109 ret = iwl_check_rxon_cmd(priv);
43d59b32 110 if (ret) {
15b1687c 111 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 112 return -EINVAL;
113 }
114
0924e519
WYG		 115 /*
116 * receive commit_rxon request
117 * abort any previous channel switch if still in process
118 */
119 if (priv->switch_rxon.switch_in_progress &&
120 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
121 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
122 le16_to_cpu(priv->switch_rxon.channel));
79d07325 123 iwl_chswitch_done(priv, false);
0924e519
WYG		 124 }
125
b481de9c 126 /* If we don't need to send a full RXON, we can use
5b9f8cd3 127 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 128 * and other flags for the current radio configuration. */
54559703 129 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG		 130 ret = iwl_send_rxon_assoc(priv);
131 if (ret) {
15b1687c 132 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 133 return ret;
b481de9c
ZY		 134 }
135
136 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 137 iwl_print_rx_config_cmd(priv);
b481de9c
ZY		 138 return 0;
139 }
140
b481de9c
ZY		 141 /* If we are currently associated and the new config requires
142 * an RXON_ASSOC and the new config wants the associated mask enabled,
143 * we must clear the associated from the active configuration
144 * before we apply the new config */
43d59b32 145 if (iwl_is_associated(priv) && new_assoc) {
e1623446 146 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 147 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
148
43d59b32 149 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 150 sizeof(struct iwl_rxon_cmd),
b481de9c
ZY		 151 &priv->active_rxon);
152
153 /* If the mask clearing failed then we set
154 * active_rxon back to what it was previously */
43d59b32 155 if (ret) {
b481de9c 156 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 157 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 158 return ret;
b481de9c 159 }
2c810ccd 160 iwl_clear_ucode_stations(priv);
7e246191 161 iwl_restore_stations(priv);
335348b1
JB		 162 ret = iwl_restore_default_wep_keys(priv);
163 if (ret) {
164 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
165 return ret;
166 }
b481de9c
ZY		 167 }
168
e1623446 169 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 170 "* with%s RXON_FILTER_ASSOC_MSK\n"
171 "* channel = %d\n"
e174961c 172 "* bssid = %pM\n",
43d59b32 173 (new_assoc ? "" : "out"),
b481de9c 174 le16_to_cpu(priv->staging_rxon.channel),
e174961c 175 priv->staging_rxon.bssid_addr);
b481de9c 176
90e8e424 177 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG		 178
179 /* Apply the new configuration
7e246191
RC		 180 * RXON unassoc clears the station table in uCode so restoration of
181 * stations is needed after it (the RXON command) completes
43d59b32
EG		 182 */
183 if (!new_assoc) {
184 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 185 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 186 if (ret) {
15b1687c 187 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 188 return ret;
189 }
91dd6c27 190 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
43d59b32 191 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
2c810ccd 192 iwl_clear_ucode_stations(priv);
7e246191 193 iwl_restore_stations(priv);
335348b1
JB		 194 ret = iwl_restore_default_wep_keys(priv);
195 if (ret) {
196 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
197 return ret;
198 }
b481de9c
ZY		 199 }
200
19cc1087 201 priv->start_calib = 0;
9185159d 202 if (new_assoc) {
47eef9bd
WYG		 203 /*
204 * allow CTS-to-self if possible for new association.
205 * this is relevant only for 5000 series and up,
206 * but will not damage 4965
207 */
208 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
209
43d59b32
EG		 210 /* Apply the new configuration
211 * RXON assoc doesn't clear the station table in uCode,
212 */
213 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
214 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
215 if (ret) {
15b1687c 216 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 217 return ret;
218 }
219 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 220 }
a643565e 221 iwl_print_rx_config_cmd(priv);
b481de9c 222
36da7d70
ZY		 223 iwl_init_sensitivity(priv);
224
225 /* If we issue a new RXON command which required a tune then we must
226 * send a new TXPOWER command or we won't be able to Tx any frames */
227 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
228 if (ret) {
15b1687c 229 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 230 return ret;
231 }
232
b481de9c
ZY		 233 return 0;
234}
235
5b9f8cd3 236void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA		 237{
238
45823531
AK		 239 if (priv->cfg->ops->hcmd->set_rxon_chain)
240 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 241 iwlcore_commit_rxon(priv);
5da4b55f
MA		 242}
243
fcab423d 244static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 245{
246 struct list_head *element;
247
e1623446 248 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 249 priv->frames_count);
250
251 while (!list_empty(&priv->free_frames)) {
252 element = priv->free_frames.next;
253 list_del(element);
fcab423d 254 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 255 priv->frames_count--;
256 }
257
258 if (priv->frames_count) {
39aadf8c 259 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 260 priv->frames_count);
261 priv->frames_count = 0;
262 }
263}
264
fcab423d 265static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 266{
fcab423d 267 struct iwl_frame *frame;
b481de9c
ZY		 268 struct list_head *element;
269 if (list_empty(&priv->free_frames)) {
270 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
271 if (!frame) {
15b1687c 272 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 273 return NULL;
274 }
275
276 priv->frames_count++;
277 return frame;
278 }
279
280 element = priv->free_frames.next;
281 list_del(element);
fcab423d 282 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 283}
284
fcab423d 285static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 286{
287 memset(frame, 0, sizeof(*frame));
288 list_add(&frame->list, &priv->free_frames);
289}
290
47ff65c4 291static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 292 struct ieee80211_hdr *hdr,
73ec1cc2 293 int left)
b481de9c 294{
3109ece1 295 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 296 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
297 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 298 return 0;
299
300 if (priv->ibss_beacon->len > left)
301 return 0;
302
303 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
304
305 return priv->ibss_beacon->len;
306}
307
47ff65c4
DH		 308/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
309static void iwl_set_beacon_tim(struct iwl_priv *priv,
310 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
311 u8 *beacon, u32 frame_size)
312{
313 u16 tim_idx;
314 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
315
316 /*
317 * The index is relative to frame start but we start looking at the
318 * variable-length part of the beacon.
319 */
320 tim_idx = mgmt->u.beacon.variable - beacon;
321
322 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
323 while ((tim_idx < (frame_size - 2)) &&
324 (beacon[tim_idx] != WLAN_EID_TIM))
325 tim_idx += beacon[tim_idx+1] + 2;
326
327 /* If TIM field was found, set variables */
328 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
329 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
330 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
331 } else
332 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
333}
334
5b9f8cd3 335static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 336 struct iwl_frame *frame)
4bf64efd
TW		 337{
338 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 339 u32 frame_size;
340 u32 rate_flags;
341 u32 rate;
342 /*
343 * We have to set up the TX command, the TX Beacon command, and the
344 * beacon contents.
345 */
4bf64efd 346
47ff65c4 347 /* Initialize memory */
4bf64efd
TW		 348 tx_beacon_cmd = &frame->u.beacon;
349 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
350
47ff65c4 351 /* Set up TX beacon contents */
4bf64efd 352 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 353 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 354 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
355 return 0;
4bf64efd 356
47ff65c4 357 /* Set up TX command fields */
4bf64efd 358 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH		 359 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
360 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
361 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
362 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 363
47ff65c4
DH		 364 /* Set up TX beacon command fields */
365 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
366 frame_size);
4bf64efd 367
47ff65c4
DH		 368 /* Set up packet rate and flags */
369 rate = iwl_rate_get_lowest_plcp(priv);
0e1654fa
JB		 370 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
371 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 372 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
373 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
374 rate_flags |= RATE_MCS_CCK_MSK;
375 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
376 rate_flags);
4bf64efd
TW		 377
378 return sizeof(*tx_beacon_cmd) + frame_size;
379}
5b9f8cd3 380static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 381{
fcab423d 382 struct iwl_frame *frame;
b481de9c
ZY		 383 unsigned int frame_size;
384 int rc;
b481de9c 385
fcab423d 386 frame = iwl_get_free_frame(priv);
b481de9c 387 if (!frame) {
15b1687c 388 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 389 "command.\n");
390 return -ENOMEM;
391 }
392
47ff65c4
DH		 393 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
394 if (!frame_size) {
395 IWL_ERR(priv, "Error configuring the beacon command\n");
396 iwl_free_frame(priv, frame);
397 return -EINVAL;
398 }
b481de9c 399
857485c0 400 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 401 &frame->u.cmd[0]);
402
fcab423d 403 iwl_free_frame(priv, frame);
b481de9c
ZY		 404
405 return rc;
406}
407
7aaa1d79
SO		 408static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
409{
410 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
411
412 dma_addr_t addr = get_unaligned_le32(&tb->lo);
413 if (sizeof(dma_addr_t) > sizeof(u32))
414 addr |=
415 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
416
417 return addr;
418}
419
420static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
421{
422 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
423
424 return le16_to_cpu(tb->hi_n_len) >> 4;
425}
426
427static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
428 dma_addr_t addr, u16 len)
429{
430 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
431 u16 hi_n_len = len << 4;
432
433 put_unaligned_le32(addr, &tb->lo);
434 if (sizeof(dma_addr_t) > sizeof(u32))
435 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
436
437 tb->hi_n_len = cpu_to_le16(hi_n_len);
438
439 tfd->num_tbs = idx + 1;
440}
441
442static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
443{
444 return tfd->num_tbs & 0x1f;
445}
446
447/**
448 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
449 * @priv - driver private data
450 * @txq - tx queue
451 *
452 * Does NOT advance any TFD circular buffer read/write indexes
453 * Does NOT free the TFD itself (which is within circular buffer)
454 */
455void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
456{
59606ffa 457 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 458 struct iwl_tfd *tfd;
459 struct pci_dev *dev = priv->pci_dev;
460 int index = txq->q.read_ptr;
461 int i;
462 int num_tbs;
463
464 tfd = &tfd_tmp[index];
465
466 /* Sanity check on number of chunks */
467 num_tbs = iwl_tfd_get_num_tbs(tfd);
468
469 if (num_tbs >= IWL_NUM_OF_TBS) {
470 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
471 /* @todo issue fatal error, it is quite serious situation */
472 return;
473 }
474
475 /* Unmap tx_cmd */
476 if (num_tbs)
477 pci_unmap_single(dev,
2e724443
FT		 478 dma_unmap_addr(&txq->meta[index], mapping),
479 dma_unmap_len(&txq->meta[index], len),
96891cee 480 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 481
482 /* Unmap chunks, if any. */
ff0d91c3 483 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 484 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
485 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
486
ff0d91c3
JB		 487 /* free SKB */
488 if (txq->txb) {
489 struct sk_buff *skb;
6f80240e 490
ff0d91c3 491 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 492
ff0d91c3
JB		 493 /* can be called from irqs-disabled context */
494 if (skb) {
495 dev_kfree_skb_any(skb);
496 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 497 }
498 }
499}
500
501int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
502 struct iwl_tx_queue *txq,
503 dma_addr_t addr, u16 len,
504 u8 reset, u8 pad)
505{
506 struct iwl_queue *q;
59606ffa 507 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 508 u32 num_tbs;
509
510 q = &txq->q;
59606ffa
SO		 511 tfd_tmp = (struct iwl_tfd *)txq->tfds;
512 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 513
514 if (reset)
515 memset(tfd, 0, sizeof(*tfd));
516
517 num_tbs = iwl_tfd_get_num_tbs(tfd);
518
519 /* Each TFD can point to a maximum 20 Tx buffers */
520 if (num_tbs >= IWL_NUM_OF_TBS) {
521 IWL_ERR(priv, "Error can not send more than %d chunks\n",
522 IWL_NUM_OF_TBS);
523 return -EINVAL;
524 }
525
526 BUG_ON(addr & ~DMA_BIT_MASK(36));
527 if (unlikely(addr & ~IWL_TX_DMA_MASK))
528 IWL_ERR(priv, "Unaligned address = %llx\n",
529 (unsigned long long)addr);
530
531 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
532
533 return 0;
534}
535
a8e74e27
SO		 536/*
537 * Tell nic where to find circular buffer of Tx Frame Descriptors for
538 * given Tx queue, and enable the DMA channel used for that queue.
539 *
540 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
541 * channels supported in hardware.
542 */
543int iwl_hw_tx_queue_init(struct iwl_priv *priv,
544 struct iwl_tx_queue *txq)
545{
a8e74e27
SO		 546 int txq_id = txq->q.id;
547
a8e74e27
SO		 548 /* Circular buffer (TFD queue in DRAM) physical base address */
549 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
550 txq->q.dma_addr >> 8);
551
a8e74e27
SO		 552 return 0;
553}
554
b481de9c
ZY		 555/******************************************************************************
556 *
557 * Generic RX handler implementations
558 *
559 ******************************************************************************/
885ba202
TW		 560static void iwl_rx_reply_alive(struct iwl_priv *priv,
561 struct iwl_rx_mem_buffer *rxb)
b481de9c 562{
2f301227 563 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 564 struct iwl_alive_resp *palive;
b481de9c
ZY		 565 struct delayed_work *pwork;
566
567 palive = &pkt->u.alive_frame;
568
e1623446 569 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 570 "0x%01X 0x%01X\n",
571 palive->is_valid, palive->ver_type,
572 palive->ver_subtype);
573
574 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 575 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 576 memcpy(&priv->card_alive_init,
577 &pkt->u.alive_frame,
885ba202 578 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 579 pwork = &priv->init_alive_start;
580 } else {
e1623446 581 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 582 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 583 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 584 pwork = &priv->alive_start;
585 }
586
587 /* We delay the ALIVE response by 5ms to
588 * give the HW RF Kill time to activate... */
589 if (palive->is_valid == UCODE_VALID_OK)
590 queue_delayed_work(priv->workqueue, pwork,
591 msecs_to_jiffies(5));
592 else
39aadf8c 593 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 594}
595
5b9f8cd3 596static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 597{
c79dd5b5
TW		 598 struct iwl_priv *priv =
599 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 600 struct sk_buff *beacon;
601
602 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 603 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 604
605 if (!beacon) {
15b1687c 606 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 607 return;
608 }
609
610 mutex_lock(&priv->mutex);
611 /* new beacon skb is allocated every time; dispose previous.*/
612 if (priv->ibss_beacon)
613 dev_kfree_skb(priv->ibss_beacon);
614
615 priv->ibss_beacon = beacon;
616 mutex_unlock(&priv->mutex);
617
5b9f8cd3 618 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 619}
620
4e39317d 621/**
5b9f8cd3 622 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 623 *
624 * This callback is provided in order to send a statistics request.
625 *
626 * This timer function is continually reset to execute within
627 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
628 * was received. We need to ensure we receive the statistics in order
629 * to update the temperature used for calibrating the TXPOWER.
630 */
5b9f8cd3 631static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 632{
633 struct iwl_priv *priv = (struct iwl_priv *)data;
634
635 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
636 return;
637
61780ee3
MA		 638 /* dont send host command if rf-kill is on */
639 if (!iwl_is_ready_rf(priv))
640 return;
641
ef8d5529 642 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 643}
644
a9e1cb6a
WYG		 645
646static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
647 u32 start_idx, u32 num_events,
648 u32 mode)
649{
650 u32 i;
651 u32 ptr; /* SRAM byte address of log data */
652 u32 ev, time, data; /* event log data */
653 unsigned long reg_flags;
654
655 if (mode == 0)
656 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
657 else
658 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
659
660 /* Make sure device is powered up for SRAM reads */
661 spin_lock_irqsave(&priv->reg_lock, reg_flags);
662 if (iwl_grab_nic_access(priv)) {
663 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
664 return;
665 }
666
667 /* Set starting address; reads will auto-increment */
668 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
669 rmb();
670
671 /*
672 * "time" is actually "data" for mode 0 (no timestamp).
673 * place event id # at far right for easier visual parsing.
674 */
675 for (i = 0; i < num_events; i++) {
676 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
677 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
678 if (mode == 0) {
679 trace_iwlwifi_dev_ucode_cont_event(priv,
680 0, time, ev);
681 } else {
682 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
683 trace_iwlwifi_dev_ucode_cont_event(priv,
684 time, data, ev);
685 }
686 }
687 /* Allow device to power down */
688 iwl_release_nic_access(priv);
689 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
690}
691
875295f1 692static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 693{
694 u32 capacity; /* event log capacity in # entries */
695 u32 base; /* SRAM byte address of event log header */
696 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
697 u32 num_wraps; /* # times uCode wrapped to top of log */
698 u32 next_entry; /* index of next entry to be written by uCode */
699
700 if (priv->ucode_type == UCODE_INIT)
701 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
702 else
703 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
704 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
705 capacity = iwl_read_targ_mem(priv, base);
706 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
707 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
708 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
709 } else
710 return;
711
712 if (num_wraps == priv->event_log.num_wraps) {
713 iwl_print_cont_event_trace(priv,
714 base, priv->event_log.next_entry,
715 next_entry - priv->event_log.next_entry,
716 mode);
717 priv->event_log.non_wraps_count++;
718 } else {
719 if ((num_wraps - priv->event_log.num_wraps) > 1)
720 priv->event_log.wraps_more_count++;
721 else
722 priv->event_log.wraps_once_count++;
723 trace_iwlwifi_dev_ucode_wrap_event(priv,
724 num_wraps - priv->event_log.num_wraps,
725 next_entry, priv->event_log.next_entry);
726 if (next_entry < priv->event_log.next_entry) {
727 iwl_print_cont_event_trace(priv, base,
728 priv->event_log.next_entry,
729 capacity - priv->event_log.next_entry,
730 mode);
731
732 iwl_print_cont_event_trace(priv, base, 0,
733 next_entry, mode);
734 } else {
735 iwl_print_cont_event_trace(priv, base,
736 next_entry, capacity - next_entry,
737 mode);
738
739 iwl_print_cont_event_trace(priv, base, 0,
740 next_entry, mode);
741 }
742 }
743 priv->event_log.num_wraps = num_wraps;
744 priv->event_log.next_entry = next_entry;
745}
746
747/**
748 * iwl_bg_ucode_trace - Timer callback to log ucode event
749 *
750 * The timer is continually set to execute every
751 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
752 * this function is to perform continuous uCode event logging operation
753 * if enabled
754 */
755static void iwl_bg_ucode_trace(unsigned long data)
756{
757 struct iwl_priv *priv = (struct iwl_priv *)data;
758
759 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
760 return;
761
762 if (priv->event_log.ucode_trace) {
763 iwl_continuous_event_trace(priv);
764 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
765 mod_timer(&priv->ucode_trace,
766 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
767 }
768}
769
5b9f8cd3 770static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 771 struct iwl_rx_mem_buffer *rxb)
b481de9c 772{
0a6857e7 773#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 774 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 775 struct iwl4965_beacon_notif *beacon =
776 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 777 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 778
e1623446 779 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 780 "tsf %d %d rate %d\n",
25a6572c 781 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 782 beacon->beacon_notify_hdr.failure_frame,
783 le32_to_cpu(beacon->ibss_mgr_status),
784 le32_to_cpu(beacon->high_tsf),
785 le32_to_cpu(beacon->low_tsf), rate);
786#endif
787
05c914fe 788 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 789 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
790 queue_work(priv->workqueue, &priv->beacon_update);
791}
792
b481de9c
ZY		 793/* Handle notification from uCode that card's power state is changing
794 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 795static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 796 struct iwl_rx_mem_buffer *rxb)
b481de9c 797{
2f301227 798 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 799 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
800 unsigned long status = priv->status;
801
3a41bbd5 802 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 803 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 804 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
805 (flags & CT_CARD_DISABLED) ?
806 "Reached" : "Not reached");
b481de9c
ZY		 807
808 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 809 CT_CARD_DISABLED)) {
b481de9c 810
3395f6e9 811 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 812 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
813
a8b50a0a
MA		 814 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
815 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 816
817 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 818 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 819 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 820 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 821 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 822 }
3a41bbd5 823 if (flags & CT_CARD_DISABLED)
39b73fb1 824 iwl_tt_enter_ct_kill(priv);
b481de9c 825 }
3a41bbd5 826 if (!(flags & CT_CARD_DISABLED))
39b73fb1 827 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 828
829 if (flags & HW_CARD_DISABLED)
830 set_bit(STATUS_RF_KILL_HW, &priv->status);
831 else
832 clear_bit(STATUS_RF_KILL_HW, &priv->status);
833
834
b481de9c 835 if (!(flags & RXON_CARD_DISABLED))
2a421b91 836 iwl_scan_cancel(priv);
b481de9c
ZY		 837
838 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 839 test_bit(STATUS_RF_KILL_HW, &priv->status)))
840 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
841 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 842 else
843 wake_up_interruptible(&priv->wait_command_queue);
844}
845
5b9f8cd3 846int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 847{
e2e3c57b 848 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 849 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 850 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
851 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
852 ~APMG_PS_CTRL_MSK_PWR_SRC);
853 } else {
854 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
855 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
856 ~APMG_PS_CTRL_MSK_PWR_SRC);
857 }
858
a8b50a0a 859 return 0;
e2e3c57b
TW		 860}
861
b481de9c 862/**
5b9f8cd3 863 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 864 *
865 * Setup the RX handlers for each of the reply types sent from the uCode
866 * to the host.
867 *
868 * This function chains into the hardware specific files for them to setup
869 * any hardware specific handlers as well.
870 */
653fa4a0 871static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 872{
885ba202 873 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 874 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
875 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 876 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
877 iwl_rx_spectrum_measure_notif;
5b9f8cd3 878 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 879 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 880 iwl_rx_pm_debug_statistics_notif;
881 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 882
9fbab516
BC		 883 /*
884 * The same handler is used for both the REPLY to a discrete
885 * statistics request from the host as well as for the periodic
886 * statistics notifications (after received beacons) from the uCode.
b481de9c 887 */
ef8d5529 888 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 889 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 890
891 iwl_setup_rx_scan_handlers(priv);
892
37a44211 893 /* status change handler */
5b9f8cd3 894 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 895
c1354754
TW		 896 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
897 iwl_rx_missed_beacon_notif;
37a44211 898 /* Rx handlers */
8d801080
WYG		 899 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
900 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 901 /* block ack */
74bcdb33 902 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 903 /* Set up hardware specific Rx handlers */
d4789efe 904 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 905}
906
b481de9c 907/**
a55360e4 908 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 909 *
910 * Uses the priv->rx_handlers callback function array to invoke
911 * the appropriate handlers, including command responses,
912 * frame-received notifications, and other notifications.
913 */
a55360e4 914void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 915{
a55360e4 916 struct iwl_rx_mem_buffer *rxb;
db11d634 917 struct iwl_rx_packet *pkt;
a55360e4 918 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 919 u32 r, i;
920 int reclaim;
921 unsigned long flags;
5c0eef96 922 u8 fill_rx = 0;
d68ab680 923 u32 count = 8;
4752c93c 924 int total_empty;
b481de9c 925
6440adb5
CB		 926 /* uCode's read index (stored in shared DRAM) indicates the last Rx
927 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 928 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 929 i = rxq->read;
930
931 /* Rx interrupt, but nothing sent from uCode */
932 if (i == r)
e1623446 933 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 934
4752c93c 935 /* calculate total frames need to be restock after handling RX */
7300515d 936 total_empty = r - rxq->write_actual;
4752c93c
MA		 937 if (total_empty < 0)
938 total_empty += RX_QUEUE_SIZE;
939
940 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 941 fill_rx = 1;
942
b481de9c 943 while (i != r) {
f4989d9b
JB		 944 int len;
945
b481de9c
ZY		 946 rxb = rxq->queue[i];
947
9fbab516 948 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 949 * then a bug has been introduced in the queue refilling
950 * routines -- catch it here */
951 BUG_ON(rxb == NULL);
952
953 rxq->queue[i] = NULL;
954
2f301227
ZY		 955 pci_unmap_page(priv->pci_dev, rxb->page_dma,
956 PAGE_SIZE << priv->hw_params.rx_page_order,
957 PCI_DMA_FROMDEVICE);
958 pkt = rxb_addr(rxb);
b481de9c 959
f4989d9b
JB		 960 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
961 len += sizeof(u32); /* account for status word */
962 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 963
b481de9c
ZY		 964 /* Reclaim a command buffer only if this packet is a response
965 * to a (driver-originated) command.
966 * If the packet (e.g. Rx frame) originated from uCode,
967 * there is no command buffer to reclaim.
968 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
969 * but apparently a few don't get set; catch them here. */
970 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
971 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 972 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 973 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 974 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 975 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
976 (pkt->hdr.cmd != REPLY_TX);
977
978 /* Based on type of command response or notification,
979 * handle those that need handling via function in
5b9f8cd3 980 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 981 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 982 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 983 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 984 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 985 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 986 } else {
987 /* No handling needed */
e1623446 988 IWL_DEBUG_RX(priv,
b481de9c
ZY		 989 "r %d i %d No handler needed for %s, 0x%02x\n",
990 r, i, get_cmd_string(pkt->hdr.cmd),
991 pkt->hdr.cmd);
992 }
993
29b1b268
ZY		 994 /*
995 * XXX: After here, we should always check rxb->page
996 * against NULL before touching it or its virtual
997 * memory (pkt). Because some rx_handler might have
998 * already taken or freed the pages.
999 */
1000
b481de9c 1001 if (reclaim) {
2f301227
ZY		 1002 /* Invoke any callbacks, transfer the buffer to caller,
1003 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1004 * as we reclaim the driver command queue */
29b1b268 1005 if (rxb->page)
17b88929 1006 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1007 else
39aadf8c 1008 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1009 }
1010
7300515d
ZY		 1011 /* Reuse the page if possible. For notification packets and
1012 * SKBs that fail to Rx correctly, add them back into the
1013 * rx_free list for reuse later. */
1014 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1015 if (rxb->page != NULL) {
7300515d
ZY		 1016 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1017 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1018 PCI_DMA_FROMDEVICE);
1019 list_add_tail(&rxb->list, &rxq->rx_free);
1020 rxq->free_count++;
1021 } else
1022 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1023
b481de9c 1024 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1025
b481de9c 1026 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1027 /* If there are a lot of unused frames,
1028 * restock the Rx queue so ucode wont assert. */
1029 if (fill_rx) {
1030 count++;
1031 if (count >= 8) {
7300515d 1032 rxq->read = i;
54b81550 1033 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1034 count = 0;
1035 }
1036 }
b481de9c
ZY		 1037 }
1038
1039 /* Backtrack one entry */
7300515d 1040 rxq->read = i;
4752c93c 1041 if (fill_rx)
54b81550 1042 iwlagn_rx_replenish_now(priv);
4752c93c 1043 else
54b81550 1044 iwlagn_rx_queue_restock(priv);
a55360e4 1045}
a55360e4 1046
0359facc
MA		 1047/* call this function to flush any scheduled tasklet */
1048static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1049{
a96a27f9 1050 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1051 synchronize_irq(priv->pci_dev->irq);
1052 tasklet_kill(&priv->irq_tasklet);
1053}
1054
ef850d7c 1055static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1056{
1057 u32 inta, handled = 0;
1058 u32 inta_fh;
1059 unsigned long flags;
c2e61da2 1060 u32 i;
0a6857e7 1061#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1062 u32 inta_mask;
1063#endif
1064
1065 spin_lock_irqsave(&priv->lock, flags);
1066
1067 /* Ack/clear/reset pending uCode interrupts.
1068 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1069 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1070 inta = iwl_read32(priv, CSR_INT);
1071 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1072
1073 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1074 * Any new interrupts that happen after this, either while we're
1075 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1076 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1077 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1078
0a6857e7 1079#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1080 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1081 /* just for debug */
3395f6e9 1082 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1083 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1084 inta, inta_mask, inta_fh);
1085 }
1086#endif
1087
2f301227
ZY		 1088 spin_unlock_irqrestore(&priv->lock, flags);
1089
b481de9c
ZY		 1090 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1091 * atomic, make sure that inta covers all the interrupts that
1092 * we've discovered, even if FH interrupt came in just after
1093 * reading CSR_INT. */
6f83eaa1 1094 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1095 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1096 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1097 inta |= CSR_INT_BIT_FH_TX;
1098
1099 /* Now service all interrupt bits discovered above. */
1100 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1101 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1102
1103 /* Tell the device to stop sending interrupts */
5b9f8cd3 1104 iwl_disable_interrupts(priv);
b481de9c 1105
a83b9141 1106 priv->isr_stats.hw++;
5b9f8cd3 1107 iwl_irq_handle_error(priv);
b481de9c
ZY		 1108
1109 handled |= CSR_INT_BIT_HW_ERR;
1110
b481de9c
ZY		 1111 return;
1112 }
1113
0a6857e7 1114#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1115 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1116 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1117 if (inta & CSR_INT_BIT_SCD) {
e1623446 1118 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1119 "the frame/frames.\n");
a83b9141
WYG		 1120 priv->isr_stats.sch++;
1121 }
b481de9c
ZY		 1122
1123 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1124 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1125 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1126 priv->isr_stats.alive++;
1127 }
b481de9c
ZY		 1128 }
1129#endif
1130 /* Safely ignore these bits for debug checks below */
25c03d8e 1131 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1132
9fbab516 1133 /* HW RF KILL switch toggled */
b481de9c
ZY		 1134 if (inta & CSR_INT_BIT_RF_KILL) {
1135 int hw_rf_kill = 0;
3395f6e9 1136 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1137 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1138 hw_rf_kill = 1;
1139
4c423a2b 1140 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1141 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1142
a83b9141
WYG		 1143 priv->isr_stats.rfkill++;
1144
a9efa652 1145 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1146 * the driver allows loading the ucode even if the radio
1147 * is killed. Hence update the killswitch state here. The
1148 * rfkill handler will care about restarting if needed.
a9efa652 1149 */
6cd0b1cb
HS		 1150 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1151 if (hw_rf_kill)
1152 set_bit(STATUS_RF_KILL_HW, &priv->status);
1153 else
1154 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1155 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1156 }
b481de9c
ZY		 1157
1158 handled |= CSR_INT_BIT_RF_KILL;
1159 }
1160
9fbab516 1161 /* Chip got too hot and stopped itself */
b481de9c 1162 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1163 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1164 priv->isr_stats.ctkill++;
b481de9c
ZY		 1165 handled |= CSR_INT_BIT_CT_KILL;
1166 }
1167
1168 /* Error detected by uCode */
1169 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1170 IWL_ERR(priv, "Microcode SW error detected. "
1171 " Restarting 0x%X.\n", inta);
a83b9141
WYG		 1172 priv->isr_stats.sw++;
1173 priv->isr_stats.sw_err = inta;
5b9f8cd3 1174 iwl_irq_handle_error(priv);
b481de9c
ZY		 1175 handled |= CSR_INT_BIT_SW_ERR;
1176 }
1177
c2e61da2
BC		 1178 /*
1179 * uCode wakes up after power-down sleep.
1180 * Tell device about any new tx or host commands enqueued,
1181 * and about any Rx buffers made available while asleep.
1182 */
b481de9c 1183 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1184 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1185 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1186 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1187 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1188 priv->isr_stats.wakeup++;
b481de9c
ZY		 1189 handled |= CSR_INT_BIT_WAKEUP;
1190 }
1191
1192 /* All uCode command responses, including Tx command responses,
1193 * Rx "responses" (frame-received notification), and other
1194 * notifications from uCode come through here*/
1195 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1196 iwl_rx_handle(priv);
a83b9141 1197 priv->isr_stats.rx++;
b481de9c
ZY		 1198 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1199 }
1200
c72cd19f 1201 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1202 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1203 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1204 priv->isr_stats.tx++;
b481de9c 1205 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1206 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1207 priv->ucode_write_complete = 1;
1208 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1209 }
1210
a83b9141 1211 if (inta & ~handled) {
15b1687c 1212 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1213 priv->isr_stats.unhandled++;
1214 }
b481de9c 1215
40cefda9 1216 if (inta & ~(priv->inta_mask)) {
39aadf8c 1217 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1218 inta & ~priv->inta_mask);
39aadf8c 1219 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1220 }
1221
1222 /* Re-enable all interrupts */
0359facc
MA		 1223 /* only Re-enable if diabled by irq */
1224 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1225 iwl_enable_interrupts(priv);
b481de9c 1226
0a6857e7 1227#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1228 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1229 inta = iwl_read32(priv, CSR_INT);
1230 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1231 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1232 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1233 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1234 }
1235#endif
b481de9c
ZY		 1236}
1237
ef850d7c
MA		 1238/* tasklet for iwlagn interrupt */
1239static void iwl_irq_tasklet(struct iwl_priv *priv)
1240{
1241 u32 inta = 0;
1242 u32 handled = 0;
1243 unsigned long flags;
8756990f 1244 u32 i;
ef850d7c
MA		 1245#ifdef CONFIG_IWLWIFI_DEBUG
1246 u32 inta_mask;
1247#endif
1248
1249 spin_lock_irqsave(&priv->lock, flags);
1250
1251 /* Ack/clear/reset pending uCode interrupts.
1252 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1253 */
48a6be6a
SZ		 1254 /* There is a hardware bug in the interrupt mask function that some
1255 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1256 * they are disabled in the CSR_INT_MASK register. Furthermore the
1257 * ICT interrupt handling mechanism has another bug that might cause
1258 * these unmasked interrupts fail to be detected. We workaround the
1259 * hardware bugs here by ACKing all the possible interrupts so that
1260 * interrupt coalescing can still be achieved.
1261 */
4a35ecf8 1262 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1263
a4c8b2a6 1264 inta = priv->_agn.inta;
ef850d7c
MA		 1265
1266#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1267 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1268 /* just for debug */
1269 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1270 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1271 inta, inta_mask);
1272 }
1273#endif
2f301227
ZY		 1274
1275 spin_unlock_irqrestore(&priv->lock, flags);
1276
a4c8b2a6
JB		 1277 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1278 priv->_agn.inta = 0;
ef850d7c
MA		 1279
1280 /* Now service all interrupt bits discovered above. */
1281 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1282 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1283
1284 /* Tell the device to stop sending interrupts */
1285 iwl_disable_interrupts(priv);
1286
1287 priv->isr_stats.hw++;
1288 iwl_irq_handle_error(priv);
1289
1290 handled |= CSR_INT_BIT_HW_ERR;
1291
ef850d7c
MA		 1292 return;
1293 }
1294
1295#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1296 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1297 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1298 if (inta & CSR_INT_BIT_SCD) {
1299 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1300 "the frame/frames.\n");
1301 priv->isr_stats.sch++;
1302 }
1303
1304 /* Alive notification via Rx interrupt will do the real work */
1305 if (inta & CSR_INT_BIT_ALIVE) {
1306 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1307 priv->isr_stats.alive++;
1308 }
1309 }
1310#endif
1311 /* Safely ignore these bits for debug checks below */
1312 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1313
1314 /* HW RF KILL switch toggled */
1315 if (inta & CSR_INT_BIT_RF_KILL) {
1316 int hw_rf_kill = 0;
1317 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1318 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1319 hw_rf_kill = 1;
1320
4c423a2b 1321 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1322 hw_rf_kill ? "disable radio" : "enable radio");
1323
1324 priv->isr_stats.rfkill++;
1325
1326 /* driver only loads ucode once setting the interface up.
1327 * the driver allows loading the ucode even if the radio
1328 * is killed. Hence update the killswitch state here. The
1329 * rfkill handler will care about restarting if needed.
1330 */
1331 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1332 if (hw_rf_kill)
1333 set_bit(STATUS_RF_KILL_HW, &priv->status);
1334 else
1335 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1336 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1337 }
1338
1339 handled |= CSR_INT_BIT_RF_KILL;
1340 }
1341
1342 /* Chip got too hot and stopped itself */
1343 if (inta & CSR_INT_BIT_CT_KILL) {
1344 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1345 priv->isr_stats.ctkill++;
1346 handled |= CSR_INT_BIT_CT_KILL;
1347 }
1348
1349 /* Error detected by uCode */
1350 if (inta & CSR_INT_BIT_SW_ERR) {
1351 IWL_ERR(priv, "Microcode SW error detected. "
1352 " Restarting 0x%X.\n", inta);
1353 priv->isr_stats.sw++;
1354 priv->isr_stats.sw_err = inta;
1355 iwl_irq_handle_error(priv);
1356 handled |= CSR_INT_BIT_SW_ERR;
1357 }
1358
1359 /* uCode wakes up after power-down sleep */
1360 if (inta & CSR_INT_BIT_WAKEUP) {
1361 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1362 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1363 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1364 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1365
1366 priv->isr_stats.wakeup++;
1367
1368 handled |= CSR_INT_BIT_WAKEUP;
1369 }
1370
1371 /* All uCode command responses, including Tx command responses,
1372 * Rx "responses" (frame-received notification), and other
1373 * notifications from uCode come through here*/
40cefda9
MA		 1374 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1375 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1376 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1377 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1378 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1379 iwl_write32(priv, CSR_FH_INT_STATUS,
1380 CSR49_FH_INT_RX_MASK);
1381 }
1382 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1383 handled |= CSR_INT_BIT_RX_PERIODIC;
1384 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1385 }
1386 /* Sending RX interrupt require many steps to be done in the
1387 * the device:
1388 * 1- write interrupt to current index in ICT table.
1389 * 2- dma RX frame.
1390 * 3- update RX shared data to indicate last write index.
1391 * 4- send interrupt.
1392 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1393 * but the shared data changes does not reflect this;
1394 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1395 */
74ba67ed
BC		 1396
1397 /* Disable periodic interrupt; we use it as just a one-shot. */
1398 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1399 CSR_INT_PERIODIC_DIS);
ef850d7c 1400 iwl_rx_handle(priv);
74ba67ed
BC		 1401
1402 /*
1403 * Enable periodic interrupt in 8 msec only if we received
1404 * real RX interrupt (instead of just periodic int), to catch
1405 * any dangling Rx interrupt. If it was just the periodic
1406 * interrupt, there was no dangling Rx activity, and no need
1407 * to extend the periodic interrupt; one-shot is enough.
1408 */
40cefda9 1409 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1410 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1411 CSR_INT_PERIODIC_ENA);
1412
ef850d7c 1413 priv->isr_stats.rx++;
ef850d7c
MA		 1414 }
1415
c72cd19f 1416 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1417 if (inta & CSR_INT_BIT_FH_TX) {
1418 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1419 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1420 priv->isr_stats.tx++;
1421 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1422 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1423 priv->ucode_write_complete = 1;
1424 wake_up_interruptible(&priv->wait_command_queue);
1425 }
1426
1427 if (inta & ~handled) {
1428 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1429 priv->isr_stats.unhandled++;
1430 }
1431
40cefda9 1432 if (inta & ~(priv->inta_mask)) {
ef850d7c 1433 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1434 inta & ~priv->inta_mask);
ef850d7c
MA		 1435 }
1436
ef850d7c
MA		 1437 /* Re-enable all interrupts */
1438 /* only Re-enable if diabled by irq */
1439 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1440 iwl_enable_interrupts(priv);
ef850d7c
MA		 1441}
1442
872c8ddc
WYG		 1443/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1444#define ACK_CNT_RATIO (50)
1445#define BA_TIMEOUT_CNT (5)
1446#define BA_TIMEOUT_MAX (16)
1447
1448/**
1449 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1450 *
1451 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1452 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1453 * operation state.
1454 */
1455bool iwl_good_ack_health(struct iwl_priv *priv,
1456 struct iwl_rx_packet *pkt)
1457{
1458 bool rc = true;
1459 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1460 int ba_timeout_delta;
1461
1462 actual_ack_cnt_delta =
1463 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
2daf6c15 1464 le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1465 expected_ack_cnt_delta =
1466 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
2daf6c15 1467 le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1468 ba_timeout_delta =
1469 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
2daf6c15 1470 le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1471 if ((priv->_agn.agg_tids_count > 0) &&
1472 (expected_ack_cnt_delta > 0) &&
1473 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1474 < ACK_CNT_RATIO) &&
1475 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1476 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1477 " expected_ack_cnt = %d\n",
1478 actual_ack_cnt_delta, expected_ack_cnt_delta);
1479
d73e4923
JB		 1480#ifdef CONFIG_IWLWIFI_DEBUGFS
1481 /*
1482 * This is ifdef'ed on DEBUGFS because otherwise the
1483 * statistics aren't available. If DEBUGFS is set but
1484 * DEBUG is not, these will just compile out.
1485 */
872c8ddc 1486 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
2daf6c15 1487 priv->delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1488 IWL_DEBUG_RADIO(priv,
1489 "ack_or_ba_timeout_collision delta = %d\n",
2daf6c15 1490 priv->delta_statistics.tx.
872c8ddc
WYG		 1491 ack_or_ba_timeout_collision);
1492#endif
1493 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1494 ba_timeout_delta);
1495 if (!actual_ack_cnt_delta &&
1496 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1497 rc = false;
1498 }
1499 return rc;
1500}
1501
a83b9141 1502
7d47618a
EG		 1503/*****************************************************************************
1504 *
1505 * sysfs attributes
1506 *
1507 *****************************************************************************/
1508
1509#ifdef CONFIG_IWLWIFI_DEBUG
1510
1511/*
1512 * The following adds a new attribute to the sysfs representation
1513 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1514 * used for controlling the debug level.
1515 *
1516 * See the level definitions in iwl for details.
1517 *
1518 * The debug_level being managed using sysfs below is a per device debug
1519 * level that is used instead of the global debug level if it (the per
1520 * device debug level) is set.
1521 */
1522static ssize_t show_debug_level(struct device *d,
1523 struct device_attribute *attr, char *buf)
1524{
1525 struct iwl_priv *priv = dev_get_drvdata(d);
1526 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1527}
1528static ssize_t store_debug_level(struct device *d,
1529 struct device_attribute *attr,
1530 const char *buf, size_t count)
1531{
1532 struct iwl_priv *priv = dev_get_drvdata(d);
1533 unsigned long val;
1534 int ret;
1535
1536 ret = strict_strtoul(buf, 0, &val);
1537 if (ret)
1538 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1539 else {
1540 priv->debug_level = val;
1541 if (iwl_alloc_traffic_mem(priv))
1542 IWL_ERR(priv,
1543 "Not enough memory to generate traffic log\n");
1544 }
1545 return strnlen(buf, count);
1546}
1547
1548static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1549 show_debug_level, store_debug_level);
1550
1551
1552#endif /* CONFIG_IWLWIFI_DEBUG */
1553
1554
1555static ssize_t show_temperature(struct device *d,
1556 struct device_attribute *attr, char *buf)
1557{
1558 struct iwl_priv *priv = dev_get_drvdata(d);
1559
1560 if (!iwl_is_alive(priv))
1561 return -EAGAIN;
1562
1563 return sprintf(buf, "%d\n", priv->temperature);
1564}
1565
1566static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1567
1568static ssize_t show_tx_power(struct device *d,
1569 struct device_attribute *attr, char *buf)
1570{
1571 struct iwl_priv *priv = dev_get_drvdata(d);
1572
1573 if (!iwl_is_ready_rf(priv))
1574 return sprintf(buf, "off\n");
1575 else
1576 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1577}
1578
1579static ssize_t store_tx_power(struct device *d,
1580 struct device_attribute *attr,
1581 const char *buf, size_t count)
1582{
1583 struct iwl_priv *priv = dev_get_drvdata(d);
1584 unsigned long val;
1585 int ret;
1586
1587 ret = strict_strtoul(buf, 10, &val);
1588 if (ret)
1589 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1590 else {
1591 ret = iwl_set_tx_power(priv, val, false);
1592 if (ret)
1593 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1594 ret);
1595 else
1596 ret = count;
1597 }
1598 return ret;
1599}
1600
1601static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1602
1603static ssize_t show_rts_ht_protection(struct device *d,
1604 struct device_attribute *attr, char *buf)
1605{
1606 struct iwl_priv *priv = dev_get_drvdata(d);
1607
1608 return sprintf(buf, "%s\n",
1609 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
1610}
1611
1612static ssize_t store_rts_ht_protection(struct device *d,
1613 struct device_attribute *attr,
1614 const char *buf, size_t count)
1615{
1616 struct iwl_priv *priv = dev_get_drvdata(d);
1617 unsigned long val;
1618 int ret;
1619
1620 ret = strict_strtoul(buf, 10, &val);
1621 if (ret)
1622 IWL_INFO(priv, "Input is not in decimal form.\n");
1623 else {
1624 if (!iwl_is_associated(priv))
1625 priv->cfg->use_rts_for_ht = val ? true : false;
1626 else
1627 IWL_ERR(priv, "Sta associated with AP - "
1628 "Change protection mechanism is not allowed\n");
1629 ret = count;
1630 }
1631 return ret;
1632}
1633
1634static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
1635 show_rts_ht_protection, store_rts_ht_protection);
1636
1637
1638static struct attribute *iwl_sysfs_entries[] = {
1639 &dev_attr_temperature.attr,
1640 &dev_attr_tx_power.attr,
1641 &dev_attr_rts_ht_protection.attr,
1642#ifdef CONFIG_IWLWIFI_DEBUG
1643 &dev_attr_debug_level.attr,
1644#endif
1645 NULL
1646};
1647
1648static struct attribute_group iwl_attribute_group = {
1649 .name = NULL, /* put in device directory */
1650 .attrs = iwl_sysfs_entries,
1651};
1652
b481de9c
ZY		 1653/******************************************************************************
1654 *
1655 * uCode download functions
1656 *
1657 ******************************************************************************/
1658
5b9f8cd3 1659static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1660{
98c92211
TW		 1661 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1662 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1663 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1664 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1665 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1666 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1667}
1668
5b9f8cd3 1669static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1670{
1671 /* Remove all resets to allow NIC to operate */
1672 iwl_write32(priv, CSR_RESET, 0);
1673}
1674
dd7a2509
JB		 1675struct iwlagn_ucode_capabilities {
1676 u32 max_probe_length;
1677};
edcdf8b2 1678
b08dfd04 1679static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1680static int iwl_mac_setup_register(struct iwl_priv *priv,
1681 struct iwlagn_ucode_capabilities *capa);
b08dfd04
JB		 1682
1683static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1684{
1685 const char *name_pre = priv->cfg->fw_name_pre;
1686
1687 if (first)
1688 priv->fw_index = priv->cfg->ucode_api_max;
1689 else
1690 priv->fw_index--;
1691
1692 if (priv->fw_index < priv->cfg->ucode_api_min) {
1693 IWL_ERR(priv, "no suitable firmware found!\n");
1694 return -ENOENT;
1695 }
1696
1697 sprintf(priv->firmware_name, "%s%d%s",
1698 name_pre, priv->fw_index, ".ucode");
1699
1700 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1701 priv->firmware_name);
1702
1703 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1704 &priv->pci_dev->dev, GFP_KERNEL, priv,
1705 iwl_ucode_callback);
1706}
1707
0e9a44dc
JB		 1708struct iwlagn_firmware_pieces {
1709 const void *inst, *data, *init, *init_data, *boot;
1710 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1711
1712 u32 build;
b2e640d4
JB		 1713
1714 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1715 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1716};
1717
1718static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1719 const struct firmware *ucode_raw,
1720 struct iwlagn_firmware_pieces *pieces)
1721{
1722 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1723 u32 api_ver, hdr_size;
1724 const u8 *src;
1725
1726 priv->ucode_ver = le32_to_cpu(ucode->ver);
1727 api_ver = IWL_UCODE_API(priv->ucode_ver);
1728
1729 switch (api_ver) {
1730 default:
1731 /*
1732 * 4965 doesn't revision the firmware file format
1733 * along with the API version, it always uses v1
1734 * file format.
1735 */
1736 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1737 CSR_HW_REV_TYPE_4965) {
1738 hdr_size = 28;
1739 if (ucode_raw->size < hdr_size) {
1740 IWL_ERR(priv, "File size too small!\n");
1741 return -EINVAL;
1742 }
1743 pieces->build = le32_to_cpu(ucode->u.v2.build);
1744 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1745 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1746 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1747 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1748 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1749 src = ucode->u.v2.data;
1750 break;
1751 }
1752 /* fall through for 4965 */
1753 case 0:
1754 case 1:
1755 case 2:
1756 hdr_size = 24;
1757 if (ucode_raw->size < hdr_size) {
1758 IWL_ERR(priv, "File size too small!\n");
1759 return -EINVAL;
1760 }
1761 pieces->build = 0;
1762 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1763 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1764 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1765 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1766 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1767 src = ucode->u.v1.data;
1768 break;
1769 }
1770
1771 /* Verify size of file vs. image size info in file's header */
1772 if (ucode_raw->size != hdr_size + pieces->inst_size +
1773 pieces->data_size + pieces->init_size +
1774 pieces->init_data_size + pieces->boot_size) {
1775
1776 IWL_ERR(priv,
1777 "uCode file size %d does not match expected size\n",
1778 (int)ucode_raw->size);
1779 return -EINVAL;
1780 }
1781
1782 pieces->inst = src;
1783 src += pieces->inst_size;
1784 pieces->data = src;
1785 src += pieces->data_size;
1786 pieces->init = src;
1787 src += pieces->init_size;
1788 pieces->init_data = src;
1789 src += pieces->init_data_size;
1790 pieces->boot = src;
1791 src += pieces->boot_size;
1792
1793 return 0;
1794}
1795
dd7a2509
JB		 1796static int iwlagn_wanted_ucode_alternative = 1;
1797
1798static int iwlagn_load_firmware(struct iwl_priv *priv,
1799 const struct firmware *ucode_raw,
1800 struct iwlagn_firmware_pieces *pieces,
1801 struct iwlagn_ucode_capabilities *capa)
1802{
1803 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1804 struct iwl_ucode_tlv *tlv;
1805 size_t len = ucode_raw->size;
1806 const u8 *data;
1807 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1808 u64 alternatives;
1809
1810 if (len < sizeof(*ucode))
1811 return -EINVAL;
1812
1813 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC))
1814 return -EINVAL;
1815
1816 /*
1817 * Check which alternatives are present, and "downgrade"
1818 * when the chosen alternative is not present, warning
1819 * the user when that happens. Some files may not have
1820 * any alternatives, so don't warn in that case.
1821 */
1822 alternatives = le64_to_cpu(ucode->alternatives);
1823 tmp = wanted_alternative;
1824 if (wanted_alternative > 63)
1825 wanted_alternative = 63;
1826 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1827 wanted_alternative--;
1828 if (wanted_alternative && wanted_alternative != tmp)
1829 IWL_WARN(priv,
1830 "uCode alternative %d not available, choosing %d\n",
1831 tmp, wanted_alternative);
1832
1833 priv->ucode_ver = le32_to_cpu(ucode->ver);
1834 pieces->build = le32_to_cpu(ucode->build);
1835 data = ucode->data;
1836
1837 len -= sizeof(*ucode);
1838
1839 while (len >= sizeof(*tlv)) {
1840 u32 tlv_len;
1841 enum iwl_ucode_tlv_type tlv_type;
1842 u16 tlv_alt;
1843 const u8 *tlv_data;
1844
1845 len -= sizeof(*tlv);
1846 tlv = (void *)data;
1847
1848 tlv_len = le32_to_cpu(tlv->length);
1849 tlv_type = le16_to_cpu(tlv->type);
1850 tlv_alt = le16_to_cpu(tlv->alternative);
1851 tlv_data = tlv->data;
1852
1853 if (len < tlv_len)
1854 return -EINVAL;
1855 len -= ALIGN(tlv_len, 4);
1856 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1857
1858 /*
1859 * Alternative 0 is always valid.
1860 *
1861 * Skip alternative TLVs that are not selected.
1862 */
1863 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1864 continue;
1865
1866 switch (tlv_type) {
1867 case IWL_UCODE_TLV_INST:
1868 pieces->inst = tlv_data;
1869 pieces->inst_size = tlv_len;
1870 break;
1871 case IWL_UCODE_TLV_DATA:
1872 pieces->data = tlv_data;
1873 pieces->data_size = tlv_len;
1874 break;
1875 case IWL_UCODE_TLV_INIT:
1876 pieces->init = tlv_data;
1877 pieces->init_size = tlv_len;
1878 break;
1879 case IWL_UCODE_TLV_INIT_DATA:
1880 pieces->init_data = tlv_data;
1881 pieces->init_data_size = tlv_len;
1882 break;
1883 case IWL_UCODE_TLV_BOOT:
1884 pieces->boot = tlv_data;
1885 pieces->boot_size = tlv_len;
1886 break;
1887 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1888 if (tlv_len != 4)
1889 return -EINVAL;
1890 capa->max_probe_length =
1891 le32_to_cpup((__le32 *)tlv_data);
1892 break;
b2e640d4
JB		 1893 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1894 if (tlv_len != 4)
1895 return -EINVAL;
1896 pieces->init_evtlog_ptr =
1897 le32_to_cpup((__le32 *)tlv_data);
1898 break;
1899 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1900 if (tlv_len != 4)
1901 return -EINVAL;
1902 pieces->init_evtlog_size =
1903 le32_to_cpup((__le32 *)tlv_data);
1904 break;
1905 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1906 if (tlv_len != 4)
1907 return -EINVAL;
1908 pieces->init_errlog_ptr =
1909 le32_to_cpup((__le32 *)tlv_data);
1910 break;
1911 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1912 if (tlv_len != 4)
1913 return -EINVAL;
1914 pieces->inst_evtlog_ptr =
1915 le32_to_cpup((__le32 *)tlv_data);
1916 break;
1917 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1918 if (tlv_len != 4)
1919 return -EINVAL;
1920 pieces->inst_evtlog_size =
1921 le32_to_cpup((__le32 *)tlv_data);
1922 break;
1923 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1924 if (tlv_len != 4)
1925 return -EINVAL;
1926 pieces->inst_errlog_ptr =
1927 le32_to_cpup((__le32 *)tlv_data);
1928 break;
dd7a2509
JB		 1929 default:
1930 break;
1931 }
1932 }
1933
1934 if (len)
1935 return -EINVAL;
1936
1937 return 0;
1938}
1939
b481de9c 1940/**
b08dfd04 1941 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1942 *
b08dfd04
JB		 1943 * If loaded successfully, copies the firmware into buffers
1944 * for the card to fetch (via DMA).
b481de9c 1945 */
b08dfd04 1946static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1947{
b08dfd04 1948 struct iwl_priv *priv = context;
cc0f555d 1949 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 1950 int err;
1951 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 1952 const unsigned int api_max = priv->cfg->ucode_api_max;
1953 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 1954 u32 api_ver;
3e4de761 1955 char buildstr[25];
0e9a44dc 1956 u32 build;
dd7a2509
JB		 1957 struct iwlagn_ucode_capabilities ucode_capa = {
1958 .max_probe_length = 200,
1959 };
0e9a44dc
JB		 1960
1961 memset(&pieces, 0, sizeof(pieces));
b481de9c 1962
b08dfd04
JB		 1963 if (!ucode_raw) {
1964 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1965 priv->firmware_name);
1966 goto try_again;
b481de9c
ZY		 1967 }
1968
b08dfd04
JB		 1969 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1970 priv->firmware_name, ucode_raw->size);
b481de9c 1971
22adba2a
JB		 1972 /* Make sure that we got at least the API version number */
1973 if (ucode_raw->size < 4) {
15b1687c 1974 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1975 goto try_again;
b481de9c
ZY		 1976 }
1977
1978 /* Data from ucode file: header followed by uCode images */
cc0f555d 1979 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1980
0e9a44dc
JB		 1981 if (ucode->ver)
1982 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1983 else
dd7a2509
JB		 1984 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1985 &ucode_capa);
22adba2a 1986
0e9a44dc
JB		 1987 if (err)
1988 goto try_again;
b481de9c 1989
a0987a8d 1990 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 1991 build = pieces.build;
a0987a8d 1992
0e9a44dc
JB		 1993 /*
1994 * api_ver should match the api version forming part of the
1995 * firmware filename ... but we don't check for that and only rely
1996 * on the API version read from firmware header from here on forward
1997 */
a0987a8d 1998 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1999 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2000 "Driver supports v%u, firmware is v%u.\n",
2001 api_max, api_ver);
b08dfd04 2002 goto try_again;
a0987a8d 2003 }
b08dfd04 2004
a0987a8d 2005 if (api_ver != api_max)
978785a3 2006 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2007 "got v%u. New firmware can be obtained "
2008 "from http://www.intellinuxwireless.org.\n",
2009 api_max, api_ver);
2010
3e4de761
JB		 2011 if (build)
2012 sprintf(buildstr, " build %u", build);
2013 else
2014 buildstr[0] = '\0';
2015
2016 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2017 IWL_UCODE_MAJOR(priv->ucode_ver),
2018 IWL_UCODE_MINOR(priv->ucode_ver),
2019 IWL_UCODE_API(priv->ucode_ver),
2020 IWL_UCODE_SERIAL(priv->ucode_ver),
2021 buildstr);
a0987a8d 2022
5ebeb5a6
RC		 2023 snprintf(priv->hw->wiphy->fw_version,
2024 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2025 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2026 IWL_UCODE_MAJOR(priv->ucode_ver),
2027 IWL_UCODE_MINOR(priv->ucode_ver),
2028 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2029 IWL_UCODE_SERIAL(priv->ucode_ver),
2030 buildstr);
b481de9c 2031
b08dfd04
JB		 2032 /*
2033 * For any of the failures below (before allocating pci memory)
2034 * we will try to load a version with a smaller API -- maybe the
2035 * user just got a corrupted version of the latest API.
2036 */
2037
0e9a44dc
JB		 2038 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2039 priv->ucode_ver);
2040 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2041 pieces.inst_size);
2042 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2043 pieces.data_size);
2044 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2045 pieces.init_size);
2046 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2047 pieces.init_data_size);
2048 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2049 pieces.boot_size);
b481de9c
ZY		 2050
2051 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2052 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2053 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2054 pieces.inst_size);
b08dfd04 2055 goto try_again;
b481de9c
ZY		 2056 }
2057
0e9a44dc
JB		 2058 if (pieces.data_size > priv->hw_params.max_data_size) {
2059 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2060 pieces.data_size);
b08dfd04 2061 goto try_again;
b481de9c 2062 }
0e9a44dc
JB		 2063
2064 if (pieces.init_size > priv->hw_params.max_inst_size) {
2065 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2066 pieces.init_size);
b08dfd04 2067 goto try_again;
b481de9c 2068 }
0e9a44dc
JB		 2069
2070 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2071 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2072 pieces.init_data_size);
b08dfd04 2073 goto try_again;
b481de9c 2074 }
0e9a44dc
JB		 2075
2076 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2077 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2078 pieces.boot_size);
b08dfd04 2079 goto try_again;
b481de9c
ZY		 2080 }
2081
2082 /* Allocate ucode buffers for card's bus-master loading ... */
2083
2084 /* Runtime instructions and 2 copies of data:
2085 * 1) unmodified from disk
2086 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2087 priv->ucode_code.len = pieces.inst_size;
98c92211 2088 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2089
0e9a44dc 2090 priv->ucode_data.len = pieces.data_size;
98c92211 2091 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2092
0e9a44dc 2093 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2094 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2095
1f304e4e
ZY		 2096 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2097 !priv->ucode_data_backup.v_addr)
2098 goto err_pci_alloc;
2099
b481de9c 2100 /* Initialization instructions and data */
0e9a44dc
JB		 2101 if (pieces.init_size && pieces.init_data_size) {
2102 priv->ucode_init.len = pieces.init_size;
98c92211 2103 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2104
0e9a44dc 2105 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2106 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2107
2108 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2109 goto err_pci_alloc;
2110 }
b481de9c
ZY		 2111
2112 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2113 if (pieces.boot_size) {
2114 priv->ucode_boot.len = pieces.boot_size;
98c92211 2115 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2116
90e759d1
TW		 2117 if (!priv->ucode_boot.v_addr)
2118 goto err_pci_alloc;
2119 }
b481de9c 2120
b2e640d4
JB		 2121 /* Now that we can no longer fail, copy information */
2122
2123 /*
2124 * The (size - 16) / 12 formula is based on the information recorded
2125 * for each event, which is of mode 1 (including timestamp) for all
2126 * new microcodes that include this information.
2127 */
2128 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2129 if (pieces.init_evtlog_size)
2130 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2131 else
2132 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2133 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2134 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2135 if (pieces.inst_evtlog_size)
2136 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2137 else
2138 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2139 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2140
b481de9c
ZY		 2141 /* Copy images into buffers for card's bus-master reads ... */
2142
2143 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2144 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2145 pieces.inst_size);
2146 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2147
e1623446 2148 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2149 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2150
0e9a44dc
JB		 2151 /*
2152 * Runtime data
2153 * NOTE: Copy into backup buffer will be done in iwl_up()
2154 */
2155 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2156 pieces.data_size);
2157 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2158 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2159
2160 /* Initialization instructions */
2161 if (pieces.init_size) {
e1623446 2162 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2163 pieces.init_size);
2164 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2165 }
2166
0e9a44dc
JB		 2167 /* Initialization data */
2168 if (pieces.init_data_size) {
e1623446 2169 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2170 pieces.init_data_size);
2171 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2172 pieces.init_data_size);
b481de9c
ZY		 2173 }
2174
0e9a44dc
JB		 2175 /* Bootstrap instructions */
2176 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2177 pieces.boot_size);
2178 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2179
b08dfd04
JB		 2180 /**************************************************
2181 * This is still part of probe() in a sense...
2182 *
2183 * 9. Setup and register with mac80211 and debugfs
2184 **************************************************/
dd7a2509 2185 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2186 if (err)
2187 goto out_unbind;
2188
2189 err = iwl_dbgfs_register(priv, DRV_NAME);
2190 if (err)
2191 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2192
7d47618a
EG		 2193 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2194 &iwl_attribute_group);
2195 if (err) {
2196 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2197 goto out_unbind;
2198 }
2199
b481de9c
ZY		 2200 /* We have our copies now, allow OS release its copies */
2201 release_firmware(ucode_raw);
a15707d8 2202 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2203 return;
2204
2205 try_again:
2206 /* try next, if any */
2207 if (iwl_request_firmware(priv, false))
2208 goto out_unbind;
2209 release_firmware(ucode_raw);
2210 return;
b481de9c
ZY		 2211
2212 err_pci_alloc:
15b1687c 2213 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2214 iwl_dealloc_ucode_pci(priv);
b08dfd04 2215 out_unbind:
a15707d8 2216 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2217 device_release_driver(&priv->pci_dev->dev);
b481de9c 2218 release_firmware(ucode_raw);
b481de9c
ZY		 2219}
2220
b7a79404
RC		 2221static const char *desc_lookup_text[] = {
2222 "OK",
2223 "FAIL",
2224 "BAD_PARAM",
2225 "BAD_CHECKSUM",
2226 "NMI_INTERRUPT_WDG",
2227 "SYSASSERT",
2228 "FATAL_ERROR",
2229 "BAD_COMMAND",
2230 "HW_ERROR_TUNE_LOCK",
2231 "HW_ERROR_TEMPERATURE",
2232 "ILLEGAL_CHAN_FREQ",
2233 "VCC_NOT_STABLE",
2234 "FH_ERROR",
2235 "NMI_INTERRUPT_HOST",
2236 "NMI_INTERRUPT_ACTION_PT",
2237 "NMI_INTERRUPT_UNKNOWN",
2238 "UCODE_VERSION_MISMATCH",
2239 "HW_ERROR_ABS_LOCK",
2240 "HW_ERROR_CAL_LOCK_FAIL",
2241 "NMI_INTERRUPT_INST_ACTION_PT",
2242 "NMI_INTERRUPT_DATA_ACTION_PT",
2243 "NMI_TRM_HW_ER",
2244 "NMI_INTERRUPT_TRM",
2245 "NMI_INTERRUPT_BREAK_POINT"
2246 "DEBUG_0",
2247 "DEBUG_1",
2248 "DEBUG_2",
2249 "DEBUG_3",
a7fce6ee 2250 "ADVANCED SYSASSERT"
b7a79404
RC		 2251};
2252
2253static const char *desc_lookup(int i)
2254{
2255 int max = ARRAY_SIZE(desc_lookup_text) - 1;
2256
2257 if (i < 0 || i > max)
2258 i = max;
2259
2260 return desc_lookup_text[i];
2261}
2262
2263#define ERROR_START_OFFSET (1 * sizeof(u32))
2264#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2265
2266void iwl_dump_nic_error_log(struct iwl_priv *priv)
2267{
2268 u32 data2, line;
2269 u32 desc, time, count, base, data1;
2270 u32 blink1, blink2, ilink1, ilink2;
461ef382 2271 u32 pc, hcmd;
b7a79404 2272
b2e640d4 2273 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2274 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2275 if (!base)
2276 base = priv->_agn.init_errlog_ptr;
2277 } else {
b7a79404 2278 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2279 if (!base)
2280 base = priv->_agn.inst_errlog_ptr;
2281 }
b7a79404
RC		 2282
2283 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2284 IWL_ERR(priv,
2285 "Not valid error log pointer 0x%08X for %s uCode\n",
2286 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2287 return;
2288 }
2289
2290 count = iwl_read_targ_mem(priv, base);
2291
2292 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2293 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2294 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2295 priv->status, count);
2296 }
2297
2298 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 2299 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2300 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2301 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2302 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2303 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2304 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2305 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2306 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2307 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2308 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2309
be1a71a1
JB		 2310 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2311 blink1, blink2, ilink1, ilink2);
2312
b7a79404
RC		 2313 IWL_ERR(priv, "Desc Time "
2314 "data1 data2 line\n");
2315 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
2316 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2317 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2318 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2319 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2320}
2321
2322#define EVENT_START_OFFSET (4 * sizeof(u32))
2323
2324/**
2325 * iwl_print_event_log - Dump error event log to syslog
2326 *
2327 */
b03d7d0f
WYG		 2328static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2329 u32 num_events, u32 mode,
2330 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2331{
2332 u32 i;
2333 u32 base; /* SRAM byte address of event log header */
2334 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2335 u32 ptr; /* SRAM byte address of log data */
2336 u32 ev, time, data; /* event log data */
e5854471 2337 unsigned long reg_flags;
b7a79404
RC		 2338
2339 if (num_events == 0)
b03d7d0f 2340 return pos;
b2e640d4
JB		 2341
2342 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2343 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2344 if (!base)
2345 base = priv->_agn.init_evtlog_ptr;
2346 } else {
b7a79404 2347 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2348 if (!base)
2349 base = priv->_agn.inst_evtlog_ptr;
2350 }
b7a79404
RC		 2351
2352 if (mode == 0)
2353 event_size = 2 * sizeof(u32);
2354 else
2355 event_size = 3 * sizeof(u32);
2356
2357 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2358
e5854471
BC		 2359 /* Make sure device is powered up for SRAM reads */
2360 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2361 iwl_grab_nic_access(priv);
2362
2363 /* Set starting address; reads will auto-increment */
2364 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2365 rmb();
2366
b7a79404
RC		 2367 /* "time" is actually "data" for mode 0 (no timestamp).
2368 * place event id # at far right for easier visual parsing. */
2369 for (i = 0; i < num_events; i++) {
e5854471
BC		 2370 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2371 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2372 if (mode == 0) {
2373 /* data, ev */
b03d7d0f
WYG		 2374 if (bufsz) {
2375 pos += scnprintf(*buf + pos, bufsz - pos,
2376 "EVT_LOG:0x%08x:%04u\n",
2377 time, ev);
2378 } else {
2379 trace_iwlwifi_dev_ucode_event(priv, 0,
2380 time, ev);
2381 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2382 time, ev);
2383 }
b7a79404 2384 } else {
e5854471 2385 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2386 if (bufsz) {
2387 pos += scnprintf(*buf + pos, bufsz - pos,
2388 "EVT_LOGT:%010u:0x%08x:%04u\n",
2389 time, data, ev);
2390 } else {
2391 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2392 time, data, ev);
b03d7d0f
WYG		 2393 trace_iwlwifi_dev_ucode_event(priv, time,
2394 data, ev);
2395 }
b7a79404
RC		 2396 }
2397 }
e5854471
BC		 2398
2399 /* Allow device to power down */
2400 iwl_release_nic_access(priv);
2401 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2402 return pos;
b7a79404
RC		 2403}
2404
c341ddb2
WYG		 2405/**
2406 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2407 */
b03d7d0f
WYG		 2408static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2409 u32 num_wraps, u32 next_entry,
2410 u32 size, u32 mode,
2411 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2412{
2413 /*
2414 * display the newest DEFAULT_LOG_ENTRIES entries
2415 * i.e the entries just before the next ont that uCode would fill.
2416 */
2417 if (num_wraps) {
2418 if (next_entry < size) {
b03d7d0f
WYG		 2419 pos = iwl_print_event_log(priv,
2420 capacity - (size - next_entry),
2421 size - next_entry, mode,
2422 pos, buf, bufsz);
2423 pos = iwl_print_event_log(priv, 0,
2424 next_entry, mode,
2425 pos, buf, bufsz);
c341ddb2 2426 } else
b03d7d0f
WYG		 2427 pos = iwl_print_event_log(priv, next_entry - size,
2428 size, mode, pos, buf, bufsz);
c341ddb2 2429 } else {
b03d7d0f
WYG		 2430 if (next_entry < size) {
2431 pos = iwl_print_event_log(priv, 0, next_entry,
2432 mode, pos, buf, bufsz);
2433 } else {
2434 pos = iwl_print_event_log(priv, next_entry - size,
2435 size, mode, pos, buf, bufsz);
2436 }
c341ddb2 2437 }
b03d7d0f 2438 return pos;
c341ddb2
WYG		 2439}
2440
c341ddb2
WYG		 2441#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2442
b03d7d0f
WYG		 2443int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2444 char **buf, bool display)
b7a79404
RC		 2445{
2446 u32 base; /* SRAM byte address of event log header */
2447 u32 capacity; /* event log capacity in # entries */
2448 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2449 u32 num_wraps; /* # times uCode wrapped to top of log */
2450 u32 next_entry; /* index of next entry to be written by uCode */
2451 u32 size; /* # entries that we'll print */
b2e640d4 2452 u32 logsize;
b03d7d0f
WYG		 2453 int pos = 0;
2454 size_t bufsz = 0;
b7a79404 2455
b2e640d4 2456 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2457 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2458 logsize = priv->_agn.init_evtlog_size;
2459 if (!base)
2460 base = priv->_agn.init_evtlog_ptr;
2461 } else {
b7a79404 2462 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2463 logsize = priv->_agn.inst_evtlog_size;
2464 if (!base)
2465 base = priv->_agn.inst_evtlog_ptr;
2466 }
b7a79404
RC		 2467
2468 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2469 IWL_ERR(priv,
2470 "Invalid event log pointer 0x%08X for %s uCode\n",
2471 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2472 return -EINVAL;
b7a79404
RC		 2473 }
2474
2475 /* event log header */
2476 capacity = iwl_read_targ_mem(priv, base);
2477 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2478 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2479 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2480
b2e640d4 2481 if (capacity > logsize) {
84c40692 2482 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2483 capacity, logsize);
2484 capacity = logsize;
84c40692
BC		 2485 }
2486
b2e640d4 2487 if (next_entry > logsize) {
84c40692 2488 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2489 next_entry, logsize);
2490 next_entry = logsize;
84c40692
BC		 2491 }
2492
b7a79404
RC		 2493 size = num_wraps ? capacity : next_entry;
2494
2495 /* bail out if nothing in log */
2496 if (size == 0) {
2497 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2498 return pos;
b7a79404
RC		 2499 }
2500
c341ddb2 2501#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2502 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2503 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2504 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2505#else
2506 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2507 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2508#endif
2509 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2510 size);
b7a79404 2511
c341ddb2 2512#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2513 if (display) {
2514 if (full_log)
2515 bufsz = capacity * 48;
2516 else
2517 bufsz = size * 48;
2518 *buf = kmalloc(bufsz, GFP_KERNEL);
2519 if (!*buf)
937c397e 2520 return -ENOMEM;
b03d7d0f 2521 }
c341ddb2
WYG		 2522 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2523 /*
2524 * if uCode has wrapped back to top of log,
2525 * start at the oldest entry,
2526 * i.e the next one that uCode would fill.
2527 */
2528 if (num_wraps)
b03d7d0f
WYG		 2529 pos = iwl_print_event_log(priv, next_entry,
2530 capacity - next_entry, mode,
2531 pos, buf, bufsz);
c341ddb2 2532 /* (then/else) start at top of log */
b03d7d0f
WYG		 2533 pos = iwl_print_event_log(priv, 0,
2534 next_entry, mode, pos, buf, bufsz);
c341ddb2 2535 } else
b03d7d0f
WYG		 2536 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2537 next_entry, size, mode,
2538 pos, buf, bufsz);
c341ddb2 2539#else
b03d7d0f
WYG		 2540 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2541 next_entry, size, mode,
2542 pos, buf, bufsz);
b7a79404 2543#endif
b03d7d0f 2544 return pos;
c341ddb2 2545}
b7a79404 2546
b481de9c 2547/**
4a4a9e81 2548 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2549 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2550 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2551 */
4a4a9e81 2552static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2553{
57aab75a 2554 int ret = 0;
b481de9c 2555
e1623446 2556 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2557
2558 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2559 /* We had an error bringing up the hardware, so take it
2560 * all the way back down so we can try again */
e1623446 2561 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2562 goto restart;
2563 }
2564
2565 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2566 * This is a paranoid check, because we would not have gotten the
2567 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2568 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2569 /* Runtime instruction load was bad;
2570 * take it all the way back down so we can try again */
e1623446 2571 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2572 goto restart;
2573 }
2574
57aab75a
TW		 2575 ret = priv->cfg->ops->lib->alive_notify(priv);
2576 if (ret) {
39aadf8c
WT		 2577 IWL_WARN(priv,
2578 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2579 goto restart;
2580 }
2581
5b9f8cd3 2582 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2583 set_bit(STATUS_ALIVE, &priv->status);
2584
b74e31a9
WYG		 2585 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2586 /* Enable timer to monitor the driver queues */
2587 mod_timer(&priv->monitor_recover,
2588 jiffies +
2589 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2590 }
2591
fee1247a 2592 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2593 return;
2594
36d6825b 2595 ieee80211_wake_queues(priv->hw);
b481de9c 2596
470ab2dd 2597 priv->active_rate = IWL_RATES_MASK;
b481de9c 2598
2f748dec
WYG		 2599 /* Configure Tx antenna selection based on H/W config */
2600 if (priv->cfg->ops->hcmd->set_tx_ant)
2601 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2602
3109ece1 2603 if (iwl_is_associated(priv)) {
c1adf9fb
GG		 2604 struct iwl_rxon_cmd *active_rxon =
2605 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA		 2606 /* apply any changes in staging */
2607 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2608 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2609 } else {
2610 /* Initialize our rx_config data */
1dda6d28 2611 iwl_connection_init_rx_config(priv, NULL);
45823531
AK		 2612
2613 if (priv->cfg->ops->hcmd->set_rxon_chain)
2614 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY		 2615 }
2616
9fbab516 2617 /* Configure Bluetooth device coexistence support */
65b52bde 2618 priv->cfg->ops->hcmd->send_bt_config(priv);
b481de9c 2619
4a4a9e81
TW		 2620 iwl_reset_run_time_calib(priv);
2621
b481de9c 2622 /* Configure the adapter for unassociated operation */
e0158e61 2623 iwlcore_commit_rxon(priv);
b481de9c
ZY		 2624
2625 /* At this point, the NIC is initialized and operational */
47f4a587 2626 iwl_rf_kill_ct_config(priv);
5a66926a 2627
e932a609 2628 iwl_leds_init(priv);
fe00b5a5 2629
e1623446 2630 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2631 set_bit(STATUS_READY, &priv->status);
5a66926a 2632 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2633
e312c24c 2634 iwl_power_update_mode(priv, true);
7e246191
RC		 2635 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2636
c46fbefa 2637
b481de9c
ZY		 2638 return;
2639
2640 restart:
2641 queue_work(priv->workqueue, &priv->restart);
2642}
2643
4e39317d 2644static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2645
5b9f8cd3 2646static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2647{
2648 unsigned long flags;
2649 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2650
e1623446 2651 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2652
b481de9c
ZY		 2653 if (!exit_pending)
2654 set_bit(STATUS_EXIT_PENDING, &priv->status);
2655
2c810ccd
JB		 2656 iwl_clear_ucode_stations(priv);
2657 iwl_dealloc_bcast_station(priv);
db125c78 2658 iwl_clear_driver_stations(priv);
b481de9c
ZY		 2659
2660 /* Unblock any waiting calls */
2661 wake_up_interruptible_all(&priv->wait_command_queue);
2662
b481de9c
ZY		 2663 /* Wipe out the EXIT_PENDING status bit if we are not actually
2664 * exiting the module */
2665 if (!exit_pending)
2666 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2667
2668 /* stop and reset the on-board processor */
3395f6e9 2669 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2670
2671 /* tell the device to stop sending interrupts */
0359facc 2672 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2673 iwl_disable_interrupts(priv);
0359facc
MA		 2674 spin_unlock_irqrestore(&priv->lock, flags);
2675 iwl_synchronize_irq(priv);
b481de9c
ZY		 2676
2677 if (priv->mac80211_registered)
2678 ieee80211_stop_queues(priv->hw);
2679
5b9f8cd3 2680 /* If we have not previously called iwl_init() then
a60e77e5 2681 * clear all bits but the RF Kill bit and return */
fee1247a 2682 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2683 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2684 STATUS_RF_KILL_HW |
9788864e
RC		 2685 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2686 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2687 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2688 STATUS_EXIT_PENDING;
b481de9c
ZY		 2689 goto exit;
2690 }
2691
6da3a13e 2692 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2693 * bit and continue taking the NIC down. */
b481de9c
ZY		 2694 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2695 STATUS_RF_KILL_HW |
9788864e
RC		 2696 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2697 STATUS_GEO_CONFIGURED |
b481de9c 2698 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2699 STATUS_FW_ERROR |
2700 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2701 STATUS_EXIT_PENDING;
b481de9c 2702
ef850d7c
MA		 2703 /* device going down, Stop using ICT table */
2704 iwl_disable_ict(priv);
b481de9c 2705
74bcdb33 2706 iwlagn_txq_ctx_stop(priv);
54b81550 2707 iwlagn_rxq_stop(priv);
b481de9c 2708
309e731a
BC		 2709 /* Power-down device's busmaster DMA clocks */
2710 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2711 udelay(5);
2712
309e731a
BC		 2713 /* Make sure (redundant) we've released our request to stay awake */
2714 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2715
4d2ccdb9
BC		 2716 /* Stop the device, and put it in low power state */
2717 priv->cfg->ops->lib->apm_ops.stop(priv);
2718
b481de9c 2719 exit:
885ba202 2720 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2721
2722 if (priv->ibss_beacon)
2723 dev_kfree_skb(priv->ibss_beacon);
2724 priv->ibss_beacon = NULL;
2725
2726 /* clear out any free frames */
fcab423d 2727 iwl_clear_free_frames(priv);
b481de9c
ZY		 2728}
2729
5b9f8cd3 2730static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2731{
2732 mutex_lock(&priv->mutex);
5b9f8cd3 2733 __iwl_down(priv);
b481de9c 2734 mutex_unlock(&priv->mutex);
b24d22b1 2735
4e39317d 2736 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2737}
2738
086ed117
MA		 2739#define HW_READY_TIMEOUT (50)
2740
2741static int iwl_set_hw_ready(struct iwl_priv *priv)
2742{
2743 int ret = 0;
2744
2745 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2746 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2747
2748 /* See if we got it */
2749 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2750 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2751 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2752 HW_READY_TIMEOUT);
2753 if (ret != -ETIMEDOUT)
2754 priv->hw_ready = true;
2755 else
2756 priv->hw_ready = false;
2757
2758 IWL_DEBUG_INFO(priv, "hardware %s\n",
2759 (priv->hw_ready == 1) ? "ready" : "not ready");
2760 return ret;
2761}
2762
2763static int iwl_prepare_card_hw(struct iwl_priv *priv)
2764{
2765 int ret = 0;
2766
91dd6c27 2767 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2768
3354a0f6
MA		 2769 ret = iwl_set_hw_ready(priv);
2770 if (priv->hw_ready)
2771 return ret;
2772
2773 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2774 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2775 CSR_HW_IF_CONFIG_REG_PREPARE);
2776
2777 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2778 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2779 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2780
3354a0f6 2781 /* HW should be ready by now, check again. */
086ed117
MA		 2782 if (ret != -ETIMEDOUT)
2783 iwl_set_hw_ready(priv);
2784
2785 return ret;
2786}
2787
b481de9c
ZY		 2788#define MAX_HW_RESTARTS 5
2789
5b9f8cd3 2790static int __iwl_up(struct iwl_priv *priv)
b481de9c 2791{
57aab75a
TW		 2792 int i;
2793 int ret;
b481de9c
ZY		 2794
2795 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2796 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2797 return -EIO;
2798 }
2799
e903fbd4 2800 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2801 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2802 return -EIO;
2803 }
2804
2c810ccd
JB		 2805 ret = iwl_alloc_bcast_station(priv, true);
2806 if (ret)
2807 return ret;
2808
086ed117
MA		 2809 iwl_prepare_card_hw(priv);
2810
2811 if (!priv->hw_ready) {
2812 IWL_WARN(priv, "Exit HW not ready\n");
2813 return -EIO;
2814 }
2815
e655b9f0 2816 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2817 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2818 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2819 else
e655b9f0 2820 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2821
c1842d61 2822 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 2823 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2824
5b9f8cd3 2825 iwl_enable_interrupts(priv);
a60e77e5 2826 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2827 return 0;
b481de9c
ZY		 2828 }
2829
3395f6e9 2830 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2831
74bcdb33 2832 ret = iwlagn_hw_nic_init(priv);
57aab75a 2833 if (ret) {
15b1687c 2834 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2835 return ret;
b481de9c
ZY		 2836 }
2837
2838 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2839 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2840 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 2841 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2842
2843 /* clear (again), then enable host interrupts */
3395f6e9 2844 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2845 iwl_enable_interrupts(priv);
b481de9c
ZY		 2846
2847 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2848 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2849 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2850
2851 /* Copy original ucode data image from disk into backup cache.
2852 * This will be used to initialize the on-board processor's
2853 * data SRAM for a clean start when the runtime program first loads. */
2854 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2855 priv->ucode_data.len);
b481de9c 2856
b481de9c
ZY		 2857 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2858
b481de9c
ZY		 2859 /* load bootstrap state machine,
2860 * load bootstrap program into processor's memory,
2861 * prepare to load the "initialize" uCode */
57aab75a 2862 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2863
57aab75a 2864 if (ret) {
15b1687c
WT		 2865 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2866 ret);
b481de9c
ZY		 2867 continue;
2868 }
2869
2870 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2871 iwl_nic_start(priv);
b481de9c 2872
e1623446 2873 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 2874
2875 return 0;
2876 }
2877
2878 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2879 __iwl_down(priv);
64e72c3e 2880 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 2881
2882 /* tried to restart and config the device for as long as our
2883 * patience could withstand */
15b1687c 2884 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 2885 return -EIO;
2886}
2887
2888
2889/*****************************************************************************
2890 *
2891 * Workqueue callbacks
2892 *
2893 *****************************************************************************/
2894
4a4a9e81 2895static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2896{
c79dd5b5
TW		 2897 struct iwl_priv *priv =
2898 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 2899
2900 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2901 return;
2902
2903 mutex_lock(&priv->mutex);
f3ccc08c 2904 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 2905 mutex_unlock(&priv->mutex);
2906}
2907
4a4a9e81 2908static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2909{
c79dd5b5
TW		 2910 struct iwl_priv *priv =
2911 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 2912
2913 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2914 return;
2915
258c44a0
MA		 2916 /* enable dram interrupt */
2917 iwl_reset_ict(priv);
2918
b481de9c 2919 mutex_lock(&priv->mutex);
4a4a9e81 2920 iwl_alive_start(priv);
b481de9c
ZY		 2921 mutex_unlock(&priv->mutex);
2922}
2923
16e727e8
EG		 2924static void iwl_bg_run_time_calib_work(struct work_struct *work)
2925{
2926 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2927 run_time_calib_work);
2928
2929 mutex_lock(&priv->mutex);
2930
2931 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2932 test_bit(STATUS_SCANNING, &priv->status)) {
2933 mutex_unlock(&priv->mutex);
2934 return;
2935 }
2936
2937 if (priv->start_calib) {
2daf6c15 2938 iwl_chain_noise_calibration(priv, &priv->statistics);
16e727e8 2939
2daf6c15 2940 iwl_sensitivity_calibration(priv, &priv->statistics);
16e727e8
EG		 2941 }
2942
2943 mutex_unlock(&priv->mutex);
16e727e8
EG		 2944}
2945
5b9f8cd3 2946static void iwl_bg_restart(struct work_struct *data)
b481de9c 2947{
c79dd5b5 2948 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 2949
2950 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2951 return;
2952
19cc1087
JB		 2953 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2954 mutex_lock(&priv->mutex);
2955 priv->vif = NULL;
2956 priv->is_open = 0;
2957 mutex_unlock(&priv->mutex);
2958 iwl_down(priv);
2959 ieee80211_restart_hw(priv->hw);
2960 } else {
2961 iwl_down(priv);
80676518
JB		 2962
2963 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2964 return;
2965
2966 mutex_lock(&priv->mutex);
2967 __iwl_up(priv);
2968 mutex_unlock(&priv->mutex);
19cc1087 2969 }
b481de9c
ZY		 2970}
2971
5b9f8cd3 2972static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2973{
c79dd5b5
TW		 2974 struct iwl_priv *priv =
2975 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 2976
2977 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2978 return;
2979
2980 mutex_lock(&priv->mutex);
54b81550 2981 iwlagn_rx_replenish(priv);
b481de9c
ZY		 2982 mutex_unlock(&priv->mutex);
2983}
2984
7878a5a4
MA		 2985#define IWL_DELAY_NEXT_SCAN (HZ*2)
2986
1dda6d28 2987void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 2988{
b481de9c 2989 struct ieee80211_conf *conf = NULL;
857485c0 2990 int ret = 0;
b481de9c 2991
1dda6d28
JB		 2992 if (!vif || !priv->is_open)
2993 return;
2994
2995 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 2996 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 2997 return;
2998 }
2999
b481de9c
ZY		 3000 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3001 return;
3002
2a421b91 3003 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3004
b481de9c
ZY		 3005 conf = ieee80211_get_hw_conf(priv->hw);
3006
3007 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3008 iwlcore_commit_rxon(priv);
b481de9c 3009
1dda6d28 3010 iwl_setup_rxon_timing(priv, vif);
857485c0 3011 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 3012 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 3013 if (ret)
39aadf8c 3014 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3015 "Attempting to continue.\n");
3016
3017 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3018
42eb7c64 3019 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3020
45823531
AK		 3021 if (priv->cfg->ops->hcmd->set_rxon_chain)
3022 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3023
1dda6d28 3024 priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3025
e1623446 3026 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3027 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3028
c213d745 3029 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3030 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3031 else
3032 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3033
3034 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3035 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3036 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
3037 else
3038 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3039 }
3040
e0158e61 3041 iwlcore_commit_rxon(priv);
b481de9c 3042
fe6b23dd 3043 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
1dda6d28 3044 vif->bss_conf.aid, priv->active_rxon.bssid_addr);
fe6b23dd 3045
1dda6d28 3046 switch (vif->type) {
05c914fe 3047 case NL80211_IFTYPE_STATION:
b481de9c 3048 break;
05c914fe 3049 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3050 iwl_send_beacon_cmd(priv);
b481de9c 3051 break;
b481de9c 3052 default:
15b1687c 3053 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3054 __func__, vif->type);
b481de9c
ZY		 3055 break;
3056 }
3057
04816448
GE		 3058 /* the chain noise calibration will enabled PM upon completion
3059 * If chain noise has already been run, then we need to enable
3060 * power management here */
3061 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3062 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3063
3064 /* Enable Rx differential gain and sensitivity calibrations */
3065 iwl_chain_noise_reset(priv);
3066 priv->start_calib = 1;
3067
508e32e1
RC		 3068}
3069
b481de9c
ZY		 3070/*****************************************************************************
3071 *
3072 * mac80211 entry point functions
3073 *
3074 *****************************************************************************/
3075
154b25ce 3076#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3077
f0b6e2e8
RC		 3078/*
3079 * Not a mac80211 entry point function, but it fits in with all the
3080 * other mac80211 functions grouped here.
3081 */
dd7a2509
JB		 3082static int iwl_mac_setup_register(struct iwl_priv *priv,
3083 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3084{
3085 int ret;
3086 struct ieee80211_hw *hw = priv->hw;
3087 hw->rate_control_algorithm = "iwl-agn-rs";
3088
3089 /* Tell mac80211 our characteristics */
3090 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8
RC		 3091 IEEE80211_HW_AMPDU_AGGREGATION |
3092 IEEE80211_HW_SPECTRUM_MGMT;
3093
3094 if (!priv->cfg->broken_powersave)
3095 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3096 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3097
ba37a3d0
JB		 3098 if (priv->cfg->sku & IWL_SKU_N)
3099 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3100 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3101
8d9698b3 3102 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3103 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3104
f0b6e2e8
RC		 3105 hw->wiphy->interface_modes =
3106 BIT(NL80211_IFTYPE_STATION) |
3107 BIT(NL80211_IFTYPE_ADHOC);
3108
f6c8f152 3109 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3110 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3111
3112 /*
3113 * For now, disable PS by default because it affects
3114 * RX performance significantly.
3115 */
5be83de5 3116 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3117
1382c71c 3118 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3119 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3120 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3121
3122 /* Default value; 4 EDCA QOS priorities */
3123 hw->queues = 4;
3124
3125 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3126
3127 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3128 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3129 &priv->bands[IEEE80211_BAND_2GHZ];
3130 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3131 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3132 &priv->bands[IEEE80211_BAND_5GHZ];
3133
3134 ret = ieee80211_register_hw(priv->hw);
3135 if (ret) {
3136 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3137 return ret;
3138 }
3139 priv->mac80211_registered = 1;
3140
3141 return 0;
3142}
3143
3144
5b9f8cd3 3145static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3146{
c79dd5b5 3147 struct iwl_priv *priv = hw->priv;
5a66926a 3148 int ret;
b481de9c 3149
e1623446 3150 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3151
3152 /* we should be verifying the device is ready to be opened */
3153 mutex_lock(&priv->mutex);
5b9f8cd3 3154 ret = __iwl_up(priv);
b481de9c 3155 mutex_unlock(&priv->mutex);
5a66926a 3156
e655b9f0 3157 if (ret)
6cd0b1cb 3158 return ret;
e655b9f0 3159
c1842d61
TW		 3160 if (iwl_is_rfkill(priv))
3161 goto out;
3162
e1623446 3163 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3164
fe9b6b72 3165 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3166 * mac80211 will not be run successfully. */
154b25ce
EG		 3167 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3168 test_bit(STATUS_READY, &priv->status),
3169 UCODE_READY_TIMEOUT);
3170 if (!ret) {
3171 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3172 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3173 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3174 return -ETIMEDOUT;
5a66926a 3175 }
fe9b6b72 3176 }
0a078ffa 3177
e932a609
JB		 3178 iwl_led_start(priv);
3179
c1842d61 3180out:
0a078ffa 3181 priv->is_open = 1;
e1623446 3182 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3183 return 0;
3184}
3185
5b9f8cd3 3186static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3187{
c79dd5b5 3188 struct iwl_priv *priv = hw->priv;
b481de9c 3189
e1623446 3190 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3191
19cc1087 3192 if (!priv->is_open)
e655b9f0 3193 return;
e655b9f0 3194
b481de9c 3195 priv->is_open = 0;
5a66926a 3196
5bddf549 3197 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY		 3198 /* stop mac, cancel any scan request and clear
3199 * RXON_FILTER_ASSOC_MSK BIT
3200 */
5a66926a 3201 mutex_lock(&priv->mutex);
2a421b91 3202 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3203 mutex_unlock(&priv->mutex);
fde3571f
MA		 3204 }
3205
5b9f8cd3 3206 iwl_down(priv);
5a66926a
ZY		 3207
3208 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3209
3210 /* enable interrupts again in order to receive rfkill changes */
3211 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3212 iwl_enable_interrupts(priv);
948c171c 3213
e1623446 3214 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3215}
3216
5b9f8cd3 3217static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3218{
c79dd5b5 3219 struct iwl_priv *priv = hw->priv;
b481de9c 3220
e1623446 3221 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3222
e1623446 3223 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3224 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3225
74bcdb33 3226 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3227 dev_kfree_skb_any(skb);
3228
e1623446 3229 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3230 return NETDEV_TX_OK;
b481de9c
ZY		 3231}
3232
1dda6d28 3233void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3234{
857485c0 3235 int ret = 0;
b481de9c 3236
d986bcd1 3237 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3238 return;
3239
3240 /* The following should be done only at AP bring up */
3195c1f3 3241 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 3242
3243 /* RXON - unassoc (to set timing command) */
3244 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3245 iwlcore_commit_rxon(priv);
b481de9c
ZY		 3246
3247 /* RXON Timing */
1dda6d28 3248 iwl_setup_rxon_timing(priv, vif);
857485c0 3249 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 3250 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 3251 if (ret)
39aadf8c 3252 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3253 "Attempting to continue.\n");
3254
f513dfff
DH		 3255 /* AP has all antennas */
3256 priv->chain_noise_data.active_chains =
3257 priv->hw_params.valid_rx_ant;
3258 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK		 3259 if (priv->cfg->ops->hcmd->set_rxon_chain)
3260 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c 3261
1dda6d28
JB		 3262 priv->staging_rxon.assoc_id = 0;
3263
c213d745 3264 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3265 priv->staging_rxon.flags |=
3266 RXON_FLG_SHORT_PREAMBLE_MSK;
3267 else
3268 priv->staging_rxon.flags &=
3269 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3270
3271 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3272 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3273 priv->staging_rxon.flags |=
3274 RXON_FLG_SHORT_SLOT_MSK;
3275 else
3276 priv->staging_rxon.flags &=
3277 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3278 }
3279 /* restore RXON assoc */
3280 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3281 iwlcore_commit_rxon(priv);
e1493deb 3282 }
5b9f8cd3 3283 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3284
3285 /* FIXME - we need to add code here to detect a totally new
3286 * configuration, reset the AP, unassoc, rxon timing, assoc,
3287 * clear sta table, add BCAST sta... */
3288}
3289
5b9f8cd3 3290static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3291 struct ieee80211_vif *vif,
3292 struct ieee80211_key_conf *keyconf,
3293 struct ieee80211_sta *sta,
3294 u32 iv32, u16 *phase1key)
ab885f8c 3295{
ab885f8c 3296
9f58671e 3297 struct iwl_priv *priv = hw->priv;
e1623446 3298 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3299
bdbb612f 3300 iwl_update_tkip_key(priv, keyconf, sta,
b3fbdcf4 3301 iv32, phase1key);
ab885f8c 3302
e1623446 3303 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3304}
3305
5b9f8cd3 3306static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3307 struct ieee80211_vif *vif,
3308 struct ieee80211_sta *sta,
b481de9c
ZY		 3309 struct ieee80211_key_conf *key)
3310{
c79dd5b5 3311 struct iwl_priv *priv = hw->priv;
42986796
WT		 3312 int ret;
3313 u8 sta_id;
3314 bool is_default_wep_key = false;
b481de9c 3315
e1623446 3316 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3317
90e8e424 3318 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3319 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3320 return -EOPNOTSUPP;
3321 }
b481de9c 3322
0af8bcae
JB		 3323 sta_id = iwl_sta_id_or_broadcast(priv, sta);
3324 if (sta_id == IWL_INVALID_STATION)
3325 return -EINVAL;
b481de9c 3326
6974e363 3327 mutex_lock(&priv->mutex);
2a421b91 3328 iwl_scan_cancel_timeout(priv, 100);
6974e363 3329
a90178fa
JB		 3330 /*
3331 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3332 * so far, we are in legacy wep mode (group key only), otherwise we are
3333 * in 1X mode.
a90178fa
JB		 3334 * In legacy wep mode, we use another host command to the uCode.
3335 */
3336 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
6974e363
EG		 3337 if (cmd == SET_KEY)
3338 is_default_wep_key = !priv->key_mapping_key;
3339 else
ccc038ab
EG		 3340 is_default_wep_key =
3341 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3342 }
052c4b9f 3343
b481de9c 3344 switch (cmd) {
deb09c43 3345 case SET_KEY:
6974e363
EG		 3346 if (is_default_wep_key)
3347 ret = iwl_set_default_wep_key(priv, key);
deb09c43 3348 else
7480513f 3349 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 3350
e1623446 3351 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3352 break;
3353 case DISABLE_KEY:
6974e363
EG		 3354 if (is_default_wep_key)
3355 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 3356 else
3ec47732 3357 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 3358
e1623446 3359 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3360 break;
3361 default:
deb09c43 3362 ret = -EINVAL;
b481de9c
ZY		 3363 }
3364
72e15d71 3365 mutex_unlock(&priv->mutex);
e1623446 3366 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3367
deb09c43 3368 return ret;
b481de9c
ZY		 3369}
3370
5b9f8cd3 3371static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3372 struct ieee80211_vif *vif,
832f47e3
JB		 3373 enum ieee80211_ampdu_mlme_action action,
3374 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3375{
3376 struct iwl_priv *priv = hw->priv;
5c2207c6 3377 int ret;
d783b061 3378
e1623446 3379 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3380 sta->addr, tid);
d783b061
TW		 3381
3382 if (!(priv->cfg->sku & IWL_SKU_N))
3383 return -EACCES;
3384
3385 switch (action) {
3386 case IEEE80211_AMPDU_RX_START:
e1623446 3387 IWL_DEBUG_HT(priv, "start Rx\n");
619753ff 3388 return iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
d783b061 3389 case IEEE80211_AMPDU_RX_STOP:
e1623446 3390 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3391 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6
WYG		 3392 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3393 return 0;
3394 else
3395 return ret;
d783b061 3396 case IEEE80211_AMPDU_TX_START:
e1623446 3397 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3398 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3399 if (ret == 0) {
3400 priv->_agn.agg_tids_count++;
3401 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3402 priv->_agn.agg_tids_count);
3403 }
3404 return ret;
d783b061 3405 case IEEE80211_AMPDU_TX_STOP:
e1623446 3406 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3407 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3408 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3409 priv->_agn.agg_tids_count--;
3410 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3411 priv->_agn.agg_tids_count);
3412 }
5c2207c6
WYG		 3413 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3414 return 0;
3415 else
3416 return ret;
f0527971
WYG		 3417 case IEEE80211_AMPDU_TX_OPERATIONAL:
3418 /* do nothing */
3419 return -EOPNOTSUPP;
d783b061 3420 default:
e1623446 3421 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW		 3422 return -EINVAL;
3423 break;
3424 }
3425 return 0;
3426}
9f58671e 3427
6ab10ff8
JB		 3428static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3429 struct ieee80211_vif *vif,
3430 enum sta_notify_cmd cmd,
3431 struct ieee80211_sta *sta)
3432{
3433 struct iwl_priv *priv = hw->priv;
3434 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3435 int sta_id;
3436
6ab10ff8 3437 switch (cmd) {
6ab10ff8
JB		 3438 case STA_NOTIFY_SLEEP:
3439 WARN_ON(!sta_priv->client);
3440 sta_priv->asleep = true;
3441 if (atomic_read(&sta_priv->pending_frames) > 0)
3442 ieee80211_sta_block_awake(hw, sta, true);
3443 break;
3444 case STA_NOTIFY_AWAKE:
3445 WARN_ON(!sta_priv->client);
49dcc819
DH		 3446 if (!sta_priv->asleep)
3447 break;
6ab10ff8 3448 sta_priv->asleep = false;
2a87c26b 3449 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3450 if (sta_id != IWL_INVALID_STATION)
3451 iwl_sta_modify_ps_wake(priv, sta_id);
3452 break;
3453 default:
3454 break;
3455 }
3456}
3457
fe6b23dd
RC		 3458static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3459 struct ieee80211_vif *vif,
3460 struct ieee80211_sta *sta)
3461{
3462 struct iwl_priv *priv = hw->priv;
3463 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
eafdfbd3 3464 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3465 int ret;
3466 u8 sta_id;
3467
fd1af15d
JB		 3468 sta_priv->common.sta_id = IWL_INVALID_STATION;
3469
fe6b23dd
RC		 3470 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3471 sta->addr);
3472
3473 atomic_set(&sta_priv->pending_frames, 0);
3474 if (vif->type == NL80211_IFTYPE_AP)
3475 sta_priv->client = true;
3476
3477 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3478 &sta_id);
3479 if (ret) {
3480 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3481 sta->addr, ret);
3482 /* Should we return success if return code is EEXIST ? */
3483 return ret;
3484 }
3485
fd1af15d
JB		 3486 sta_priv->common.sta_id = sta_id;
3487
fe6b23dd 3488 /* Initialize rate scaling */
91dd6c27 3489 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3490 sta->addr);
3491 iwl_rs_rate_init(priv, sta, sta_id);
3492
fd1af15d 3493 return 0;
fe6b23dd
RC		 3494}
3495
79d07325
WYG		 3496static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3497 struct ieee80211_channel_switch *ch_switch)
3498{
3499 struct iwl_priv *priv = hw->priv;
3500 const struct iwl_channel_info *ch_info;
3501 struct ieee80211_conf *conf = &hw->conf;
3502 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3503 u16 ch;
3504 unsigned long flags = 0;
3505
3506 IWL_DEBUG_MAC80211(priv, "enter\n");
3507
3508 if (iwl_is_rfkill(priv))
3509 goto out_exit;
3510
3511 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3512 test_bit(STATUS_SCANNING, &priv->status))
3513 goto out_exit;
3514
3515 if (!iwl_is_associated(priv))
3516 goto out_exit;
3517
3518 /* channel switch in progress */
3519 if (priv->switch_rxon.switch_in_progress == true)
3520 goto out_exit;
3521
3522 mutex_lock(&priv->mutex);
3523 if (priv->cfg->ops->lib->set_channel_switch) {
3524
3525 ch = ieee80211_frequency_to_channel(
3526 ch_switch->channel->center_freq);
3527 if (le16_to_cpu(priv->active_rxon.channel) != ch) {
3528 ch_info = iwl_get_channel_info(priv,
3529 conf->channel->band,
3530 ch);
3531 if (!is_channel_valid(ch_info)) {
3532 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3533 goto out;
3534 }
3535 spin_lock_irqsave(&priv->lock, flags);
3536
3537 priv->current_ht_config.smps = conf->smps_mode;
3538
3539 /* Configure HT40 channels */
3540 ht_conf->is_ht = conf_is_ht(conf);
3541 if (ht_conf->is_ht) {
3542 if (conf_is_ht40_minus(conf)) {
3543 ht_conf->extension_chan_offset =
3544 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3545 ht_conf->is_40mhz = true;
3546 } else if (conf_is_ht40_plus(conf)) {
3547 ht_conf->extension_chan_offset =
3548 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3549 ht_conf->is_40mhz = true;
3550 } else {
3551 ht_conf->extension_chan_offset =
3552 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3553 ht_conf->is_40mhz = false;
3554 }
3555 } else
3556 ht_conf->is_40mhz = false;
3557
3558 /* if we are switching from ht to 2.4 clear flags
3559 * from any ht related info since 2.4 does not
3560 * support ht */
3561 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
3562 priv->staging_rxon.flags = 0;
3563
3564 iwl_set_rxon_channel(priv, conf->channel);
3565 iwl_set_rxon_ht(priv, ht_conf);
3566 iwl_set_flags_for_band(priv, conf->channel->band,
3567 priv->vif);
3568 spin_unlock_irqrestore(&priv->lock, flags);
3569
3570 iwl_set_rate(priv);
3571 /*
3572 * at this point, staging_rxon has the
3573 * configuration for channel switch
3574 */
3575 if (priv->cfg->ops->lib->set_channel_switch(priv,
3576 ch_switch))
3577 priv->switch_rxon.switch_in_progress = false;
3578 }
3579 }
3580out:
3581 mutex_unlock(&priv->mutex);
3582out_exit:
3583 if (!priv->switch_rxon.switch_in_progress)
3584 ieee80211_chswitch_done(priv->vif, false);
3585 IWL_DEBUG_MAC80211(priv, "leave\n");
3586}
3587
b481de9c
ZY		 3588/*****************************************************************************
3589 *
3590 * driver setup and teardown
3591 *
3592 *****************************************************************************/
3593
4e39317d 3594static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3595{
d21050c7 3596 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3597
3598 init_waitqueue_head(&priv->wait_command_queue);
3599
5b9f8cd3
EG		 3600 INIT_WORK(&priv->restart, iwl_bg_restart);
3601 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3602 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3603 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW		 3604 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3605 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3606
2a421b91 3607 iwl_setup_scan_deferred_work(priv);
bb8c093b 3608
4e39317d
EG		 3609 if (priv->cfg->ops->lib->setup_deferred_work)
3610 priv->cfg->ops->lib->setup_deferred_work(priv);
3611
3612 init_timer(&priv->statistics_periodic);
3613 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3614 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3615
a9e1cb6a
WYG		 3616 init_timer(&priv->ucode_trace);
3617 priv->ucode_trace.data = (unsigned long)priv;
3618 priv->ucode_trace.function = iwl_bg_ucode_trace;
3619
b74e31a9
WYG		 3620 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3621 init_timer(&priv->monitor_recover);
3622 priv->monitor_recover.data = (unsigned long)priv;
3623 priv->monitor_recover.function =
3624 priv->cfg->ops->lib->recover_from_tx_stall;
3625 }
3626
ef850d7c
MA		 3627 if (!priv->cfg->use_isr_legacy)
3628 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3629 iwl_irq_tasklet, (unsigned long)priv);
3630 else
3631 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3632 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3633}
3634
4e39317d 3635static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3636{
4e39317d
EG		 3637 if (priv->cfg->ops->lib->cancel_deferred_work)
3638 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3639
3ae6a054 3640 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3641 cancel_delayed_work(&priv->scan_check);
88be0264 3642 cancel_work_sync(&priv->start_internal_scan);
b481de9c 3643 cancel_delayed_work(&priv->alive_start);
b481de9c 3644 cancel_work_sync(&priv->beacon_update);
4e39317d 3645 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3646 del_timer_sync(&priv->ucode_trace);
b74e31a9
WYG		 3647 if (priv->cfg->ops->lib->recover_from_tx_stall)
3648 del_timer_sync(&priv->monitor_recover);
b481de9c
ZY		 3649}
3650
89f186a8
RC		 3651static void iwl_init_hw_rates(struct iwl_priv *priv,
3652 struct ieee80211_rate *rates)
3653{
3654 int i;
3655
3656 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3657 rates[i].bitrate = iwl_rates[i].ieee * 5;
3658 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3659 rates[i].hw_value_short = i;
3660 rates[i].flags = 0;
3661 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3662 /*
3663 * If CCK != 1M then set short preamble rate flag.
3664 */
3665 rates[i].flags |=
3666 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3667 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3668 }
3669 }
3670}
3671
3672static int iwl_init_drv(struct iwl_priv *priv)
3673{
3674 int ret;
3675
3676 priv->ibss_beacon = NULL;
3677
89f186a8
RC		 3678 spin_lock_init(&priv->sta_lock);
3679 spin_lock_init(&priv->hcmd_lock);
3680
3681 INIT_LIST_HEAD(&priv->free_frames);
3682
3683 mutex_init(&priv->mutex);
d2dfe6df 3684 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3685
89f186a8
RC		 3686 priv->ieee_channels = NULL;
3687 priv->ieee_rates = NULL;
3688 priv->band = IEEE80211_BAND_2GHZ;
3689
3690 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3691 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3692 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3693 priv->_agn.agg_tids_count = 0;
89f186a8 3694
8a472da4
WYG		 3695 /* initialize force reset */
3696 priv->force_reset[IWL_RF_RESET].reset_duration =
3697 IWL_DELAY_NEXT_FORCE_RF_RESET;
3698 priv->force_reset[IWL_FW_RESET].reset_duration =
3699 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 3700
3701 /* Choose which receivers/antennas to use */
3702 if (priv->cfg->ops->hcmd->set_rxon_chain)
3703 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3704
3705 iwl_init_scan_params(priv);
3706
89f186a8
RC		 3707 /* Set the tx_power_user_lmt to the lowest power level
3708 * this value will get overwritten by channel max power avg
3709 * from eeprom */
b744cb79 3710 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 3711
3712 ret = iwl_init_channel_map(priv);
3713 if (ret) {
3714 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3715 goto err;
3716 }
3717
3718 ret = iwlcore_init_geos(priv);
3719 if (ret) {
3720 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3721 goto err_free_channel_map;
3722 }
3723 iwl_init_hw_rates(priv, priv->ieee_rates);
3724
3725 return 0;
3726
3727err_free_channel_map:
3728 iwl_free_channel_map(priv);
3729err:
3730 return ret;
3731}
3732
3733static void iwl_uninit_drv(struct iwl_priv *priv)
3734{
3735 iwl_calib_free_results(priv);
3736 iwlcore_free_geos(priv);
3737 iwl_free_channel_map(priv);
811ecc99 3738 kfree(priv->scan_cmd);
89f186a8
RC		 3739}
3740
5b9f8cd3
EG		 3741static struct ieee80211_ops iwl_hw_ops = {
3742 .tx = iwl_mac_tx,
3743 .start = iwl_mac_start,
3744 .stop = iwl_mac_stop,
3745 .add_interface = iwl_mac_add_interface,
3746 .remove_interface = iwl_mac_remove_interface,
3747 .config = iwl_mac_config,
5b9f8cd3
EG		 3748 .configure_filter = iwl_configure_filter,
3749 .set_key = iwl_mac_set_key,
3750 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 3751 .conf_tx = iwl_mac_conf_tx,
3752 .reset_tsf = iwl_mac_reset_tsf,
3753 .bss_info_changed = iwl_bss_info_changed,
3754 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 3755 .hw_scan = iwl_mac_hw_scan,
3756 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 3757 .sta_add = iwlagn_mac_sta_add,
3758 .sta_remove = iwl_mac_sta_remove,
79d07325 3759 .channel_switch = iwl_mac_channel_switch,
b481de9c
ZY		 3760};
3761
5b9f8cd3 3762static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 3763{
3764 int err = 0;
c79dd5b5 3765 struct iwl_priv *priv;
b481de9c 3766 struct ieee80211_hw *hw;
82b9a121 3767 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3768 unsigned long flags;
6cd0b1cb 3769 u16 pci_cmd;
30eabc17 3770 u8 perm_addr[ETH_ALEN];
b481de9c 3771
316c30d9
AK		 3772 /************************
3773 * 1. Allocating HW data
3774 ************************/
3775
6440adb5
CB		 3776 /* Disabling hardware scan means that mac80211 will perform scans
3777 * "the hard way", rather than using device's scan. */
1ea87396 3778 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3779 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK		 3780 dev_printk(KERN_DEBUG, &(pdev->dev),
3781 "Disabling hw_scan\n");
5b9f8cd3 3782 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 3783 }
3784
5b9f8cd3 3785 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3786 if (!hw) {
b481de9c
ZY		 3787 err = -ENOMEM;
3788 goto out;
3789 }
1d0a082d
AK		 3790 priv = hw->priv;
3791 /* At this point both hw and priv are allocated. */
3792
b481de9c
ZY		 3793 SET_IEEE80211_DEV(hw, &pdev->dev);
3794
e1623446 3795 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3796 priv->cfg = cfg;
b481de9c 3797 priv->pci_dev = pdev;
40cefda9 3798 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3799
20594eb0
WYG		 3800 if (iwl_alloc_traffic_mem(priv))
3801 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3802
316c30d9
AK		 3803 /**************************
3804 * 2. Initializing PCI bus
3805 **************************/
3806 if (pci_enable_device(pdev)) {
3807 err = -ENODEV;
3808 goto out_ieee80211_free_hw;
3809 }
3810
3811 pci_set_master(pdev);
3812
093d874c 3813 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3814 if (!err)
093d874c 3815 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3816 if (err) {
093d874c 3817 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3818 if (!err)
093d874c 3819 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3820 /* both attempts failed: */
316c30d9 3821 if (err) {
978785a3 3822 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3823 goto out_pci_disable_device;
cc2a8ea8 3824 }
316c30d9
AK		 3825 }
3826
3827 err = pci_request_regions(pdev, DRV_NAME);
3828 if (err)
3829 goto out_pci_disable_device;
3830
3831 pci_set_drvdata(pdev, priv);
3832
316c30d9
AK		 3833
3834 /***********************
3835 * 3. Read REV register
3836 ***********************/
3837 priv->hw_base = pci_iomap(pdev, 0, 0);
3838 if (!priv->hw_base) {
3839 err = -ENODEV;
3840 goto out_pci_release_regions;
3841 }
3842
e1623446 3843 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3844 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3845 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3846
731a29b7 3847 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 3848 * we should init now
3849 */
3850 spin_lock_init(&priv->reg_lock);
731a29b7 3851 spin_lock_init(&priv->lock);
4843b5a7
RC		 3852
3853 /*
3854 * stop and reset the on-board processor just in case it is in a
3855 * strange state ... like being left stranded by a primary kernel
3856 * and this is now the kdump kernel trying to start up
3857 */
3858 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3859
b661c819 3860 iwl_hw_detect(priv);
c11362c0 3861 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 3862 priv->cfg->name, priv->hw_rev);
316c30d9 3863
e7b63581
TW		 3864 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3865 * PCI Tx retries from interfering with C3 CPU state */
3866 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3867
086ed117
MA		 3868 iwl_prepare_card_hw(priv);
3869 if (!priv->hw_ready) {
3870 IWL_WARN(priv, "Failed, HW not ready\n");
3871 goto out_iounmap;
3872 }
3873
91238714
TW		 3874 /*****************
3875 * 4. Read EEPROM
3876 *****************/
316c30d9
AK		 3877 /* Read the EEPROM */
3878 err = iwl_eeprom_init(priv);
3879 if (err) {
15b1687c 3880 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 3881 goto out_iounmap;
3882 }
8614f360
TW		 3883 err = iwl_eeprom_check_version(priv);
3884 if (err)
c8f16138 3885 goto out_free_eeprom;
8614f360 3886
02883017 3887 /* extract MAC Address */
30eabc17
JB		 3888 iwl_eeprom_get_mac(priv, perm_addr);
3889 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", perm_addr);
3890 SET_IEEE80211_PERM_ADDR(priv->hw, perm_addr);
316c30d9
AK		 3891
3892 /************************
3893 * 5. Setup HW constants
3894 ************************/
da154e30 3895 if (iwl_set_hw_params(priv)) {
15b1687c 3896 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3897 goto out_free_eeprom;
316c30d9
AK		 3898 }
3899
3900 /*******************
6ba87956 3901 * 6. Setup priv
316c30d9 3902 *******************/
b481de9c 3903
6ba87956 3904 err = iwl_init_drv(priv);
bf85ea4f 3905 if (err)
399f4900 3906 goto out_free_eeprom;
bf85ea4f 3907 /* At this point both hw and priv are initialized. */
316c30d9 3908
316c30d9 3909 /********************
09f9bf79 3910 * 7. Setup services
316c30d9 3911 ********************/
0359facc 3912 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3913 iwl_disable_interrupts(priv);
0359facc 3914 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3915
6cd0b1cb
HS		 3916 pci_enable_msi(priv->pci_dev);
3917
ef850d7c
MA		 3918 iwl_alloc_isr_ict(priv);
3919 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3920 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 3921 if (err) {
3922 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3923 goto out_disable_msi;
3924 }
316c30d9 3925
4e39317d 3926 iwl_setup_deferred_work(priv);
653fa4a0 3927 iwl_setup_rx_handlers(priv);
316c30d9 3928
158bea07
JB		 3929 /*********************************************
3930 * 8. Enable interrupts and read RFKILL state
3931 *********************************************/
6ba87956 3932
6cd0b1cb
HS		 3933 /* enable interrupts if needed: hw bug w/a */
3934 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3935 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3936 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3937 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3938 }
3939
3940 iwl_enable_interrupts(priv);
3941
6cd0b1cb
HS		 3942 /* If platform's RF_KILL switch is NOT set to KILL */
3943 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3944 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3945 else
3946 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3947
a60e77e5
JB		 3948 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3949 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3950
58d0f361 3951 iwl_power_initialize(priv);
39b73fb1 3952 iwl_tt_initialize(priv);
158bea07 3953
a15707d8 3954 init_completion(&priv->_agn.firmware_loading_complete);
562db532 3955
b08dfd04 3956 err = iwl_request_firmware(priv, true);
158bea07 3957 if (err)
7d47618a 3958 goto out_destroy_workqueue;
158bea07 3959
b481de9c
ZY		 3960 return 0;
3961
7d47618a 3962 out_destroy_workqueue:
c8f16138
RC		 3963 destroy_workqueue(priv->workqueue);
3964 priv->workqueue = NULL;
795cc0ad 3965 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3966 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 3967 out_disable_msi:
3968 pci_disable_msi(priv->pci_dev);
6ba87956 3969 iwl_uninit_drv(priv);
073d3f5f
TW		 3970 out_free_eeprom:
3971 iwl_eeprom_free(priv);
b481de9c
ZY		 3972 out_iounmap:
3973 pci_iounmap(pdev, priv->hw_base);
3974 out_pci_release_regions:
316c30d9 3975 pci_set_drvdata(pdev, NULL);
623d563e 3976 pci_release_regions(pdev);
b481de9c
ZY		 3977 out_pci_disable_device:
3978 pci_disable_device(pdev);
b481de9c 3979 out_ieee80211_free_hw:
20594eb0 3980 iwl_free_traffic_mem(priv);
d7c76f4c 3981 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 3982 out:
3983 return err;
3984}
3985
5b9f8cd3 3986static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3987{
c79dd5b5 3988 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3989 unsigned long flags;
b481de9c
ZY		 3990
3991 if (!priv)
3992 return;
3993
a15707d8 3994 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 3995
e1623446 3996 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3997
67249625 3998 iwl_dbgfs_unregister(priv);
5b9f8cd3 3999 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4000
5b9f8cd3
EG		 4001 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4002 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4003 * we need to set STATUS_EXIT_PENDING bit.
4004 */
4005 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4006 if (priv->mac80211_registered) {
4007 ieee80211_unregister_hw(priv->hw);
4008 priv->mac80211_registered = 0;
0b124c31 4009 } else {
5b9f8cd3 4010 iwl_down(priv);
c4f55232
RR		 4011 }
4012
c166b25a
BC		 4013 /*
4014 * Make sure device is reset to low power before unloading driver.
4015 * This may be redundant with iwl_down(), but there are paths to
4016 * run iwl_down() without calling apm_ops.stop(), and there are
4017 * paths to avoid running iwl_down() at all before leaving driver.
4018 * This (inexpensive) call *makes sure* device is reset.
4019 */
4020 priv->cfg->ops->lib->apm_ops.stop(priv);
4021
39b73fb1
WYG		 4022 iwl_tt_exit(priv);
4023
0359facc
MA		 4024 /* make sure we flush any pending irq or
4025 * tasklet for the driver
4026 */
4027 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4028 iwl_disable_interrupts(priv);
0359facc
MA		 4029 spin_unlock_irqrestore(&priv->lock, flags);
4030
4031 iwl_synchronize_irq(priv);
4032
5b9f8cd3 4033 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4034
4035 if (priv->rxq.bd)
54b81550 4036 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4037 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4038
073d3f5f 4039 iwl_eeprom_free(priv);
b481de9c 4040
b481de9c 4041
948c171c
MA		 4042 /*netif_stop_queue(dev); */
4043 flush_workqueue(priv->workqueue);
4044
5b9f8cd3 4045 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4046 * priv->workqueue... so we can't take down the workqueue
4047 * until now... */
4048 destroy_workqueue(priv->workqueue);
4049 priv->workqueue = NULL;
20594eb0 4050 iwl_free_traffic_mem(priv);
b481de9c 4051
6cd0b1cb
HS		 4052 free_irq(priv->pci_dev->irq, priv);
4053 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4054 pci_iounmap(pdev, priv->hw_base);
4055 pci_release_regions(pdev);
4056 pci_disable_device(pdev);
4057 pci_set_drvdata(pdev, NULL);
4058
6ba87956 4059 iwl_uninit_drv(priv);
b481de9c 4060
ef850d7c
MA		 4061 iwl_free_isr_ict(priv);
4062
b481de9c
ZY		 4063 if (priv->ibss_beacon)
4064 dev_kfree_skb(priv->ibss_beacon);
4065
4066 ieee80211_free_hw(priv->hw);
4067}
4068
b481de9c
ZY		 4069
4070/*****************************************************************************
4071 *
4072 * driver and module entry point
4073 *
4074 *****************************************************************************/
4075
fed9017e 4076/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4077static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4078#ifdef CONFIG_IWL4965
fed9017e
RR		 4079 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4080 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4081#endif /* CONFIG_IWL4965 */
5a6a256e 4082#ifdef CONFIG_IWL5000
ac592574
WYG		 4083/* 5100 Series WiFi */
4084 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4085 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4086 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4087 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4088 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4089 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4090 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4091 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4092 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4093 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4094 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4095 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4096 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4097 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4098 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4099 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4100 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4101 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4102 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4103 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4104 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4105 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4106 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4107 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4108
4109/* 5300 Series WiFi */
4110 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4111 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4112 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4113 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4114 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4115 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4116 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4117 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4118 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4119 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4120 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4121 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4122
4123/* 5350 Series WiFi/WiMax */
4124 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4125 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4126 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4127
4128/* 5150 Series Wifi/WiMax */
4129 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4130 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4131 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4132 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4133 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4134 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4135
4136 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4137 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4138 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4139 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4140
4141/* 6x00 Series */
5953a62e
WYG		 4142 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4143 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4144 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4145 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4146 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4147 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4148 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4149 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4150 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4151 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4152
95b13014
SZ		 4153/* 6x00 Series Gen2a */
4154 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4155 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4156 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4157 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4158 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4159 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4160 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4161 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4162 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4163 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4164 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4165 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4166 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4167 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4168
4169/* 6x00 Series Gen2b */
4170 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4171 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4172 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4173 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4174 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4175 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4176 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4177 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4178 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4179 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4180 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4181 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4182 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4183 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4184 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4185 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4186 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4187 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4188 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4189 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4190 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4191 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4192 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4193 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4194 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4195 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4196 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4197 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4198
4199/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4200 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4201 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4202 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4203 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4204 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4205 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4206
77dcb6a9 4207/* 1000 Series WiFi */
4bd0914f
WYG		 4208 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4209 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4210 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4211 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4212 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4213 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4214 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4215 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4216 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4217 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4218 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4219 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 4220#endif /* CONFIG_IWL5000 */
7100e924 4221
fed9017e
RR		 4222 {0}
4223};
4224MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4225
4226static struct pci_driver iwl_driver = {
b481de9c 4227 .name = DRV_NAME,
fed9017e 4228 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4229 .probe = iwl_pci_probe,
4230 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4231#ifdef CONFIG_PM
5b9f8cd3
EG		 4232 .suspend = iwl_pci_suspend,
4233 .resume = iwl_pci_resume,
b481de9c
ZY		 4234#endif
4235};
4236
5b9f8cd3 4237static int __init iwl_init(void)
b481de9c
ZY		 4238{
4239
4240 int ret;
4241 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4242 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 4243
e227ceac 4244 ret = iwlagn_rate_control_register();
897e1cf2 4245 if (ret) {
a3139c59
SO		 4246 printk(KERN_ERR DRV_NAME
4247 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4248 return ret;
4249 }
4250
fed9017e 4251 ret = pci_register_driver(&iwl_driver);
b481de9c 4252 if (ret) {
a3139c59 4253 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4254 goto error_register;
b481de9c 4255 }
b481de9c
ZY		 4256
4257 return ret;
897e1cf2 4258
897e1cf2 4259error_register:
e227ceac 4260 iwlagn_rate_control_unregister();
897e1cf2 4261 return ret;
b481de9c
ZY		 4262}
4263
5b9f8cd3 4264static void __exit iwl_exit(void)
b481de9c 4265{
fed9017e 4266 pci_unregister_driver(&iwl_driver);
e227ceac 4267 iwlagn_rate_control_unregister();
b481de9c
ZY		 4268}
4269
5b9f8cd3
EG		 4270module_exit(iwl_exit);
4271module_init(iwl_init);
a562a9dd
RC		 4272
4273#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4274module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4275MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4276module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4277MODULE_PARM_DESC(debug, "debug output mask");
4278#endif
4279
2b068618
WYG		 4280module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4281MODULE_PARM_DESC(swcrypto50,
4282 "using crypto in software (default 0 [hardware]) (deprecated)");
4283module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4284MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4285module_param_named(queues_num50,
4286 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4287MODULE_PARM_DESC(queues_num50,
4288 "number of hw queues in 50xx series (deprecated)");
4289module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4290MODULE_PARM_DESC(queues_num, "number of hw queues.");
4291module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4292MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4293module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4294MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4295module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4296 int, S_IRUGO);
4297MODULE_PARM_DESC(amsdu_size_8K50,
4298 "enable 8K amsdu size in 50XX series (deprecated)");
4299module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4300 int, S_IRUGO);
4301MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4302module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4303MODULE_PARM_DESC(fw_restart50,
4304 "restart firmware in case of error (deprecated)");
4305module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4306MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4307module_param_named(
4308 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4309MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
dd7a2509
JB		 4310
4311module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4312 S_IRUGO);
4313MODULE_PARM_DESC(ucode_alternative,
4314 "specify ucode alternative to use from ucode file");
Linux kernel - Deliverables
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