Commit | Line | Data |
---|---|---|
df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
901069c7 | 5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
d43c36dc | 32 | #include <linux/sched.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
1d0a082d | 34 | #include <net/mac80211.h> |
df48c323 | 35 | |
6bc913bd | 36 | #include "iwl-eeprom.h" |
19335774 | 37 | #include "iwl-debug.h" |
df48c323 | 38 | #include "iwl-core.h" |
b661c819 | 39 | #include "iwl-io.h" |
5da4b55f | 40 | #include "iwl-power.h" |
c6baf7fb | 41 | #include "iwl-agn.h" |
48f20d35 | 42 | #include "iwl-shared.h" |
9d143e9a | 43 | #include "iwl-agn.h" |
bdfbf092 | 44 | #include "iwl-trans.h" |
df48c323 | 45 | |
57bd1bea | 46 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
57bd1bea | 47 | |
d9fe60de JB |
48 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
49 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
b39488a9 | 50 | static void iwl_init_ht_hw_capab(const struct iwl_priv *priv, |
d9fe60de | 51 | struct ieee80211_sta_ht_cap *ht_info, |
c7de35cd RR |
52 | enum ieee80211_band band) |
53 | { | |
39130df3 | 54 | u16 max_bit_rate = 0; |
d6189124 EG |
55 | u8 rx_chains_num = hw_params(priv).rx_chains_num; |
56 | u8 tx_chains_num = hw_params(priv).tx_chains_num; | |
39130df3 | 57 | |
c7de35cd | 58 | ht_info->cap = 0; |
d9fe60de | 59 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
c7de35cd | 60 | |
d9fe60de | 61 | ht_info->ht_supported = true; |
c7de35cd | 62 | |
38622419 DF |
63 | if (cfg(priv)->ht_params && |
64 | cfg(priv)->ht_params->ht_greenfield_support) | |
b261793d | 65 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; |
d9fe60de | 66 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; |
39130df3 | 67 | max_bit_rate = MAX_BIT_RATE_20_MHZ; |
d6189124 | 68 | if (hw_params(priv).ht40_channel & BIT(band)) { |
d9fe60de JB |
69 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
70 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
71 | ht_info->mcs.rx_mask[4] = 0x01; | |
39130df3 | 72 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 73 | } |
c7de35cd | 74 | |
9d143e9a | 75 | if (iwlagn_mod_params.amsdu_size_8K) |
d9fe60de | 76 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
c7de35cd RR |
77 | |
78 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
79 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
80 | ||
d9fe60de | 81 | ht_info->mcs.rx_mask[0] = 0xFF; |
39130df3 | 82 | if (rx_chains_num >= 2) |
d9fe60de | 83 | ht_info->mcs.rx_mask[1] = 0xFF; |
39130df3 | 84 | if (rx_chains_num >= 3) |
d9fe60de | 85 | ht_info->mcs.rx_mask[2] = 0xFF; |
39130df3 RR |
86 | |
87 | /* Highest supported Rx data rate */ | |
88 | max_bit_rate *= rx_chains_num; | |
d9fe60de JB |
89 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
90 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
39130df3 RR |
91 | |
92 | /* Tx MCS capabilities */ | |
d9fe60de | 93 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
39130df3 | 94 | if (tx_chains_num != rx_chains_num) { |
d9fe60de JB |
95 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
96 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << | |
97 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
39130df3 | 98 | } |
c7de35cd | 99 | } |
c7de35cd | 100 | |
c7de35cd | 101 | /** |
b39488a9 | 102 | * iwl_init_geos - Initialize mac80211's geo/channel info based from eeprom |
c7de35cd | 103 | */ |
b39488a9 | 104 | int iwl_init_geos(struct iwl_priv *priv) |
c7de35cd RR |
105 | { |
106 | struct iwl_channel_info *ch; | |
107 | struct ieee80211_supported_band *sband; | |
108 | struct ieee80211_channel *channels; | |
109 | struct ieee80211_channel *geo_ch; | |
110 | struct ieee80211_rate *rates; | |
111 | int i = 0; | |
75d80cad | 112 | s8 max_tx_power = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
c7de35cd RR |
113 | |
114 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
115 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
e1623446 | 116 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
63013ae3 | 117 | set_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status); |
c7de35cd RR |
118 | return 0; |
119 | } | |
120 | ||
7f90dce1 EG |
121 | channels = kcalloc(priv->channel_count, |
122 | sizeof(struct ieee80211_channel), GFP_KERNEL); | |
c7de35cd RR |
123 | if (!channels) |
124 | return -ENOMEM; | |
125 | ||
7f90dce1 | 126 | rates = kcalloc(IWL_RATE_COUNT_LEGACY, sizeof(struct ieee80211_rate), |
c7de35cd RR |
127 | GFP_KERNEL); |
128 | if (!rates) { | |
129 | kfree(channels); | |
130 | return -ENOMEM; | |
131 | } | |
132 | ||
133 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
134 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
135 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
136 | /* just OFDM */ | |
137 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
5027309b | 138 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE; |
c7de35cd | 139 | |
38622419 | 140 | if (cfg(priv)->sku & EEPROM_SKU_CAP_11N_ENABLE) |
b39488a9 | 141 | iwl_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 142 | IEEE80211_BAND_5GHZ); |
c7de35cd RR |
143 | |
144 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
145 | sband->channels = channels; | |
146 | /* OFDM & CCK */ | |
147 | sband->bitrates = rates; | |
5027309b | 148 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY; |
c7de35cd | 149 | |
38622419 | 150 | if (cfg(priv)->sku & EEPROM_SKU_CAP_11N_ENABLE) |
b39488a9 | 151 | iwl_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 152 | IEEE80211_BAND_2GHZ); |
c7de35cd RR |
153 | |
154 | priv->ieee_channels = channels; | |
155 | priv->ieee_rates = rates; | |
156 | ||
c7de35cd RR |
157 | for (i = 0; i < priv->channel_count; i++) { |
158 | ch = &priv->channel_info[i]; | |
159 | ||
160 | /* FIXME: might be removed if scan is OK */ | |
161 | if (!is_channel_valid(ch)) | |
162 | continue; | |
163 | ||
5a3a0352 | 164 | sband = &priv->bands[ch->band]; |
c7de35cd RR |
165 | |
166 | geo_ch = &sband->channels[sband->n_channels++]; | |
167 | ||
168 | geo_ch->center_freq = | |
5a3a0352 | 169 | ieee80211_channel_to_frequency(ch->channel, ch->band); |
c7de35cd RR |
170 | geo_ch->max_power = ch->max_power_avg; |
171 | geo_ch->max_antenna_gain = 0xff; | |
172 | geo_ch->hw_value = ch->channel; | |
173 | ||
174 | if (is_channel_valid(ch)) { | |
175 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
176 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
177 | ||
178 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
179 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
180 | ||
181 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
182 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
183 | ||
7aafef1c | 184 | geo_ch->flags |= ch->ht40_extension_channel; |
4d38c2e8 | 185 | |
75d80cad SG |
186 | if (ch->max_power_avg > max_tx_power) |
187 | max_tx_power = ch->max_power_avg; | |
c7de35cd RR |
188 | } else { |
189 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
190 | } | |
191 | ||
e1623446 | 192 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
193 | ch->channel, geo_ch->center_freq, |
194 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
195 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
196 | "restricted" : "valid", | |
197 | geo_ch->flags); | |
198 | } | |
199 | ||
75d80cad SG |
200 | priv->tx_power_device_lmt = max_tx_power; |
201 | priv->tx_power_user_lmt = max_tx_power; | |
202 | priv->tx_power_next = max_tx_power; | |
203 | ||
c7de35cd | 204 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
38622419 | 205 | cfg(priv)->sku & EEPROM_SKU_CAP_BAND_52GHZ) { |
19707bac | 206 | char buf[32]; |
62e73169 | 207 | bus_get_hw_id_string(bus(priv), buf, sizeof(buf)); |
978785a3 | 208 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
19707bac | 209 | "Please send your %s to maintainer.\n", buf); |
38622419 | 210 | cfg(priv)->sku &= ~EEPROM_SKU_CAP_BAND_52GHZ; |
c7de35cd RR |
211 | } |
212 | ||
978785a3 | 213 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
a3139c59 SO |
214 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
215 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
c7de35cd | 216 | |
63013ae3 | 217 | set_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status); |
c7de35cd RR |
218 | |
219 | return 0; | |
220 | } | |
221 | ||
222 | /* | |
b39488a9 | 223 | * iwl_free_geos - undo allocations in iwl_init_geos |
c7de35cd | 224 | */ |
b39488a9 | 225 | void iwl_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
226 | { |
227 | kfree(priv->ieee_channels); | |
228 | kfree(priv->ieee_rates); | |
63013ae3 | 229 | clear_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status); |
c7de35cd | 230 | } |
c7de35cd | 231 | |
7e6a5886 JB |
232 | static bool iwl_is_channel_extension(struct iwl_priv *priv, |
233 | enum ieee80211_band band, | |
234 | u16 channel, u8 extension_chan_offset) | |
47c5196e TW |
235 | { |
236 | const struct iwl_channel_info *ch_info; | |
237 | ||
238 | ch_info = iwl_get_channel_info(priv, band, channel); | |
239 | if (!is_channel_valid(ch_info)) | |
7e6a5886 | 240 | return false; |
47c5196e | 241 | |
d9fe60de | 242 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
7aafef1c | 243 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 244 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 245 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
7aafef1c | 246 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 247 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e | 248 | |
7e6a5886 | 249 | return false; |
47c5196e TW |
250 | } |
251 | ||
7e6a5886 JB |
252 | bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
253 | struct iwl_rxon_context *ctx, | |
254 | struct ieee80211_sta_ht_cap *ht_cap) | |
47c5196e | 255 | { |
7e6a5886 JB |
256 | if (!ctx->ht.enabled || !ctx->ht.is_40mhz) |
257 | return false; | |
47c5196e | 258 | |
7e6a5886 JB |
259 | /* |
260 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
a2b0f02e WYG |
261 | * the bit will not set if it is pure 40MHz case |
262 | */ | |
7e6a5886 JB |
263 | if (ht_cap && !ht_cap->ht_supported) |
264 | return false; | |
265 | ||
d73e4923 | 266 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1e4247d4 | 267 | if (priv->disable_ht40) |
7e6a5886 | 268 | return false; |
1e4247d4 | 269 | #endif |
7e6a5886 | 270 | |
611d3eb7 | 271 | return iwl_is_channel_extension(priv, priv->band, |
246ed355 | 272 | le16_to_cpu(ctx->staging.channel), |
7e6a5886 | 273 | ctx->ht.extension_chan_offset); |
47c5196e | 274 | } |
47c5196e | 275 | |
2c2f3b33 TW |
276 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
277 | { | |
ea196fdb JB |
278 | u16 new_val; |
279 | u16 beacon_factor; | |
280 | ||
281 | /* | |
282 | * If mac80211 hasn't given us a beacon interval, program | |
283 | * the default into the device (not checking this here | |
284 | * would cause the adjustment below to return the maximum | |
285 | * value, which may break PAN.) | |
286 | */ | |
287 | if (!beacon_val) | |
288 | return DEFAULT_BEACON_INTERVAL; | |
289 | ||
290 | /* | |
291 | * If the beacon interval we obtained from the peer | |
292 | * is too large, we'll have to wake up more often | |
293 | * (and in IBSS case, we'll beacon too much) | |
294 | * | |
295 | * For example, if max_beacon_val is 4096, and the | |
296 | * requested beacon interval is 7000, we'll have to | |
297 | * use 3500 to be able to wake up on the beacons. | |
298 | * | |
299 | * This could badly influence beacon detection stats. | |
300 | */ | |
2c2f3b33 TW |
301 | |
302 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
303 | new_val = beacon_val / beacon_factor; | |
304 | ||
305 | if (!new_val) | |
306 | new_val = max_beacon_val; | |
307 | ||
308 | return new_val; | |
309 | } | |
310 | ||
47313e34 | 311 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
2c2f3b33 TW |
312 | { |
313 | u64 tsf; | |
314 | s32 interval_tm, rem; | |
2c2f3b33 TW |
315 | struct ieee80211_conf *conf = NULL; |
316 | u16 beacon_int; | |
47313e34 | 317 | struct ieee80211_vif *vif = ctx->vif; |
2c2f3b33 | 318 | |
8c222544 | 319 | conf = &priv->hw->conf; |
2c2f3b33 | 320 | |
6ac2f839 | 321 | lockdep_assert_held(&priv->shrd->mutex); |
948f5a2f | 322 | |
246ed355 | 323 | memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
948f5a2f | 324 | |
246ed355 JB |
325 | ctx->timing.timestamp = cpu_to_le64(priv->timestamp); |
326 | ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
2c2f3b33 | 327 | |
47313e34 | 328 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; |
2c2f3b33 | 329 | |
47313e34 JB |
330 | /* |
331 | * TODO: For IBSS we need to get atim_window from mac80211, | |
332 | * for now just always use 0 | |
333 | */ | |
334 | ctx->timing.atim_window = 0; | |
2c2f3b33 | 335 | |
bde4530e | 336 | if (ctx->ctxid == IWL_RXON_CTX_PAN && |
f1f270b2 JB |
337 | (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) && |
338 | iwl_is_associated(priv, IWL_RXON_CTX_BSS) && | |
339 | priv->contexts[IWL_RXON_CTX_BSS].vif && | |
340 | priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) { | |
bde4530e JB |
341 | ctx->timing.beacon_interval = |
342 | priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; | |
343 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
f1f270b2 JB |
344 | } else if (ctx->ctxid == IWL_RXON_CTX_BSS && |
345 | iwl_is_associated(priv, IWL_RXON_CTX_PAN) && | |
346 | priv->contexts[IWL_RXON_CTX_PAN].vif && | |
347 | priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int && | |
348 | (!iwl_is_associated_ctx(ctx) || !ctx->vif || | |
349 | !ctx->vif->bss_conf.beacon_int)) { | |
350 | ctx->timing.beacon_interval = | |
351 | priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; | |
352 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
bde4530e JB |
353 | } else { |
354 | beacon_int = iwl_adjust_beacon_interval(beacon_int, | |
ab9e212e | 355 | IWL_MAX_UCODE_BEACON_INTERVAL * TIME_UNIT); |
bde4530e JB |
356 | ctx->timing.beacon_interval = cpu_to_le16(beacon_int); |
357 | } | |
2c2f3b33 | 358 | |
bbb05cb5 JB |
359 | ctx->beacon_int = beacon_int; |
360 | ||
2c2f3b33 | 361 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
f8525e55 | 362 | interval_tm = beacon_int * TIME_UNIT; |
2c2f3b33 | 363 | rem = do_div(tsf, interval_tm); |
246ed355 | 364 | ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
2c2f3b33 | 365 | |
47313e34 | 366 | ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; |
2491fa42 | 367 | |
2c2f3b33 TW |
368 | IWL_DEBUG_ASSOC(priv, |
369 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
246ed355 JB |
370 | le16_to_cpu(ctx->timing.beacon_interval), |
371 | le32_to_cpu(ctx->timing.beacon_init_val), | |
372 | le16_to_cpu(ctx->timing.atim_window)); | |
948f5a2f | 373 | |
e6bb4c9c | 374 | return iwl_trans_send_cmd_pdu(trans(priv), ctx->rxon_timing_cmd, |
e419d62d | 375 | CMD_SYNC, sizeof(ctx->timing), &ctx->timing); |
2c2f3b33 | 376 | } |
2c2f3b33 | 377 | |
246ed355 JB |
378 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx, |
379 | int hw_decrypt) | |
8ccde88a | 380 | { |
246ed355 | 381 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a SO |
382 | |
383 | if (hw_decrypt) | |
384 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
385 | else | |
386 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
387 | ||
388 | } | |
8ccde88a | 389 | |
dacefedb | 390 | /* validate RXON structure is valid */ |
246ed355 | 391 | int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
8ccde88a | 392 | { |
246ed355 | 393 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
c914ac26 | 394 | u32 errors = 0; |
8ccde88a SO |
395 | |
396 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
dacefedb JB |
397 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { |
398 | IWL_WARN(priv, "check 2.4G: wrong narrow\n"); | |
c914ac26 | 399 | errors |= BIT(0); |
dacefedb JB |
400 | } |
401 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
402 | IWL_WARN(priv, "check 2.4G: wrong radar\n"); | |
c914ac26 | 403 | errors |= BIT(1); |
dacefedb | 404 | } |
8ccde88a | 405 | } else { |
dacefedb JB |
406 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { |
407 | IWL_WARN(priv, "check 5.2G: not short slot!\n"); | |
c914ac26 | 408 | errors |= BIT(2); |
dacefedb JB |
409 | } |
410 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
411 | IWL_WARN(priv, "check 5.2G: CCK!\n"); | |
c914ac26 | 412 | errors |= BIT(3); |
dacefedb JB |
413 | } |
414 | } | |
415 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
416 | IWL_WARN(priv, "mac/bssid mcast!\n"); | |
c914ac26 | 417 | errors |= BIT(4); |
8ccde88a | 418 | } |
8ccde88a SO |
419 | |
420 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
dacefedb JB |
421 | if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 && |
422 | (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) { | |
423 | IWL_WARN(priv, "neither 1 nor 6 are basic\n"); | |
c914ac26 | 424 | errors |= BIT(5); |
dacefedb | 425 | } |
8ccde88a | 426 | |
dacefedb JB |
427 | if (le16_to_cpu(rxon->assoc_id) > 2007) { |
428 | IWL_WARN(priv, "aid > 2007\n"); | |
c914ac26 | 429 | errors |= BIT(6); |
dacefedb | 430 | } |
8ccde88a | 431 | |
dacefedb JB |
432 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) |
433 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
434 | IWL_WARN(priv, "CCK and short slot\n"); | |
c914ac26 | 435 | errors |= BIT(7); |
dacefedb | 436 | } |
8ccde88a | 437 | |
dacefedb JB |
438 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) |
439 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
440 | IWL_WARN(priv, "CCK and auto detect"); | |
c914ac26 | 441 | errors |= BIT(8); |
dacefedb | 442 | } |
8ccde88a | 443 | |
dacefedb JB |
444 | if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | |
445 | RXON_FLG_TGG_PROTECT_MSK)) == | |
446 | RXON_FLG_TGG_PROTECT_MSK) { | |
447 | IWL_WARN(priv, "TGg but no auto-detect\n"); | |
c914ac26 | 448 | errors |= BIT(9); |
dacefedb | 449 | } |
8ccde88a | 450 | |
c914ac26 JB |
451 | if (rxon->channel == 0) { |
452 | IWL_WARN(priv, "zero channel is invalid\n"); | |
453 | errors |= BIT(10); | |
8ccde88a | 454 | } |
c914ac26 JB |
455 | |
456 | WARN(errors, "Invalid RXON (%#x), channel %d", | |
457 | errors, le16_to_cpu(rxon->channel)); | |
458 | ||
459 | return errors ? -EINVAL : 0; | |
8ccde88a | 460 | } |
8ccde88a SO |
461 | |
462 | /** | |
463 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
464 | * @priv: staging_rxon is compared to active_rxon | |
465 | * | |
466 | * If the RXON structure is changing enough to require a new tune, | |
467 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
468 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
469 | */ | |
246ed355 JB |
470 | int iwl_full_rxon_required(struct iwl_priv *priv, |
471 | struct iwl_rxon_context *ctx) | |
8ccde88a | 472 | { |
246ed355 JB |
473 | const struct iwl_rxon_cmd *staging = &ctx->staging; |
474 | const struct iwl_rxon_cmd *active = &ctx->active; | |
475 | ||
476 | #define CHK(cond) \ | |
477 | if ((cond)) { \ | |
478 | IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \ | |
479 | return 1; \ | |
480 | } | |
481 | ||
482 | #define CHK_NEQ(c1, c2) \ | |
483 | if ((c1) != (c2)) { \ | |
484 | IWL_DEBUG_INFO(priv, "need full RXON - " \ | |
485 | #c1 " != " #c2 " - %d != %d\n", \ | |
486 | (c1), (c2)); \ | |
487 | return 1; \ | |
488 | } | |
8ccde88a SO |
489 | |
490 | /* These items are only settable from the full RXON command */ | |
246ed355 JB |
491 | CHK(!iwl_is_associated_ctx(ctx)); |
492 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); | |
493 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
494 | CHK(compare_ether_addr(staging->wlap_bssid_addr, | |
495 | active->wlap_bssid_addr)); | |
496 | CHK_NEQ(staging->dev_type, active->dev_type); | |
497 | CHK_NEQ(staging->channel, active->channel); | |
498 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
499 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
500 | active->ofdm_ht_single_stream_basic_rates); | |
501 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
502 | active->ofdm_ht_dual_stream_basic_rates); | |
503 | CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates, | |
504 | active->ofdm_ht_triple_stream_basic_rates); | |
505 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
8ccde88a SO |
506 | |
507 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
508 | * be updated with the RXON_ASSOC command -- however only some | |
509 | * flag transitions are allowed using RXON_ASSOC */ | |
510 | ||
511 | /* Check if we are not switching bands */ | |
246ed355 JB |
512 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, |
513 | active->flags & RXON_FLG_BAND_24G_MSK); | |
8ccde88a SO |
514 | |
515 | /* Check if we are switching association toggle */ | |
246ed355 JB |
516 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, |
517 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
518 | ||
519 | #undef CHK | |
520 | #undef CHK_NEQ | |
8ccde88a SO |
521 | |
522 | return 0; | |
523 | } | |
8ccde88a | 524 | |
246ed355 JB |
525 | static void _iwl_set_rxon_ht(struct iwl_priv *priv, |
526 | struct iwl_ht_config *ht_conf, | |
527 | struct iwl_rxon_context *ctx) | |
47c5196e | 528 | { |
246ed355 | 529 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
47c5196e | 530 | |
7e6a5886 | 531 | if (!ctx->ht.enabled) { |
a2b0f02e | 532 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 | 533 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
7aafef1c | 534 | RXON_FLG_HT40_PROT_MSK | |
42eb7c64 | 535 | RXON_FLG_HT_PROT_MSK); |
47c5196e | 536 | return; |
42eb7c64 | 537 | } |
47c5196e | 538 | |
7e6a5886 | 539 | /* FIXME: if the definition of ht.protection changed, the "translation" |
a2b0f02e WYG |
540 | * will be needed for rxon->flags |
541 | */ | |
7e6a5886 | 542 | rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); |
a2b0f02e WYG |
543 | |
544 | /* Set up channel bandwidth: | |
7aafef1c | 545 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
a2b0f02e WYG |
546 | /* clear the HT channel mode before set the mode */ |
547 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
548 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
7e6a5886 | 549 | if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) { |
7aafef1c | 550 | /* pure ht40 */ |
7e6a5886 | 551 | if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
a2b0f02e | 552 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
508b08e7 | 553 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 554 | switch (ctx->ht.extension_chan_offset) { |
508b08e7 WYG |
555 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
556 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
557 | break; | |
558 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
559 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
560 | break; | |
561 | } | |
562 | } else { | |
a2b0f02e | 563 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 564 | switch (ctx->ht.extension_chan_offset) { |
a2b0f02e WYG |
565 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
566 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
567 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
568 | break; | |
569 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
570 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
571 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
572 | break; | |
573 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
574 | default: | |
575 | /* channel location only valid if in Mixed mode */ | |
576 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
577 | break; | |
578 | } | |
579 | } | |
580 | } else { | |
581 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
582 | } |
583 | ||
e3f10cea | 584 | iwlagn_set_rxon_chain(priv, ctx); |
47c5196e | 585 | |
02bb1bea | 586 | IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 587 | "extension channel offset 0x%x\n", |
7e6a5886 JB |
588 | le32_to_cpu(rxon->flags), ctx->ht.protection, |
589 | ctx->ht.extension_chan_offset); | |
47c5196e | 590 | } |
246ed355 JB |
591 | |
592 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf) | |
593 | { | |
594 | struct iwl_rxon_context *ctx; | |
595 | ||
596 | for_each_context(priv, ctx) | |
597 | _iwl_set_rxon_ht(priv, ht_conf, ctx); | |
598 | } | |
47c5196e | 599 | |
246ed355 | 600 | /* Return valid, unused, channel for a passive scan to reset the RF */ |
14023641 | 601 | u8 iwl_get_single_channel_number(struct iwl_priv *priv, |
246ed355 | 602 | enum ieee80211_band band) |
14023641 AK |
603 | { |
604 | const struct iwl_channel_info *ch_info; | |
605 | int i; | |
606 | u8 channel = 0; | |
246ed355 JB |
607 | u8 min, max; |
608 | struct iwl_rxon_context *ctx; | |
14023641 | 609 | |
14023641 | 610 | if (band == IEEE80211_BAND_5GHZ) { |
246ed355 JB |
611 | min = 14; |
612 | max = priv->channel_count; | |
14023641 | 613 | } else { |
246ed355 JB |
614 | min = 0; |
615 | max = 14; | |
616 | } | |
617 | ||
618 | for (i = min; i < max; i++) { | |
619 | bool busy = false; | |
620 | ||
621 | for_each_context(priv, ctx) { | |
622 | busy = priv->channel_info[i].channel == | |
623 | le16_to_cpu(ctx->staging.channel); | |
624 | if (busy) | |
625 | break; | |
14023641 | 626 | } |
246ed355 JB |
627 | |
628 | if (busy) | |
629 | continue; | |
630 | ||
631 | channel = priv->channel_info[i].channel; | |
632 | ch_info = iwl_get_channel_info(priv, band, channel); | |
633 | if (is_channel_valid(ch_info)) | |
634 | break; | |
14023641 AK |
635 | } |
636 | ||
637 | return channel; | |
638 | } | |
14023641 | 639 | |
bf85ea4f | 640 | /** |
3edb5fd6 SZ |
641 | * iwl_set_rxon_channel - Set the band and channel values in staging RXON |
642 | * @ch: requested channel as a pointer to struct ieee80211_channel | |
bf85ea4f | 643 | |
bf85ea4f | 644 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
3edb5fd6 | 645 | * in the staging RXON flag structure based on the ch->band |
bf85ea4f | 646 | */ |
246ed355 JB |
647 | int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch, |
648 | struct iwl_rxon_context *ctx) | |
bf85ea4f | 649 | { |
17e72782 | 650 | enum ieee80211_band band = ch->band; |
81e95430 | 651 | u16 channel = ch->hw_value; |
17e72782 | 652 | |
246ed355 | 653 | if ((le16_to_cpu(ctx->staging.channel) == channel) && |
bf85ea4f AK |
654 | (priv->band == band)) |
655 | return 0; | |
656 | ||
246ed355 | 657 | ctx->staging.channel = cpu_to_le16(channel); |
bf85ea4f | 658 | if (band == IEEE80211_BAND_5GHZ) |
246ed355 | 659 | ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK; |
bf85ea4f | 660 | else |
246ed355 | 661 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
bf85ea4f AK |
662 | |
663 | priv->band = band; | |
664 | ||
e1623446 | 665 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f AK |
666 | |
667 | return 0; | |
668 | } | |
bf85ea4f | 669 | |
79d07325 | 670 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
246ed355 | 671 | struct iwl_rxon_context *ctx, |
79d07325 WYG |
672 | enum ieee80211_band band, |
673 | struct ieee80211_vif *vif) | |
8ccde88a SO |
674 | { |
675 | if (band == IEEE80211_BAND_5GHZ) { | |
246ed355 | 676 | ctx->staging.flags &= |
8ccde88a SO |
677 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
678 | | RXON_FLG_CCK_MSK); | |
246ed355 | 679 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a SO |
680 | } else { |
681 | /* Copied from iwl_post_associate() */ | |
c213d745 | 682 | if (vif && vif->bss_conf.use_short_slot) |
246ed355 | 683 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 684 | else |
246ed355 | 685 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 686 | |
246ed355 JB |
687 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
688 | ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
689 | ctx->staging.flags &= ~RXON_FLG_CCK_MSK; | |
8ccde88a SO |
690 | } |
691 | } | |
8ccde88a SO |
692 | |
693 | /* | |
694 | * initialize rxon structure with default values from eeprom | |
695 | */ | |
1dda6d28 | 696 | void iwl_connection_init_rx_config(struct iwl_priv *priv, |
d0fe478c | 697 | struct iwl_rxon_context *ctx) |
8ccde88a SO |
698 | { |
699 | const struct iwl_channel_info *ch_info; | |
700 | ||
246ed355 | 701 | memset(&ctx->staging, 0, sizeof(ctx->staging)); |
8ccde88a | 702 | |
d0fe478c JB |
703 | if (!ctx->vif) { |
704 | ctx->staging.dev_type = ctx->unused_devtype; | |
705 | } else switch (ctx->vif->type) { | |
8ccde88a | 706 | case NL80211_IFTYPE_AP: |
d0fe478c | 707 | ctx->staging.dev_type = ctx->ap_devtype; |
8ccde88a SO |
708 | break; |
709 | ||
710 | case NL80211_IFTYPE_STATION: | |
d0fe478c | 711 | ctx->staging.dev_type = ctx->station_devtype; |
246ed355 | 712 | ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; |
8ccde88a SO |
713 | break; |
714 | ||
715 | case NL80211_IFTYPE_ADHOC: | |
d0fe478c | 716 | ctx->staging.dev_type = ctx->ibss_devtype; |
246ed355 JB |
717 | ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; |
718 | ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
8ccde88a SO |
719 | RXON_FILTER_ACCEPT_GRP_MSK; |
720 | break; | |
721 | ||
8ccde88a | 722 | default: |
d0fe478c JB |
723 | IWL_ERR(priv, "Unsupported interface type %d\n", |
724 | ctx->vif->type); | |
8ccde88a SO |
725 | break; |
726 | } | |
727 | ||
728 | #if 0 | |
729 | /* TODO: Figure out when short_preamble would be set and cache from | |
730 | * that */ | |
731 | if (!hw_to_local(priv->hw)->short_preamble) | |
246ed355 | 732 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a | 733 | else |
246ed355 | 734 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a SO |
735 | #endif |
736 | ||
737 | ch_info = iwl_get_channel_info(priv, priv->band, | |
246ed355 | 738 | le16_to_cpu(ctx->active.channel)); |
8ccde88a SO |
739 | |
740 | if (!ch_info) | |
741 | ch_info = &priv->channel_info[0]; | |
742 | ||
246ed355 | 743 | ctx->staging.channel = cpu_to_le16(ch_info->channel); |
8ccde88a SO |
744 | priv->band = ch_info->band; |
745 | ||
d0fe478c | 746 | iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif); |
8ccde88a | 747 | |
246ed355 | 748 | ctx->staging.ofdm_basic_rates = |
8ccde88a | 749 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
246ed355 | 750 | ctx->staging.cck_basic_rates = |
8ccde88a SO |
751 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
752 | ||
a2b0f02e | 753 | /* clear both MIX and PURE40 mode flag */ |
246ed355 | 754 | ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | |
a2b0f02e | 755 | RXON_FLG_CHANNEL_MODE_PURE_40); |
d0fe478c JB |
756 | if (ctx->vif) |
757 | memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN); | |
7684c408 | 758 | |
246ed355 JB |
759 | ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff; |
760 | ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
761 | ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff; | |
8ccde88a | 762 | } |
8ccde88a | 763 | |
79d07325 | 764 | void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
765 | { |
766 | const struct ieee80211_supported_band *hw = NULL; | |
767 | struct ieee80211_rate *rate; | |
246ed355 | 768 | struct iwl_rxon_context *ctx; |
8ccde88a SO |
769 | int i; |
770 | ||
771 | hw = iwl_get_hw_mode(priv, priv->band); | |
772 | if (!hw) { | |
773 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
774 | return; | |
775 | } | |
776 | ||
777 | priv->active_rate = 0; | |
8ccde88a SO |
778 | |
779 | for (i = 0; i < hw->n_bitrates; i++) { | |
780 | rate = &(hw->bitrates[i]); | |
5027309b | 781 | if (rate->hw_value < IWL_RATE_COUNT_LEGACY) |
8ccde88a SO |
782 | priv->active_rate |= (1 << rate->hw_value); |
783 | } | |
784 | ||
4a02886b | 785 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate); |
8ccde88a | 786 | |
246ed355 JB |
787 | for_each_context(priv, ctx) { |
788 | ctx->staging.cck_basic_rates = | |
789 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
4a02886b | 790 | |
246ed355 JB |
791 | ctx->staging.ofdm_basic_rates = |
792 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
793 | } | |
8ccde88a | 794 | } |
79d07325 WYG |
795 | |
796 | void iwl_chswitch_done(struct iwl_priv *priv, bool is_success) | |
797 | { | |
8bd413e6 JB |
798 | /* |
799 | * MULTI-FIXME | |
ade4c649 | 800 | * See iwlagn_mac_channel_switch. |
8bd413e6 JB |
801 | */ |
802 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
803 | ||
63013ae3 | 804 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
79d07325 WYG |
805 | return; |
806 | ||
63013ae3 EG |
807 | if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, |
808 | &priv->shrd->status)) | |
8bd413e6 | 809 | ieee80211_chswitch_done(ctx->vif, is_success); |
79d07325 | 810 | } |
8ccde88a | 811 | |
8ccde88a | 812 | #ifdef CONFIG_IWLWIFI_DEBUG |
14991a9d EG |
813 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, |
814 | enum iwl_rxon_context_id ctxid) | |
8ccde88a | 815 | { |
522376d2 | 816 | struct iwl_rxon_context *ctx = &priv->contexts[ctxid]; |
246ed355 | 817 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a | 818 | |
e1623446 | 819 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
3d816c77 | 820 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
821 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
822 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
823 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 824 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
825 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
826 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 827 | rxon->ofdm_basic_rates); |
e1623446 TW |
828 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
829 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
830 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
831 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a | 832 | } |
6686d17e | 833 | #endif |
e649437f JB |
834 | |
835 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) | |
8ccde88a | 836 | { |
491bc292 WYG |
837 | unsigned int reload_msec; |
838 | unsigned long reload_jiffies; | |
839 | ||
8ccde88a | 840 | /* Set the FW error flag -- cleared on iwl_down */ |
63013ae3 | 841 | set_bit(STATUS_FW_ERROR, &priv->shrd->status); |
8ccde88a SO |
842 | |
843 | /* Cancel currently queued command. */ | |
63013ae3 | 844 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
8ccde88a | 845 | |
79e3b16b | 846 | iwl_abort_notification_waits(priv->shrd); |
e74fe233 | 847 | |
e649437f JB |
848 | /* Keep the restart process from trying to send host |
849 | * commands by clearing the ready bit */ | |
63013ae3 | 850 | clear_bit(STATUS_READY, &priv->shrd->status); |
e649437f | 851 | |
effd4d9a | 852 | wake_up(&priv->shrd->wait_command_queue); |
e649437f JB |
853 | |
854 | if (!ondemand) { | |
855 | /* | |
856 | * If firmware keep reloading, then it indicate something | |
857 | * serious wrong and firmware having problem to recover | |
858 | * from it. Instead of keep trying which will fill the syslog | |
859 | * and hang the system, let's just stop it | |
860 | */ | |
861 | reload_jiffies = jiffies; | |
862 | reload_msec = jiffies_to_msecs((long) reload_jiffies - | |
863 | (long) priv->reload_jiffies); | |
864 | priv->reload_jiffies = reload_jiffies; | |
865 | if (reload_msec <= IWL_MIN_RELOAD_DURATION) { | |
866 | priv->reload_count++; | |
867 | if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) { | |
868 | IWL_ERR(priv, "BUG_ON, Stop restarting\n"); | |
869 | return; | |
870 | } | |
871 | } else | |
872 | priv->reload_count = 0; | |
873 | } | |
874 | ||
63013ae3 | 875 | if (!test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) { |
9d143e9a | 876 | if (iwlagn_mod_params.restart_fw) { |
9ca06f0a | 877 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f | 878 | "Restarting adapter due to uCode error.\n"); |
74e28e44 | 879 | queue_work(priv->shrd->workqueue, &priv->restart); |
e649437f | 880 | } else |
9ca06f0a | 881 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f JB |
882 | "Detected FW error, but not restarting\n"); |
883 | } | |
884 | } | |
885 | ||
f8e200de | 886 | static int iwl_apm_stop_master(struct iwl_priv *priv) |
d68b603c | 887 | { |
5220af0c | 888 | int ret = 0; |
d68b603c | 889 | |
5220af0c | 890 | /* stop device's busmaster DMA activity */ |
83ed9015 | 891 | iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
d68b603c | 892 | |
83ed9015 EG |
893 | ret = iwl_poll_bit(bus(priv), CSR_RESET, |
894 | CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
d68b603c | 895 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
5220af0c BC |
896 | if (ret) |
897 | IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n"); | |
d68b603c | 898 | |
d68b603c AK |
899 | IWL_DEBUG_INFO(priv, "stop master\n"); |
900 | ||
5220af0c | 901 | return ret; |
d68b603c | 902 | } |
d68b603c AK |
903 | |
904 | void iwl_apm_stop(struct iwl_priv *priv) | |
905 | { | |
fadb3582 BC |
906 | IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n"); |
907 | ||
63013ae3 | 908 | clear_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status); |
9d39e5ba | 909 | |
5220af0c | 910 | /* Stop device's DMA activity */ |
d68b603c AK |
911 | iwl_apm_stop_master(priv); |
912 | ||
5220af0c | 913 | /* Reset the entire device */ |
83ed9015 | 914 | iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
d68b603c AK |
915 | |
916 | udelay(10); | |
5220af0c BC |
917 | |
918 | /* | |
919 | * Clear "initialization complete" bit to move adapter from | |
920 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
921 | */ | |
83ed9015 | 922 | iwl_clear_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
d68b603c | 923 | } |
d68b603c | 924 | |
fadb3582 BC |
925 | |
926 | /* | |
927 | * Start up NIC's basic functionality after it has been reset | |
928 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
929 | * NOTE: This does not load uCode nor start the embedded processor | |
930 | */ | |
931 | int iwl_apm_init(struct iwl_priv *priv) | |
932 | { | |
933 | int ret = 0; | |
fadb3582 BC |
934 | IWL_DEBUG_INFO(priv, "Init card's basic functions\n"); |
935 | ||
936 | /* | |
937 | * Use "set_bit" below rather than "write", to preserve any hardware | |
938 | * bits already set by default after reset. | |
939 | */ | |
940 | ||
941 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
83ed9015 | 942 | iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS, |
fadb3582 BC |
943 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
944 | ||
945 | /* | |
946 | * Disable L0s without affecting L1; | |
947 | * don't wait for ICH L0s (ICH bug W/A) | |
948 | */ | |
83ed9015 | 949 | iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS, |
fadb3582 BC |
950 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
951 | ||
952 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
83ed9015 | 953 | iwl_set_bit(bus(priv), CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
fadb3582 BC |
954 | |
955 | /* | |
956 | * Enable HAP INTA (interrupt from management bus) to | |
957 | * wake device's PCI Express link L1a -> L0s | |
fadb3582 | 958 | */ |
83ed9015 | 959 | iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG, |
fadb3582 BC |
960 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
961 | ||
26bfc0cf | 962 | bus_apm_config(bus(priv)); |
fadb3582 BC |
963 | |
964 | /* Configure analog phase-lock-loop before activating to D0A */ | |
38622419 | 965 | if (cfg(priv)->base_params->pll_cfg_val) |
83ed9015 | 966 | iwl_set_bit(bus(priv), CSR_ANA_PLL_CFG, |
38622419 | 967 | cfg(priv)->base_params->pll_cfg_val); |
fadb3582 BC |
968 | |
969 | /* | |
970 | * Set "initialization complete" bit to move adapter from | |
971 | * D0U* --> D0A* (powered-up active) state. | |
972 | */ | |
83ed9015 | 973 | iwl_set_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
fadb3582 BC |
974 | |
975 | /* | |
976 | * Wait for clock stabilization; once stabilized, access to | |
977 | * device-internal resources is supported, e.g. iwl_write_prph() | |
978 | * and accesses to uCode SRAM. | |
979 | */ | |
83ed9015 | 980 | ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL, |
fadb3582 BC |
981 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
982 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
983 | if (ret < 0) { | |
984 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); | |
985 | goto out; | |
986 | } | |
987 | ||
988 | /* | |
917b6777 | 989 | * Enable DMA clock and wait for it to stabilize. |
fadb3582 BC |
990 | * |
991 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
992 | * do not disable clocks. This preserves any hardware bits already | |
993 | * set by default in "CLK_CTRL_REG" after reset. | |
994 | */ | |
83ed9015 | 995 | iwl_write_prph(bus(priv), APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
fadb3582 BC |
996 | udelay(20); |
997 | ||
998 | /* Disable L1-Active */ | |
83ed9015 | 999 | iwl_set_bits_prph(bus(priv), APMG_PCIDEV_STT_REG, |
fadb3582 BC |
1000 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
1001 | ||
63013ae3 | 1002 | set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status); |
9d39e5ba | 1003 | |
fadb3582 BC |
1004 | out: |
1005 | return ret; | |
1006 | } | |
fadb3582 BC |
1007 | |
1008 | ||
630fe9b6 TW |
1009 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
1010 | { | |
a25a66ac SG |
1011 | int ret; |
1012 | s8 prev_tx_power; | |
f844a709 SG |
1013 | bool defer; |
1014 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
a25a66ac | 1015 | |
6ac2f839 | 1016 | lockdep_assert_held(&priv->shrd->mutex); |
a25a66ac SG |
1017 | |
1018 | if (priv->tx_power_user_lmt == tx_power && !force) | |
1019 | return 0; | |
1020 | ||
b744cb79 WYG |
1021 | if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) { |
1022 | IWL_WARN(priv, | |
1023 | "Requested user TXPOWER %d below lower limit %d.\n", | |
daf518de | 1024 | tx_power, |
b744cb79 | 1025 | IWLAGN_TX_POWER_TARGET_POWER_MIN); |
630fe9b6 TW |
1026 | return -EINVAL; |
1027 | } | |
1028 | ||
dc1b0973 | 1029 | if (tx_power > priv->tx_power_device_lmt) { |
08f2d58d WYG |
1030 | IWL_WARN(priv, |
1031 | "Requested user TXPOWER %d above upper limit %d.\n", | |
dc1b0973 | 1032 | tx_power, priv->tx_power_device_lmt); |
630fe9b6 TW |
1033 | return -EINVAL; |
1034 | } | |
1035 | ||
845a9c0d | 1036 | if (!iwl_is_ready_rf(priv->shrd)) |
a25a66ac | 1037 | return -EIO; |
630fe9b6 | 1038 | |
f844a709 SG |
1039 | /* scan complete and commit_rxon use tx_power_next value, |
1040 | * it always need to be updated for newest request */ | |
a25a66ac | 1041 | priv->tx_power_next = tx_power; |
f844a709 SG |
1042 | |
1043 | /* do not set tx power when scanning or channel changing */ | |
63013ae3 | 1044 | defer = test_bit(STATUS_SCANNING, &priv->shrd->status) || |
f844a709 SG |
1045 | memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)); |
1046 | if (defer && !force) { | |
1047 | IWL_DEBUG_INFO(priv, "Deferring tx power set\n"); | |
a25a66ac | 1048 | return 0; |
5eadd94b | 1049 | } |
630fe9b6 | 1050 | |
a25a66ac SG |
1051 | prev_tx_power = priv->tx_power_user_lmt; |
1052 | priv->tx_power_user_lmt = tx_power; | |
1053 | ||
5beaaf37 | 1054 | ret = iwlagn_send_tx_power(priv); |
a25a66ac SG |
1055 | |
1056 | /* if fail to set tx_power, restore the orig. tx power */ | |
1057 | if (ret) { | |
1058 | priv->tx_power_user_lmt = prev_tx_power; | |
1059 | priv->tx_power_next = prev_tx_power; | |
1060 | } | |
630fe9b6 TW |
1061 | return ret; |
1062 | } | |
630fe9b6 | 1063 | |
65b52bde | 1064 | void iwl_send_bt_config(struct iwl_priv *priv) |
17f841cd SO |
1065 | { |
1066 | struct iwl_bt_cmd bt_cmd = { | |
456d0f76 WYG |
1067 | .lead_time = BT_LEAD_TIME_DEF, |
1068 | .max_kill = BT_MAX_KILL_DEF, | |
17f841cd SO |
1069 | .kill_ack_mask = 0, |
1070 | .kill_cts_mask = 0, | |
1071 | }; | |
1072 | ||
b60eec9b | 1073 | if (!iwlagn_mod_params.bt_coex_active) |
06702a73 WYG |
1074 | bt_cmd.flags = BT_COEX_DISABLE; |
1075 | else | |
1076 | bt_cmd.flags = BT_COEX_ENABLE; | |
1077 | ||
f21dd005 | 1078 | priv->bt_enable_flag = bt_cmd.flags; |
06702a73 WYG |
1079 | IWL_DEBUG_INFO(priv, "BT coex %s\n", |
1080 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); | |
1081 | ||
e6bb4c9c | 1082 | if (iwl_trans_send_cmd_pdu(trans(priv), REPLY_BT_CONFIG, |
e419d62d | 1083 | CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd)) |
65b52bde | 1084 | IWL_ERR(priv, "failed to send BT Coex Config\n"); |
17f841cd | 1085 | } |
17f841cd | 1086 | |
ef8d5529 | 1087 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear) |
49ea8596 | 1088 | { |
ef8d5529 WYG |
1089 | struct iwl_statistics_cmd statistics_cmd = { |
1090 | .configuration_flags = | |
1091 | clear ? IWL_STATS_CONF_CLEAR_STATS : 0, | |
49ea8596 | 1092 | }; |
ef8d5529 WYG |
1093 | |
1094 | if (flags & CMD_ASYNC) | |
e6bb4c9c | 1095 | return iwl_trans_send_cmd_pdu(trans(priv), REPLY_STATISTICS_CMD, |
e419d62d | 1096 | CMD_ASYNC, |
ef8d5529 | 1097 | sizeof(struct iwl_statistics_cmd), |
e419d62d | 1098 | &statistics_cmd); |
ef8d5529 | 1099 | else |
e6bb4c9c | 1100 | return iwl_trans_send_cmd_pdu(trans(priv), REPLY_STATISTICS_CMD, |
e419d62d | 1101 | CMD_SYNC, |
ef8d5529 WYG |
1102 | sizeof(struct iwl_statistics_cmd), |
1103 | &statistics_cmd); | |
49ea8596 | 1104 | } |
7e8c519e | 1105 | |
488829f1 | 1106 | |
727882d6 | 1107 | |
d8052319 | 1108 | |
20594eb0 WYG |
1109 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1110 | ||
1111 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) | |
1112 | ||
1113 | void iwl_reset_traffic_log(struct iwl_priv *priv) | |
1114 | { | |
1115 | priv->tx_traffic_idx = 0; | |
1116 | priv->rx_traffic_idx = 0; | |
1117 | if (priv->tx_traffic) | |
1118 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1119 | if (priv->rx_traffic) | |
1120 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1121 | } | |
1122 | ||
1123 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) | |
1124 | { | |
1125 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; | |
1126 | ||
8f470ce3 | 1127 | if (iwl_get_debug_level(priv->shrd) & IWL_DL_TX) { |
20594eb0 WYG |
1128 | if (!priv->tx_traffic) { |
1129 | priv->tx_traffic = | |
1130 | kzalloc(traffic_size, GFP_KERNEL); | |
1131 | if (!priv->tx_traffic) | |
1132 | return -ENOMEM; | |
1133 | } | |
1134 | } | |
8f470ce3 | 1135 | if (iwl_get_debug_level(priv->shrd) & IWL_DL_RX) { |
20594eb0 WYG |
1136 | if (!priv->rx_traffic) { |
1137 | priv->rx_traffic = | |
1138 | kzalloc(traffic_size, GFP_KERNEL); | |
1139 | if (!priv->rx_traffic) | |
1140 | return -ENOMEM; | |
1141 | } | |
1142 | } | |
1143 | iwl_reset_traffic_log(priv); | |
1144 | return 0; | |
1145 | } | |
20594eb0 WYG |
1146 | |
1147 | void iwl_free_traffic_mem(struct iwl_priv *priv) | |
1148 | { | |
1149 | kfree(priv->tx_traffic); | |
1150 | priv->tx_traffic = NULL; | |
1151 | ||
1152 | kfree(priv->rx_traffic); | |
1153 | priv->rx_traffic = NULL; | |
1154 | } | |
20594eb0 WYG |
1155 | |
1156 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | |
1157 | u16 length, struct ieee80211_hdr *header) | |
1158 | { | |
1159 | __le16 fc; | |
1160 | u16 len; | |
1161 | ||
8f470ce3 | 1162 | if (likely(!(iwl_get_debug_level(priv->shrd) & IWL_DL_TX))) |
20594eb0 WYG |
1163 | return; |
1164 | ||
1165 | if (!priv->tx_traffic) | |
1166 | return; | |
1167 | ||
1168 | fc = header->frame_control; | |
1169 | if (ieee80211_is_data(fc)) { | |
1170 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1171 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1172 | memcpy((priv->tx_traffic + | |
1173 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1174 | header, len); | |
1175 | priv->tx_traffic_idx = | |
1176 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1177 | } | |
1178 | } | |
20594eb0 WYG |
1179 | |
1180 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | |
1181 | u16 length, struct ieee80211_hdr *header) | |
1182 | { | |
1183 | __le16 fc; | |
1184 | u16 len; | |
1185 | ||
8f470ce3 | 1186 | if (likely(!(iwl_get_debug_level(priv->shrd) & IWL_DL_RX))) |
20594eb0 WYG |
1187 | return; |
1188 | ||
1189 | if (!priv->rx_traffic) | |
1190 | return; | |
1191 | ||
1192 | fc = header->frame_control; | |
1193 | if (ieee80211_is_data(fc)) { | |
1194 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1195 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1196 | memcpy((priv->rx_traffic + | |
1197 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1198 | header, len); | |
1199 | priv->rx_traffic_idx = | |
1200 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1201 | } | |
1202 | } | |
22fdf3c9 WYG |
1203 | |
1204 | const char *get_mgmt_string(int cmd) | |
1205 | { | |
1206 | switch (cmd) { | |
1207 | IWL_CMD(MANAGEMENT_ASSOC_REQ); | |
1208 | IWL_CMD(MANAGEMENT_ASSOC_RESP); | |
1209 | IWL_CMD(MANAGEMENT_REASSOC_REQ); | |
1210 | IWL_CMD(MANAGEMENT_REASSOC_RESP); | |
1211 | IWL_CMD(MANAGEMENT_PROBE_REQ); | |
1212 | IWL_CMD(MANAGEMENT_PROBE_RESP); | |
1213 | IWL_CMD(MANAGEMENT_BEACON); | |
1214 | IWL_CMD(MANAGEMENT_ATIM); | |
1215 | IWL_CMD(MANAGEMENT_DISASSOC); | |
1216 | IWL_CMD(MANAGEMENT_AUTH); | |
1217 | IWL_CMD(MANAGEMENT_DEAUTH); | |
1218 | IWL_CMD(MANAGEMENT_ACTION); | |
1219 | default: | |
1220 | return "UNKNOWN"; | |
1221 | ||
1222 | } | |
1223 | } | |
1224 | ||
1225 | const char *get_ctrl_string(int cmd) | |
1226 | { | |
1227 | switch (cmd) { | |
1228 | IWL_CMD(CONTROL_BACK_REQ); | |
1229 | IWL_CMD(CONTROL_BACK); | |
1230 | IWL_CMD(CONTROL_PSPOLL); | |
1231 | IWL_CMD(CONTROL_RTS); | |
1232 | IWL_CMD(CONTROL_CTS); | |
1233 | IWL_CMD(CONTROL_ACK); | |
1234 | IWL_CMD(CONTROL_CFEND); | |
1235 | IWL_CMD(CONTROL_CFENDACK); | |
1236 | default: | |
1237 | return "UNKNOWN"; | |
1238 | ||
1239 | } | |
1240 | } | |
1241 | ||
7163b8a4 | 1242 | void iwl_clear_traffic_stats(struct iwl_priv *priv) |
22fdf3c9 WYG |
1243 | { |
1244 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); | |
22fdf3c9 WYG |
1245 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); |
1246 | } | |
1247 | ||
1248 | /* | |
1249 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will | |
1250 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. | |
1251 | * Use debugFs to display the rx/rx_statistics | |
1252 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL | |
1253 | * information will be recorded, but DATA pkt still will be recorded | |
1254 | * for the reason of iwl_led.c need to control the led blinking based on | |
1255 | * number of tx and rx data. | |
1256 | * | |
1257 | */ | |
1258 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) | |
1259 | { | |
1260 | struct traffic_stats *stats; | |
1261 | ||
1262 | if (is_tx) | |
1263 | stats = &priv->tx_stats; | |
1264 | else | |
1265 | stats = &priv->rx_stats; | |
1266 | ||
1267 | if (ieee80211_is_mgmt(fc)) { | |
1268 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1269 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
1270 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
1271 | break; | |
1272 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
1273 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
1274 | break; | |
1275 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
1276 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
1277 | break; | |
1278 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
1279 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
1280 | break; | |
1281 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
1282 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
1283 | break; | |
1284 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
1285 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
1286 | break; | |
1287 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
1288 | stats->mgmt[MANAGEMENT_BEACON]++; | |
1289 | break; | |
1290 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
1291 | stats->mgmt[MANAGEMENT_ATIM]++; | |
1292 | break; | |
1293 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
1294 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
1295 | break; | |
1296 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
1297 | stats->mgmt[MANAGEMENT_AUTH]++; | |
1298 | break; | |
1299 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
1300 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
1301 | break; | |
1302 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
1303 | stats->mgmt[MANAGEMENT_ACTION]++; | |
1304 | break; | |
1305 | } | |
1306 | } else if (ieee80211_is_ctl(fc)) { | |
1307 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1308 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
1309 | stats->ctrl[CONTROL_BACK_REQ]++; | |
1310 | break; | |
1311 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
1312 | stats->ctrl[CONTROL_BACK]++; | |
1313 | break; | |
1314 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
1315 | stats->ctrl[CONTROL_PSPOLL]++; | |
1316 | break; | |
1317 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
1318 | stats->ctrl[CONTROL_RTS]++; | |
1319 | break; | |
1320 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
1321 | stats->ctrl[CONTROL_CTS]++; | |
1322 | break; | |
1323 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
1324 | stats->ctrl[CONTROL_ACK]++; | |
1325 | break; | |
1326 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
1327 | stats->ctrl[CONTROL_CFEND]++; | |
1328 | break; | |
1329 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
1330 | stats->ctrl[CONTROL_CFENDACK]++; | |
1331 | break; | |
1332 | } | |
1333 | } else { | |
1334 | /* data */ | |
1335 | stats->data_cnt++; | |
1336 | stats->data_bytes += len; | |
1337 | } | |
1338 | } | |
20594eb0 WYG |
1339 | #endif |
1340 | ||
a93e7973 | 1341 | static void iwl_force_rf_reset(struct iwl_priv *priv) |
afbdd69a | 1342 | { |
63013ae3 | 1343 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
afbdd69a WYG |
1344 | return; |
1345 | ||
246ed355 | 1346 | if (!iwl_is_any_associated(priv)) { |
afbdd69a WYG |
1347 | IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n"); |
1348 | return; | |
1349 | } | |
1350 | /* | |
1351 | * There is no easy and better way to force reset the radio, | |
1352 | * the only known method is switching channel which will force to | |
1353 | * reset and tune the radio. | |
1354 | * Use internal short scan (single channel) operation to should | |
1355 | * achieve this objective. | |
1356 | * Driver should reset the radio when number of consecutive missed | |
1357 | * beacon, or any other uCode error condition detected. | |
1358 | */ | |
1359 | IWL_DEBUG_INFO(priv, "perform radio reset.\n"); | |
1360 | iwl_internal_short_hw_scan(priv); | |
afbdd69a | 1361 | } |
a93e7973 | 1362 | |
a93e7973 | 1363 | |
c04f9f22 | 1364 | int iwl_force_reset(struct iwl_priv *priv, int mode, bool external) |
a93e7973 | 1365 | { |
8a472da4 WYG |
1366 | struct iwl_force_reset *force_reset; |
1367 | ||
63013ae3 | 1368 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
a93e7973 WYG |
1369 | return -EINVAL; |
1370 | ||
8a472da4 WYG |
1371 | if (mode >= IWL_MAX_FORCE_RESET) { |
1372 | IWL_DEBUG_INFO(priv, "invalid reset request.\n"); | |
1373 | return -EINVAL; | |
1374 | } | |
1375 | force_reset = &priv->force_reset[mode]; | |
1376 | force_reset->reset_request_count++; | |
c04f9f22 WYG |
1377 | if (!external) { |
1378 | if (force_reset->last_force_reset_jiffies && | |
1379 | time_after(force_reset->last_force_reset_jiffies + | |
1380 | force_reset->reset_duration, jiffies)) { | |
1381 | IWL_DEBUG_INFO(priv, "force reset rejected\n"); | |
1382 | force_reset->reset_reject_count++; | |
1383 | return -EAGAIN; | |
1384 | } | |
a93e7973 | 1385 | } |
8a472da4 WYG |
1386 | force_reset->reset_success_count++; |
1387 | force_reset->last_force_reset_jiffies = jiffies; | |
a93e7973 | 1388 | IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode); |
a93e7973 WYG |
1389 | switch (mode) { |
1390 | case IWL_RF_RESET: | |
1391 | iwl_force_rf_reset(priv); | |
1392 | break; | |
1393 | case IWL_FW_RESET: | |
c04f9f22 WYG |
1394 | /* |
1395 | * if the request is from external(ex: debugfs), | |
1396 | * then always perform the request in regardless the module | |
1397 | * parameter setting | |
1398 | * if the request is from internal (uCode error or driver | |
1399 | * detect failure), then fw_restart module parameter | |
1400 | * need to be check before performing firmware reload | |
1401 | */ | |
9d143e9a | 1402 | if (!external && !iwlagn_mod_params.restart_fw) { |
c04f9f22 WYG |
1403 | IWL_DEBUG_INFO(priv, "Cancel firmware reload based on " |
1404 | "module parameter setting\n"); | |
1405 | break; | |
1406 | } | |
a93e7973 | 1407 | IWL_ERR(priv, "On demand firmware reload\n"); |
e649437f | 1408 | iwlagn_fw_error(priv, true); |
a93e7973 | 1409 | break; |
a93e7973 | 1410 | } |
a93e7973 WYG |
1411 | return 0; |
1412 | } | |
b74e31a9 | 1413 | |
d4daaea6 | 1414 | |
317d09f7 WYG |
1415 | int iwl_cmd_echo_test(struct iwl_priv *priv) |
1416 | { | |
7e4005cc | 1417 | int ret; |
317d09f7 WYG |
1418 | struct iwl_host_cmd cmd = { |
1419 | .id = REPLY_ECHO, | |
89db3b97 | 1420 | .len = { 0 }, |
317d09f7 WYG |
1421 | .flags = CMD_SYNC, |
1422 | }; | |
1423 | ||
7e4005cc WYG |
1424 | ret = iwl_trans_send_cmd(trans(priv), &cmd); |
1425 | if (ret) | |
1426 | IWL_ERR(priv, "echo testing fail: 0X%x\n", ret); | |
1427 | else | |
1428 | IWL_DEBUG_INFO(priv, "echo testing pass\n"); | |
1429 | return ret; | |
317d09f7 WYG |
1430 | } |
1431 | ||
f22be624 | 1432 | static inline int iwl_check_stuck_queue(struct iwl_priv *priv, int txq) |
b74e31a9 | 1433 | { |
f22be624 | 1434 | if (iwl_trans_check_stuck_queue(trans(priv), txq)) { |
317d09f7 | 1435 | int ret; |
317d09f7 | 1436 | ret = iwl_force_reset(priv, IWL_FW_RESET, false); |
22de94de | 1437 | return (ret == -EAGAIN) ? 0 : 1; |
b74e31a9 WYG |
1438 | } |
1439 | return 0; | |
1440 | } | |
1441 | ||
22de94de SG |
1442 | /* |
1443 | * Making watchdog tick be a quarter of timeout assure we will | |
1444 | * discover the queue hung between timeout and 1.25*timeout | |
1445 | */ | |
1446 | #define IWL_WD_TICK(timeout) ((timeout) / 4) | |
1447 | ||
1448 | /* | |
1449 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
1450 | * we reset the firmware. If everything is fine just rearm the timer. | |
1451 | */ | |
1452 | void iwl_bg_watchdog(unsigned long data) | |
b74e31a9 WYG |
1453 | { |
1454 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
1455 | int cnt; | |
22de94de | 1456 | unsigned long timeout; |
b74e31a9 | 1457 | |
63013ae3 | 1458 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
b74e31a9 WYG |
1459 | return; |
1460 | ||
46e7741e WYG |
1461 | if (iwl_is_rfkill(priv->shrd)) |
1462 | return; | |
1463 | ||
38622419 | 1464 | timeout = cfg(priv)->base_params->wd_timeout; |
22de94de SG |
1465 | if (timeout == 0) |
1466 | return; | |
1467 | ||
b74e31a9 | 1468 | /* monitor and check for stuck cmd queue */ |
cefeaa5f | 1469 | if (iwl_check_stuck_queue(priv, priv->shrd->cmd_queue)) |
b74e31a9 WYG |
1470 | return; |
1471 | ||
1472 | /* monitor and check for other stuck queues */ | |
246ed355 | 1473 | if (iwl_is_any_associated(priv)) { |
d6189124 | 1474 | for (cnt = 0; cnt < hw_params(priv).max_txq_num; cnt++) { |
b74e31a9 | 1475 | /* skip as we already checked the command queue */ |
cefeaa5f | 1476 | if (cnt == priv->shrd->cmd_queue) |
b74e31a9 WYG |
1477 | continue; |
1478 | if (iwl_check_stuck_queue(priv, cnt)) | |
1479 | return; | |
1480 | } | |
1481 | } | |
22de94de SG |
1482 | |
1483 | mod_timer(&priv->watchdog, jiffies + | |
1484 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
b74e31a9 | 1485 | } |
22de94de SG |
1486 | |
1487 | void iwl_setup_watchdog(struct iwl_priv *priv) | |
1488 | { | |
38622419 | 1489 | unsigned int timeout = cfg(priv)->base_params->wd_timeout; |
afbdd69a | 1490 | |
9995ffe5 WYG |
1491 | if (!iwlagn_mod_params.wd_disable) { |
1492 | /* use system default */ | |
38622419 | 1493 | if (timeout && !cfg(priv)->base_params->wd_disable) |
9995ffe5 WYG |
1494 | mod_timer(&priv->watchdog, |
1495 | jiffies + | |
1496 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1497 | else | |
1498 | del_timer(&priv->watchdog); | |
1499 | } else { | |
1500 | /* module parameter overwrite default configuration */ | |
1501 | if (timeout && iwlagn_mod_params.wd_disable == 2) | |
1502 | mod_timer(&priv->watchdog, | |
1503 | jiffies + | |
1504 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1505 | else | |
1506 | del_timer(&priv->watchdog); | |
1507 | } | |
22de94de | 1508 | } |
a0ee74cf | 1509 | |
8c222544 EG |
1510 | /** |
1511 | * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time | |
1512 | * @priv -- pointer to iwl_priv data structure | |
1513 | * @tsf_bits -- number of bits need to shift for masking) | |
1514 | */ | |
1515 | static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv, | |
1516 | u16 tsf_bits) | |
1517 | { | |
1518 | return (1 << tsf_bits) - 1; | |
1519 | } | |
1520 | ||
1521 | /** | |
1522 | * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time | |
1523 | * @priv -- pointer to iwl_priv data structure | |
1524 | * @tsf_bits -- number of bits need to shift for masking) | |
1525 | */ | |
1526 | static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv, | |
1527 | u16 tsf_bits) | |
1528 | { | |
1529 | return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; | |
1530 | } | |
1531 | ||
a0ee74cf WYG |
1532 | /* |
1533 | * extended beacon time format | |
1534 | * time in usec will be changed into a 32-bit value in extended:internal format | |
1535 | * the extended part is the beacon counts | |
1536 | * the internal part is the time in usec within one beacon interval | |
1537 | */ | |
1538 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval) | |
1539 | { | |
1540 | u32 quot; | |
1541 | u32 rem; | |
1542 | u32 interval = beacon_interval * TIME_UNIT; | |
1543 | ||
1544 | if (!interval || !usec) | |
1545 | return 0; | |
1546 | ||
1547 | quot = (usec / interval) & | |
403ba56a DF |
1548 | (iwl_beacon_time_mask_high(priv, IWLAGN_EXT_BEACON_TIME_POS) >> |
1549 | IWLAGN_EXT_BEACON_TIME_POS); | |
a0ee74cf | 1550 | rem = (usec % interval) & iwl_beacon_time_mask_low(priv, |
403ba56a | 1551 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1552 | |
403ba56a | 1553 | return (quot << IWLAGN_EXT_BEACON_TIME_POS) + rem; |
a0ee74cf | 1554 | } |
a0ee74cf WYG |
1555 | |
1556 | /* base is usually what we get from ucode with each received frame, | |
1557 | * the same as HW timer counter counting down | |
1558 | */ | |
1559 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | |
1560 | u32 addon, u32 beacon_interval) | |
1561 | { | |
1562 | u32 base_low = base & iwl_beacon_time_mask_low(priv, | |
403ba56a | 1563 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1564 | u32 addon_low = addon & iwl_beacon_time_mask_low(priv, |
403ba56a | 1565 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf WYG |
1566 | u32 interval = beacon_interval * TIME_UNIT; |
1567 | u32 res = (base & iwl_beacon_time_mask_high(priv, | |
403ba56a | 1568 | IWLAGN_EXT_BEACON_TIME_POS)) + |
a0ee74cf | 1569 | (addon & iwl_beacon_time_mask_high(priv, |
403ba56a | 1570 | IWLAGN_EXT_BEACON_TIME_POS)); |
a0ee74cf WYG |
1571 | |
1572 | if (base_low > addon_low) | |
1573 | res += base_low - addon_low; | |
1574 | else if (base_low < addon_low) { | |
1575 | res += interval + base_low - addon_low; | |
403ba56a | 1576 | res += (1 << IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1577 | } else |
403ba56a | 1578 | res += (1 << IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf WYG |
1579 | |
1580 | return cpu_to_le32(res); | |
1581 | } | |
a0ee74cf | 1582 | |
3e10caeb EG |
1583 | void iwl_set_hw_rfkill_state(struct iwl_priv *priv, bool state) |
1584 | { | |
1585 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, state); | |
1586 | } | |
7a10e3e4 EG |
1587 | |
1588 | void iwl_nic_config(struct iwl_priv *priv) | |
1589 | { | |
38622419 | 1590 | cfg(priv)->lib->nic_config(priv); |
7a10e3e4 | 1591 | } |
909e9b23 EG |
1592 | |
1593 | void iwl_free_skb(struct iwl_priv *priv, struct sk_buff *skb) | |
1594 | { | |
1595 | struct ieee80211_tx_info *info; | |
1596 | ||
1597 | info = IEEE80211_SKB_CB(skb); | |
1598 | kmem_cache_free(priv->tx_cmd_pool, (info->driver_data[1])); | |
1599 | dev_kfree_skb_any(skb); | |
1600 | } | |
859cfb0a EG |
1601 | |
1602 | void iwl_stop_sw_queue(struct iwl_priv *priv, u8 ac) | |
1603 | { | |
1604 | ieee80211_stop_queue(priv->hw, ac); | |
1605 | } | |
1606 | ||
1607 | void iwl_wake_sw_queue(struct iwl_priv *priv, u8 ac) | |
1608 | { | |
1609 | ieee80211_wake_queue(priv->hw, ac); | |
1610 | } |