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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
4e318262 | 5 | * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
d43c36dc | 32 | #include <linux/sched.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
1d0a082d | 34 | #include <net/mac80211.h> |
df48c323 | 35 | |
6bc913bd | 36 | #include "iwl-eeprom.h" |
19335774 | 37 | #include "iwl-debug.h" |
df48c323 | 38 | #include "iwl-core.h" |
b661c819 | 39 | #include "iwl-io.h" |
5da4b55f | 40 | #include "iwl-power.h" |
48f20d35 | 41 | #include "iwl-shared.h" |
9d143e9a | 42 | #include "iwl-agn.h" |
bdfbf092 | 43 | #include "iwl-trans.h" |
df48c323 | 44 | |
57bd1bea | 45 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
57bd1bea | 46 | |
d9fe60de JB |
47 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
48 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
b39488a9 | 49 | static void iwl_init_ht_hw_capab(const struct iwl_priv *priv, |
d9fe60de | 50 | struct ieee80211_sta_ht_cap *ht_info, |
c7de35cd RR |
51 | enum ieee80211_band band) |
52 | { | |
39130df3 | 53 | u16 max_bit_rate = 0; |
d6189124 EG |
54 | u8 rx_chains_num = hw_params(priv).rx_chains_num; |
55 | u8 tx_chains_num = hw_params(priv).tx_chains_num; | |
39130df3 | 56 | |
c7de35cd | 57 | ht_info->cap = 0; |
d9fe60de | 58 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
c7de35cd | 59 | |
d9fe60de | 60 | ht_info->ht_supported = true; |
c7de35cd | 61 | |
38622419 DF |
62 | if (cfg(priv)->ht_params && |
63 | cfg(priv)->ht_params->ht_greenfield_support) | |
b261793d | 64 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; |
d9fe60de | 65 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; |
39130df3 | 66 | max_bit_rate = MAX_BIT_RATE_20_MHZ; |
d6189124 | 67 | if (hw_params(priv).ht40_channel & BIT(band)) { |
d9fe60de JB |
68 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
69 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
70 | ht_info->mcs.rx_mask[4] = 0x01; | |
39130df3 | 71 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 72 | } |
c7de35cd | 73 | |
9d143e9a | 74 | if (iwlagn_mod_params.amsdu_size_8K) |
d9fe60de | 75 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
c7de35cd RR |
76 | |
77 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
78 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
79 | ||
d9fe60de | 80 | ht_info->mcs.rx_mask[0] = 0xFF; |
39130df3 | 81 | if (rx_chains_num >= 2) |
d9fe60de | 82 | ht_info->mcs.rx_mask[1] = 0xFF; |
39130df3 | 83 | if (rx_chains_num >= 3) |
d9fe60de | 84 | ht_info->mcs.rx_mask[2] = 0xFF; |
39130df3 RR |
85 | |
86 | /* Highest supported Rx data rate */ | |
87 | max_bit_rate *= rx_chains_num; | |
d9fe60de JB |
88 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
89 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
39130df3 RR |
90 | |
91 | /* Tx MCS capabilities */ | |
d9fe60de | 92 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
39130df3 | 93 | if (tx_chains_num != rx_chains_num) { |
d9fe60de JB |
94 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
95 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << | |
96 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
39130df3 | 97 | } |
c7de35cd | 98 | } |
c7de35cd | 99 | |
c7de35cd | 100 | /** |
b39488a9 | 101 | * iwl_init_geos - Initialize mac80211's geo/channel info based from eeprom |
c7de35cd | 102 | */ |
b39488a9 | 103 | int iwl_init_geos(struct iwl_priv *priv) |
c7de35cd RR |
104 | { |
105 | struct iwl_channel_info *ch; | |
106 | struct ieee80211_supported_band *sband; | |
107 | struct ieee80211_channel *channels; | |
108 | struct ieee80211_channel *geo_ch; | |
109 | struct ieee80211_rate *rates; | |
110 | int i = 0; | |
75d80cad | 111 | s8 max_tx_power = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
c7de35cd RR |
112 | |
113 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
114 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
e1623446 | 115 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
83626404 | 116 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
c7de35cd RR |
117 | return 0; |
118 | } | |
119 | ||
7f90dce1 EG |
120 | channels = kcalloc(priv->channel_count, |
121 | sizeof(struct ieee80211_channel), GFP_KERNEL); | |
c7de35cd RR |
122 | if (!channels) |
123 | return -ENOMEM; | |
124 | ||
7f90dce1 | 125 | rates = kcalloc(IWL_RATE_COUNT_LEGACY, sizeof(struct ieee80211_rate), |
c7de35cd RR |
126 | GFP_KERNEL); |
127 | if (!rates) { | |
128 | kfree(channels); | |
129 | return -ENOMEM; | |
130 | } | |
131 | ||
132 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
133 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
134 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
135 | /* just OFDM */ | |
136 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
5027309b | 137 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE; |
c7de35cd | 138 | |
54708d8d | 139 | if (hw_params(priv).sku & EEPROM_SKU_CAP_11N_ENABLE) |
b39488a9 | 140 | iwl_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 141 | IEEE80211_BAND_5GHZ); |
c7de35cd RR |
142 | |
143 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
144 | sband->channels = channels; | |
145 | /* OFDM & CCK */ | |
146 | sband->bitrates = rates; | |
5027309b | 147 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY; |
c7de35cd | 148 | |
54708d8d | 149 | if (hw_params(priv).sku & EEPROM_SKU_CAP_11N_ENABLE) |
b39488a9 | 150 | iwl_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 151 | IEEE80211_BAND_2GHZ); |
c7de35cd RR |
152 | |
153 | priv->ieee_channels = channels; | |
154 | priv->ieee_rates = rates; | |
155 | ||
c7de35cd RR |
156 | for (i = 0; i < priv->channel_count; i++) { |
157 | ch = &priv->channel_info[i]; | |
158 | ||
159 | /* FIXME: might be removed if scan is OK */ | |
160 | if (!is_channel_valid(ch)) | |
161 | continue; | |
162 | ||
5a3a0352 | 163 | sband = &priv->bands[ch->band]; |
c7de35cd RR |
164 | |
165 | geo_ch = &sband->channels[sband->n_channels++]; | |
166 | ||
167 | geo_ch->center_freq = | |
5a3a0352 | 168 | ieee80211_channel_to_frequency(ch->channel, ch->band); |
c7de35cd RR |
169 | geo_ch->max_power = ch->max_power_avg; |
170 | geo_ch->max_antenna_gain = 0xff; | |
171 | geo_ch->hw_value = ch->channel; | |
172 | ||
173 | if (is_channel_valid(ch)) { | |
174 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
175 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
176 | ||
177 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
178 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
179 | ||
180 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
181 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
182 | ||
7aafef1c | 183 | geo_ch->flags |= ch->ht40_extension_channel; |
4d38c2e8 | 184 | |
75d80cad SG |
185 | if (ch->max_power_avg > max_tx_power) |
186 | max_tx_power = ch->max_power_avg; | |
c7de35cd RR |
187 | } else { |
188 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
189 | } | |
190 | ||
e1623446 | 191 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
192 | ch->channel, geo_ch->center_freq, |
193 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
194 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
195 | "restricted" : "valid", | |
196 | geo_ch->flags); | |
197 | } | |
198 | ||
75d80cad SG |
199 | priv->tx_power_device_lmt = max_tx_power; |
200 | priv->tx_power_user_lmt = max_tx_power; | |
201 | priv->tx_power_next = max_tx_power; | |
202 | ||
c7de35cd | 203 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
54708d8d | 204 | hw_params(priv).sku & EEPROM_SKU_CAP_BAND_52GHZ) { |
978785a3 | 205 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
9ca85961 EG |
206 | "Please send your %s to maintainer.\n", |
207 | trans(priv)->hw_id_str); | |
54708d8d | 208 | hw_params(priv).sku &= ~EEPROM_SKU_CAP_BAND_52GHZ; |
c7de35cd RR |
209 | } |
210 | ||
978785a3 | 211 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
a3139c59 SO |
212 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
213 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
c7de35cd | 214 | |
83626404 | 215 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
c7de35cd RR |
216 | |
217 | return 0; | |
218 | } | |
219 | ||
220 | /* | |
b39488a9 | 221 | * iwl_free_geos - undo allocations in iwl_init_geos |
c7de35cd | 222 | */ |
b39488a9 | 223 | void iwl_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
224 | { |
225 | kfree(priv->ieee_channels); | |
226 | kfree(priv->ieee_rates); | |
83626404 | 227 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); |
c7de35cd | 228 | } |
c7de35cd | 229 | |
7e6a5886 JB |
230 | static bool iwl_is_channel_extension(struct iwl_priv *priv, |
231 | enum ieee80211_band band, | |
232 | u16 channel, u8 extension_chan_offset) | |
47c5196e TW |
233 | { |
234 | const struct iwl_channel_info *ch_info; | |
235 | ||
236 | ch_info = iwl_get_channel_info(priv, band, channel); | |
237 | if (!is_channel_valid(ch_info)) | |
7e6a5886 | 238 | return false; |
47c5196e | 239 | |
d9fe60de | 240 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
7aafef1c | 241 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 242 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 243 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
7aafef1c | 244 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 245 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e | 246 | |
7e6a5886 | 247 | return false; |
47c5196e TW |
248 | } |
249 | ||
7e6a5886 JB |
250 | bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
251 | struct iwl_rxon_context *ctx, | |
252 | struct ieee80211_sta_ht_cap *ht_cap) | |
47c5196e | 253 | { |
7e6a5886 JB |
254 | if (!ctx->ht.enabled || !ctx->ht.is_40mhz) |
255 | return false; | |
47c5196e | 256 | |
7e6a5886 JB |
257 | /* |
258 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
a2b0f02e WYG |
259 | * the bit will not set if it is pure 40MHz case |
260 | */ | |
7e6a5886 JB |
261 | if (ht_cap && !ht_cap->ht_supported) |
262 | return false; | |
263 | ||
d73e4923 | 264 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1e4247d4 | 265 | if (priv->disable_ht40) |
7e6a5886 | 266 | return false; |
1e4247d4 | 267 | #endif |
7e6a5886 | 268 | |
611d3eb7 | 269 | return iwl_is_channel_extension(priv, priv->band, |
246ed355 | 270 | le16_to_cpu(ctx->staging.channel), |
7e6a5886 | 271 | ctx->ht.extension_chan_offset); |
47c5196e | 272 | } |
47c5196e | 273 | |
2c2f3b33 TW |
274 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
275 | { | |
ea196fdb JB |
276 | u16 new_val; |
277 | u16 beacon_factor; | |
278 | ||
279 | /* | |
280 | * If mac80211 hasn't given us a beacon interval, program | |
281 | * the default into the device (not checking this here | |
282 | * would cause the adjustment below to return the maximum | |
283 | * value, which may break PAN.) | |
284 | */ | |
285 | if (!beacon_val) | |
286 | return DEFAULT_BEACON_INTERVAL; | |
287 | ||
288 | /* | |
289 | * If the beacon interval we obtained from the peer | |
290 | * is too large, we'll have to wake up more often | |
291 | * (and in IBSS case, we'll beacon too much) | |
292 | * | |
293 | * For example, if max_beacon_val is 4096, and the | |
294 | * requested beacon interval is 7000, we'll have to | |
295 | * use 3500 to be able to wake up on the beacons. | |
296 | * | |
297 | * This could badly influence beacon detection stats. | |
298 | */ | |
2c2f3b33 TW |
299 | |
300 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
301 | new_val = beacon_val / beacon_factor; | |
302 | ||
303 | if (!new_val) | |
304 | new_val = max_beacon_val; | |
305 | ||
306 | return new_val; | |
307 | } | |
308 | ||
47313e34 | 309 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
2c2f3b33 TW |
310 | { |
311 | u64 tsf; | |
312 | s32 interval_tm, rem; | |
2c2f3b33 TW |
313 | struct ieee80211_conf *conf = NULL; |
314 | u16 beacon_int; | |
47313e34 | 315 | struct ieee80211_vif *vif = ctx->vif; |
2c2f3b33 | 316 | |
8c222544 | 317 | conf = &priv->hw->conf; |
2c2f3b33 | 318 | |
b1eea297 | 319 | lockdep_assert_held(&priv->mutex); |
948f5a2f | 320 | |
246ed355 | 321 | memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
948f5a2f | 322 | |
246ed355 JB |
323 | ctx->timing.timestamp = cpu_to_le64(priv->timestamp); |
324 | ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
2c2f3b33 | 325 | |
47313e34 | 326 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; |
2c2f3b33 | 327 | |
47313e34 JB |
328 | /* |
329 | * TODO: For IBSS we need to get atim_window from mac80211, | |
330 | * for now just always use 0 | |
331 | */ | |
332 | ctx->timing.atim_window = 0; | |
2c2f3b33 | 333 | |
bde4530e | 334 | if (ctx->ctxid == IWL_RXON_CTX_PAN && |
f1f270b2 JB |
335 | (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) && |
336 | iwl_is_associated(priv, IWL_RXON_CTX_BSS) && | |
337 | priv->contexts[IWL_RXON_CTX_BSS].vif && | |
338 | priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) { | |
bde4530e JB |
339 | ctx->timing.beacon_interval = |
340 | priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; | |
341 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
f1f270b2 JB |
342 | } else if (ctx->ctxid == IWL_RXON_CTX_BSS && |
343 | iwl_is_associated(priv, IWL_RXON_CTX_PAN) && | |
344 | priv->contexts[IWL_RXON_CTX_PAN].vif && | |
345 | priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int && | |
346 | (!iwl_is_associated_ctx(ctx) || !ctx->vif || | |
347 | !ctx->vif->bss_conf.beacon_int)) { | |
348 | ctx->timing.beacon_interval = | |
349 | priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; | |
350 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
bde4530e JB |
351 | } else { |
352 | beacon_int = iwl_adjust_beacon_interval(beacon_int, | |
ab9e212e | 353 | IWL_MAX_UCODE_BEACON_INTERVAL * TIME_UNIT); |
bde4530e JB |
354 | ctx->timing.beacon_interval = cpu_to_le16(beacon_int); |
355 | } | |
2c2f3b33 | 356 | |
bbb05cb5 JB |
357 | ctx->beacon_int = beacon_int; |
358 | ||
2c2f3b33 | 359 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
f8525e55 | 360 | interval_tm = beacon_int * TIME_UNIT; |
2c2f3b33 | 361 | rem = do_div(tsf, interval_tm); |
246ed355 | 362 | ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
2c2f3b33 | 363 | |
47313e34 | 364 | ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; |
2491fa42 | 365 | |
2c2f3b33 TW |
366 | IWL_DEBUG_ASSOC(priv, |
367 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
246ed355 JB |
368 | le16_to_cpu(ctx->timing.beacon_interval), |
369 | le32_to_cpu(ctx->timing.beacon_init_val), | |
370 | le16_to_cpu(ctx->timing.atim_window)); | |
948f5a2f | 371 | |
e10a0533 | 372 | return iwl_dvm_send_cmd_pdu(priv, ctx->rxon_timing_cmd, |
e419d62d | 373 | CMD_SYNC, sizeof(ctx->timing), &ctx->timing); |
2c2f3b33 | 374 | } |
2c2f3b33 | 375 | |
246ed355 JB |
376 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx, |
377 | int hw_decrypt) | |
8ccde88a | 378 | { |
246ed355 | 379 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a SO |
380 | |
381 | if (hw_decrypt) | |
382 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
383 | else | |
384 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
385 | ||
386 | } | |
8ccde88a | 387 | |
dacefedb | 388 | /* validate RXON structure is valid */ |
246ed355 | 389 | int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
8ccde88a | 390 | { |
246ed355 | 391 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
c914ac26 | 392 | u32 errors = 0; |
8ccde88a SO |
393 | |
394 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
dacefedb JB |
395 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { |
396 | IWL_WARN(priv, "check 2.4G: wrong narrow\n"); | |
c914ac26 | 397 | errors |= BIT(0); |
dacefedb JB |
398 | } |
399 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
400 | IWL_WARN(priv, "check 2.4G: wrong radar\n"); | |
c914ac26 | 401 | errors |= BIT(1); |
dacefedb | 402 | } |
8ccde88a | 403 | } else { |
dacefedb JB |
404 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { |
405 | IWL_WARN(priv, "check 5.2G: not short slot!\n"); | |
c914ac26 | 406 | errors |= BIT(2); |
dacefedb JB |
407 | } |
408 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
409 | IWL_WARN(priv, "check 5.2G: CCK!\n"); | |
c914ac26 | 410 | errors |= BIT(3); |
dacefedb JB |
411 | } |
412 | } | |
413 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
414 | IWL_WARN(priv, "mac/bssid mcast!\n"); | |
c914ac26 | 415 | errors |= BIT(4); |
8ccde88a | 416 | } |
8ccde88a SO |
417 | |
418 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
dacefedb JB |
419 | if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 && |
420 | (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) { | |
421 | IWL_WARN(priv, "neither 1 nor 6 are basic\n"); | |
c914ac26 | 422 | errors |= BIT(5); |
dacefedb | 423 | } |
8ccde88a | 424 | |
dacefedb JB |
425 | if (le16_to_cpu(rxon->assoc_id) > 2007) { |
426 | IWL_WARN(priv, "aid > 2007\n"); | |
c914ac26 | 427 | errors |= BIT(6); |
dacefedb | 428 | } |
8ccde88a | 429 | |
dacefedb JB |
430 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) |
431 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
432 | IWL_WARN(priv, "CCK and short slot\n"); | |
c914ac26 | 433 | errors |= BIT(7); |
dacefedb | 434 | } |
8ccde88a | 435 | |
dacefedb JB |
436 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) |
437 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
438 | IWL_WARN(priv, "CCK and auto detect"); | |
c914ac26 | 439 | errors |= BIT(8); |
dacefedb | 440 | } |
8ccde88a | 441 | |
dacefedb JB |
442 | if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | |
443 | RXON_FLG_TGG_PROTECT_MSK)) == | |
444 | RXON_FLG_TGG_PROTECT_MSK) { | |
445 | IWL_WARN(priv, "TGg but no auto-detect\n"); | |
c914ac26 | 446 | errors |= BIT(9); |
dacefedb | 447 | } |
8ccde88a | 448 | |
c914ac26 JB |
449 | if (rxon->channel == 0) { |
450 | IWL_WARN(priv, "zero channel is invalid\n"); | |
451 | errors |= BIT(10); | |
8ccde88a | 452 | } |
c914ac26 JB |
453 | |
454 | WARN(errors, "Invalid RXON (%#x), channel %d", | |
455 | errors, le16_to_cpu(rxon->channel)); | |
456 | ||
457 | return errors ? -EINVAL : 0; | |
8ccde88a | 458 | } |
8ccde88a SO |
459 | |
460 | /** | |
461 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
462 | * @priv: staging_rxon is compared to active_rxon | |
463 | * | |
464 | * If the RXON structure is changing enough to require a new tune, | |
465 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
466 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
467 | */ | |
246ed355 JB |
468 | int iwl_full_rxon_required(struct iwl_priv *priv, |
469 | struct iwl_rxon_context *ctx) | |
8ccde88a | 470 | { |
246ed355 JB |
471 | const struct iwl_rxon_cmd *staging = &ctx->staging; |
472 | const struct iwl_rxon_cmd *active = &ctx->active; | |
473 | ||
474 | #define CHK(cond) \ | |
475 | if ((cond)) { \ | |
476 | IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \ | |
477 | return 1; \ | |
478 | } | |
479 | ||
480 | #define CHK_NEQ(c1, c2) \ | |
481 | if ((c1) != (c2)) { \ | |
482 | IWL_DEBUG_INFO(priv, "need full RXON - " \ | |
483 | #c1 " != " #c2 " - %d != %d\n", \ | |
484 | (c1), (c2)); \ | |
485 | return 1; \ | |
486 | } | |
8ccde88a SO |
487 | |
488 | /* These items are only settable from the full RXON command */ | |
246ed355 JB |
489 | CHK(!iwl_is_associated_ctx(ctx)); |
490 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); | |
491 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
492 | CHK(compare_ether_addr(staging->wlap_bssid_addr, | |
493 | active->wlap_bssid_addr)); | |
494 | CHK_NEQ(staging->dev_type, active->dev_type); | |
495 | CHK_NEQ(staging->channel, active->channel); | |
496 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
497 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
498 | active->ofdm_ht_single_stream_basic_rates); | |
499 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
500 | active->ofdm_ht_dual_stream_basic_rates); | |
501 | CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates, | |
502 | active->ofdm_ht_triple_stream_basic_rates); | |
503 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
8ccde88a SO |
504 | |
505 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
506 | * be updated with the RXON_ASSOC command -- however only some | |
507 | * flag transitions are allowed using RXON_ASSOC */ | |
508 | ||
509 | /* Check if we are not switching bands */ | |
246ed355 JB |
510 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, |
511 | active->flags & RXON_FLG_BAND_24G_MSK); | |
8ccde88a SO |
512 | |
513 | /* Check if we are switching association toggle */ | |
246ed355 JB |
514 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, |
515 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
516 | ||
517 | #undef CHK | |
518 | #undef CHK_NEQ | |
8ccde88a SO |
519 | |
520 | return 0; | |
521 | } | |
8ccde88a | 522 | |
246ed355 JB |
523 | static void _iwl_set_rxon_ht(struct iwl_priv *priv, |
524 | struct iwl_ht_config *ht_conf, | |
525 | struct iwl_rxon_context *ctx) | |
47c5196e | 526 | { |
246ed355 | 527 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
47c5196e | 528 | |
7e6a5886 | 529 | if (!ctx->ht.enabled) { |
a2b0f02e | 530 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 | 531 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
7aafef1c | 532 | RXON_FLG_HT40_PROT_MSK | |
42eb7c64 | 533 | RXON_FLG_HT_PROT_MSK); |
47c5196e | 534 | return; |
42eb7c64 | 535 | } |
47c5196e | 536 | |
7e6a5886 | 537 | /* FIXME: if the definition of ht.protection changed, the "translation" |
a2b0f02e WYG |
538 | * will be needed for rxon->flags |
539 | */ | |
7e6a5886 | 540 | rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); |
a2b0f02e WYG |
541 | |
542 | /* Set up channel bandwidth: | |
7aafef1c | 543 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
a2b0f02e WYG |
544 | /* clear the HT channel mode before set the mode */ |
545 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
546 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
7e6a5886 | 547 | if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) { |
7aafef1c | 548 | /* pure ht40 */ |
7e6a5886 | 549 | if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
a2b0f02e | 550 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
508b08e7 | 551 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 552 | switch (ctx->ht.extension_chan_offset) { |
508b08e7 WYG |
553 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
554 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
555 | break; | |
556 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
557 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
558 | break; | |
559 | } | |
560 | } else { | |
a2b0f02e | 561 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 562 | switch (ctx->ht.extension_chan_offset) { |
a2b0f02e WYG |
563 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
564 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
565 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
566 | break; | |
567 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
568 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
569 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
570 | break; | |
571 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
572 | default: | |
573 | /* channel location only valid if in Mixed mode */ | |
574 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
575 | break; | |
576 | } | |
577 | } | |
578 | } else { | |
579 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
580 | } |
581 | ||
e3f10cea | 582 | iwlagn_set_rxon_chain(priv, ctx); |
47c5196e | 583 | |
02bb1bea | 584 | IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 585 | "extension channel offset 0x%x\n", |
7e6a5886 JB |
586 | le32_to_cpu(rxon->flags), ctx->ht.protection, |
587 | ctx->ht.extension_chan_offset); | |
47c5196e | 588 | } |
246ed355 JB |
589 | |
590 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf) | |
591 | { | |
592 | struct iwl_rxon_context *ctx; | |
593 | ||
594 | for_each_context(priv, ctx) | |
595 | _iwl_set_rxon_ht(priv, ht_conf, ctx); | |
596 | } | |
47c5196e | 597 | |
246ed355 | 598 | /* Return valid, unused, channel for a passive scan to reset the RF */ |
14023641 | 599 | u8 iwl_get_single_channel_number(struct iwl_priv *priv, |
246ed355 | 600 | enum ieee80211_band band) |
14023641 AK |
601 | { |
602 | const struct iwl_channel_info *ch_info; | |
603 | int i; | |
604 | u8 channel = 0; | |
246ed355 JB |
605 | u8 min, max; |
606 | struct iwl_rxon_context *ctx; | |
14023641 | 607 | |
14023641 | 608 | if (band == IEEE80211_BAND_5GHZ) { |
246ed355 JB |
609 | min = 14; |
610 | max = priv->channel_count; | |
14023641 | 611 | } else { |
246ed355 JB |
612 | min = 0; |
613 | max = 14; | |
614 | } | |
615 | ||
616 | for (i = min; i < max; i++) { | |
617 | bool busy = false; | |
618 | ||
619 | for_each_context(priv, ctx) { | |
620 | busy = priv->channel_info[i].channel == | |
621 | le16_to_cpu(ctx->staging.channel); | |
622 | if (busy) | |
623 | break; | |
14023641 | 624 | } |
246ed355 JB |
625 | |
626 | if (busy) | |
627 | continue; | |
628 | ||
629 | channel = priv->channel_info[i].channel; | |
630 | ch_info = iwl_get_channel_info(priv, band, channel); | |
631 | if (is_channel_valid(ch_info)) | |
632 | break; | |
14023641 AK |
633 | } |
634 | ||
635 | return channel; | |
636 | } | |
14023641 | 637 | |
bf85ea4f | 638 | /** |
3edb5fd6 SZ |
639 | * iwl_set_rxon_channel - Set the band and channel values in staging RXON |
640 | * @ch: requested channel as a pointer to struct ieee80211_channel | |
bf85ea4f | 641 | |
bf85ea4f | 642 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
3edb5fd6 | 643 | * in the staging RXON flag structure based on the ch->band |
bf85ea4f | 644 | */ |
dd63b84e | 645 | void iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch, |
246ed355 | 646 | struct iwl_rxon_context *ctx) |
bf85ea4f | 647 | { |
17e72782 | 648 | enum ieee80211_band band = ch->band; |
81e95430 | 649 | u16 channel = ch->hw_value; |
17e72782 | 650 | |
246ed355 | 651 | if ((le16_to_cpu(ctx->staging.channel) == channel) && |
bf85ea4f | 652 | (priv->band == band)) |
dd63b84e | 653 | return; |
bf85ea4f | 654 | |
246ed355 | 655 | ctx->staging.channel = cpu_to_le16(channel); |
bf85ea4f | 656 | if (band == IEEE80211_BAND_5GHZ) |
246ed355 | 657 | ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK; |
bf85ea4f | 658 | else |
246ed355 | 659 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
bf85ea4f AK |
660 | |
661 | priv->band = band; | |
662 | ||
e1623446 | 663 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f | 664 | |
bf85ea4f | 665 | } |
bf85ea4f | 666 | |
79d07325 | 667 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
246ed355 | 668 | struct iwl_rxon_context *ctx, |
79d07325 WYG |
669 | enum ieee80211_band band, |
670 | struct ieee80211_vif *vif) | |
8ccde88a SO |
671 | { |
672 | if (band == IEEE80211_BAND_5GHZ) { | |
246ed355 | 673 | ctx->staging.flags &= |
8ccde88a SO |
674 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
675 | | RXON_FLG_CCK_MSK); | |
246ed355 | 676 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a SO |
677 | } else { |
678 | /* Copied from iwl_post_associate() */ | |
c213d745 | 679 | if (vif && vif->bss_conf.use_short_slot) |
246ed355 | 680 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 681 | else |
246ed355 | 682 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 683 | |
246ed355 JB |
684 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
685 | ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
686 | ctx->staging.flags &= ~RXON_FLG_CCK_MSK; | |
8ccde88a SO |
687 | } |
688 | } | |
8ccde88a SO |
689 | |
690 | /* | |
691 | * initialize rxon structure with default values from eeprom | |
692 | */ | |
1dda6d28 | 693 | void iwl_connection_init_rx_config(struct iwl_priv *priv, |
d0fe478c | 694 | struct iwl_rxon_context *ctx) |
8ccde88a SO |
695 | { |
696 | const struct iwl_channel_info *ch_info; | |
697 | ||
246ed355 | 698 | memset(&ctx->staging, 0, sizeof(ctx->staging)); |
8ccde88a | 699 | |
d0fe478c JB |
700 | if (!ctx->vif) { |
701 | ctx->staging.dev_type = ctx->unused_devtype; | |
702 | } else switch (ctx->vif->type) { | |
8ccde88a | 703 | case NL80211_IFTYPE_AP: |
d0fe478c | 704 | ctx->staging.dev_type = ctx->ap_devtype; |
8ccde88a SO |
705 | break; |
706 | ||
707 | case NL80211_IFTYPE_STATION: | |
d0fe478c | 708 | ctx->staging.dev_type = ctx->station_devtype; |
246ed355 | 709 | ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; |
8ccde88a SO |
710 | break; |
711 | ||
712 | case NL80211_IFTYPE_ADHOC: | |
d0fe478c | 713 | ctx->staging.dev_type = ctx->ibss_devtype; |
246ed355 JB |
714 | ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; |
715 | ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
8ccde88a SO |
716 | RXON_FILTER_ACCEPT_GRP_MSK; |
717 | break; | |
718 | ||
8ccde88a | 719 | default: |
d0fe478c JB |
720 | IWL_ERR(priv, "Unsupported interface type %d\n", |
721 | ctx->vif->type); | |
8ccde88a SO |
722 | break; |
723 | } | |
724 | ||
725 | #if 0 | |
726 | /* TODO: Figure out when short_preamble would be set and cache from | |
727 | * that */ | |
728 | if (!hw_to_local(priv->hw)->short_preamble) | |
246ed355 | 729 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a | 730 | else |
246ed355 | 731 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a SO |
732 | #endif |
733 | ||
734 | ch_info = iwl_get_channel_info(priv, priv->band, | |
246ed355 | 735 | le16_to_cpu(ctx->active.channel)); |
8ccde88a SO |
736 | |
737 | if (!ch_info) | |
738 | ch_info = &priv->channel_info[0]; | |
739 | ||
246ed355 | 740 | ctx->staging.channel = cpu_to_le16(ch_info->channel); |
8ccde88a SO |
741 | priv->band = ch_info->band; |
742 | ||
d0fe478c | 743 | iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif); |
8ccde88a | 744 | |
246ed355 | 745 | ctx->staging.ofdm_basic_rates = |
8ccde88a | 746 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
246ed355 | 747 | ctx->staging.cck_basic_rates = |
8ccde88a SO |
748 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
749 | ||
a2b0f02e | 750 | /* clear both MIX and PURE40 mode flag */ |
246ed355 | 751 | ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | |
a2b0f02e | 752 | RXON_FLG_CHANNEL_MODE_PURE_40); |
d0fe478c JB |
753 | if (ctx->vif) |
754 | memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN); | |
7684c408 | 755 | |
246ed355 JB |
756 | ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff; |
757 | ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
758 | ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff; | |
8ccde88a | 759 | } |
8ccde88a | 760 | |
79d07325 | 761 | void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
762 | { |
763 | const struct ieee80211_supported_band *hw = NULL; | |
764 | struct ieee80211_rate *rate; | |
246ed355 | 765 | struct iwl_rxon_context *ctx; |
8ccde88a SO |
766 | int i; |
767 | ||
768 | hw = iwl_get_hw_mode(priv, priv->band); | |
769 | if (!hw) { | |
770 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
771 | return; | |
772 | } | |
773 | ||
774 | priv->active_rate = 0; | |
8ccde88a SO |
775 | |
776 | for (i = 0; i < hw->n_bitrates; i++) { | |
777 | rate = &(hw->bitrates[i]); | |
5027309b | 778 | if (rate->hw_value < IWL_RATE_COUNT_LEGACY) |
8ccde88a SO |
779 | priv->active_rate |= (1 << rate->hw_value); |
780 | } | |
781 | ||
4a02886b | 782 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate); |
8ccde88a | 783 | |
246ed355 JB |
784 | for_each_context(priv, ctx) { |
785 | ctx->staging.cck_basic_rates = | |
786 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
4a02886b | 787 | |
246ed355 JB |
788 | ctx->staging.ofdm_basic_rates = |
789 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
790 | } | |
8ccde88a | 791 | } |
79d07325 WYG |
792 | |
793 | void iwl_chswitch_done(struct iwl_priv *priv, bool is_success) | |
794 | { | |
8bd413e6 JB |
795 | /* |
796 | * MULTI-FIXME | |
ade4c649 | 797 | * See iwlagn_mac_channel_switch. |
8bd413e6 JB |
798 | */ |
799 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
800 | ||
83626404 | 801 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
79d07325 WYG |
802 | return; |
803 | ||
83626404 | 804 | if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status)) |
8bd413e6 | 805 | ieee80211_chswitch_done(ctx->vif, is_success); |
79d07325 | 806 | } |
8ccde88a | 807 | |
8ccde88a | 808 | #ifdef CONFIG_IWLWIFI_DEBUG |
14991a9d EG |
809 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, |
810 | enum iwl_rxon_context_id ctxid) | |
8ccde88a | 811 | { |
522376d2 | 812 | struct iwl_rxon_context *ctx = &priv->contexts[ctxid]; |
246ed355 | 813 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a | 814 | |
e1623446 | 815 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
3d816c77 | 816 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
817 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
818 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
819 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 820 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
821 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
822 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 823 | rxon->ofdm_basic_rates); |
e1623446 TW |
824 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
825 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
826 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
827 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a | 828 | } |
6686d17e | 829 | #endif |
e649437f | 830 | |
b7e21bf0 | 831 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) |
8ccde88a | 832 | { |
491bc292 WYG |
833 | unsigned int reload_msec; |
834 | unsigned long reload_jiffies; | |
835 | ||
3e6895c5 | 836 | #ifdef CONFIG_IWLWIFI_DEBUG |
a8bceb39 | 837 | if (iwl_have_debug_level(IWL_DL_FW_ERRORS)) |
3e6895c5 EG |
838 | iwl_print_rx_config_cmd(priv, IWL_RXON_CTX_BSS); |
839 | #endif | |
840 | ||
8f7ffbe2 DS |
841 | /* uCode is no longer loaded. */ |
842 | priv->ucode_loaded = false; | |
843 | ||
8ccde88a | 844 | /* Set the FW error flag -- cleared on iwl_down */ |
63013ae3 | 845 | set_bit(STATUS_FW_ERROR, &priv->shrd->status); |
8ccde88a SO |
846 | |
847 | /* Cancel currently queued command. */ | |
63013ae3 | 848 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
8ccde88a | 849 | |
4bd14dd5 | 850 | iwl_abort_notification_waits(&priv->notif_wait); |
e74fe233 | 851 | |
e649437f JB |
852 | /* Keep the restart process from trying to send host |
853 | * commands by clearing the ready bit */ | |
83626404 | 854 | clear_bit(STATUS_READY, &priv->status); |
e649437f | 855 | |
69a10b29 | 856 | wake_up(&trans(priv)->wait_command_queue); |
e649437f JB |
857 | |
858 | if (!ondemand) { | |
859 | /* | |
860 | * If firmware keep reloading, then it indicate something | |
861 | * serious wrong and firmware having problem to recover | |
862 | * from it. Instead of keep trying which will fill the syslog | |
863 | * and hang the system, let's just stop it | |
864 | */ | |
865 | reload_jiffies = jiffies; | |
866 | reload_msec = jiffies_to_msecs((long) reload_jiffies - | |
867 | (long) priv->reload_jiffies); | |
868 | priv->reload_jiffies = reload_jiffies; | |
869 | if (reload_msec <= IWL_MIN_RELOAD_DURATION) { | |
870 | priv->reload_count++; | |
871 | if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) { | |
872 | IWL_ERR(priv, "BUG_ON, Stop restarting\n"); | |
873 | return; | |
874 | } | |
875 | } else | |
876 | priv->reload_count = 0; | |
877 | } | |
878 | ||
83626404 | 879 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
9d143e9a | 880 | if (iwlagn_mod_params.restart_fw) { |
9ca06f0a | 881 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f | 882 | "Restarting adapter due to uCode error.\n"); |
1ee158d8 | 883 | queue_work(priv->workqueue, &priv->restart); |
e649437f | 884 | } else |
9ca06f0a | 885 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f JB |
886 | "Detected FW error, but not restarting\n"); |
887 | } | |
888 | } | |
889 | ||
630fe9b6 TW |
890 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
891 | { | |
a25a66ac SG |
892 | int ret; |
893 | s8 prev_tx_power; | |
f844a709 SG |
894 | bool defer; |
895 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
a25a66ac | 896 | |
b1eea297 | 897 | lockdep_assert_held(&priv->mutex); |
a25a66ac SG |
898 | |
899 | if (priv->tx_power_user_lmt == tx_power && !force) | |
900 | return 0; | |
901 | ||
b744cb79 WYG |
902 | if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) { |
903 | IWL_WARN(priv, | |
904 | "Requested user TXPOWER %d below lower limit %d.\n", | |
daf518de | 905 | tx_power, |
b744cb79 | 906 | IWLAGN_TX_POWER_TARGET_POWER_MIN); |
630fe9b6 TW |
907 | return -EINVAL; |
908 | } | |
909 | ||
dc1b0973 | 910 | if (tx_power > priv->tx_power_device_lmt) { |
08f2d58d WYG |
911 | IWL_WARN(priv, |
912 | "Requested user TXPOWER %d above upper limit %d.\n", | |
dc1b0973 | 913 | tx_power, priv->tx_power_device_lmt); |
630fe9b6 TW |
914 | return -EINVAL; |
915 | } | |
916 | ||
83626404 | 917 | if (!iwl_is_ready_rf(priv)) |
a25a66ac | 918 | return -EIO; |
630fe9b6 | 919 | |
f844a709 SG |
920 | /* scan complete and commit_rxon use tx_power_next value, |
921 | * it always need to be updated for newest request */ | |
a25a66ac | 922 | priv->tx_power_next = tx_power; |
f844a709 SG |
923 | |
924 | /* do not set tx power when scanning or channel changing */ | |
83626404 | 925 | defer = test_bit(STATUS_SCANNING, &priv->status) || |
f844a709 SG |
926 | memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)); |
927 | if (defer && !force) { | |
928 | IWL_DEBUG_INFO(priv, "Deferring tx power set\n"); | |
a25a66ac | 929 | return 0; |
5eadd94b | 930 | } |
630fe9b6 | 931 | |
a25a66ac SG |
932 | prev_tx_power = priv->tx_power_user_lmt; |
933 | priv->tx_power_user_lmt = tx_power; | |
934 | ||
5beaaf37 | 935 | ret = iwlagn_send_tx_power(priv); |
a25a66ac SG |
936 | |
937 | /* if fail to set tx_power, restore the orig. tx power */ | |
938 | if (ret) { | |
939 | priv->tx_power_user_lmt = prev_tx_power; | |
940 | priv->tx_power_next = prev_tx_power; | |
941 | } | |
630fe9b6 TW |
942 | return ret; |
943 | } | |
630fe9b6 | 944 | |
65b52bde | 945 | void iwl_send_bt_config(struct iwl_priv *priv) |
17f841cd SO |
946 | { |
947 | struct iwl_bt_cmd bt_cmd = { | |
456d0f76 WYG |
948 | .lead_time = BT_LEAD_TIME_DEF, |
949 | .max_kill = BT_MAX_KILL_DEF, | |
17f841cd SO |
950 | .kill_ack_mask = 0, |
951 | .kill_cts_mask = 0, | |
952 | }; | |
953 | ||
b60eec9b | 954 | if (!iwlagn_mod_params.bt_coex_active) |
06702a73 WYG |
955 | bt_cmd.flags = BT_COEX_DISABLE; |
956 | else | |
957 | bt_cmd.flags = BT_COEX_ENABLE; | |
958 | ||
f21dd005 | 959 | priv->bt_enable_flag = bt_cmd.flags; |
06702a73 WYG |
960 | IWL_DEBUG_INFO(priv, "BT coex %s\n", |
961 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); | |
962 | ||
e10a0533 | 963 | if (iwl_dvm_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
e419d62d | 964 | CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd)) |
65b52bde | 965 | IWL_ERR(priv, "failed to send BT Coex Config\n"); |
17f841cd | 966 | } |
17f841cd | 967 | |
ef8d5529 | 968 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear) |
49ea8596 | 969 | { |
ef8d5529 WYG |
970 | struct iwl_statistics_cmd statistics_cmd = { |
971 | .configuration_flags = | |
972 | clear ? IWL_STATS_CONF_CLEAR_STATS : 0, | |
49ea8596 | 973 | }; |
ef8d5529 WYG |
974 | |
975 | if (flags & CMD_ASYNC) | |
e10a0533 | 976 | return iwl_dvm_send_cmd_pdu(priv, REPLY_STATISTICS_CMD, |
e419d62d | 977 | CMD_ASYNC, |
ef8d5529 | 978 | sizeof(struct iwl_statistics_cmd), |
e419d62d | 979 | &statistics_cmd); |
ef8d5529 | 980 | else |
e10a0533 | 981 | return iwl_dvm_send_cmd_pdu(priv, REPLY_STATISTICS_CMD, |
e419d62d | 982 | CMD_SYNC, |
ef8d5529 WYG |
983 | sizeof(struct iwl_statistics_cmd), |
984 | &statistics_cmd); | |
49ea8596 | 985 | } |
7e8c519e | 986 | |
488829f1 | 987 | |
727882d6 | 988 | |
d8052319 | 989 | |
20594eb0 WYG |
990 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
991 | ||
992 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) | |
993 | ||
994 | void iwl_reset_traffic_log(struct iwl_priv *priv) | |
995 | { | |
996 | priv->tx_traffic_idx = 0; | |
997 | priv->rx_traffic_idx = 0; | |
998 | if (priv->tx_traffic) | |
999 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1000 | if (priv->rx_traffic) | |
1001 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1002 | } | |
1003 | ||
1004 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) | |
1005 | { | |
1006 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; | |
1007 | ||
a8bceb39 | 1008 | if (iwl_have_debug_level(IWL_DL_TX)) { |
20594eb0 WYG |
1009 | if (!priv->tx_traffic) { |
1010 | priv->tx_traffic = | |
1011 | kzalloc(traffic_size, GFP_KERNEL); | |
1012 | if (!priv->tx_traffic) | |
1013 | return -ENOMEM; | |
1014 | } | |
1015 | } | |
a8bceb39 | 1016 | if (iwl_have_debug_level(IWL_DL_RX)) { |
20594eb0 WYG |
1017 | if (!priv->rx_traffic) { |
1018 | priv->rx_traffic = | |
1019 | kzalloc(traffic_size, GFP_KERNEL); | |
1020 | if (!priv->rx_traffic) | |
1021 | return -ENOMEM; | |
1022 | } | |
1023 | } | |
1024 | iwl_reset_traffic_log(priv); | |
1025 | return 0; | |
1026 | } | |
20594eb0 WYG |
1027 | |
1028 | void iwl_free_traffic_mem(struct iwl_priv *priv) | |
1029 | { | |
1030 | kfree(priv->tx_traffic); | |
1031 | priv->tx_traffic = NULL; | |
1032 | ||
1033 | kfree(priv->rx_traffic); | |
1034 | priv->rx_traffic = NULL; | |
1035 | } | |
20594eb0 WYG |
1036 | |
1037 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | |
1038 | u16 length, struct ieee80211_hdr *header) | |
1039 | { | |
1040 | __le16 fc; | |
1041 | u16 len; | |
1042 | ||
a8bceb39 | 1043 | if (likely(!iwl_have_debug_level(IWL_DL_TX))) |
20594eb0 WYG |
1044 | return; |
1045 | ||
1046 | if (!priv->tx_traffic) | |
1047 | return; | |
1048 | ||
1049 | fc = header->frame_control; | |
1050 | if (ieee80211_is_data(fc)) { | |
1051 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1052 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1053 | memcpy((priv->tx_traffic + | |
1054 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1055 | header, len); | |
1056 | priv->tx_traffic_idx = | |
1057 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1058 | } | |
1059 | } | |
20594eb0 WYG |
1060 | |
1061 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | |
1062 | u16 length, struct ieee80211_hdr *header) | |
1063 | { | |
1064 | __le16 fc; | |
1065 | u16 len; | |
1066 | ||
a8bceb39 | 1067 | if (likely(!iwl_have_debug_level(IWL_DL_RX))) |
20594eb0 WYG |
1068 | return; |
1069 | ||
1070 | if (!priv->rx_traffic) | |
1071 | return; | |
1072 | ||
1073 | fc = header->frame_control; | |
1074 | if (ieee80211_is_data(fc)) { | |
1075 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1076 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1077 | memcpy((priv->rx_traffic + | |
1078 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1079 | header, len); | |
1080 | priv->rx_traffic_idx = | |
1081 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1082 | } | |
1083 | } | |
22fdf3c9 WYG |
1084 | |
1085 | const char *get_mgmt_string(int cmd) | |
1086 | { | |
1087 | switch (cmd) { | |
1088 | IWL_CMD(MANAGEMENT_ASSOC_REQ); | |
1089 | IWL_CMD(MANAGEMENT_ASSOC_RESP); | |
1090 | IWL_CMD(MANAGEMENT_REASSOC_REQ); | |
1091 | IWL_CMD(MANAGEMENT_REASSOC_RESP); | |
1092 | IWL_CMD(MANAGEMENT_PROBE_REQ); | |
1093 | IWL_CMD(MANAGEMENT_PROBE_RESP); | |
1094 | IWL_CMD(MANAGEMENT_BEACON); | |
1095 | IWL_CMD(MANAGEMENT_ATIM); | |
1096 | IWL_CMD(MANAGEMENT_DISASSOC); | |
1097 | IWL_CMD(MANAGEMENT_AUTH); | |
1098 | IWL_CMD(MANAGEMENT_DEAUTH); | |
1099 | IWL_CMD(MANAGEMENT_ACTION); | |
1100 | default: | |
1101 | return "UNKNOWN"; | |
1102 | ||
1103 | } | |
1104 | } | |
1105 | ||
1106 | const char *get_ctrl_string(int cmd) | |
1107 | { | |
1108 | switch (cmd) { | |
1109 | IWL_CMD(CONTROL_BACK_REQ); | |
1110 | IWL_CMD(CONTROL_BACK); | |
1111 | IWL_CMD(CONTROL_PSPOLL); | |
1112 | IWL_CMD(CONTROL_RTS); | |
1113 | IWL_CMD(CONTROL_CTS); | |
1114 | IWL_CMD(CONTROL_ACK); | |
1115 | IWL_CMD(CONTROL_CFEND); | |
1116 | IWL_CMD(CONTROL_CFENDACK); | |
1117 | default: | |
1118 | return "UNKNOWN"; | |
1119 | ||
1120 | } | |
1121 | } | |
1122 | ||
7163b8a4 | 1123 | void iwl_clear_traffic_stats(struct iwl_priv *priv) |
22fdf3c9 WYG |
1124 | { |
1125 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); | |
22fdf3c9 WYG |
1126 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); |
1127 | } | |
1128 | ||
1129 | /* | |
1130 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will | |
1131 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. | |
1132 | * Use debugFs to display the rx/rx_statistics | |
1133 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL | |
1134 | * information will be recorded, but DATA pkt still will be recorded | |
1135 | * for the reason of iwl_led.c need to control the led blinking based on | |
1136 | * number of tx and rx data. | |
1137 | * | |
1138 | */ | |
1139 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) | |
1140 | { | |
1141 | struct traffic_stats *stats; | |
1142 | ||
1143 | if (is_tx) | |
1144 | stats = &priv->tx_stats; | |
1145 | else | |
1146 | stats = &priv->rx_stats; | |
1147 | ||
1148 | if (ieee80211_is_mgmt(fc)) { | |
1149 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1150 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
1151 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
1152 | break; | |
1153 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
1154 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
1155 | break; | |
1156 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
1157 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
1158 | break; | |
1159 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
1160 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
1161 | break; | |
1162 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
1163 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
1164 | break; | |
1165 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
1166 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
1167 | break; | |
1168 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
1169 | stats->mgmt[MANAGEMENT_BEACON]++; | |
1170 | break; | |
1171 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
1172 | stats->mgmt[MANAGEMENT_ATIM]++; | |
1173 | break; | |
1174 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
1175 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
1176 | break; | |
1177 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
1178 | stats->mgmt[MANAGEMENT_AUTH]++; | |
1179 | break; | |
1180 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
1181 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
1182 | break; | |
1183 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
1184 | stats->mgmt[MANAGEMENT_ACTION]++; | |
1185 | break; | |
1186 | } | |
1187 | } else if (ieee80211_is_ctl(fc)) { | |
1188 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1189 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
1190 | stats->ctrl[CONTROL_BACK_REQ]++; | |
1191 | break; | |
1192 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
1193 | stats->ctrl[CONTROL_BACK]++; | |
1194 | break; | |
1195 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
1196 | stats->ctrl[CONTROL_PSPOLL]++; | |
1197 | break; | |
1198 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
1199 | stats->ctrl[CONTROL_RTS]++; | |
1200 | break; | |
1201 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
1202 | stats->ctrl[CONTROL_CTS]++; | |
1203 | break; | |
1204 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
1205 | stats->ctrl[CONTROL_ACK]++; | |
1206 | break; | |
1207 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
1208 | stats->ctrl[CONTROL_CFEND]++; | |
1209 | break; | |
1210 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
1211 | stats->ctrl[CONTROL_CFENDACK]++; | |
1212 | break; | |
1213 | } | |
1214 | } else { | |
1215 | /* data */ | |
1216 | stats->data_cnt++; | |
1217 | stats->data_bytes += len; | |
1218 | } | |
1219 | } | |
20594eb0 WYG |
1220 | #endif |
1221 | ||
a93e7973 | 1222 | static void iwl_force_rf_reset(struct iwl_priv *priv) |
afbdd69a | 1223 | { |
83626404 | 1224 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
afbdd69a WYG |
1225 | return; |
1226 | ||
246ed355 | 1227 | if (!iwl_is_any_associated(priv)) { |
afbdd69a WYG |
1228 | IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n"); |
1229 | return; | |
1230 | } | |
1231 | /* | |
1232 | * There is no easy and better way to force reset the radio, | |
1233 | * the only known method is switching channel which will force to | |
1234 | * reset and tune the radio. | |
1235 | * Use internal short scan (single channel) operation to should | |
1236 | * achieve this objective. | |
1237 | * Driver should reset the radio when number of consecutive missed | |
1238 | * beacon, or any other uCode error condition detected. | |
1239 | */ | |
1240 | IWL_DEBUG_INFO(priv, "perform radio reset.\n"); | |
1241 | iwl_internal_short_hw_scan(priv); | |
afbdd69a | 1242 | } |
a93e7973 | 1243 | |
a93e7973 | 1244 | |
c04f9f22 | 1245 | int iwl_force_reset(struct iwl_priv *priv, int mode, bool external) |
a93e7973 | 1246 | { |
8a472da4 WYG |
1247 | struct iwl_force_reset *force_reset; |
1248 | ||
83626404 | 1249 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
a93e7973 WYG |
1250 | return -EINVAL; |
1251 | ||
8a472da4 WYG |
1252 | if (mode >= IWL_MAX_FORCE_RESET) { |
1253 | IWL_DEBUG_INFO(priv, "invalid reset request.\n"); | |
1254 | return -EINVAL; | |
1255 | } | |
1256 | force_reset = &priv->force_reset[mode]; | |
1257 | force_reset->reset_request_count++; | |
c04f9f22 WYG |
1258 | if (!external) { |
1259 | if (force_reset->last_force_reset_jiffies && | |
1260 | time_after(force_reset->last_force_reset_jiffies + | |
1261 | force_reset->reset_duration, jiffies)) { | |
1262 | IWL_DEBUG_INFO(priv, "force reset rejected\n"); | |
1263 | force_reset->reset_reject_count++; | |
1264 | return -EAGAIN; | |
1265 | } | |
a93e7973 | 1266 | } |
8a472da4 WYG |
1267 | force_reset->reset_success_count++; |
1268 | force_reset->last_force_reset_jiffies = jiffies; | |
a93e7973 | 1269 | IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode); |
a93e7973 WYG |
1270 | switch (mode) { |
1271 | case IWL_RF_RESET: | |
1272 | iwl_force_rf_reset(priv); | |
1273 | break; | |
1274 | case IWL_FW_RESET: | |
c04f9f22 WYG |
1275 | /* |
1276 | * if the request is from external(ex: debugfs), | |
1277 | * then always perform the request in regardless the module | |
1278 | * parameter setting | |
1279 | * if the request is from internal (uCode error or driver | |
1280 | * detect failure), then fw_restart module parameter | |
1281 | * need to be check before performing firmware reload | |
1282 | */ | |
9d143e9a | 1283 | if (!external && !iwlagn_mod_params.restart_fw) { |
c04f9f22 WYG |
1284 | IWL_DEBUG_INFO(priv, "Cancel firmware reload based on " |
1285 | "module parameter setting\n"); | |
1286 | break; | |
1287 | } | |
a93e7973 | 1288 | IWL_ERR(priv, "On demand firmware reload\n"); |
e649437f | 1289 | iwlagn_fw_error(priv, true); |
a93e7973 | 1290 | break; |
a93e7973 | 1291 | } |
a93e7973 WYG |
1292 | return 0; |
1293 | } | |
b74e31a9 | 1294 | |
d4daaea6 | 1295 | |
317d09f7 WYG |
1296 | int iwl_cmd_echo_test(struct iwl_priv *priv) |
1297 | { | |
7e4005cc | 1298 | int ret; |
317d09f7 WYG |
1299 | struct iwl_host_cmd cmd = { |
1300 | .id = REPLY_ECHO, | |
89db3b97 | 1301 | .len = { 0 }, |
317d09f7 WYG |
1302 | .flags = CMD_SYNC, |
1303 | }; | |
1304 | ||
e10a0533 | 1305 | ret = iwl_dvm_send_cmd(priv, &cmd); |
7e4005cc WYG |
1306 | if (ret) |
1307 | IWL_ERR(priv, "echo testing fail: 0X%x\n", ret); | |
1308 | else | |
1309 | IWL_DEBUG_INFO(priv, "echo testing pass\n"); | |
1310 | return ret; | |
317d09f7 WYG |
1311 | } |
1312 | ||
f22be624 | 1313 | static inline int iwl_check_stuck_queue(struct iwl_priv *priv, int txq) |
b74e31a9 | 1314 | { |
f22be624 | 1315 | if (iwl_trans_check_stuck_queue(trans(priv), txq)) { |
317d09f7 | 1316 | int ret; |
317d09f7 | 1317 | ret = iwl_force_reset(priv, IWL_FW_RESET, false); |
22de94de | 1318 | return (ret == -EAGAIN) ? 0 : 1; |
b74e31a9 WYG |
1319 | } |
1320 | return 0; | |
1321 | } | |
1322 | ||
22de94de SG |
1323 | /* |
1324 | * Making watchdog tick be a quarter of timeout assure we will | |
1325 | * discover the queue hung between timeout and 1.25*timeout | |
1326 | */ | |
1327 | #define IWL_WD_TICK(timeout) ((timeout) / 4) | |
1328 | ||
1329 | /* | |
1330 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
1331 | * we reset the firmware. If everything is fine just rearm the timer. | |
1332 | */ | |
1333 | void iwl_bg_watchdog(unsigned long data) | |
b74e31a9 WYG |
1334 | { |
1335 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
1336 | int cnt; | |
22de94de | 1337 | unsigned long timeout; |
b74e31a9 | 1338 | |
83626404 | 1339 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b74e31a9 WYG |
1340 | return; |
1341 | ||
83626404 | 1342 | if (iwl_is_rfkill(priv)) |
46e7741e WYG |
1343 | return; |
1344 | ||
e7a09438 | 1345 | timeout = hw_params(priv).wd_timeout; |
22de94de SG |
1346 | if (timeout == 0) |
1347 | return; | |
1348 | ||
342bbf3f | 1349 | /* monitor and check for stuck queues */ |
3cc241ad | 1350 | for (cnt = 0; cnt < cfg(priv)->base_params->num_of_queues; cnt++) |
342bbf3f JB |
1351 | if (iwl_check_stuck_queue(priv, cnt)) |
1352 | return; | |
22de94de SG |
1353 | |
1354 | mod_timer(&priv->watchdog, jiffies + | |
1355 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
b74e31a9 | 1356 | } |
22de94de SG |
1357 | |
1358 | void iwl_setup_watchdog(struct iwl_priv *priv) | |
1359 | { | |
e7a09438 | 1360 | unsigned int timeout = hw_params(priv).wd_timeout; |
afbdd69a | 1361 | |
9995ffe5 WYG |
1362 | if (!iwlagn_mod_params.wd_disable) { |
1363 | /* use system default */ | |
38622419 | 1364 | if (timeout && !cfg(priv)->base_params->wd_disable) |
9995ffe5 WYG |
1365 | mod_timer(&priv->watchdog, |
1366 | jiffies + | |
1367 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1368 | else | |
1369 | del_timer(&priv->watchdog); | |
1370 | } else { | |
1371 | /* module parameter overwrite default configuration */ | |
1372 | if (timeout && iwlagn_mod_params.wd_disable == 2) | |
1373 | mod_timer(&priv->watchdog, | |
1374 | jiffies + | |
1375 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1376 | else | |
1377 | del_timer(&priv->watchdog); | |
1378 | } | |
22de94de | 1379 | } |
a0ee74cf | 1380 | |
8c222544 EG |
1381 | /** |
1382 | * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time | |
1383 | * @priv -- pointer to iwl_priv data structure | |
1384 | * @tsf_bits -- number of bits need to shift for masking) | |
1385 | */ | |
1386 | static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv, | |
1387 | u16 tsf_bits) | |
1388 | { | |
1389 | return (1 << tsf_bits) - 1; | |
1390 | } | |
1391 | ||
1392 | /** | |
1393 | * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time | |
1394 | * @priv -- pointer to iwl_priv data structure | |
1395 | * @tsf_bits -- number of bits need to shift for masking) | |
1396 | */ | |
1397 | static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv, | |
1398 | u16 tsf_bits) | |
1399 | { | |
1400 | return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; | |
1401 | } | |
1402 | ||
a0ee74cf WYG |
1403 | /* |
1404 | * extended beacon time format | |
1405 | * time in usec will be changed into a 32-bit value in extended:internal format | |
1406 | * the extended part is the beacon counts | |
1407 | * the internal part is the time in usec within one beacon interval | |
1408 | */ | |
1409 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval) | |
1410 | { | |
1411 | u32 quot; | |
1412 | u32 rem; | |
1413 | u32 interval = beacon_interval * TIME_UNIT; | |
1414 | ||
1415 | if (!interval || !usec) | |
1416 | return 0; | |
1417 | ||
1418 | quot = (usec / interval) & | |
403ba56a DF |
1419 | (iwl_beacon_time_mask_high(priv, IWLAGN_EXT_BEACON_TIME_POS) >> |
1420 | IWLAGN_EXT_BEACON_TIME_POS); | |
a0ee74cf | 1421 | rem = (usec % interval) & iwl_beacon_time_mask_low(priv, |
403ba56a | 1422 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1423 | |
403ba56a | 1424 | return (quot << IWLAGN_EXT_BEACON_TIME_POS) + rem; |
a0ee74cf | 1425 | } |
a0ee74cf WYG |
1426 | |
1427 | /* base is usually what we get from ucode with each received frame, | |
1428 | * the same as HW timer counter counting down | |
1429 | */ | |
1430 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | |
1431 | u32 addon, u32 beacon_interval) | |
1432 | { | |
1433 | u32 base_low = base & iwl_beacon_time_mask_low(priv, | |
403ba56a | 1434 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1435 | u32 addon_low = addon & iwl_beacon_time_mask_low(priv, |
403ba56a | 1436 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf WYG |
1437 | u32 interval = beacon_interval * TIME_UNIT; |
1438 | u32 res = (base & iwl_beacon_time_mask_high(priv, | |
403ba56a | 1439 | IWLAGN_EXT_BEACON_TIME_POS)) + |
a0ee74cf | 1440 | (addon & iwl_beacon_time_mask_high(priv, |
403ba56a | 1441 | IWLAGN_EXT_BEACON_TIME_POS)); |
a0ee74cf WYG |
1442 | |
1443 | if (base_low > addon_low) | |
1444 | res += base_low - addon_low; | |
1445 | else if (base_low < addon_low) { | |
1446 | res += interval + base_low - addon_low; | |
403ba56a | 1447 | res += (1 << IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1448 | } else |
403ba56a | 1449 | res += (1 << IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf WYG |
1450 | |
1451 | return cpu_to_le32(res); | |
1452 | } | |
a0ee74cf | 1453 | |
bcb9321c EG |
1454 | void iwl_nic_error(struct iwl_op_mode *op_mode) |
1455 | { | |
1456 | struct iwl_priv *priv = IWL_OP_MODE_GET_DVM(op_mode); | |
1457 | ||
1458 | iwlagn_fw_error(priv, false); | |
1459 | } | |
1460 | ||
7120d989 | 1461 | void iwl_set_hw_rfkill_state(struct iwl_op_mode *op_mode, bool state) |
3e10caeb | 1462 | { |
7120d989 EG |
1463 | struct iwl_priv *priv = IWL_OP_MODE_GET_DVM(op_mode); |
1464 | ||
c9eec95c | 1465 | if (state) |
83626404 | 1466 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
c9eec95c | 1467 | else |
83626404 | 1468 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
c9eec95c | 1469 | |
3e10caeb EG |
1470 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, state); |
1471 | } | |
7a10e3e4 | 1472 | |
ed277c93 | 1473 | void iwl_free_skb(struct iwl_op_mode *op_mode, struct sk_buff *skb) |
909e9b23 EG |
1474 | { |
1475 | struct ieee80211_tx_info *info; | |
1476 | ||
1477 | info = IEEE80211_SKB_CB(skb); | |
354928dd | 1478 | kmem_cache_free(iwl_tx_cmd_pool, (info->driver_data[1])); |
909e9b23 EG |
1479 | dev_kfree_skb_any(skb); |
1480 | } |