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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
901069c7 | 5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
d43c36dc | 32 | #include <linux/sched.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
1d0a082d | 34 | #include <net/mac80211.h> |
df48c323 | 35 | |
6bc913bd | 36 | #include "iwl-eeprom.h" |
3e0d4cb1 | 37 | #include "iwl-dev.h" /* FIXME: remove */ |
19335774 | 38 | #include "iwl-debug.h" |
df48c323 | 39 | #include "iwl-core.h" |
b661c819 | 40 | #include "iwl-io.h" |
5da4b55f | 41 | #include "iwl-power.h" |
83dde8c9 | 42 | #include "iwl-sta.h" |
ef850d7c | 43 | #include "iwl-helpers.h" |
9d143e9a | 44 | #include "iwl-agn.h" |
df48c323 | 45 | |
a562a9dd | 46 | u32 iwl_debug_level; |
a562a9dd | 47 | |
57bd1bea | 48 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
57bd1bea | 49 | |
d9fe60de JB |
50 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
51 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
c7de35cd | 52 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
d9fe60de | 53 | struct ieee80211_sta_ht_cap *ht_info, |
c7de35cd RR |
54 | enum ieee80211_band band) |
55 | { | |
39130df3 RR |
56 | u16 max_bit_rate = 0; |
57 | u8 rx_chains_num = priv->hw_params.rx_chains_num; | |
58 | u8 tx_chains_num = priv->hw_params.tx_chains_num; | |
59 | ||
c7de35cd | 60 | ht_info->cap = 0; |
d9fe60de | 61 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
c7de35cd | 62 | |
d9fe60de | 63 | ht_info->ht_supported = true; |
c7de35cd | 64 | |
7cb1b088 WYG |
65 | if (priv->cfg->ht_params && |
66 | priv->cfg->ht_params->ht_greenfield_support) | |
b261793d | 67 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; |
d9fe60de | 68 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; |
39130df3 | 69 | max_bit_rate = MAX_BIT_RATE_20_MHZ; |
7aafef1c | 70 | if (priv->hw_params.ht40_channel & BIT(band)) { |
d9fe60de JB |
71 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
72 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
73 | ht_info->mcs.rx_mask[4] = 0x01; | |
39130df3 | 74 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 75 | } |
c7de35cd | 76 | |
9d143e9a | 77 | if (iwlagn_mod_params.amsdu_size_8K) |
d9fe60de | 78 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
c7de35cd RR |
79 | |
80 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
7cb1b088 WYG |
81 | if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_factor) |
82 | ht_info->ampdu_factor = priv->cfg->bt_params->ampdu_factor; | |
c7de35cd | 83 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; |
7cb1b088 WYG |
84 | if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_density) |
85 | ht_info->ampdu_density = priv->cfg->bt_params->ampdu_density; | |
c7de35cd | 86 | |
d9fe60de | 87 | ht_info->mcs.rx_mask[0] = 0xFF; |
39130df3 | 88 | if (rx_chains_num >= 2) |
d9fe60de | 89 | ht_info->mcs.rx_mask[1] = 0xFF; |
39130df3 | 90 | if (rx_chains_num >= 3) |
d9fe60de | 91 | ht_info->mcs.rx_mask[2] = 0xFF; |
39130df3 RR |
92 | |
93 | /* Highest supported Rx data rate */ | |
94 | max_bit_rate *= rx_chains_num; | |
d9fe60de JB |
95 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
96 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
39130df3 RR |
97 | |
98 | /* Tx MCS capabilities */ | |
d9fe60de | 99 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
39130df3 | 100 | if (tx_chains_num != rx_chains_num) { |
d9fe60de JB |
101 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
102 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << | |
103 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
39130df3 | 104 | } |
c7de35cd | 105 | } |
c7de35cd | 106 | |
c7de35cd RR |
107 | /** |
108 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom | |
109 | */ | |
534166de | 110 | int iwlcore_init_geos(struct iwl_priv *priv) |
c7de35cd RR |
111 | { |
112 | struct iwl_channel_info *ch; | |
113 | struct ieee80211_supported_band *sband; | |
114 | struct ieee80211_channel *channels; | |
115 | struct ieee80211_channel *geo_ch; | |
116 | struct ieee80211_rate *rates; | |
117 | int i = 0; | |
75d80cad | 118 | s8 max_tx_power = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
c7de35cd RR |
119 | |
120 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
121 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
e1623446 | 122 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
c7de35cd RR |
123 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
124 | return 0; | |
125 | } | |
126 | ||
127 | channels = kzalloc(sizeof(struct ieee80211_channel) * | |
128 | priv->channel_count, GFP_KERNEL); | |
129 | if (!channels) | |
130 | return -ENOMEM; | |
131 | ||
5027309b | 132 | rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY), |
c7de35cd RR |
133 | GFP_KERNEL); |
134 | if (!rates) { | |
135 | kfree(channels); | |
136 | return -ENOMEM; | |
137 | } | |
138 | ||
139 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
140 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
141 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
142 | /* just OFDM */ | |
143 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
5027309b | 144 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE; |
c7de35cd | 145 | |
88950758 | 146 | if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE) |
d9fe60de | 147 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 148 | IEEE80211_BAND_5GHZ); |
c7de35cd RR |
149 | |
150 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
151 | sband->channels = channels; | |
152 | /* OFDM & CCK */ | |
153 | sband->bitrates = rates; | |
5027309b | 154 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY; |
c7de35cd | 155 | |
88950758 | 156 | if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE) |
d9fe60de | 157 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 158 | IEEE80211_BAND_2GHZ); |
c7de35cd RR |
159 | |
160 | priv->ieee_channels = channels; | |
161 | priv->ieee_rates = rates; | |
162 | ||
c7de35cd RR |
163 | for (i = 0; i < priv->channel_count; i++) { |
164 | ch = &priv->channel_info[i]; | |
165 | ||
166 | /* FIXME: might be removed if scan is OK */ | |
167 | if (!is_channel_valid(ch)) | |
168 | continue; | |
169 | ||
5a3a0352 | 170 | sband = &priv->bands[ch->band]; |
c7de35cd RR |
171 | |
172 | geo_ch = &sband->channels[sband->n_channels++]; | |
173 | ||
174 | geo_ch->center_freq = | |
5a3a0352 | 175 | ieee80211_channel_to_frequency(ch->channel, ch->band); |
c7de35cd RR |
176 | geo_ch->max_power = ch->max_power_avg; |
177 | geo_ch->max_antenna_gain = 0xff; | |
178 | geo_ch->hw_value = ch->channel; | |
179 | ||
180 | if (is_channel_valid(ch)) { | |
181 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
182 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
183 | ||
184 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
185 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
186 | ||
187 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
188 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
189 | ||
7aafef1c | 190 | geo_ch->flags |= ch->ht40_extension_channel; |
4d38c2e8 | 191 | |
75d80cad SG |
192 | if (ch->max_power_avg > max_tx_power) |
193 | max_tx_power = ch->max_power_avg; | |
c7de35cd RR |
194 | } else { |
195 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
196 | } | |
197 | ||
e1623446 | 198 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
199 | ch->channel, geo_ch->center_freq, |
200 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
201 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
202 | "restricted" : "valid", | |
203 | geo_ch->flags); | |
204 | } | |
205 | ||
75d80cad SG |
206 | priv->tx_power_device_lmt = max_tx_power; |
207 | priv->tx_power_user_lmt = max_tx_power; | |
208 | priv->tx_power_next = max_tx_power; | |
209 | ||
c7de35cd | 210 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
88950758 | 211 | priv->cfg->sku & EEPROM_SKU_CAP_BAND_52GHZ) { |
19707bac EG |
212 | char buf[32]; |
213 | priv->bus.ops->get_hw_id(&priv->bus, buf, sizeof(buf)); | |
978785a3 | 214 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
19707bac | 215 | "Please send your %s to maintainer.\n", buf); |
88950758 | 216 | priv->cfg->sku &= ~EEPROM_SKU_CAP_BAND_52GHZ; |
c7de35cd RR |
217 | } |
218 | ||
978785a3 | 219 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
a3139c59 SO |
220 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
221 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
c7de35cd RR |
222 | |
223 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | /* | |
229 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos | |
230 | */ | |
534166de | 231 | void iwlcore_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
232 | { |
233 | kfree(priv->ieee_channels); | |
234 | kfree(priv->ieee_rates); | |
235 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
236 | } | |
c7de35cd | 237 | |
7e6a5886 JB |
238 | static bool iwl_is_channel_extension(struct iwl_priv *priv, |
239 | enum ieee80211_band band, | |
240 | u16 channel, u8 extension_chan_offset) | |
47c5196e TW |
241 | { |
242 | const struct iwl_channel_info *ch_info; | |
243 | ||
244 | ch_info = iwl_get_channel_info(priv, band, channel); | |
245 | if (!is_channel_valid(ch_info)) | |
7e6a5886 | 246 | return false; |
47c5196e | 247 | |
d9fe60de | 248 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
7aafef1c | 249 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 250 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 251 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
7aafef1c | 252 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 253 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e | 254 | |
7e6a5886 | 255 | return false; |
47c5196e TW |
256 | } |
257 | ||
7e6a5886 JB |
258 | bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
259 | struct iwl_rxon_context *ctx, | |
260 | struct ieee80211_sta_ht_cap *ht_cap) | |
47c5196e | 261 | { |
7e6a5886 JB |
262 | if (!ctx->ht.enabled || !ctx->ht.is_40mhz) |
263 | return false; | |
47c5196e | 264 | |
7e6a5886 JB |
265 | /* |
266 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
a2b0f02e WYG |
267 | * the bit will not set if it is pure 40MHz case |
268 | */ | |
7e6a5886 JB |
269 | if (ht_cap && !ht_cap->ht_supported) |
270 | return false; | |
271 | ||
d73e4923 | 272 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1e4247d4 | 273 | if (priv->disable_ht40) |
7e6a5886 | 274 | return false; |
1e4247d4 | 275 | #endif |
7e6a5886 | 276 | |
611d3eb7 | 277 | return iwl_is_channel_extension(priv, priv->band, |
246ed355 | 278 | le16_to_cpu(ctx->staging.channel), |
7e6a5886 | 279 | ctx->ht.extension_chan_offset); |
47c5196e | 280 | } |
47c5196e | 281 | |
2c2f3b33 TW |
282 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
283 | { | |
ea196fdb JB |
284 | u16 new_val; |
285 | u16 beacon_factor; | |
286 | ||
287 | /* | |
288 | * If mac80211 hasn't given us a beacon interval, program | |
289 | * the default into the device (not checking this here | |
290 | * would cause the adjustment below to return the maximum | |
291 | * value, which may break PAN.) | |
292 | */ | |
293 | if (!beacon_val) | |
294 | return DEFAULT_BEACON_INTERVAL; | |
295 | ||
296 | /* | |
297 | * If the beacon interval we obtained from the peer | |
298 | * is too large, we'll have to wake up more often | |
299 | * (and in IBSS case, we'll beacon too much) | |
300 | * | |
301 | * For example, if max_beacon_val is 4096, and the | |
302 | * requested beacon interval is 7000, we'll have to | |
303 | * use 3500 to be able to wake up on the beacons. | |
304 | * | |
305 | * This could badly influence beacon detection stats. | |
306 | */ | |
2c2f3b33 TW |
307 | |
308 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
309 | new_val = beacon_val / beacon_factor; | |
310 | ||
311 | if (!new_val) | |
312 | new_val = max_beacon_val; | |
313 | ||
314 | return new_val; | |
315 | } | |
316 | ||
47313e34 | 317 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
2c2f3b33 TW |
318 | { |
319 | u64 tsf; | |
320 | s32 interval_tm, rem; | |
2c2f3b33 TW |
321 | struct ieee80211_conf *conf = NULL; |
322 | u16 beacon_int; | |
47313e34 | 323 | struct ieee80211_vif *vif = ctx->vif; |
2c2f3b33 TW |
324 | |
325 | conf = ieee80211_get_hw_conf(priv->hw); | |
326 | ||
948f5a2f JB |
327 | lockdep_assert_held(&priv->mutex); |
328 | ||
246ed355 | 329 | memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
948f5a2f | 330 | |
246ed355 JB |
331 | ctx->timing.timestamp = cpu_to_le64(priv->timestamp); |
332 | ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
2c2f3b33 | 333 | |
47313e34 | 334 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; |
2c2f3b33 | 335 | |
47313e34 JB |
336 | /* |
337 | * TODO: For IBSS we need to get atim_window from mac80211, | |
338 | * for now just always use 0 | |
339 | */ | |
340 | ctx->timing.atim_window = 0; | |
2c2f3b33 | 341 | |
bde4530e | 342 | if (ctx->ctxid == IWL_RXON_CTX_PAN && |
f1f270b2 JB |
343 | (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) && |
344 | iwl_is_associated(priv, IWL_RXON_CTX_BSS) && | |
345 | priv->contexts[IWL_RXON_CTX_BSS].vif && | |
346 | priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) { | |
bde4530e JB |
347 | ctx->timing.beacon_interval = |
348 | priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; | |
349 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
f1f270b2 JB |
350 | } else if (ctx->ctxid == IWL_RXON_CTX_BSS && |
351 | iwl_is_associated(priv, IWL_RXON_CTX_PAN) && | |
352 | priv->contexts[IWL_RXON_CTX_PAN].vif && | |
353 | priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int && | |
354 | (!iwl_is_associated_ctx(ctx) || !ctx->vif || | |
355 | !ctx->vif->bss_conf.beacon_int)) { | |
356 | ctx->timing.beacon_interval = | |
357 | priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; | |
358 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
bde4530e JB |
359 | } else { |
360 | beacon_int = iwl_adjust_beacon_interval(beacon_int, | |
f8525e55 | 361 | priv->hw_params.max_beacon_itrvl * TIME_UNIT); |
bde4530e JB |
362 | ctx->timing.beacon_interval = cpu_to_le16(beacon_int); |
363 | } | |
2c2f3b33 TW |
364 | |
365 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ | |
f8525e55 | 366 | interval_tm = beacon_int * TIME_UNIT; |
2c2f3b33 | 367 | rem = do_div(tsf, interval_tm); |
246ed355 | 368 | ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
2c2f3b33 | 369 | |
47313e34 | 370 | ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; |
2491fa42 | 371 | |
2c2f3b33 TW |
372 | IWL_DEBUG_ASSOC(priv, |
373 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
246ed355 JB |
374 | le16_to_cpu(ctx->timing.beacon_interval), |
375 | le32_to_cpu(ctx->timing.beacon_init_val), | |
376 | le16_to_cpu(ctx->timing.atim_window)); | |
948f5a2f | 377 | |
e419d62d EG |
378 | return priv->trans.ops->send_cmd_pdu(priv, ctx->rxon_timing_cmd, |
379 | CMD_SYNC, sizeof(ctx->timing), &ctx->timing); | |
2c2f3b33 | 380 | } |
2c2f3b33 | 381 | |
246ed355 JB |
382 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx, |
383 | int hw_decrypt) | |
8ccde88a | 384 | { |
246ed355 | 385 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a SO |
386 | |
387 | if (hw_decrypt) | |
388 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
389 | else | |
390 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
391 | ||
392 | } | |
8ccde88a | 393 | |
dacefedb | 394 | /* validate RXON structure is valid */ |
246ed355 | 395 | int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
8ccde88a | 396 | { |
246ed355 | 397 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
c914ac26 | 398 | u32 errors = 0; |
8ccde88a SO |
399 | |
400 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
dacefedb JB |
401 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { |
402 | IWL_WARN(priv, "check 2.4G: wrong narrow\n"); | |
c914ac26 | 403 | errors |= BIT(0); |
dacefedb JB |
404 | } |
405 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
406 | IWL_WARN(priv, "check 2.4G: wrong radar\n"); | |
c914ac26 | 407 | errors |= BIT(1); |
dacefedb | 408 | } |
8ccde88a | 409 | } else { |
dacefedb JB |
410 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { |
411 | IWL_WARN(priv, "check 5.2G: not short slot!\n"); | |
c914ac26 | 412 | errors |= BIT(2); |
dacefedb JB |
413 | } |
414 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
415 | IWL_WARN(priv, "check 5.2G: CCK!\n"); | |
c914ac26 | 416 | errors |= BIT(3); |
dacefedb JB |
417 | } |
418 | } | |
419 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
420 | IWL_WARN(priv, "mac/bssid mcast!\n"); | |
c914ac26 | 421 | errors |= BIT(4); |
8ccde88a | 422 | } |
8ccde88a SO |
423 | |
424 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
dacefedb JB |
425 | if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 && |
426 | (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) { | |
427 | IWL_WARN(priv, "neither 1 nor 6 are basic\n"); | |
c914ac26 | 428 | errors |= BIT(5); |
dacefedb | 429 | } |
8ccde88a | 430 | |
dacefedb JB |
431 | if (le16_to_cpu(rxon->assoc_id) > 2007) { |
432 | IWL_WARN(priv, "aid > 2007\n"); | |
c914ac26 | 433 | errors |= BIT(6); |
dacefedb | 434 | } |
8ccde88a | 435 | |
dacefedb JB |
436 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) |
437 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
438 | IWL_WARN(priv, "CCK and short slot\n"); | |
c914ac26 | 439 | errors |= BIT(7); |
dacefedb | 440 | } |
8ccde88a | 441 | |
dacefedb JB |
442 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) |
443 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
444 | IWL_WARN(priv, "CCK and auto detect"); | |
c914ac26 | 445 | errors |= BIT(8); |
dacefedb | 446 | } |
8ccde88a | 447 | |
dacefedb JB |
448 | if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | |
449 | RXON_FLG_TGG_PROTECT_MSK)) == | |
450 | RXON_FLG_TGG_PROTECT_MSK) { | |
451 | IWL_WARN(priv, "TGg but no auto-detect\n"); | |
c914ac26 | 452 | errors |= BIT(9); |
dacefedb | 453 | } |
8ccde88a | 454 | |
c914ac26 JB |
455 | if (rxon->channel == 0) { |
456 | IWL_WARN(priv, "zero channel is invalid\n"); | |
457 | errors |= BIT(10); | |
8ccde88a | 458 | } |
c914ac26 JB |
459 | |
460 | WARN(errors, "Invalid RXON (%#x), channel %d", | |
461 | errors, le16_to_cpu(rxon->channel)); | |
462 | ||
463 | return errors ? -EINVAL : 0; | |
8ccde88a | 464 | } |
8ccde88a SO |
465 | |
466 | /** | |
467 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
468 | * @priv: staging_rxon is compared to active_rxon | |
469 | * | |
470 | * If the RXON structure is changing enough to require a new tune, | |
471 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
472 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
473 | */ | |
246ed355 JB |
474 | int iwl_full_rxon_required(struct iwl_priv *priv, |
475 | struct iwl_rxon_context *ctx) | |
8ccde88a | 476 | { |
246ed355 JB |
477 | const struct iwl_rxon_cmd *staging = &ctx->staging; |
478 | const struct iwl_rxon_cmd *active = &ctx->active; | |
479 | ||
480 | #define CHK(cond) \ | |
481 | if ((cond)) { \ | |
482 | IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \ | |
483 | return 1; \ | |
484 | } | |
485 | ||
486 | #define CHK_NEQ(c1, c2) \ | |
487 | if ((c1) != (c2)) { \ | |
488 | IWL_DEBUG_INFO(priv, "need full RXON - " \ | |
489 | #c1 " != " #c2 " - %d != %d\n", \ | |
490 | (c1), (c2)); \ | |
491 | return 1; \ | |
492 | } | |
8ccde88a SO |
493 | |
494 | /* These items are only settable from the full RXON command */ | |
246ed355 JB |
495 | CHK(!iwl_is_associated_ctx(ctx)); |
496 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); | |
497 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
498 | CHK(compare_ether_addr(staging->wlap_bssid_addr, | |
499 | active->wlap_bssid_addr)); | |
500 | CHK_NEQ(staging->dev_type, active->dev_type); | |
501 | CHK_NEQ(staging->channel, active->channel); | |
502 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
503 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
504 | active->ofdm_ht_single_stream_basic_rates); | |
505 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
506 | active->ofdm_ht_dual_stream_basic_rates); | |
507 | CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates, | |
508 | active->ofdm_ht_triple_stream_basic_rates); | |
509 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
8ccde88a SO |
510 | |
511 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
512 | * be updated with the RXON_ASSOC command -- however only some | |
513 | * flag transitions are allowed using RXON_ASSOC */ | |
514 | ||
515 | /* Check if we are not switching bands */ | |
246ed355 JB |
516 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, |
517 | active->flags & RXON_FLG_BAND_24G_MSK); | |
8ccde88a SO |
518 | |
519 | /* Check if we are switching association toggle */ | |
246ed355 JB |
520 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, |
521 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
522 | ||
523 | #undef CHK | |
524 | #undef CHK_NEQ | |
8ccde88a SO |
525 | |
526 | return 0; | |
527 | } | |
8ccde88a | 528 | |
246ed355 JB |
529 | static void _iwl_set_rxon_ht(struct iwl_priv *priv, |
530 | struct iwl_ht_config *ht_conf, | |
531 | struct iwl_rxon_context *ctx) | |
47c5196e | 532 | { |
246ed355 | 533 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
47c5196e | 534 | |
7e6a5886 | 535 | if (!ctx->ht.enabled) { |
a2b0f02e | 536 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 | 537 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
7aafef1c | 538 | RXON_FLG_HT40_PROT_MSK | |
42eb7c64 | 539 | RXON_FLG_HT_PROT_MSK); |
47c5196e | 540 | return; |
42eb7c64 | 541 | } |
47c5196e | 542 | |
7e6a5886 | 543 | /* FIXME: if the definition of ht.protection changed, the "translation" |
a2b0f02e WYG |
544 | * will be needed for rxon->flags |
545 | */ | |
7e6a5886 | 546 | rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); |
a2b0f02e WYG |
547 | |
548 | /* Set up channel bandwidth: | |
7aafef1c | 549 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
a2b0f02e WYG |
550 | /* clear the HT channel mode before set the mode */ |
551 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
552 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
7e6a5886 | 553 | if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) { |
7aafef1c | 554 | /* pure ht40 */ |
7e6a5886 | 555 | if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
a2b0f02e | 556 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
508b08e7 | 557 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 558 | switch (ctx->ht.extension_chan_offset) { |
508b08e7 WYG |
559 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
560 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
561 | break; | |
562 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
563 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
564 | break; | |
565 | } | |
566 | } else { | |
a2b0f02e | 567 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 568 | switch (ctx->ht.extension_chan_offset) { |
a2b0f02e WYG |
569 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
570 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
571 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
572 | break; | |
573 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
574 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
575 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
576 | break; | |
577 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
578 | default: | |
579 | /* channel location only valid if in Mixed mode */ | |
580 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
581 | break; | |
582 | } | |
583 | } | |
584 | } else { | |
585 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
586 | } |
587 | ||
e3f10cea | 588 | iwlagn_set_rxon_chain(priv, ctx); |
47c5196e | 589 | |
02bb1bea | 590 | IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 591 | "extension channel offset 0x%x\n", |
7e6a5886 JB |
592 | le32_to_cpu(rxon->flags), ctx->ht.protection, |
593 | ctx->ht.extension_chan_offset); | |
47c5196e | 594 | } |
246ed355 JB |
595 | |
596 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf) | |
597 | { | |
598 | struct iwl_rxon_context *ctx; | |
599 | ||
600 | for_each_context(priv, ctx) | |
601 | _iwl_set_rxon_ht(priv, ht_conf, ctx); | |
602 | } | |
47c5196e | 603 | |
246ed355 | 604 | /* Return valid, unused, channel for a passive scan to reset the RF */ |
14023641 | 605 | u8 iwl_get_single_channel_number(struct iwl_priv *priv, |
246ed355 | 606 | enum ieee80211_band band) |
14023641 AK |
607 | { |
608 | const struct iwl_channel_info *ch_info; | |
609 | int i; | |
610 | u8 channel = 0; | |
246ed355 JB |
611 | u8 min, max; |
612 | struct iwl_rxon_context *ctx; | |
14023641 | 613 | |
14023641 | 614 | if (band == IEEE80211_BAND_5GHZ) { |
246ed355 JB |
615 | min = 14; |
616 | max = priv->channel_count; | |
14023641 | 617 | } else { |
246ed355 JB |
618 | min = 0; |
619 | max = 14; | |
620 | } | |
621 | ||
622 | for (i = min; i < max; i++) { | |
623 | bool busy = false; | |
624 | ||
625 | for_each_context(priv, ctx) { | |
626 | busy = priv->channel_info[i].channel == | |
627 | le16_to_cpu(ctx->staging.channel); | |
628 | if (busy) | |
629 | break; | |
14023641 | 630 | } |
246ed355 JB |
631 | |
632 | if (busy) | |
633 | continue; | |
634 | ||
635 | channel = priv->channel_info[i].channel; | |
636 | ch_info = iwl_get_channel_info(priv, band, channel); | |
637 | if (is_channel_valid(ch_info)) | |
638 | break; | |
14023641 AK |
639 | } |
640 | ||
641 | return channel; | |
642 | } | |
14023641 | 643 | |
bf85ea4f | 644 | /** |
3edb5fd6 SZ |
645 | * iwl_set_rxon_channel - Set the band and channel values in staging RXON |
646 | * @ch: requested channel as a pointer to struct ieee80211_channel | |
bf85ea4f | 647 | |
bf85ea4f | 648 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
3edb5fd6 | 649 | * in the staging RXON flag structure based on the ch->band |
bf85ea4f | 650 | */ |
246ed355 JB |
651 | int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch, |
652 | struct iwl_rxon_context *ctx) | |
bf85ea4f | 653 | { |
17e72782 | 654 | enum ieee80211_band band = ch->band; |
81e95430 | 655 | u16 channel = ch->hw_value; |
17e72782 | 656 | |
246ed355 | 657 | if ((le16_to_cpu(ctx->staging.channel) == channel) && |
bf85ea4f AK |
658 | (priv->band == band)) |
659 | return 0; | |
660 | ||
246ed355 | 661 | ctx->staging.channel = cpu_to_le16(channel); |
bf85ea4f | 662 | if (band == IEEE80211_BAND_5GHZ) |
246ed355 | 663 | ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK; |
bf85ea4f | 664 | else |
246ed355 | 665 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
bf85ea4f AK |
666 | |
667 | priv->band = band; | |
668 | ||
e1623446 | 669 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f AK |
670 | |
671 | return 0; | |
672 | } | |
bf85ea4f | 673 | |
79d07325 | 674 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
246ed355 | 675 | struct iwl_rxon_context *ctx, |
79d07325 WYG |
676 | enum ieee80211_band band, |
677 | struct ieee80211_vif *vif) | |
8ccde88a SO |
678 | { |
679 | if (band == IEEE80211_BAND_5GHZ) { | |
246ed355 | 680 | ctx->staging.flags &= |
8ccde88a SO |
681 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
682 | | RXON_FLG_CCK_MSK); | |
246ed355 | 683 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a SO |
684 | } else { |
685 | /* Copied from iwl_post_associate() */ | |
c213d745 | 686 | if (vif && vif->bss_conf.use_short_slot) |
246ed355 | 687 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 688 | else |
246ed355 | 689 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 690 | |
246ed355 JB |
691 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
692 | ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
693 | ctx->staging.flags &= ~RXON_FLG_CCK_MSK; | |
8ccde88a SO |
694 | } |
695 | } | |
8ccde88a SO |
696 | |
697 | /* | |
698 | * initialize rxon structure with default values from eeprom | |
699 | */ | |
1dda6d28 | 700 | void iwl_connection_init_rx_config(struct iwl_priv *priv, |
d0fe478c | 701 | struct iwl_rxon_context *ctx) |
8ccde88a SO |
702 | { |
703 | const struct iwl_channel_info *ch_info; | |
704 | ||
246ed355 | 705 | memset(&ctx->staging, 0, sizeof(ctx->staging)); |
8ccde88a | 706 | |
d0fe478c JB |
707 | if (!ctx->vif) { |
708 | ctx->staging.dev_type = ctx->unused_devtype; | |
709 | } else switch (ctx->vif->type) { | |
8ccde88a | 710 | case NL80211_IFTYPE_AP: |
d0fe478c | 711 | ctx->staging.dev_type = ctx->ap_devtype; |
8ccde88a SO |
712 | break; |
713 | ||
714 | case NL80211_IFTYPE_STATION: | |
d0fe478c | 715 | ctx->staging.dev_type = ctx->station_devtype; |
246ed355 | 716 | ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; |
8ccde88a SO |
717 | break; |
718 | ||
719 | case NL80211_IFTYPE_ADHOC: | |
d0fe478c | 720 | ctx->staging.dev_type = ctx->ibss_devtype; |
246ed355 JB |
721 | ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; |
722 | ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
8ccde88a SO |
723 | RXON_FILTER_ACCEPT_GRP_MSK; |
724 | break; | |
725 | ||
8ccde88a | 726 | default: |
d0fe478c JB |
727 | IWL_ERR(priv, "Unsupported interface type %d\n", |
728 | ctx->vif->type); | |
8ccde88a SO |
729 | break; |
730 | } | |
731 | ||
732 | #if 0 | |
733 | /* TODO: Figure out when short_preamble would be set and cache from | |
734 | * that */ | |
735 | if (!hw_to_local(priv->hw)->short_preamble) | |
246ed355 | 736 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a | 737 | else |
246ed355 | 738 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a SO |
739 | #endif |
740 | ||
741 | ch_info = iwl_get_channel_info(priv, priv->band, | |
246ed355 | 742 | le16_to_cpu(ctx->active.channel)); |
8ccde88a SO |
743 | |
744 | if (!ch_info) | |
745 | ch_info = &priv->channel_info[0]; | |
746 | ||
246ed355 | 747 | ctx->staging.channel = cpu_to_le16(ch_info->channel); |
8ccde88a SO |
748 | priv->band = ch_info->band; |
749 | ||
d0fe478c | 750 | iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif); |
8ccde88a | 751 | |
246ed355 | 752 | ctx->staging.ofdm_basic_rates = |
8ccde88a | 753 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
246ed355 | 754 | ctx->staging.cck_basic_rates = |
8ccde88a SO |
755 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
756 | ||
a2b0f02e | 757 | /* clear both MIX and PURE40 mode flag */ |
246ed355 | 758 | ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | |
a2b0f02e | 759 | RXON_FLG_CHANNEL_MODE_PURE_40); |
d0fe478c JB |
760 | if (ctx->vif) |
761 | memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN); | |
7684c408 | 762 | |
246ed355 JB |
763 | ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff; |
764 | ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
765 | ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff; | |
8ccde88a | 766 | } |
8ccde88a | 767 | |
79d07325 | 768 | void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
769 | { |
770 | const struct ieee80211_supported_band *hw = NULL; | |
771 | struct ieee80211_rate *rate; | |
246ed355 | 772 | struct iwl_rxon_context *ctx; |
8ccde88a SO |
773 | int i; |
774 | ||
775 | hw = iwl_get_hw_mode(priv, priv->band); | |
776 | if (!hw) { | |
777 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
778 | return; | |
779 | } | |
780 | ||
781 | priv->active_rate = 0; | |
8ccde88a SO |
782 | |
783 | for (i = 0; i < hw->n_bitrates; i++) { | |
784 | rate = &(hw->bitrates[i]); | |
5027309b | 785 | if (rate->hw_value < IWL_RATE_COUNT_LEGACY) |
8ccde88a SO |
786 | priv->active_rate |= (1 << rate->hw_value); |
787 | } | |
788 | ||
4a02886b | 789 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate); |
8ccde88a | 790 | |
246ed355 JB |
791 | for_each_context(priv, ctx) { |
792 | ctx->staging.cck_basic_rates = | |
793 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
4a02886b | 794 | |
246ed355 JB |
795 | ctx->staging.ofdm_basic_rates = |
796 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
797 | } | |
8ccde88a | 798 | } |
79d07325 WYG |
799 | |
800 | void iwl_chswitch_done(struct iwl_priv *priv, bool is_success) | |
801 | { | |
8bd413e6 JB |
802 | /* |
803 | * MULTI-FIXME | |
804 | * See iwl_mac_channel_switch. | |
805 | */ | |
806 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
807 | ||
79d07325 WYG |
808 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
809 | return; | |
810 | ||
6f213ff1 | 811 | if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status)) |
8bd413e6 | 812 | ieee80211_chswitch_done(ctx->vif, is_success); |
79d07325 | 813 | } |
8ccde88a | 814 | |
8ccde88a | 815 | #ifdef CONFIG_IWLWIFI_DEBUG |
246ed355 JB |
816 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, |
817 | struct iwl_rxon_context *ctx) | |
8ccde88a | 818 | { |
246ed355 | 819 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a | 820 | |
e1623446 | 821 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
3d816c77 | 822 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
823 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
824 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
825 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 826 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
827 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
828 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 829 | rxon->ofdm_basic_rates); |
e1623446 TW |
830 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
831 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
832 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
833 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a | 834 | } |
6686d17e | 835 | #endif |
e649437f | 836 | |
e74fe233 JB |
837 | static void iwlagn_abort_notification_waits(struct iwl_priv *priv) |
838 | { | |
839 | unsigned long flags; | |
840 | struct iwl_notification_wait *wait_entry; | |
841 | ||
842 | spin_lock_irqsave(&priv->_agn.notif_wait_lock, flags); | |
843 | list_for_each_entry(wait_entry, &priv->_agn.notif_waits, list) | |
844 | wait_entry->aborted = true; | |
845 | spin_unlock_irqrestore(&priv->_agn.notif_wait_lock, flags); | |
846 | ||
847 | wake_up_all(&priv->_agn.notif_waitq); | |
848 | } | |
849 | ||
e649437f | 850 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) |
8ccde88a | 851 | { |
491bc292 WYG |
852 | unsigned int reload_msec; |
853 | unsigned long reload_jiffies; | |
854 | ||
8ccde88a SO |
855 | /* Set the FW error flag -- cleared on iwl_down */ |
856 | set_bit(STATUS_FW_ERROR, &priv->status); | |
857 | ||
858 | /* Cancel currently queued command. */ | |
859 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
860 | ||
e74fe233 JB |
861 | iwlagn_abort_notification_waits(priv); |
862 | ||
e649437f JB |
863 | /* Keep the restart process from trying to send host |
864 | * commands by clearing the ready bit */ | |
865 | clear_bit(STATUS_READY, &priv->status); | |
866 | ||
867 | wake_up_interruptible(&priv->wait_command_queue); | |
868 | ||
869 | if (!ondemand) { | |
870 | /* | |
871 | * If firmware keep reloading, then it indicate something | |
872 | * serious wrong and firmware having problem to recover | |
873 | * from it. Instead of keep trying which will fill the syslog | |
874 | * and hang the system, let's just stop it | |
875 | */ | |
876 | reload_jiffies = jiffies; | |
877 | reload_msec = jiffies_to_msecs((long) reload_jiffies - | |
878 | (long) priv->reload_jiffies); | |
879 | priv->reload_jiffies = reload_jiffies; | |
880 | if (reload_msec <= IWL_MIN_RELOAD_DURATION) { | |
881 | priv->reload_count++; | |
882 | if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) { | |
883 | IWL_ERR(priv, "BUG_ON, Stop restarting\n"); | |
884 | return; | |
885 | } | |
886 | } else | |
887 | priv->reload_count = 0; | |
888 | } | |
889 | ||
890 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
9d143e9a | 891 | if (iwlagn_mod_params.restart_fw) { |
e649437f JB |
892 | IWL_DEBUG(priv, IWL_DL_FW_ERRORS, |
893 | "Restarting adapter due to uCode error.\n"); | |
894 | queue_work(priv->workqueue, &priv->restart); | |
895 | } else | |
896 | IWL_DEBUG(priv, IWL_DL_FW_ERRORS, | |
897 | "Detected FW error, but not restarting\n"); | |
898 | } | |
899 | } | |
900 | ||
901 | /** | |
902 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
903 | */ | |
904 | void iwl_irq_handle_error(struct iwl_priv *priv) | |
905 | { | |
50619ac9 WYG |
906 | /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ |
907 | if (priv->cfg->internal_wimax_coex && | |
908 | (!(iwl_read_prph(priv, APMG_CLK_CTRL_REG) & | |
909 | APMS_CLK_VAL_MRB_FUNC_MODE) || | |
910 | (iwl_read_prph(priv, APMG_PS_CTRL_REG) & | |
911 | APMG_PS_CTRL_VAL_RESET_REQ))) { | |
50619ac9 | 912 | /* |
e649437f JB |
913 | * Keep the restart process from trying to send host |
914 | * commands by clearing the ready bit. | |
50619ac9 WYG |
915 | */ |
916 | clear_bit(STATUS_READY, &priv->status); | |
e649437f JB |
917 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
918 | wake_up_interruptible(&priv->wait_command_queue); | |
50619ac9 WYG |
919 | IWL_ERR(priv, "RF is used by WiMAX\n"); |
920 | return; | |
921 | } | |
922 | ||
459bc732 SZ |
923 | IWL_ERR(priv, "Loaded firmware version: %s\n", |
924 | priv->hw->wiphy->fw_version); | |
925 | ||
3ecccbcd WYG |
926 | iwl_dump_nic_error_log(priv); |
927 | iwl_dump_csr(priv); | |
928 | iwl_dump_fh(priv, NULL, false); | |
929 | iwl_dump_nic_event_log(priv, false, NULL, false); | |
8ccde88a | 930 | #ifdef CONFIG_IWLWIFI_DEBUG |
c341ddb2 | 931 | if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) |
246ed355 JB |
932 | iwl_print_rx_config_cmd(priv, |
933 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
8ccde88a SO |
934 | #endif |
935 | ||
e649437f | 936 | iwlagn_fw_error(priv, false); |
8ccde88a | 937 | } |
8ccde88a | 938 | |
f8e200de | 939 | static int iwl_apm_stop_master(struct iwl_priv *priv) |
d68b603c | 940 | { |
5220af0c | 941 | int ret = 0; |
d68b603c | 942 | |
5220af0c | 943 | /* stop device's busmaster DMA activity */ |
d68b603c AK |
944 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
945 | ||
5220af0c | 946 | ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, |
d68b603c | 947 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
5220af0c BC |
948 | if (ret) |
949 | IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n"); | |
d68b603c | 950 | |
d68b603c AK |
951 | IWL_DEBUG_INFO(priv, "stop master\n"); |
952 | ||
5220af0c | 953 | return ret; |
d68b603c | 954 | } |
d68b603c AK |
955 | |
956 | void iwl_apm_stop(struct iwl_priv *priv) | |
957 | { | |
fadb3582 BC |
958 | IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n"); |
959 | ||
9d39e5ba JB |
960 | clear_bit(STATUS_DEVICE_ENABLED, &priv->status); |
961 | ||
5220af0c | 962 | /* Stop device's DMA activity */ |
d68b603c AK |
963 | iwl_apm_stop_master(priv); |
964 | ||
5220af0c | 965 | /* Reset the entire device */ |
d68b603c AK |
966 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
967 | ||
968 | udelay(10); | |
5220af0c BC |
969 | |
970 | /* | |
971 | * Clear "initialization complete" bit to move adapter from | |
972 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
973 | */ | |
d68b603c | 974 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
d68b603c | 975 | } |
d68b603c | 976 | |
fadb3582 BC |
977 | |
978 | /* | |
979 | * Start up NIC's basic functionality after it has been reset | |
980 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
981 | * NOTE: This does not load uCode nor start the embedded processor | |
982 | */ | |
983 | int iwl_apm_init(struct iwl_priv *priv) | |
984 | { | |
985 | int ret = 0; | |
fadb3582 BC |
986 | IWL_DEBUG_INFO(priv, "Init card's basic functions\n"); |
987 | ||
988 | /* | |
989 | * Use "set_bit" below rather than "write", to preserve any hardware | |
990 | * bits already set by default after reset. | |
991 | */ | |
992 | ||
993 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
994 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
995 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
996 | ||
997 | /* | |
998 | * Disable L0s without affecting L1; | |
999 | * don't wait for ICH L0s (ICH bug W/A) | |
1000 | */ | |
1001 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
1002 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
1003 | ||
1004 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
1005 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
1006 | ||
1007 | /* | |
1008 | * Enable HAP INTA (interrupt from management bus) to | |
1009 | * wake device's PCI Express link L1a -> L0s | |
fadb3582 BC |
1010 | */ |
1011 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1012 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
1013 | ||
d57fa99d | 1014 | priv->bus.ops->apm_config(&priv->bus); |
fadb3582 BC |
1015 | |
1016 | /* Configure analog phase-lock-loop before activating to D0A */ | |
7cb1b088 WYG |
1017 | if (priv->cfg->base_params->pll_cfg_val) |
1018 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, | |
1019 | priv->cfg->base_params->pll_cfg_val); | |
fadb3582 BC |
1020 | |
1021 | /* | |
1022 | * Set "initialization complete" bit to move adapter from | |
1023 | * D0U* --> D0A* (powered-up active) state. | |
1024 | */ | |
1025 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1026 | ||
1027 | /* | |
1028 | * Wait for clock stabilization; once stabilized, access to | |
1029 | * device-internal resources is supported, e.g. iwl_write_prph() | |
1030 | * and accesses to uCode SRAM. | |
1031 | */ | |
1032 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
1033 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1034 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
1035 | if (ret < 0) { | |
1036 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); | |
1037 | goto out; | |
1038 | } | |
1039 | ||
1040 | /* | |
917b6777 | 1041 | * Enable DMA clock and wait for it to stabilize. |
fadb3582 BC |
1042 | * |
1043 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
1044 | * do not disable clocks. This preserves any hardware bits already | |
1045 | * set by default in "CLK_CTRL_REG" after reset. | |
1046 | */ | |
917b6777 | 1047 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
fadb3582 BC |
1048 | udelay(20); |
1049 | ||
1050 | /* Disable L1-Active */ | |
1051 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
1052 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
1053 | ||
9d39e5ba JB |
1054 | set_bit(STATUS_DEVICE_ENABLED, &priv->status); |
1055 | ||
fadb3582 BC |
1056 | out: |
1057 | return ret; | |
1058 | } | |
fadb3582 BC |
1059 | |
1060 | ||
630fe9b6 TW |
1061 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
1062 | { | |
a25a66ac SG |
1063 | int ret; |
1064 | s8 prev_tx_power; | |
f844a709 SG |
1065 | bool defer; |
1066 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
a25a66ac SG |
1067 | |
1068 | lockdep_assert_held(&priv->mutex); | |
1069 | ||
1070 | if (priv->tx_power_user_lmt == tx_power && !force) | |
1071 | return 0; | |
1072 | ||
b744cb79 WYG |
1073 | if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) { |
1074 | IWL_WARN(priv, | |
1075 | "Requested user TXPOWER %d below lower limit %d.\n", | |
daf518de | 1076 | tx_power, |
b744cb79 | 1077 | IWLAGN_TX_POWER_TARGET_POWER_MIN); |
630fe9b6 TW |
1078 | return -EINVAL; |
1079 | } | |
1080 | ||
dc1b0973 | 1081 | if (tx_power > priv->tx_power_device_lmt) { |
08f2d58d WYG |
1082 | IWL_WARN(priv, |
1083 | "Requested user TXPOWER %d above upper limit %d.\n", | |
dc1b0973 | 1084 | tx_power, priv->tx_power_device_lmt); |
630fe9b6 TW |
1085 | return -EINVAL; |
1086 | } | |
1087 | ||
a25a66ac SG |
1088 | if (!iwl_is_ready_rf(priv)) |
1089 | return -EIO; | |
630fe9b6 | 1090 | |
f844a709 SG |
1091 | /* scan complete and commit_rxon use tx_power_next value, |
1092 | * it always need to be updated for newest request */ | |
a25a66ac | 1093 | priv->tx_power_next = tx_power; |
f844a709 SG |
1094 | |
1095 | /* do not set tx power when scanning or channel changing */ | |
1096 | defer = test_bit(STATUS_SCANNING, &priv->status) || | |
1097 | memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)); | |
1098 | if (defer && !force) { | |
1099 | IWL_DEBUG_INFO(priv, "Deferring tx power set\n"); | |
a25a66ac | 1100 | return 0; |
5eadd94b | 1101 | } |
630fe9b6 | 1102 | |
a25a66ac SG |
1103 | prev_tx_power = priv->tx_power_user_lmt; |
1104 | priv->tx_power_user_lmt = tx_power; | |
1105 | ||
5beaaf37 | 1106 | ret = iwlagn_send_tx_power(priv); |
a25a66ac SG |
1107 | |
1108 | /* if fail to set tx_power, restore the orig. tx power */ | |
1109 | if (ret) { | |
1110 | priv->tx_power_user_lmt = prev_tx_power; | |
1111 | priv->tx_power_next = prev_tx_power; | |
1112 | } | |
630fe9b6 TW |
1113 | return ret; |
1114 | } | |
630fe9b6 | 1115 | |
65b52bde | 1116 | void iwl_send_bt_config(struct iwl_priv *priv) |
17f841cd SO |
1117 | { |
1118 | struct iwl_bt_cmd bt_cmd = { | |
456d0f76 WYG |
1119 | .lead_time = BT_LEAD_TIME_DEF, |
1120 | .max_kill = BT_MAX_KILL_DEF, | |
17f841cd SO |
1121 | .kill_ack_mask = 0, |
1122 | .kill_cts_mask = 0, | |
1123 | }; | |
1124 | ||
b60eec9b | 1125 | if (!iwlagn_mod_params.bt_coex_active) |
06702a73 WYG |
1126 | bt_cmd.flags = BT_COEX_DISABLE; |
1127 | else | |
1128 | bt_cmd.flags = BT_COEX_ENABLE; | |
1129 | ||
f21dd005 | 1130 | priv->bt_enable_flag = bt_cmd.flags; |
06702a73 WYG |
1131 | IWL_DEBUG_INFO(priv, "BT coex %s\n", |
1132 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); | |
1133 | ||
e419d62d EG |
1134 | if (priv->trans.ops->send_cmd_pdu(priv, REPLY_BT_CONFIG, |
1135 | CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd)) | |
65b52bde | 1136 | IWL_ERR(priv, "failed to send BT Coex Config\n"); |
17f841cd | 1137 | } |
17f841cd | 1138 | |
ef8d5529 | 1139 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear) |
49ea8596 | 1140 | { |
ef8d5529 WYG |
1141 | struct iwl_statistics_cmd statistics_cmd = { |
1142 | .configuration_flags = | |
1143 | clear ? IWL_STATS_CONF_CLEAR_STATS : 0, | |
49ea8596 | 1144 | }; |
ef8d5529 WYG |
1145 | |
1146 | if (flags & CMD_ASYNC) | |
e419d62d EG |
1147 | return priv->trans.ops->send_cmd_pdu(priv, REPLY_STATISTICS_CMD, |
1148 | CMD_ASYNC, | |
ef8d5529 | 1149 | sizeof(struct iwl_statistics_cmd), |
e419d62d | 1150 | &statistics_cmd); |
ef8d5529 | 1151 | else |
e419d62d EG |
1152 | return priv->trans.ops->send_cmd_pdu(priv, REPLY_STATISTICS_CMD, |
1153 | CMD_SYNC, | |
ef8d5529 WYG |
1154 | sizeof(struct iwl_statistics_cmd), |
1155 | &statistics_cmd); | |
49ea8596 | 1156 | } |
7e8c519e | 1157 | |
a83b9141 WYG |
1158 | void iwl_clear_isr_stats(struct iwl_priv *priv) |
1159 | { | |
1160 | memset(&priv->isr_stats, 0, sizeof(priv->isr_stats)); | |
1161 | } | |
a83b9141 | 1162 | |
488829f1 AK |
1163 | int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
1164 | const struct ieee80211_tx_queue_params *params) | |
1165 | { | |
1166 | struct iwl_priv *priv = hw->priv; | |
8dfdb9d5 | 1167 | struct iwl_rxon_context *ctx; |
488829f1 AK |
1168 | unsigned long flags; |
1169 | int q; | |
1170 | ||
1171 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
1172 | ||
1173 | if (!iwl_is_ready_rf(priv)) { | |
1174 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
1175 | return -EIO; | |
1176 | } | |
1177 | ||
1178 | if (queue >= AC_NUM) { | |
1179 | IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue); | |
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | q = AC_NUM - 1 - queue; | |
1184 | ||
1185 | spin_lock_irqsave(&priv->lock, flags); | |
1186 | ||
8dfdb9d5 JB |
1187 | /* |
1188 | * MULTI-FIXME | |
1189 | * This may need to be done per interface in nl80211/cfg80211/mac80211. | |
1190 | */ | |
1191 | for_each_context(priv, ctx) { | |
1192 | ctx->qos_data.def_qos_parm.ac[q].cw_min = | |
1193 | cpu_to_le16(params->cw_min); | |
1194 | ctx->qos_data.def_qos_parm.ac[q].cw_max = | |
1195 | cpu_to_le16(params->cw_max); | |
1196 | ctx->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
1197 | ctx->qos_data.def_qos_parm.ac[q].edca_txop = | |
1198 | cpu_to_le16((params->txop * 32)); | |
1199 | ||
1200 | ctx->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
1201 | } | |
488829f1 AK |
1202 | |
1203 | spin_unlock_irqrestore(&priv->lock, flags); | |
1204 | ||
1205 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
1206 | return 0; | |
1207 | } | |
5bbe233b | 1208 | |
a85d7cca JB |
1209 | int iwl_mac_tx_last_beacon(struct ieee80211_hw *hw) |
1210 | { | |
1211 | struct iwl_priv *priv = hw->priv; | |
1212 | ||
1213 | return priv->ibss_manager == IWL_IBSS_MANAGER; | |
1214 | } | |
a85d7cca | 1215 | |
d4daaea6 | 1216 | static int iwl_set_mode(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
727882d6 | 1217 | { |
d0fe478c | 1218 | iwl_connection_init_rx_config(priv, ctx); |
727882d6 | 1219 | |
e3f10cea | 1220 | iwlagn_set_rxon_chain(priv, ctx); |
727882d6 | 1221 | |
805a3b81 | 1222 | return iwlagn_commit_rxon(priv, ctx); |
727882d6 | 1223 | } |
727882d6 | 1224 | |
d4daaea6 JB |
1225 | static int iwl_setup_interface(struct iwl_priv *priv, |
1226 | struct iwl_rxon_context *ctx) | |
1227 | { | |
1228 | struct ieee80211_vif *vif = ctx->vif; | |
1229 | int err; | |
1230 | ||
1231 | lockdep_assert_held(&priv->mutex); | |
1232 | ||
1233 | /* | |
1234 | * This variable will be correct only when there's just | |
1235 | * a single context, but all code using it is for hardware | |
1236 | * that supports only one context. | |
1237 | */ | |
1238 | priv->iw_mode = vif->type; | |
1239 | ||
1240 | ctx->is_active = true; | |
1241 | ||
1242 | err = iwl_set_mode(priv, ctx); | |
1243 | if (err) { | |
1244 | if (!ctx->always_active) | |
1245 | ctx->is_active = false; | |
1246 | return err; | |
1247 | } | |
1248 | ||
1249 | if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist && | |
1250 | vif->type == NL80211_IFTYPE_ADHOC) { | |
1251 | /* | |
1252 | * pretend to have high BT traffic as long as we | |
1253 | * are operating in IBSS mode, as this will cause | |
1254 | * the rate scaling etc. to behave as intended. | |
1255 | */ | |
1256 | priv->bt_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_HIGH; | |
1257 | } | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
b55e75ed | 1262 | int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
cbb6ab94 AK |
1263 | { |
1264 | struct iwl_priv *priv = hw->priv; | |
246ed355 | 1265 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
d0fe478c | 1266 | struct iwl_rxon_context *tmp, *ctx = NULL; |
d4daaea6 | 1267 | int err; |
f35c0c56 | 1268 | enum nl80211_iftype viftype = ieee80211_vif_type_p2p(vif); |
cbb6ab94 | 1269 | |
3779db10 | 1270 | IWL_DEBUG_MAC80211(priv, "enter: type %d, addr %pM\n", |
f35c0c56 | 1271 | viftype, vif->addr); |
cbb6ab94 | 1272 | |
47e28f41 JB |
1273 | mutex_lock(&priv->mutex); |
1274 | ||
4bd530f3 SG |
1275 | if (!iwl_is_ready_rf(priv)) { |
1276 | IWL_WARN(priv, "Try to add interface when device not ready\n"); | |
b55e75ed JB |
1277 | err = -EINVAL; |
1278 | goto out; | |
1279 | } | |
1280 | ||
d0fe478c JB |
1281 | for_each_context(priv, tmp) { |
1282 | u32 possible_modes = | |
1283 | tmp->interface_modes | tmp->exclusive_interface_modes; | |
1284 | ||
1285 | if (tmp->vif) { | |
1286 | /* check if this busy context is exclusive */ | |
1287 | if (tmp->exclusive_interface_modes & | |
1288 | BIT(tmp->vif->type)) { | |
1289 | err = -EINVAL; | |
1290 | goto out; | |
1291 | } | |
1292 | continue; | |
1293 | } | |
1294 | ||
f35c0c56 | 1295 | if (!(possible_modes & BIT(viftype))) |
d0fe478c JB |
1296 | continue; |
1297 | ||
1298 | /* have maybe usable context w/o interface */ | |
1299 | ctx = tmp; | |
1300 | break; | |
1301 | } | |
1302 | ||
1303 | if (!ctx) { | |
47e28f41 JB |
1304 | err = -EOPNOTSUPP; |
1305 | goto out; | |
cbb6ab94 AK |
1306 | } |
1307 | ||
d0fe478c | 1308 | vif_priv->ctx = ctx; |
8bd413e6 | 1309 | ctx->vif = vif; |
59079949 | 1310 | |
d4daaea6 JB |
1311 | err = iwl_setup_interface(priv, ctx); |
1312 | if (!err) | |
1313 | goto out; | |
cbb6ab94 | 1314 | |
8bd413e6 | 1315 | ctx->vif = NULL; |
b55e75ed | 1316 | priv->iw_mode = NL80211_IFTYPE_STATION; |
47e28f41 | 1317 | out: |
cbb6ab94 AK |
1318 | mutex_unlock(&priv->mutex); |
1319 | ||
1320 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
47e28f41 | 1321 | return err; |
cbb6ab94 | 1322 | } |
cbb6ab94 | 1323 | |
d4daaea6 JB |
1324 | static void iwl_teardown_interface(struct iwl_priv *priv, |
1325 | struct ieee80211_vif *vif, | |
1326 | bool mode_change) | |
d8052319 | 1327 | { |
246ed355 | 1328 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); |
d8052319 | 1329 | |
d4daaea6 | 1330 | lockdep_assert_held(&priv->mutex); |
d0fe478c | 1331 | |
e7e16b90 SG |
1332 | if (priv->scan_vif == vif) { |
1333 | iwl_scan_cancel_timeout(priv, 200); | |
1334 | iwl_force_scan_end(priv); | |
1335 | } | |
8bd413e6 | 1336 | |
d4daaea6 JB |
1337 | if (!mode_change) { |
1338 | iwl_set_mode(priv, ctx); | |
1339 | if (!ctx->always_active) | |
1340 | ctx->is_active = false; | |
1341 | } | |
763cc3bf | 1342 | |
59079949 JB |
1343 | /* |
1344 | * When removing the IBSS interface, overwrite the | |
1345 | * BT traffic load with the stored one from the last | |
1346 | * notification, if any. If this is a device that | |
1347 | * doesn't implement this, this has no effect since | |
1348 | * both values are the same and zero. | |
1349 | */ | |
1350 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
66e863a5 | 1351 | priv->bt_traffic_load = priv->last_bt_traffic_load; |
d4daaea6 JB |
1352 | } |
1353 | ||
1354 | void iwl_mac_remove_interface(struct ieee80211_hw *hw, | |
1355 | struct ieee80211_vif *vif) | |
1356 | { | |
1357 | struct iwl_priv *priv = hw->priv; | |
1358 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); | |
1359 | ||
1360 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
1361 | ||
1362 | mutex_lock(&priv->mutex); | |
1363 | ||
1364 | WARN_ON(ctx->vif != vif); | |
1365 | ctx->vif = NULL; | |
1366 | ||
1367 | iwl_teardown_interface(priv, vif, false); | |
59079949 | 1368 | |
d8052319 AK |
1369 | mutex_unlock(&priv->mutex); |
1370 | ||
1371 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
1372 | ||
1373 | } | |
d8052319 | 1374 | |
20594eb0 WYG |
1375 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1376 | ||
1377 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) | |
1378 | ||
1379 | void iwl_reset_traffic_log(struct iwl_priv *priv) | |
1380 | { | |
1381 | priv->tx_traffic_idx = 0; | |
1382 | priv->rx_traffic_idx = 0; | |
1383 | if (priv->tx_traffic) | |
1384 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1385 | if (priv->rx_traffic) | |
1386 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1387 | } | |
1388 | ||
1389 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) | |
1390 | { | |
1391 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; | |
1392 | ||
1393 | if (iwl_debug_level & IWL_DL_TX) { | |
1394 | if (!priv->tx_traffic) { | |
1395 | priv->tx_traffic = | |
1396 | kzalloc(traffic_size, GFP_KERNEL); | |
1397 | if (!priv->tx_traffic) | |
1398 | return -ENOMEM; | |
1399 | } | |
1400 | } | |
1401 | if (iwl_debug_level & IWL_DL_RX) { | |
1402 | if (!priv->rx_traffic) { | |
1403 | priv->rx_traffic = | |
1404 | kzalloc(traffic_size, GFP_KERNEL); | |
1405 | if (!priv->rx_traffic) | |
1406 | return -ENOMEM; | |
1407 | } | |
1408 | } | |
1409 | iwl_reset_traffic_log(priv); | |
1410 | return 0; | |
1411 | } | |
20594eb0 WYG |
1412 | |
1413 | void iwl_free_traffic_mem(struct iwl_priv *priv) | |
1414 | { | |
1415 | kfree(priv->tx_traffic); | |
1416 | priv->tx_traffic = NULL; | |
1417 | ||
1418 | kfree(priv->rx_traffic); | |
1419 | priv->rx_traffic = NULL; | |
1420 | } | |
20594eb0 WYG |
1421 | |
1422 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | |
1423 | u16 length, struct ieee80211_hdr *header) | |
1424 | { | |
1425 | __le16 fc; | |
1426 | u16 len; | |
1427 | ||
1428 | if (likely(!(iwl_debug_level & IWL_DL_TX))) | |
1429 | return; | |
1430 | ||
1431 | if (!priv->tx_traffic) | |
1432 | return; | |
1433 | ||
1434 | fc = header->frame_control; | |
1435 | if (ieee80211_is_data(fc)) { | |
1436 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1437 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1438 | memcpy((priv->tx_traffic + | |
1439 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1440 | header, len); | |
1441 | priv->tx_traffic_idx = | |
1442 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1443 | } | |
1444 | } | |
20594eb0 WYG |
1445 | |
1446 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | |
1447 | u16 length, struct ieee80211_hdr *header) | |
1448 | { | |
1449 | __le16 fc; | |
1450 | u16 len; | |
1451 | ||
1452 | if (likely(!(iwl_debug_level & IWL_DL_RX))) | |
1453 | return; | |
1454 | ||
1455 | if (!priv->rx_traffic) | |
1456 | return; | |
1457 | ||
1458 | fc = header->frame_control; | |
1459 | if (ieee80211_is_data(fc)) { | |
1460 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1461 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1462 | memcpy((priv->rx_traffic + | |
1463 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1464 | header, len); | |
1465 | priv->rx_traffic_idx = | |
1466 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1467 | } | |
1468 | } | |
22fdf3c9 WYG |
1469 | |
1470 | const char *get_mgmt_string(int cmd) | |
1471 | { | |
1472 | switch (cmd) { | |
1473 | IWL_CMD(MANAGEMENT_ASSOC_REQ); | |
1474 | IWL_CMD(MANAGEMENT_ASSOC_RESP); | |
1475 | IWL_CMD(MANAGEMENT_REASSOC_REQ); | |
1476 | IWL_CMD(MANAGEMENT_REASSOC_RESP); | |
1477 | IWL_CMD(MANAGEMENT_PROBE_REQ); | |
1478 | IWL_CMD(MANAGEMENT_PROBE_RESP); | |
1479 | IWL_CMD(MANAGEMENT_BEACON); | |
1480 | IWL_CMD(MANAGEMENT_ATIM); | |
1481 | IWL_CMD(MANAGEMENT_DISASSOC); | |
1482 | IWL_CMD(MANAGEMENT_AUTH); | |
1483 | IWL_CMD(MANAGEMENT_DEAUTH); | |
1484 | IWL_CMD(MANAGEMENT_ACTION); | |
1485 | default: | |
1486 | return "UNKNOWN"; | |
1487 | ||
1488 | } | |
1489 | } | |
1490 | ||
1491 | const char *get_ctrl_string(int cmd) | |
1492 | { | |
1493 | switch (cmd) { | |
1494 | IWL_CMD(CONTROL_BACK_REQ); | |
1495 | IWL_CMD(CONTROL_BACK); | |
1496 | IWL_CMD(CONTROL_PSPOLL); | |
1497 | IWL_CMD(CONTROL_RTS); | |
1498 | IWL_CMD(CONTROL_CTS); | |
1499 | IWL_CMD(CONTROL_ACK); | |
1500 | IWL_CMD(CONTROL_CFEND); | |
1501 | IWL_CMD(CONTROL_CFENDACK); | |
1502 | default: | |
1503 | return "UNKNOWN"; | |
1504 | ||
1505 | } | |
1506 | } | |
1507 | ||
7163b8a4 | 1508 | void iwl_clear_traffic_stats(struct iwl_priv *priv) |
22fdf3c9 WYG |
1509 | { |
1510 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); | |
22fdf3c9 WYG |
1511 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); |
1512 | } | |
1513 | ||
1514 | /* | |
1515 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will | |
1516 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. | |
1517 | * Use debugFs to display the rx/rx_statistics | |
1518 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL | |
1519 | * information will be recorded, but DATA pkt still will be recorded | |
1520 | * for the reason of iwl_led.c need to control the led blinking based on | |
1521 | * number of tx and rx data. | |
1522 | * | |
1523 | */ | |
1524 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) | |
1525 | { | |
1526 | struct traffic_stats *stats; | |
1527 | ||
1528 | if (is_tx) | |
1529 | stats = &priv->tx_stats; | |
1530 | else | |
1531 | stats = &priv->rx_stats; | |
1532 | ||
1533 | if (ieee80211_is_mgmt(fc)) { | |
1534 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1535 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
1536 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
1537 | break; | |
1538 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
1539 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
1540 | break; | |
1541 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
1542 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
1543 | break; | |
1544 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
1545 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
1546 | break; | |
1547 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
1548 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
1549 | break; | |
1550 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
1551 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
1552 | break; | |
1553 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
1554 | stats->mgmt[MANAGEMENT_BEACON]++; | |
1555 | break; | |
1556 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
1557 | stats->mgmt[MANAGEMENT_ATIM]++; | |
1558 | break; | |
1559 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
1560 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
1561 | break; | |
1562 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
1563 | stats->mgmt[MANAGEMENT_AUTH]++; | |
1564 | break; | |
1565 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
1566 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
1567 | break; | |
1568 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
1569 | stats->mgmt[MANAGEMENT_ACTION]++; | |
1570 | break; | |
1571 | } | |
1572 | } else if (ieee80211_is_ctl(fc)) { | |
1573 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1574 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
1575 | stats->ctrl[CONTROL_BACK_REQ]++; | |
1576 | break; | |
1577 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
1578 | stats->ctrl[CONTROL_BACK]++; | |
1579 | break; | |
1580 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
1581 | stats->ctrl[CONTROL_PSPOLL]++; | |
1582 | break; | |
1583 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
1584 | stats->ctrl[CONTROL_RTS]++; | |
1585 | break; | |
1586 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
1587 | stats->ctrl[CONTROL_CTS]++; | |
1588 | break; | |
1589 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
1590 | stats->ctrl[CONTROL_ACK]++; | |
1591 | break; | |
1592 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
1593 | stats->ctrl[CONTROL_CFEND]++; | |
1594 | break; | |
1595 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
1596 | stats->ctrl[CONTROL_CFENDACK]++; | |
1597 | break; | |
1598 | } | |
1599 | } else { | |
1600 | /* data */ | |
1601 | stats->data_cnt++; | |
1602 | stats->data_bytes += len; | |
1603 | } | |
1604 | } | |
20594eb0 WYG |
1605 | #endif |
1606 | ||
a93e7973 | 1607 | static void iwl_force_rf_reset(struct iwl_priv *priv) |
afbdd69a WYG |
1608 | { |
1609 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1610 | return; | |
1611 | ||
246ed355 | 1612 | if (!iwl_is_any_associated(priv)) { |
afbdd69a WYG |
1613 | IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n"); |
1614 | return; | |
1615 | } | |
1616 | /* | |
1617 | * There is no easy and better way to force reset the radio, | |
1618 | * the only known method is switching channel which will force to | |
1619 | * reset and tune the radio. | |
1620 | * Use internal short scan (single channel) operation to should | |
1621 | * achieve this objective. | |
1622 | * Driver should reset the radio when number of consecutive missed | |
1623 | * beacon, or any other uCode error condition detected. | |
1624 | */ | |
1625 | IWL_DEBUG_INFO(priv, "perform radio reset.\n"); | |
1626 | iwl_internal_short_hw_scan(priv); | |
afbdd69a | 1627 | } |
a93e7973 | 1628 | |
a93e7973 | 1629 | |
c04f9f22 | 1630 | int iwl_force_reset(struct iwl_priv *priv, int mode, bool external) |
a93e7973 | 1631 | { |
8a472da4 WYG |
1632 | struct iwl_force_reset *force_reset; |
1633 | ||
a93e7973 WYG |
1634 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1635 | return -EINVAL; | |
1636 | ||
8a472da4 WYG |
1637 | if (mode >= IWL_MAX_FORCE_RESET) { |
1638 | IWL_DEBUG_INFO(priv, "invalid reset request.\n"); | |
1639 | return -EINVAL; | |
1640 | } | |
1641 | force_reset = &priv->force_reset[mode]; | |
1642 | force_reset->reset_request_count++; | |
c04f9f22 WYG |
1643 | if (!external) { |
1644 | if (force_reset->last_force_reset_jiffies && | |
1645 | time_after(force_reset->last_force_reset_jiffies + | |
1646 | force_reset->reset_duration, jiffies)) { | |
1647 | IWL_DEBUG_INFO(priv, "force reset rejected\n"); | |
1648 | force_reset->reset_reject_count++; | |
1649 | return -EAGAIN; | |
1650 | } | |
a93e7973 | 1651 | } |
8a472da4 WYG |
1652 | force_reset->reset_success_count++; |
1653 | force_reset->last_force_reset_jiffies = jiffies; | |
a93e7973 | 1654 | IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode); |
a93e7973 WYG |
1655 | switch (mode) { |
1656 | case IWL_RF_RESET: | |
1657 | iwl_force_rf_reset(priv); | |
1658 | break; | |
1659 | case IWL_FW_RESET: | |
c04f9f22 WYG |
1660 | /* |
1661 | * if the request is from external(ex: debugfs), | |
1662 | * then always perform the request in regardless the module | |
1663 | * parameter setting | |
1664 | * if the request is from internal (uCode error or driver | |
1665 | * detect failure), then fw_restart module parameter | |
1666 | * need to be check before performing firmware reload | |
1667 | */ | |
9d143e9a | 1668 | if (!external && !iwlagn_mod_params.restart_fw) { |
c04f9f22 WYG |
1669 | IWL_DEBUG_INFO(priv, "Cancel firmware reload based on " |
1670 | "module parameter setting\n"); | |
1671 | break; | |
1672 | } | |
a93e7973 | 1673 | IWL_ERR(priv, "On demand firmware reload\n"); |
e649437f | 1674 | iwlagn_fw_error(priv, true); |
a93e7973 | 1675 | break; |
a93e7973 | 1676 | } |
a93e7973 WYG |
1677 | return 0; |
1678 | } | |
b74e31a9 | 1679 | |
d4daaea6 JB |
1680 | int iwl_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1681 | enum nl80211_iftype newtype, bool newp2p) | |
1682 | { | |
1683 | struct iwl_priv *priv = hw->priv; | |
1684 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); | |
ebf8dc80 | 1685 | struct iwl_rxon_context *bss_ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
d4daaea6 | 1686 | struct iwl_rxon_context *tmp; |
5306c080 | 1687 | enum nl80211_iftype newviftype = newtype; |
d4daaea6 JB |
1688 | u32 interface_modes; |
1689 | int err; | |
1690 | ||
1691 | newtype = ieee80211_iftype_p2p(newtype, newp2p); | |
1692 | ||
1693 | mutex_lock(&priv->mutex); | |
1694 | ||
a2b76b3b JB |
1695 | if (!ctx->vif || !iwl_is_ready_rf(priv)) { |
1696 | /* | |
1697 | * Huh? But wait ... this can maybe happen when | |
1698 | * we're in the middle of a firmware restart! | |
1699 | */ | |
1700 | err = -EBUSY; | |
1701 | goto out; | |
1702 | } | |
1703 | ||
d4daaea6 JB |
1704 | interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes; |
1705 | ||
1706 | if (!(interface_modes & BIT(newtype))) { | |
1707 | err = -EBUSY; | |
1708 | goto out; | |
1709 | } | |
1710 | ||
ebf8dc80 JB |
1711 | /* |
1712 | * Refuse a change that should be done by moving from the PAN | |
1713 | * context to the BSS context instead, if the BSS context is | |
1714 | * available and can support the new interface type. | |
1715 | */ | |
1716 | if (ctx->ctxid == IWL_RXON_CTX_PAN && !bss_ctx->vif && | |
1717 | (bss_ctx->interface_modes & BIT(newtype) || | |
1718 | bss_ctx->exclusive_interface_modes & BIT(newtype))) { | |
1719 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | |
1720 | err = -EBUSY; | |
1721 | goto out; | |
1722 | } | |
1723 | ||
d4daaea6 JB |
1724 | if (ctx->exclusive_interface_modes & BIT(newtype)) { |
1725 | for_each_context(priv, tmp) { | |
1726 | if (ctx == tmp) | |
1727 | continue; | |
1728 | ||
1729 | if (!tmp->vif) | |
1730 | continue; | |
1731 | ||
1732 | /* | |
1733 | * The current mode switch would be exclusive, but | |
1734 | * another context is active ... refuse the switch. | |
1735 | */ | |
1736 | err = -EBUSY; | |
1737 | goto out; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | /* success */ | |
1742 | iwl_teardown_interface(priv, vif, true); | |
5306c080 | 1743 | vif->type = newviftype; |
a2b76b3b | 1744 | vif->p2p = newp2p; |
d4daaea6 JB |
1745 | err = iwl_setup_interface(priv, ctx); |
1746 | WARN_ON(err); | |
1747 | /* | |
1748 | * We've switched internally, but submitting to the | |
1749 | * device may have failed for some reason. Mask this | |
1750 | * error, because otherwise mac80211 will not switch | |
1751 | * (and set the interface type back) and we'll be | |
1752 | * out of sync with it. | |
1753 | */ | |
1754 | err = 0; | |
1755 | ||
1756 | out: | |
1757 | mutex_unlock(&priv->mutex); | |
1758 | return err; | |
1759 | } | |
d4daaea6 | 1760 | |
b74e31a9 | 1761 | /* |
22de94de SG |
1762 | * On every watchdog tick we check (latest) time stamp. If it does not |
1763 | * change during timeout period and queue is not empty we reset firmware. | |
b74e31a9 | 1764 | */ |
b74e31a9 WYG |
1765 | static int iwl_check_stuck_queue(struct iwl_priv *priv, int cnt) |
1766 | { | |
22de94de SG |
1767 | struct iwl_tx_queue *txq = &priv->txq[cnt]; |
1768 | struct iwl_queue *q = &txq->q; | |
1769 | unsigned long timeout; | |
1770 | int ret; | |
b74e31a9 | 1771 | |
22de94de SG |
1772 | if (q->read_ptr == q->write_ptr) { |
1773 | txq->time_stamp = jiffies; | |
7cb1b088 | 1774 | return 0; |
22de94de | 1775 | } |
7cb1b088 | 1776 | |
22de94de SG |
1777 | timeout = txq->time_stamp + |
1778 | msecs_to_jiffies(priv->cfg->base_params->wd_timeout); | |
1779 | ||
1780 | if (time_after(jiffies, timeout)) { | |
1781 | IWL_ERR(priv, "Queue %d stuck for %u ms.\n", | |
1782 | q->id, priv->cfg->base_params->wd_timeout); | |
1783 | ret = iwl_force_reset(priv, IWL_FW_RESET, false); | |
1784 | return (ret == -EAGAIN) ? 0 : 1; | |
b74e31a9 | 1785 | } |
22de94de | 1786 | |
b74e31a9 WYG |
1787 | return 0; |
1788 | } | |
1789 | ||
22de94de SG |
1790 | /* |
1791 | * Making watchdog tick be a quarter of timeout assure we will | |
1792 | * discover the queue hung between timeout and 1.25*timeout | |
1793 | */ | |
1794 | #define IWL_WD_TICK(timeout) ((timeout) / 4) | |
1795 | ||
1796 | /* | |
1797 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
1798 | * we reset the firmware. If everything is fine just rearm the timer. | |
1799 | */ | |
1800 | void iwl_bg_watchdog(unsigned long data) | |
b74e31a9 WYG |
1801 | { |
1802 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
1803 | int cnt; | |
22de94de | 1804 | unsigned long timeout; |
b74e31a9 WYG |
1805 | |
1806 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1807 | return; | |
1808 | ||
22de94de SG |
1809 | timeout = priv->cfg->base_params->wd_timeout; |
1810 | if (timeout == 0) | |
1811 | return; | |
1812 | ||
b74e31a9 | 1813 | /* monitor and check for stuck cmd queue */ |
13bb9483 | 1814 | if (iwl_check_stuck_queue(priv, priv->cmd_queue)) |
b74e31a9 WYG |
1815 | return; |
1816 | ||
1817 | /* monitor and check for other stuck queues */ | |
246ed355 | 1818 | if (iwl_is_any_associated(priv)) { |
b74e31a9 WYG |
1819 | for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) { |
1820 | /* skip as we already checked the command queue */ | |
13bb9483 | 1821 | if (cnt == priv->cmd_queue) |
b74e31a9 WYG |
1822 | continue; |
1823 | if (iwl_check_stuck_queue(priv, cnt)) | |
1824 | return; | |
1825 | } | |
1826 | } | |
22de94de SG |
1827 | |
1828 | mod_timer(&priv->watchdog, jiffies + | |
1829 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
b74e31a9 | 1830 | } |
22de94de SG |
1831 | |
1832 | void iwl_setup_watchdog(struct iwl_priv *priv) | |
1833 | { | |
1834 | unsigned int timeout = priv->cfg->base_params->wd_timeout; | |
afbdd69a | 1835 | |
300d0834 | 1836 | if (timeout && !iwlagn_mod_params.wd_disable) |
22de94de SG |
1837 | mod_timer(&priv->watchdog, |
1838 | jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1839 | else | |
1840 | del_timer(&priv->watchdog); | |
1841 | } | |
a0ee74cf WYG |
1842 | |
1843 | /* | |
1844 | * extended beacon time format | |
1845 | * time in usec will be changed into a 32-bit value in extended:internal format | |
1846 | * the extended part is the beacon counts | |
1847 | * the internal part is the time in usec within one beacon interval | |
1848 | */ | |
1849 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval) | |
1850 | { | |
1851 | u32 quot; | |
1852 | u32 rem; | |
1853 | u32 interval = beacon_interval * TIME_UNIT; | |
1854 | ||
1855 | if (!interval || !usec) | |
1856 | return 0; | |
1857 | ||
1858 | quot = (usec / interval) & | |
1859 | (iwl_beacon_time_mask_high(priv, | |
1860 | priv->hw_params.beacon_time_tsf_bits) >> | |
1861 | priv->hw_params.beacon_time_tsf_bits); | |
1862 | rem = (usec % interval) & iwl_beacon_time_mask_low(priv, | |
1863 | priv->hw_params.beacon_time_tsf_bits); | |
1864 | ||
1865 | return (quot << priv->hw_params.beacon_time_tsf_bits) + rem; | |
1866 | } | |
a0ee74cf WYG |
1867 | |
1868 | /* base is usually what we get from ucode with each received frame, | |
1869 | * the same as HW timer counter counting down | |
1870 | */ | |
1871 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | |
1872 | u32 addon, u32 beacon_interval) | |
1873 | { | |
1874 | u32 base_low = base & iwl_beacon_time_mask_low(priv, | |
1875 | priv->hw_params.beacon_time_tsf_bits); | |
1876 | u32 addon_low = addon & iwl_beacon_time_mask_low(priv, | |
1877 | priv->hw_params.beacon_time_tsf_bits); | |
1878 | u32 interval = beacon_interval * TIME_UNIT; | |
1879 | u32 res = (base & iwl_beacon_time_mask_high(priv, | |
1880 | priv->hw_params.beacon_time_tsf_bits)) + | |
1881 | (addon & iwl_beacon_time_mask_high(priv, | |
1882 | priv->hw_params.beacon_time_tsf_bits)); | |
1883 | ||
1884 | if (base_low > addon_low) | |
1885 | res += base_low - addon_low; | |
1886 | else if (base_low < addon_low) { | |
1887 | res += interval + base_low - addon_low; | |
1888 | res += (1 << priv->hw_params.beacon_time_tsf_bits); | |
1889 | } else | |
1890 | res += (1 << priv->hw_params.beacon_time_tsf_bits); | |
1891 | ||
1892 | return cpu_to_le32(res); | |
1893 | } | |
a0ee74cf | 1894 | |
6da3a13e WYG |
1895 | #ifdef CONFIG_PM |
1896 | ||
48d1a211 | 1897 | int iwl_suspend(struct iwl_priv *priv) |
6da3a13e | 1898 | { |
6da3a13e WYG |
1899 | /* |
1900 | * This function is called when system goes into suspend state | |
1901 | * mac80211 will call iwl_mac_stop() from the mac80211 suspend function | |
1902 | * first but since iwl_mac_stop() has no knowledge of who the caller is, | |
1903 | * it will not call apm_ops.stop() to stop the DMA operation. | |
1904 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
1905 | */ | |
14e8e4af | 1906 | iwl_apm_stop(priv); |
6da3a13e | 1907 | |
6da3a13e WYG |
1908 | return 0; |
1909 | } | |
6da3a13e | 1910 | |
48d1a211 | 1911 | int iwl_resume(struct iwl_priv *priv) |
6da3a13e | 1912 | { |
0ab84cff | 1913 | bool hw_rfkill = false; |
6da3a13e | 1914 | |
6da3a13e WYG |
1915 | iwl_enable_interrupts(priv); |
1916 | ||
0ab84cff JB |
1917 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
1918 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1919 | hw_rfkill = true; | |
1920 | ||
1921 | if (hw_rfkill) | |
1922 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1923 | else | |
1924 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
1925 | ||
1926 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rfkill); | |
1927 | ||
6da3a13e WYG |
1928 | return 0; |
1929 | } | |
6da3a13e WYG |
1930 | |
1931 | #endif /* CONFIG_PM */ |