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zd1211rw: improve ejecting of fake CDROM
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
d43c36dc 32#include <linux/sched.h>
1d0a082d 33#include <net/mac80211.h>
df48c323 34
6bc913bd 35#include "iwl-eeprom.h"
3e0d4cb1 36#include "iwl-dev.h" /* FIXME: remove */
19335774 37#include "iwl-debug.h"
df48c323 38#include "iwl-core.h"
b661c819 39#include "iwl-io.h"
5da4b55f 40#include "iwl-power.h"
83dde8c9 41#include "iwl-sta.h"
ef850d7c 42#include "iwl-helpers.h"
df48c323 43
1d0a082d 44
df48c323
TW		 45MODULE_DESCRIPTION("iwl core");
46MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 47MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 48MODULE_LICENSE("GPL");
df48c323 49
1933ac4d
WYG		 50static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
51 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
52 0, COEX_UNASSOC_IDLE_FLAGS},
53 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
54 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
55 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
56 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
57 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
58 0, COEX_CALIBRATION_FLAGS},
59 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
60 0, COEX_PERIODIC_CALIBRATION_FLAGS},
61 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
62 0, COEX_CONNECTION_ESTAB_FLAGS},
63 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
64 0, COEX_ASSOCIATED_IDLE_FLAGS},
65 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
66 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
67 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
68 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
69 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
70 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
71 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
72 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
73 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
74 0, COEX_STAND_ALONE_DEBUG_FLAGS},
75 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
76 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
77 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
78 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
79};
80
c7de35cd
RR		 81#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
82 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
83 IWL_RATE_SISO_##s##M_PLCP, \
84 IWL_RATE_MIMO2_##s##M_PLCP,\
85 IWL_RATE_MIMO3_##s##M_PLCP,\
86 IWL_RATE_##r##M_IEEE, \
87 IWL_RATE_##ip##M_INDEX, \
88 IWL_RATE_##in##M_INDEX, \
89 IWL_RATE_##rp##M_INDEX, \
90 IWL_RATE_##rn##M_INDEX, \
91 IWL_RATE_##pp##M_INDEX, \
92 IWL_RATE_##np##M_INDEX }
93
a562a9dd
RC		 94u32 iwl_debug_level;
95EXPORT_SYMBOL(iwl_debug_level);
96
ef850d7c
MA		 97static irqreturn_t iwl_isr(int irq, void *data);
98
c7de35cd
RR		 99/*
100 * Parameter order:
101 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
102 *
103 * If there isn't a valid next or previous rate then INV is used which
104 * maps to IWL_RATE_INVALID
105 *
106 */
1826dcc0 107const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 108 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
109 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
110 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
111 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
112 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
113 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
114 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
115 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
116 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
117 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
118 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
119 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
120 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
121 /* FIXME:RS: ^^ should be INV (legacy) */
122};
1826dcc0 123EXPORT_SYMBOL(iwl_rates);
c7de35cd 124
e7d326ac
TW		 125/**
126 * translate ucode response to mac80211 tx status control values
127 */
128void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 129 struct ieee80211_tx_info *info)
e7d326ac 130{
e6a9854b 131 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 132
e6a9854b 133 info->antenna_sel_tx =
e7d326ac
TW		 134 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
135 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 136 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 137 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 138 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 139 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 140 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 141 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 142 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 143 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 144 r->flags |= IEEE80211_TX_RC_SHORT_GI;
31513be8 145 r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
e7d326ac
TW		 146}
147EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
148
149int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
150{
151 int idx = 0;
152
153 /* HT rate format */
154 if (rate_n_flags & RATE_MCS_HT_MSK) {
155 idx = (rate_n_flags & 0xff);
156
60d32215
DH		 157 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
158 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
159 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 160 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
161
162 idx += IWL_FIRST_OFDM_RATE;
163 /* skip 9M not supported in ht*/
164 if (idx >= IWL_RATE_9M_INDEX)
165 idx += 1;
166 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
167 return idx;
168
169 /* legacy rate format, search for match in table */
170 } else {
171 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
172 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
173 return idx;
174 }
175
176 return -1;
177}
178EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
179
31513be8
DH		 180int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
181{
182 int idx = 0;
183 int band_offset = 0;
184
185 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
186 if (rate_n_flags & RATE_MCS_HT_MSK) {
187 idx = (rate_n_flags & 0xff);
188 return idx;
189 /* Legacy rate format, search for match in table */
190 } else {
191 if (band == IEEE80211_BAND_5GHZ)
192 band_offset = IWL_FIRST_OFDM_RATE;
193 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
194 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
195 return idx - band_offset;
196 }
197
198 return -1;
199}
200
76eff18b
TW		 201u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
202{
203 int i;
204 u8 ind = ant;
205 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
206 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
207 if (priv->hw_params.valid_tx_ant & BIT(ind))
208 return ind;
209 }
210 return ant;
211}
47ff65c4 212EXPORT_SYMBOL(iwl_toggle_tx_ant);
57bd1bea
TW		 213
214const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
215EXPORT_SYMBOL(iwl_bcast_addr);
216
217
1d0a082d
AK		 218/* This function both allocates and initializes hw and priv. */
219struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
220 struct ieee80211_ops *hw_ops)
221{
222 struct iwl_priv *priv;
223
224 /* mac80211 allocates memory for this device instance, including
225 * space for this driver's private structure */
226 struct ieee80211_hw *hw =
227 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
228 if (hw == NULL) {
a3139c59
SO		 229 printk(KERN_ERR "%s: Can not allocate network device\n",
230 cfg->name);
1d0a082d
AK		 231 goto out;
232 }
233
234 priv = hw->priv;
235 priv->hw = hw;
236
237out:
238 return hw;
239}
240EXPORT_SYMBOL(iwl_alloc_all);
241
b661c819
TW		 242void iwl_hw_detect(struct iwl_priv *priv)
243{
244 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
245 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
246 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
247}
248EXPORT_SYMBOL(iwl_hw_detect);
249
1053d35f
RR		 250int iwl_hw_nic_init(struct iwl_priv *priv)
251{
252 unsigned long flags;
253 struct iwl_rx_queue *rxq = &priv->rxq;
254 int ret;
255
256 /* nic_init */
1053d35f 257 spin_lock_irqsave(&priv->lock, flags);
1b73af82 258 priv->cfg->ops->lib->apm_ops.init(priv);
74ba67ed
BC		 259
260 /* Set interrupt coalescing timer to 512 usecs */
261 iwl_write8(priv, CSR_INT_COALESCING, 512 / 32);
262
1053d35f
RR		 263 spin_unlock_irqrestore(&priv->lock, flags);
264
265 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
266
267 priv->cfg->ops->lib->apm_ops.config(priv);
268
269 /* Allocate the RX queue, or reset if it is already allocated */
270 if (!rxq->bd) {
271 ret = iwl_rx_queue_alloc(priv);
272 if (ret) {
15b1687c 273 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 274 return -ENOMEM;
275 }
276 } else
277 iwl_rx_queue_reset(priv, rxq);
278
279 iwl_rx_replenish(priv);
280
281 iwl_rx_init(priv, rxq);
282
283 spin_lock_irqsave(&priv->lock, flags);
284
285 rxq->need_update = 1;
286 iwl_rx_queue_update_write_ptr(priv, rxq);
287
288 spin_unlock_irqrestore(&priv->lock, flags);
289
290 /* Allocate and init all Tx and Command queues */
291 ret = iwl_txq_ctx_reset(priv);
292 if (ret)
293 return ret;
294
295 set_bit(STATUS_INIT, &priv->status);
296
297 return 0;
298}
299EXPORT_SYMBOL(iwl_hw_nic_init);
300
14d2aac5
AK		 301/*
302 * QoS support
303*/
304void iwl_activate_qos(struct iwl_priv *priv, u8 force)
305{
306 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
307 return;
308
309 priv->qos_data.def_qos_parm.qos_flags = 0;
310
311 if (priv->qos_data.qos_cap.q_AP.queue_request &&
312 !priv->qos_data.qos_cap.q_AP.txop_request)
313 priv->qos_data.def_qos_parm.qos_flags |=
314 QOS_PARAM_FLG_TXOP_TYPE_MSK;
315 if (priv->qos_data.qos_active)
316 priv->qos_data.def_qos_parm.qos_flags |=
317 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
318
319 if (priv->current_ht_config.is_ht)
320 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
321
322 if (force || iwl_is_associated(priv)) {
323 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
324 priv->qos_data.qos_active,
325 priv->qos_data.def_qos_parm.qos_flags);
326
327 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
328 sizeof(struct iwl_qosparam_cmd),
329 &priv->qos_data.def_qos_parm, NULL);
330 }
331}
332EXPORT_SYMBOL(iwl_activate_qos);
333
f2c95b04
WYG		 334/*
335 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
336 * (802.11b) (802.11a/g)
337 * AC_BK 15 1023 7 0 0
338 * AC_BE 15 1023 3 0 0
339 * AC_VI 7 15 2 6.016ms 3.008ms
340 * AC_VO 3 7 2 3.264ms 1.504ms
341 */
c7de35cd 342void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 343{
344 u16 cw_min = 15;
345 u16 cw_max = 1023;
346 u8 aifs = 2;
30dab79e 347 bool is_legacy = false;
bf85ea4f
AK		 348 unsigned long flags;
349 int i;
350
351 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 352 /* QoS always active in AP and ADHOC mode
353 * In STA mode wait for association
354 */
355 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
356 priv->iw_mode == NL80211_IFTYPE_AP)
357 priv->qos_data.qos_active = 1;
358 else
359 priv->qos_data.qos_active = 0;
bf85ea4f 360
30dab79e
WT		 361 /* check for legacy mode */
362 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
363 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
364 (priv->iw_mode == NL80211_IFTYPE_STATION &&
365 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 366 cw_min = 31;
367 is_legacy = 1;
368 }
369
370 if (priv->qos_data.qos_active)
371 aifs = 3;
372
f2c95b04 373 /* AC_BE */
bf85ea4f
AK		 374 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
375 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
376 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
377 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
378 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
379
380 if (priv->qos_data.qos_active) {
f2c95b04 381 /* AC_BK */
bf85ea4f
AK		 382 i = 1;
383 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
384 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
385 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
386 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
387 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
388
f2c95b04 389 /* AC_VI */
bf85ea4f
AK		 390 i = 2;
391 priv->qos_data.def_qos_parm.ac[i].cw_min =
392 cpu_to_le16((cw_min + 1) / 2 - 1);
393 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 394 cpu_to_le16(cw_min);
bf85ea4f
AK		 395 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
396 if (is_legacy)
397 priv->qos_data.def_qos_parm.ac[i].edca_txop =
398 cpu_to_le16(6016);
399 else
400 priv->qos_data.def_qos_parm.ac[i].edca_txop =
401 cpu_to_le16(3008);
402 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
403
f2c95b04 404 /* AC_VO */
bf85ea4f
AK		 405 i = 3;
406 priv->qos_data.def_qos_parm.ac[i].cw_min =
407 cpu_to_le16((cw_min + 1) / 4 - 1);
408 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 409 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 410 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
411 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
412 if (is_legacy)
413 priv->qos_data.def_qos_parm.ac[i].edca_txop =
414 cpu_to_le16(3264);
415 else
416 priv->qos_data.def_qos_parm.ac[i].edca_txop =
417 cpu_to_le16(1504);
418 } else {
419 for (i = 1; i < 4; i++) {
420 priv->qos_data.def_qos_parm.ac[i].cw_min =
421 cpu_to_le16(cw_min);
422 priv->qos_data.def_qos_parm.ac[i].cw_max =
423 cpu_to_le16(cw_max);
424 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
425 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
426 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
427 }
428 }
e1623446 429 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 430
431 spin_unlock_irqrestore(&priv->lock, flags);
432}
c7de35cd
RR		 433EXPORT_SYMBOL(iwl_reset_qos);
434
d9fe60de
JB		 435#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
436#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 437static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 438 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 439 enum ieee80211_band band)
440{
39130df3
RR		 441 u16 max_bit_rate = 0;
442 u8 rx_chains_num = priv->hw_params.rx_chains_num;
443 u8 tx_chains_num = priv->hw_params.tx_chains_num;
444
c7de35cd 445 ht_info->cap = 0;
d9fe60de 446 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 447
d9fe60de 448 ht_info->ht_supported = true;
c7de35cd 449
b261793d
DH		 450 if (priv->cfg->ht_greenfield_support)
451 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de 452 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
c15d20c1
WYG		 453 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
454 (priv->cfg->sm_ps_mode << 2));
39130df3 455 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 456 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 457 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
458 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
459 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 460 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 461 }
c7de35cd
RR		 462
463 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 464 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 465
466 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
467 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
468
d9fe60de 469 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 470 if (rx_chains_num >= 2)
d9fe60de 471 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 472 if (rx_chains_num >= 3)
d9fe60de 473 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 474
475 /* Highest supported Rx data rate */
476 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 477 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
478 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 479
480 /* Tx MCS capabilities */
d9fe60de 481 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 482 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 483 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
484 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
485 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 486 }
c7de35cd 487}
c7de35cd 488
c7de35cd
RR		 489/**
490 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
491 */
534166de 492int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 493{
494 struct iwl_channel_info *ch;
495 struct ieee80211_supported_band *sband;
496 struct ieee80211_channel *channels;
497 struct ieee80211_channel *geo_ch;
498 struct ieee80211_rate *rates;
499 int i = 0;
500
501 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
502 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 503 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 504 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
505 return 0;
506 }
507
508 channels = kzalloc(sizeof(struct ieee80211_channel) *
509 priv->channel_count, GFP_KERNEL);
510 if (!channels)
511 return -ENOMEM;
512
5027309b 513 rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
c7de35cd
RR		 514 GFP_KERNEL);
515 if (!rates) {
516 kfree(channels);
517 return -ENOMEM;
518 }
519
520 /* 5.2GHz channels start after the 2.4GHz channels */
521 sband = &priv->bands[IEEE80211_BAND_5GHZ];
522 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
523 /* just OFDM */
524 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 525 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 526
49779293 527 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 528 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 529 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 530
531 sband = &priv->bands[IEEE80211_BAND_2GHZ];
532 sband->channels = channels;
533 /* OFDM & CCK */
534 sband->bitrates = rates;
5027309b 535 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 536
49779293 537 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 538 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 539 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 540
541 priv->ieee_channels = channels;
542 priv->ieee_rates = rates;
543
c7de35cd
RR		 544 for (i = 0; i < priv->channel_count; i++) {
545 ch = &priv->channel_info[i];
546
547 /* FIXME: might be removed if scan is OK */
548 if (!is_channel_valid(ch))
549 continue;
550
551 if (is_channel_a_band(ch))
552 sband = &priv->bands[IEEE80211_BAND_5GHZ];
553 else
554 sband = &priv->bands[IEEE80211_BAND_2GHZ];
555
556 geo_ch = &sband->channels[sband->n_channels++];
557
558 geo_ch->center_freq =
559 ieee80211_channel_to_frequency(ch->channel);
560 geo_ch->max_power = ch->max_power_avg;
561 geo_ch->max_antenna_gain = 0xff;
562 geo_ch->hw_value = ch->channel;
563
564 if (is_channel_valid(ch)) {
565 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
566 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
567
568 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
569 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
570
571 if (ch->flags & EEPROM_CHANNEL_RADAR)
572 geo_ch->flags |= IEEE80211_CHAN_RADAR;
573
7aafef1c 574 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 575
dc1b0973
WYG		 576 if (ch->max_power_avg > priv->tx_power_device_lmt)
577 priv->tx_power_device_lmt = ch->max_power_avg;
c7de35cd
RR		 578 } else {
579 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
580 }
581
e1623446 582 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 583 ch->channel, geo_ch->center_freq,
584 is_channel_a_band(ch) ? "5.2" : "2.4",
585 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
586 "restricted" : "valid",
587 geo_ch->flags);
588 }
589
590 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
591 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 592 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
593 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 594 priv->pci_dev->device,
595 priv->pci_dev->subsystem_device);
c7de35cd
RR		 596 priv->cfg->sku &= ~IWL_SKU_A;
597 }
598
978785a3 599 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 600 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
601 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 602
603 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
604
605 return 0;
606}
534166de 607EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 608
609/*
610 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
611 */
534166de 612void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 613{
614 kfree(priv->ieee_channels);
615 kfree(priv->ieee_rates);
616 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
617}
534166de 618EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 619
37dc70fe
AK		 620/*
621 * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
622 * function.
623 */
624void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
625 __le32 *tx_flags)
626{
627 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
628 *tx_flags |= TX_CMD_FLG_RTS_MSK;
629 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
630 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
631 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
632 *tx_flags |= TX_CMD_FLG_CTS_MSK;
633 }
634}
635EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
636
28a6b07a 637static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 638{
639 return !priv->current_ht_config.is_ht ||
02bb1bea 640 priv->current_ht_config.single_chain_sufficient;
c7de35cd 641}
963f5517 642
47c5196e
TW		 643static u8 iwl_is_channel_extension(struct iwl_priv *priv,
644 enum ieee80211_band band,
645 u16 channel, u8 extension_chan_offset)
646{
647 const struct iwl_channel_info *ch_info;
648
649 ch_info = iwl_get_channel_info(priv, band, channel);
650 if (!is_channel_valid(ch_info))
651 return 0;
652
d9fe60de 653 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 654 return !(ch_info->ht40_extension_channel &
689da1b3 655 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 656 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 657 return !(ch_info->ht40_extension_channel &
689da1b3 658 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 659
660 return 0;
661}
662
7aafef1c 663u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 664 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e 665{
fad95bf5 666 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
47c5196e 667
fad95bf5 668 if (!ht_conf->is_ht || !ht_conf->is_40mhz)
47c5196e
TW		 669 return 0;
670
a2b0f02e
WYG		 671 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
672 * the bit will not set if it is pure 40MHz case
673 */
47c5196e 674 if (sta_ht_inf) {
a2b0f02e 675 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 676 return 0;
677 }
1e4247d4
WYG		 678#ifdef CONFIG_IWLWIFI_DEBUG
679 if (priv->disable_ht40)
680 return 0;
681#endif
611d3eb7
WYG		 682 return iwl_is_channel_extension(priv, priv->band,
683 le16_to_cpu(priv->staging_rxon.channel),
fad95bf5 684 ht_conf->extension_chan_offset);
47c5196e 685}
7aafef1c 686EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 687
2c2f3b33
TW		 688static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
689{
690 u16 new_val = 0;
691 u16 beacon_factor = 0;
692
693 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
694 new_val = beacon_val / beacon_factor;
695
696 if (!new_val)
697 new_val = max_beacon_val;
698
699 return new_val;
700}
701
702void iwl_setup_rxon_timing(struct iwl_priv *priv)
703{
704 u64 tsf;
705 s32 interval_tm, rem;
706 unsigned long flags;
707 struct ieee80211_conf *conf = NULL;
708 u16 beacon_int;
709
710 conf = ieee80211_get_hw_conf(priv->hw);
711
712 spin_lock_irqsave(&priv->lock, flags);
713 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
714 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
715
716 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
717 beacon_int = priv->beacon_int;
718 priv->rxon_timing.atim_window = 0;
719 } else {
720 beacon_int = priv->vif->bss_conf.beacon_int;
721
722 /* TODO: we need to get atim_window from upper stack
723 * for now we set to 0 */
724 priv->rxon_timing.atim_window = 0;
725 }
726
727 beacon_int = iwl_adjust_beacon_interval(beacon_int,
728 priv->hw_params.max_beacon_itrvl * 1024);
729 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
730
731 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
732 interval_tm = beacon_int * 1024;
733 rem = do_div(tsf, interval_tm);
734 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
735
736 spin_unlock_irqrestore(&priv->lock, flags);
737 IWL_DEBUG_ASSOC(priv,
738 "beacon interval %d beacon timer %d beacon tim %d\n",
739 le16_to_cpu(priv->rxon_timing.beacon_interval),
740 le32_to_cpu(priv->rxon_timing.beacon_init_val),
741 le16_to_cpu(priv->rxon_timing.atim_window));
742}
743EXPORT_SYMBOL(iwl_setup_rxon_timing);
744
8ccde88a
SO		 745void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
746{
747 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
748
749 if (hw_decrypt)
750 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
751 else
752 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
753
754}
755EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
756
757/**
758 * iwl_check_rxon_cmd - validate RXON structure is valid
759 *
760 * NOTE: This is really only useful during development and can eventually
761 * be #ifdef'd out once the driver is stable and folks aren't actively
762 * making changes
763 */
764int iwl_check_rxon_cmd(struct iwl_priv *priv)
765{
766 int error = 0;
767 int counter = 1;
768 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
769
770 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
771 error |= le32_to_cpu(rxon->flags &
772 (RXON_FLG_TGJ_NARROW_BAND_MSK |
773 RXON_FLG_RADAR_DETECT_MSK));
774 if (error)
775 IWL_WARN(priv, "check 24G fields %d | %d\n",
776 counter++, error);
777 } else {
778 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
779 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
780 if (error)
781 IWL_WARN(priv, "check 52 fields %d | %d\n",
782 counter++, error);
783 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
784 if (error)
785 IWL_WARN(priv, "check 52 CCK %d | %d\n",
786 counter++, error);
787 }
788 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
789 if (error)
790 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
791
792 /* make sure basic rates 6Mbps and 1Mbps are supported */
793 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
794 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
795 if (error)
796 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
797
798 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
799 if (error)
800 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
801
802 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
803 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
804 if (error)
805 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
806 counter++, error);
807
808 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
809 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
810 if (error)
811 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
812 counter++, error);
813
814 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
815 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
816 if (error)
817 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
818 counter++, error);
819
820 if (error)
821 IWL_WARN(priv, "Tuning to channel %d\n",
822 le16_to_cpu(rxon->channel));
823
824 if (error) {
825 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
826 return -1;
827 }
828 return 0;
829}
830EXPORT_SYMBOL(iwl_check_rxon_cmd);
831
832/**
833 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
834 * @priv: staging_rxon is compared to active_rxon
835 *
836 * If the RXON structure is changing enough to require a new tune,
837 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
838 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
839 */
840int iwl_full_rxon_required(struct iwl_priv *priv)
841{
842
843 /* These items are only settable from the full RXON command */
844 if (!(iwl_is_associated(priv)) ||
845 compare_ether_addr(priv->staging_rxon.bssid_addr,
846 priv->active_rxon.bssid_addr) ||
847 compare_ether_addr(priv->staging_rxon.node_addr,
848 priv->active_rxon.node_addr) ||
849 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
850 priv->active_rxon.wlap_bssid_addr) ||
851 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
852 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
853 (priv->staging_rxon.air_propagation !=
854 priv->active_rxon.air_propagation) ||
855 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
856 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
857 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
858 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 859 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
860 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 861 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
862 return 1;
863
864 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
865 * be updated with the RXON_ASSOC command -- however only some
866 * flag transitions are allowed using RXON_ASSOC */
867
868 /* Check if we are not switching bands */
869 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
870 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
871 return 1;
872
873 /* Check if we are switching association toggle */
874 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
875 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
876 return 1;
877
878 return 0;
879}
880EXPORT_SYMBOL(iwl_full_rxon_required);
881
882u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
883{
884 int i;
885 int rate_mask;
886
887 /* Set rate mask*/
888 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
889 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
890 else
891 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
892
893 /* Find lowest valid rate */
894 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
895 i = iwl_rates[i].next_ieee) {
896 if (rate_mask & (1 << i))
897 return iwl_rates[i].plcp;
898 }
899
900 /* No valid rate was found. Assign the lowest one */
901 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
902 return IWL_RATE_1M_PLCP;
903 else
904 return IWL_RATE_6M_PLCP;
905}
906EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
907
fad95bf5 908void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
47c5196e 909{
c1adf9fb 910 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 911
fad95bf5 912 if (!ht_conf->is_ht) {
a2b0f02e 913 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 914 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 915 RXON_FLG_HT40_PROT_MSK |
42eb7c64 916 RXON_FLG_HT_PROT_MSK);
47c5196e 917 return;
42eb7c64 918 }
47c5196e 919
a2b0f02e
WYG		 920 /* FIXME: if the definition of ht_protection changed, the "translation"
921 * will be needed for rxon->flags
922 */
fad95bf5 923 rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 924
925 /* Set up channel bandwidth:
7aafef1c 926 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 927 /* clear the HT channel mode before set the mode */
928 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
929 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 930 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
931 /* pure ht40 */
fad95bf5 932 if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 933 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 934 /* Note: control channel is opposite of extension channel */
fad95bf5 935 switch (ht_conf->extension_chan_offset) {
508b08e7
WYG		 936 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
937 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
938 break;
939 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
940 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
941 break;
942 }
943 } else {
a2b0f02e 944 /* Note: control channel is opposite of extension channel */
fad95bf5 945 switch (ht_conf->extension_chan_offset) {
a2b0f02e
WYG		 946 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
947 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
948 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
949 break;
950 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
951 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
952 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
953 break;
954 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
955 default:
956 /* channel location only valid if in Mixed mode */
957 IWL_ERR(priv, "invalid extension channel offset\n");
958 break;
959 }
960 }
961 } else {
962 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 963 }
964
45823531
AK		 965 if (priv->cfg->ops->hcmd->set_rxon_chain)
966 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 967
02bb1bea 968 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 969 "extension channel offset 0x%x\n",
fad95bf5
JB		 970 le32_to_cpu(rxon->flags), ht_conf->ht_protection,
971 ht_conf->extension_chan_offset);
47c5196e
TW		 972 return;
973}
974EXPORT_SYMBOL(iwl_set_rxon_ht);
975
9e5e6c32
TW		 976#define IWL_NUM_RX_CHAINS_MULTIPLE 3
977#define IWL_NUM_RX_CHAINS_SINGLE 2
978#define IWL_NUM_IDLE_CHAINS_DUAL 2
979#define IWL_NUM_IDLE_CHAINS_SINGLE 1
980
2b396a12
JB		 981/*
982 * Determine how many receiver/antenna chains to use.
983 *
984 * More provides better reception via diversity. Fewer saves power
985 * at the expense of throughput, but only when not in powersave to
986 * start with.
987 *
c7de35cd
RR		 988 * MIMO (dual stream) requires at least 2, but works better with 3.
989 * This does not determine *which* chains to use, just how many.
990 */
28a6b07a 991static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 992{
c7de35cd 993 /* # of Rx chains to use when expecting MIMO. */
02bb1bea 994 if (is_single_rx_stream(priv))
9e5e6c32 995 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 996 else
9e5e6c32 997 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 998}
c7de35cd 999
2b396a12 1000/*
3f3e0376
WYG		 1001 * When we are in power saving mode, unless device support spatial
1002 * multiplexing power save, use the active count for rx chain count.
2b396a12 1003 */
28a6b07a
TW		 1004static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1005{
3f3e0376
WYG		 1006 int idle_cnt = active_cnt;
1007 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
1008
c15d20c1
WYG		 1009 /* # Rx chains when idling and maybe trying to save power */
1010 switch (priv->cfg->sm_ps_mode) {
1011 case WLAN_HT_CAP_SM_PS_STATIC:
1012 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
1013 break;
1014 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1015 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
1016 IWL_NUM_IDLE_CHAINS_SINGLE;
1017 break;
1018 case WLAN_HT_CAP_SM_PS_DISABLED:
1019 break;
1020 case WLAN_HT_CAP_SM_PS_INVALID:
1021 default:
1022 IWL_ERR(priv, "invalid sm_ps mode %u\n",
1023 priv->cfg->sm_ps_mode);
1024 WARN_ON(1);
1025 break;
3f3e0376
WYG		 1026 }
1027 return idle_cnt;
c7de35cd
RR		 1028}
1029
04816448
GE		 1030/* up to 4 chains */
1031static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1032{
1033 u8 res;
1034 res = (chain_bitmap & BIT(0)) >> 0;
1035 res += (chain_bitmap & BIT(1)) >> 1;
1036 res += (chain_bitmap & BIT(2)) >> 2;
9bddbab3 1037 res += (chain_bitmap & BIT(3)) >> 3;
04816448
GE		 1038 return res;
1039}
1040
4c4df78f
CR		 1041/**
1042 * iwl_is_monitor_mode - Determine if interface in monitor mode
1043 *
1044 * priv->iw_mode is set in add_interface, but add_interface is
1045 * never called for monitor mode. The only way mac80211 informs us about
1046 * monitor mode is through configuring filters (call to configure_filter).
1047 */
279b05d4 1048bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1049{
1050 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1051}
279b05d4 1052EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1053
c7de35cd
RR		 1054/**
1055 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1056 *
1057 * Selects how many and which Rx receivers/antennas/chains to use.
1058 * This should not be used for scan command ... it puts data in wrong place.
1059 */
1060void iwl_set_rxon_chain(struct iwl_priv *priv)
1061{
28a6b07a
TW		 1062 bool is_single = is_single_rx_stream(priv);
1063 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1064 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1065 u32 active_chains;
28a6b07a 1066 u16 rx_chain;
c7de35cd
RR		 1067
1068 /* Tell uCode which antennas are actually connected.
1069 * Before first association, we assume all antennas are connected.
1070 * Just after first association, iwl_chain_noise_calibration()
1071 * checks which antennas actually *are* connected. */
04816448
GE		 1072 if (priv->chain_noise_data.active_chains)
1073 active_chains = priv->chain_noise_data.active_chains;
1074 else
1075 active_chains = priv->hw_params.valid_rx_ant;
1076
1077 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1078
1079 /* How many receivers should we use? */
28a6b07a
TW		 1080 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1081 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1082
28a6b07a 1083
04816448
GE		 1084 /* correct rx chain count according hw settings
1085 * and chain noise calibration
1086 */
1087 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1088 if (valid_rx_cnt < active_rx_cnt)
1089 active_rx_cnt = valid_rx_cnt;
1090
1091 if (valid_rx_cnt < idle_rx_cnt)
1092 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1093
1094 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1095 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1096
7b841727
RF		 1097 /* copied from 'iwl_bg_request_scan()' */
1098 /* Force use of chains B and C (0x6) for Rx for 4965
1099 * Avoid A (0x1) because of its off-channel reception on A-band.
1100 * MIMO is not used here, but value is required */
1101 if (iwl_is_monitor_mode(priv) &&
1102 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1103 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1104 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1105 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1106 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1107 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1108 }
1109
28a6b07a
TW		 1110 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1111
9e5e6c32 1112 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1113 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1114 else
1115 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1116
e1623446 1117 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1118 priv->staging_rxon.rx_chain,
1119 active_rx_cnt, idle_rx_cnt);
1120
1121 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1122 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1123}
1124EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1125
1126/**
17e72782 1127 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1128 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1129 * @channel: Any channel valid for the requested phymode
1130
1131 * In addition to setting the staging RXON, priv->phymode is also set.
1132 *
1133 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1134 * in the staging RXON flag structure based on the phymode
1135 */
17e72782 1136int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1137{
17e72782
TW		 1138 enum ieee80211_band band = ch->band;
1139 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1140
8622e705 1141 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1142 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1143 channel, band);
1144 return -EINVAL;
1145 }
1146
1147 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1148 (priv->band == band))
1149 return 0;
1150
1151 priv->staging_rxon.channel = cpu_to_le16(channel);
1152 if (band == IEEE80211_BAND_5GHZ)
1153 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1154 else
1155 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1156
1157 priv->band = band;
1158
e1623446 1159 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1160
1161 return 0;
1162}
c7de35cd 1163EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1164
8ccde88a
SO		 1165void iwl_set_flags_for_band(struct iwl_priv *priv,
1166 enum ieee80211_band band)
1167{
1168 if (band == IEEE80211_BAND_5GHZ) {
1169 priv->staging_rxon.flags &=
1170 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1171 | RXON_FLG_CCK_MSK);
1172 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1173 } else {
1174 /* Copied from iwl_post_associate() */
1175 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1176 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1177 else
1178 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1179
1180 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1181 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1182
1183 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1184 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1185 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1186 }
1187}
8ccde88a
SO		 1188
1189/*
1190 * initialize rxon structure with default values from eeprom
1191 */
1192void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1193{
1194 const struct iwl_channel_info *ch_info;
1195
1196 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1197
1198 switch (mode) {
1199 case NL80211_IFTYPE_AP:
1200 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1201 break;
1202
1203 case NL80211_IFTYPE_STATION:
1204 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1205 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1206 break;
1207
1208 case NL80211_IFTYPE_ADHOC:
1209 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1210 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1211 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1212 RXON_FILTER_ACCEPT_GRP_MSK;
1213 break;
1214
8ccde88a
SO		 1215 default:
1216 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1217 break;
1218 }
1219
1220#if 0
1221 /* TODO: Figure out when short_preamble would be set and cache from
1222 * that */
1223 if (!hw_to_local(priv->hw)->short_preamble)
1224 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1225 else
1226 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1227#endif
1228
1229 ch_info = iwl_get_channel_info(priv, priv->band,
1230 le16_to_cpu(priv->active_rxon.channel));
1231
1232 if (!ch_info)
1233 ch_info = &priv->channel_info[0];
1234
1235 /*
1236 * in some case A channels are all non IBSS
1237 * in this case force B/G channel
1238 */
1239 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1240 !(is_channel_ibss(ch_info)))
1241 ch_info = &priv->channel_info[0];
1242
1243 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1244 priv->band = ch_info->band;
1245
1246 iwl_set_flags_for_band(priv, priv->band);
1247
1248 priv->staging_rxon.ofdm_basic_rates =
1249 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1250 priv->staging_rxon.cck_basic_rates =
1251 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1252
a2b0f02e
WYG		 1253 /* clear both MIX and PURE40 mode flag */
1254 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1255 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1256 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1257 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1258 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1259 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1260 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1261}
1262EXPORT_SYMBOL(iwl_connection_init_rx_config);
1263
782571f4 1264static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1265{
1266 const struct ieee80211_supported_band *hw = NULL;
1267 struct ieee80211_rate *rate;
1268 int i;
1269
1270 hw = iwl_get_hw_mode(priv, priv->band);
1271 if (!hw) {
1272 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1273 return;
1274 }
1275
1276 priv->active_rate = 0;
1277 priv->active_rate_basic = 0;
1278
1279 for (i = 0; i < hw->n_bitrates; i++) {
1280 rate = &(hw->bitrates[i]);
5027309b 1281 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 1282 priv->active_rate |= (1 << rate->hw_value);
1283 }
1284
e1623446 1285 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1286 priv->active_rate, priv->active_rate_basic);
1287
1288 /*
1289 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1290 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1291 * OFDM
1292 */
1293 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1294 priv->staging_rxon.cck_basic_rates =
1295 ((priv->active_rate_basic &
1296 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1297 else
1298 priv->staging_rxon.cck_basic_rates =
1299 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1300
1301 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1302 priv->staging_rxon.ofdm_basic_rates =
1303 ((priv->active_rate_basic &
1304 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1305 IWL_FIRST_OFDM_RATE) & 0xFF;
1306 else
1307 priv->staging_rxon.ofdm_basic_rates =
1308 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1309}
8ccde88a
SO		 1310
1311void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1312{
2f301227 1313 struct iwl_rx_packet *pkt = rxb_addr(rxb);
8ccde88a
SO		 1314 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1315 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
4a56e965 1316
0924e519
WYG		 1317 if (priv->switch_rxon.switch_in_progress) {
1318 if (!le32_to_cpu(csa->status) &&
1319 (csa->channel == priv->switch_rxon.channel)) {
1320 rxon->channel = csa->channel;
1321 priv->staging_rxon.channel = csa->channel;
1322 IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
1323 le16_to_cpu(csa->channel));
1324 } else
1325 IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
1326 le16_to_cpu(csa->channel));
1327
1328 priv->switch_rxon.switch_in_progress = false;
1329 }
8ccde88a
SO		 1330}
1331EXPORT_SYMBOL(iwl_rx_csa);
1332
1333#ifdef CONFIG_IWLWIFI_DEBUG
a643565e 1334void iwl_print_rx_config_cmd(struct iwl_priv *priv)
8ccde88a
SO		 1335{
1336 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1337
e1623446 1338 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1339 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1340 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1341 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1342 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1343 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1344 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1345 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1346 rxon->ofdm_basic_rates);
e1623446
TW		 1347 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1348 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1349 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1350 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1351}
a643565e 1352EXPORT_SYMBOL(iwl_print_rx_config_cmd);
6686d17e 1353#endif
8ccde88a
SO		 1354/**
1355 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1356 */
1357void iwl_irq_handle_error(struct iwl_priv *priv)
1358{
1359 /* Set the FW error flag -- cleared on iwl_down */
1360 set_bit(STATUS_FW_ERROR, &priv->status);
1361
1362 /* Cancel currently queued command. */
1363 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1364
3a3ff72c 1365 priv->cfg->ops->lib->dump_nic_error_log(priv);
696bdee3
WYG		 1366 if (priv->cfg->ops->lib->dump_csr)
1367 priv->cfg->ops->lib->dump_csr(priv);
b03d7d0f 1368 priv->cfg->ops->lib->dump_nic_event_log(priv, false, NULL, false);
8ccde88a 1369#ifdef CONFIG_IWLWIFI_DEBUG
c341ddb2 1370 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS)
8ccde88a 1371 iwl_print_rx_config_cmd(priv);
8ccde88a
SO		 1372#endif
1373
1374 wake_up_interruptible(&priv->wait_command_queue);
1375
1376 /* Keep the restart process from trying to send host
1377 * commands by clearing the INIT status bit */
1378 clear_bit(STATUS_READY, &priv->status);
1379
1380 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1381 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1382 "Restarting adapter due to uCode error.\n");
1383
8ccde88a
SO		 1384 if (priv->cfg->mod_params->restart_fw)
1385 queue_work(priv->workqueue, &priv->restart);
1386 }
1387}
1388EXPORT_SYMBOL(iwl_irq_handle_error);
1389
d68b603c
AK		 1390int iwl_apm_stop_master(struct iwl_priv *priv)
1391{
5220af0c 1392 int ret = 0;
d68b603c 1393
5220af0c 1394 /* stop device's busmaster DMA activity */
d68b603c
AK		 1395 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1396
5220af0c 1397 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c 1398 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
5220af0c
BC		 1399 if (ret)
1400 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
d68b603c 1401
d68b603c
AK		 1402 IWL_DEBUG_INFO(priv, "stop master\n");
1403
5220af0c 1404 return ret;
d68b603c
AK		 1405}
1406EXPORT_SYMBOL(iwl_apm_stop_master);
1407
1408void iwl_apm_stop(struct iwl_priv *priv)
1409{
fadb3582
BC		 1410 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1411
5220af0c 1412 /* Stop device's DMA activity */
d68b603c
AK		 1413 iwl_apm_stop_master(priv);
1414
5220af0c 1415 /* Reset the entire device */
d68b603c
AK		 1416 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1417
1418 udelay(10);
5220af0c
BC		 1419
1420 /*
1421 * Clear "initialization complete" bit to move adapter from
1422 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
1423 */
d68b603c 1424 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
d68b603c
AK		 1425}
1426EXPORT_SYMBOL(iwl_apm_stop);
1427
fadb3582
BC		 1428
1429/*
1430 * Start up NIC's basic functionality after it has been reset
1431 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1432 * NOTE: This does not load uCode nor start the embedded processor
1433 */
1434int iwl_apm_init(struct iwl_priv *priv)
1435{
1436 int ret = 0;
1437 u16 lctl;
1438
1439 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1440
1441 /*
1442 * Use "set_bit" below rather than "write", to preserve any hardware
1443 * bits already set by default after reset.
1444 */
1445
1446 /* Disable L0S exit timer (platform NMI Work/Around) */
1447 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1448 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1449
1450 /*
1451 * Disable L0s without affecting L1;
1452 * don't wait for ICH L0s (ICH bug W/A)
1453 */
1454 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1455 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1456
1457 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1458 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1459
1460 /*
1461 * Enable HAP INTA (interrupt from management bus) to
1462 * wake device's PCI Express link L1a -> L0s
1463 * NOTE: This is no-op for 3945 (non-existant bit)
1464 */
1465 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1466 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1467
1468 /*
a6c5c731
BC		 1469 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1470 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1471 * If so (likely), disable L0S, so device moves directly L0->L1;
1472 * costs negligible amount of power savings.
1473 * If not (unlikely), enable L0S, so there is at least some
1474 * power savings, even without L1.
fadb3582
BC		 1475 */
1476 if (priv->cfg->set_l0s) {
1477 lctl = iwl_pcie_link_ctl(priv);
1478 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1479 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1480 /* L1-ASPM enabled; disable(!) L0S */
1481 iwl_set_bit(priv, CSR_GIO_REG,
1482 CSR_GIO_REG_VAL_L0S_ENABLED);
1483 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1484 } else {
1485 /* L1-ASPM disabled; enable(!) L0S */
1486 iwl_clear_bit(priv, CSR_GIO_REG,
1487 CSR_GIO_REG_VAL_L0S_ENABLED);
1488 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1489 }
1490 }
1491
1492 /* Configure analog phase-lock-loop before activating to D0A */
1493 if (priv->cfg->pll_cfg_val)
1494 iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
1495
1496 /*
1497 * Set "initialization complete" bit to move adapter from
1498 * D0U* --> D0A* (powered-up active) state.
1499 */
1500 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1501
1502 /*
1503 * Wait for clock stabilization; once stabilized, access to
1504 * device-internal resources is supported, e.g. iwl_write_prph()
1505 * and accesses to uCode SRAM.
1506 */
1507 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1508 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1509 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1510 if (ret < 0) {
1511 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1512 goto out;
1513 }
1514
1515 /*
1516 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
1517 * BSM (Boostrap State Machine) is only in 3945 and 4965;
1518 * later devices (i.e. 5000 and later) have non-volatile SRAM,
1519 * and don't need BSM to restore data after power-saving sleep.
1520 *
1521 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1522 * do not disable clocks. This preserves any hardware bits already
1523 * set by default in "CLK_CTRL_REG" after reset.
1524 */
1525 if (priv->cfg->use_bsm)
1526 iwl_write_prph(priv, APMG_CLK_EN_REG,
1527 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
1528 else
1529 iwl_write_prph(priv, APMG_CLK_EN_REG,
1530 APMG_CLK_VAL_DMA_CLK_RQT);
1531 udelay(20);
1532
1533 /* Disable L1-Active */
1534 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1535 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1536
1537out:
1538 return ret;
1539}
1540EXPORT_SYMBOL(iwl_apm_init);
1541
1542
1543
8ccde88a
SO		 1544void iwl_configure_filter(struct ieee80211_hw *hw,
1545 unsigned int changed_flags,
1546 unsigned int *total_flags,
3ac64bee 1547 u64 multicast)
8ccde88a
SO		 1548{
1549 struct iwl_priv *priv = hw->priv;
1550 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1551
e1623446 1552 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1553 changed_flags, *total_flags);
1554
1555 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1556 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1557 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1558 else
1559 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1560 }
1561 if (changed_flags & FIF_ALLMULTI) {
1562 if (*total_flags & FIF_ALLMULTI)
1563 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1564 else
1565 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1566 }
1567 if (changed_flags & FIF_CONTROL) {
1568 if (*total_flags & FIF_CONTROL)
1569 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1570 else
1571 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1572 }
1573 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1574 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1575 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1576 else
1577 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1578 }
1579
1580 /* We avoid iwl_commit_rxon here to commit the new filter flags
1581 * since mac80211 will call ieee80211_hw_config immediately.
1582 * (mc_list is not supported at this time). Otherwise, we need to
1583 * queue a background iwl_commit_rxon work.
1584 */
1585
1586 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1587 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1588}
1589EXPORT_SYMBOL(iwl_configure_filter);
1590
da154e30
RR		 1591int iwl_set_hw_params(struct iwl_priv *priv)
1592{
da154e30
RR		 1593 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1594 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1595 if (priv->cfg->mod_params->amsdu_size_8K)
2f301227 1596 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
da154e30 1597 else
2f301227 1598 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
da154e30 1599
2c2f3b33
TW		 1600 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1601
49779293
RR		 1602 if (priv->cfg->mod_params->disable_11n)
1603 priv->cfg->sku &= ~IWL_SKU_N;
1604
da154e30
RR		 1605 /* Device-specific setup */
1606 return priv->cfg->ops->lib->set_hw_params(priv);
1607}
1608EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956 1609
630fe9b6
TW		 1610int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1611{
1612 int ret = 0;
5eadd94b
WYG		 1613 s8 prev_tx_power = priv->tx_power_user_lmt;
1614
630fe9b6 1615 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1616 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1617 tx_power,
1618 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1619 return -EINVAL;
1620 }
1621
dc1b0973 1622 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1623 IWL_WARN(priv,
1624 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1625 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1626 return -EINVAL;
1627 }
1628
1629 if (priv->tx_power_user_lmt != tx_power)
1630 force = true;
1631
019fb97d 1632 /* if nic is not up don't send command */
5eadd94b
WYG		 1633 if (iwl_is_ready_rf(priv)) {
1634 priv->tx_power_user_lmt = tx_power;
1635 if (force && priv->cfg->ops->lib->send_tx_power)
1636 ret = priv->cfg->ops->lib->send_tx_power(priv);
1637 else if (!priv->cfg->ops->lib->send_tx_power)
1638 ret = -EOPNOTSUPP;
1639 /*
1640 * if fail to set tx_power, restore the orig. tx power
1641 */
1642 if (ret)
1643 priv->tx_power_user_lmt = prev_tx_power;
1644 }
630fe9b6 1645
5eadd94b
WYG		 1646 /*
1647 * Even this is an async host command, the command
1648 * will always report success from uCode
1649 * So once driver can placing the command into the queue
1650 * successfully, driver can use priv->tx_power_user_lmt
1651 * to reflect the current tx power
1652 */
630fe9b6
TW		 1653 return ret;
1654}
1655EXPORT_SYMBOL(iwl_set_tx_power);
1656
ef850d7c
MA		 1657#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1658
1659/* Free dram table */
1660void iwl_free_isr_ict(struct iwl_priv *priv)
1661{
1662 if (priv->ict_tbl_vir) {
1663 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1664 PAGE_SIZE, priv->ict_tbl_vir,
1665 priv->ict_tbl_dma);
1666 priv->ict_tbl_vir = NULL;
1667 }
1668}
1669EXPORT_SYMBOL(iwl_free_isr_ict);
1670
1671
1672/* allocate dram shared table it is a PAGE_SIZE aligned
1673 * also reset all data related to ICT table interrupt.
1674 */
1675int iwl_alloc_isr_ict(struct iwl_priv *priv)
1676{
1677
1678 if (priv->cfg->use_isr_legacy)
1679 return 0;
1680 /* allocate shrared data table */
1681 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1682 ICT_COUNT) + PAGE_SIZE,
1683 &priv->ict_tbl_dma);
1684 if (!priv->ict_tbl_vir)
1685 return -ENOMEM;
1686
1687 /* align table to PAGE_SIZE boundry */
1688 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1689
1690 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1691 (unsigned long long)priv->ict_tbl_dma,
1692 (unsigned long long)priv->aligned_ict_tbl_dma,
1693 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1694
1695 priv->ict_tbl = priv->ict_tbl_vir +
1696 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1697
1698 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1699 priv->ict_tbl, priv->ict_tbl_vir,
1700 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1701
1702 /* reset table and index to all 0 */
1703 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1704 priv->ict_index = 0;
1705
40cefda9
MA		 1706 /* add periodic RX interrupt */
1707 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1708 return 0;
1709}
1710EXPORT_SYMBOL(iwl_alloc_isr_ict);
1711
1712/* Device is going up inform it about using ICT interrupt table,
1713 * also we need to tell the driver to start using ICT interrupt.
1714 */
1715int iwl_reset_ict(struct iwl_priv *priv)
1716{
1717 u32 val;
1718 unsigned long flags;
1719
1720 if (!priv->ict_tbl_vir)
1721 return 0;
1722
1723 spin_lock_irqsave(&priv->lock, flags);
1724 iwl_disable_interrupts(priv);
1725
1303dcfd 1726 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
ef850d7c
MA		 1727
1728 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1729
1730 val |= CSR_DRAM_INT_TBL_ENABLE;
1731 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1732
1733 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1734 "aligned dma address %Lx\n",
1735 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1736
1737 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1738 priv->use_ict = true;
1739 priv->ict_index = 0;
40cefda9 1740 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1741 iwl_enable_interrupts(priv);
1742 spin_unlock_irqrestore(&priv->lock, flags);
1743
1744 return 0;
1745}
1746EXPORT_SYMBOL(iwl_reset_ict);
1747
1748/* Device is going down disable ict interrupt usage */
1749void iwl_disable_ict(struct iwl_priv *priv)
1750{
1751 unsigned long flags;
1752
1753 spin_lock_irqsave(&priv->lock, flags);
1754 priv->use_ict = false;
1755 spin_unlock_irqrestore(&priv->lock, flags);
1756}
1757EXPORT_SYMBOL(iwl_disable_ict);
1758
1759/* interrupt handler using ict table, with this interrupt driver will
1760 * stop using INTA register to get device's interrupt, reading this register
1761 * is expensive, device will write interrupts in ICT dram table, increment
1762 * index then will fire interrupt to driver, driver will OR all ICT table
1763 * entries from current index up to table entry with 0 value. the result is
1764 * the interrupt we need to service, driver will set the entries back to 0 and
1765 * set index.
1766 */
1767irqreturn_t iwl_isr_ict(int irq, void *data)
1768{
1769 struct iwl_priv *priv = data;
1770 u32 inta, inta_mask;
1771 u32 val = 0;
1772
1773 if (!priv)
1774 return IRQ_NONE;
1775
1776 /* dram interrupt table not set yet,
1777 * use legacy interrupt.
1778 */
1779 if (!priv->use_ict)
1780 return iwl_isr(irq, data);
1781
1782 spin_lock(&priv->lock);
1783
1784 /* Disable (but don't clear!) interrupts here to avoid
1785 * back-to-back ISRs and sporadic interrupts from our NIC.
1786 * If we have something to service, the tasklet will re-enable ints.
1787 * If we *don't* have something, we'll re-enable before leaving here.
1788 */
1789 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1790 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1791
1792
1793 /* Ignore interrupt if there's nothing in NIC to service.
1794 * This may be due to IRQ shared with another device,
1795 * or due to sporadic interrupts thrown from our NIC. */
1796 if (!priv->ict_tbl[priv->ict_index]) {
1797 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1798 goto none;
1799 }
1800
1801 /* read all entries that not 0 start with ict_index */
1802 while (priv->ict_tbl[priv->ict_index]) {
1803
1303dcfd 1804 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
ef850d7c 1805 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1303dcfd
JB		 1806 priv->ict_index,
1807 le32_to_cpu(priv->ict_tbl[priv->ict_index]));
ef850d7c
MA		 1808 priv->ict_tbl[priv->ict_index] = 0;
1809 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1303dcfd 1810 ICT_COUNT);
ef850d7c
MA		 1811
1812 }
1813
1814 /* We should not get this value, just ignore it. */
1815 if (val == 0xffffffff)
1816 val = 0;
1817
1818 inta = (0xff & val) | ((0xff00 & val) << 16);
1819 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1820 inta, inta_mask, val);
1821
40cefda9 1822 inta &= priv->inta_mask;
ef850d7c
MA		 1823 priv->inta |= inta;
1824
1825 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1826 if (likely(inta))
1827 tasklet_schedule(&priv->irq_tasklet);
1828 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1829 /* Allow interrupt if was disabled by this handler and
1830 * no tasklet was schedules, We should not enable interrupt,
1831 * tasklet will enable it.
1832 */
1833 iwl_enable_interrupts(priv);
1834 }
1835
1836 spin_unlock(&priv->lock);
1837 return IRQ_HANDLED;
1838
1839 none:
1840 /* re-enable interrupts here since we don't have anything to service.
1841 * only Re-enable if disabled by irq.
1842 */
1843 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1844 iwl_enable_interrupts(priv);
1845
1846 spin_unlock(&priv->lock);
1847 return IRQ_NONE;
1848}
1849EXPORT_SYMBOL(iwl_isr_ict);
1850
1851
1852static irqreturn_t iwl_isr(int irq, void *data)
1853{
1854 struct iwl_priv *priv = data;
1855 u32 inta, inta_mask;
d651ae32 1856#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1857 u32 inta_fh;
d651ae32 1858#endif
ef850d7c
MA		 1859 if (!priv)
1860 return IRQ_NONE;
1861
1862 spin_lock(&priv->lock);
1863
1864 /* Disable (but don't clear!) interrupts here to avoid
1865 * back-to-back ISRs and sporadic interrupts from our NIC.
1866 * If we have something to service, the tasklet will re-enable ints.
1867 * If we *don't* have something, we'll re-enable before leaving here. */
1868 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1869 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1870
1871 /* Discover which interrupts are active/pending */
1872 inta = iwl_read32(priv, CSR_INT);
1873
1874 /* Ignore interrupt if there's nothing in NIC to service.
1875 * This may be due to IRQ shared with another device,
1876 * or due to sporadic interrupts thrown from our NIC. */
1877 if (!inta) {
1878 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1879 goto none;
1880 }
1881
1882 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1883 /* Hardware disappeared. It might have already raised
1884 * an interrupt */
1885 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1886 goto unplugged;
1887 }
1888
1889#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1890 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1891 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1892 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1893 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1894 }
1895#endif
1896
1897 priv->inta |= inta;
1898 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1899 if (likely(inta))
1900 tasklet_schedule(&priv->irq_tasklet);
1901 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1902 iwl_enable_interrupts(priv);
1903
1904 unplugged:
1905 spin_unlock(&priv->lock);
1906 return IRQ_HANDLED;
1907
1908 none:
1909 /* re-enable interrupts here since we don't have anything to service. */
1910 /* only Re-enable if diabled by irq and no schedules tasklet. */
1911 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1912 iwl_enable_interrupts(priv);
1913
1914 spin_unlock(&priv->lock);
1915 return IRQ_NONE;
1916}
1917
1918irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1919{
1920 struct iwl_priv *priv = data;
1921 u32 inta, inta_mask;
1922 u32 inta_fh;
1923 if (!priv)
1924 return IRQ_NONE;
1925
1926 spin_lock(&priv->lock);
1927
1928 /* Disable (but don't clear!) interrupts here to avoid
1929 * back-to-back ISRs and sporadic interrupts from our NIC.
1930 * If we have something to service, the tasklet will re-enable ints.
1931 * If we *don't* have something, we'll re-enable before leaving here. */
1932 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1933 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1934
1935 /* Discover which interrupts are active/pending */
1936 inta = iwl_read32(priv, CSR_INT);
1937 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1938
1939 /* Ignore interrupt if there's nothing in NIC to service.
1940 * This may be due to IRQ shared with another device,
1941 * or due to sporadic interrupts thrown from our NIC. */
1942 if (!inta && !inta_fh) {
1943 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1944 goto none;
1945 }
1946
1947 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1948 /* Hardware disappeared. It might have already raised
1949 * an interrupt */
1950 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1951 goto unplugged;
1952 }
1953
1954 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1955 inta, inta_mask, inta_fh);
1956
1957 inta &= ~CSR_INT_BIT_SCD;
1958
1959 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1960 if (likely(inta || inta_fh))
1961 tasklet_schedule(&priv->irq_tasklet);
1962
1963 unplugged:
1964 spin_unlock(&priv->lock);
1965 return IRQ_HANDLED;
1966
1967 none:
1968 /* re-enable interrupts here since we don't have anything to service. */
1969 /* only Re-enable if diabled by irq */
1970 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1971 iwl_enable_interrupts(priv);
1972 spin_unlock(&priv->lock);
1973 return IRQ_NONE;
1974}
ef850d7c 1975EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1976
17f841cd
SO		 1977int iwl_send_bt_config(struct iwl_priv *priv)
1978{
1979 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 1980 .flags = BT_COEX_MODE_4W,
1981 .lead_time = BT_LEAD_TIME_DEF,
1982 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 1983 .kill_ack_mask = 0,
1984 .kill_cts_mask = 0,
1985 };
1986
1987 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1988 sizeof(struct iwl_bt_cmd), &bt_cmd);
1989}
1990EXPORT_SYMBOL(iwl_send_bt_config);
1991
ef8d5529 1992int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
49ea8596 1993{
ef8d5529
WYG		 1994 struct iwl_statistics_cmd statistics_cmd = {
1995 .configuration_flags =
1996 clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
49ea8596 1997 };
ef8d5529
WYG		 1998
1999 if (flags & CMD_ASYNC)
2000 return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
2001 sizeof(struct iwl_statistics_cmd),
2002 &statistics_cmd, NULL);
2003 else
2004 return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
2005 sizeof(struct iwl_statistics_cmd),
2006 &statistics_cmd);
49ea8596
EG		 2007}
2008EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2009
b0692f2f
EG		 2010/**
2011 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2012 * using sample data 100 bytes apart. If these sample points are good,
2013 * it's a pretty good bet that everything between them is good, too.
2014 */
2015static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2016{
2017 u32 val;
2018 int ret = 0;
2019 u32 errcnt = 0;
2020 u32 i;
2021
e1623446 2022 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2023
b0692f2f
EG		 2024 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2025 /* read data comes through single port, auto-incr addr */
2026 /* NOTE: Use the debugless read so we don't flood kernel log
2027 * if IWL_DL_IO is set */
2028 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2029 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2030 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2031 if (val != le32_to_cpu(*image)) {
2032 ret = -EIO;
2033 errcnt++;
2034 if (errcnt >= 3)
2035 break;
2036 }
2037 }
2038
b0692f2f
EG		 2039 return ret;
2040}
2041
2042/**
2043 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2044 * looking at all data.
2045 */
2046static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2047 u32 len)
2048{
2049 u32 val;
2050 u32 save_len = len;
2051 int ret = 0;
2052 u32 errcnt;
2053
e1623446 2054 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2055
250bdd21
SO		 2056 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2057 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2058
2059 errcnt = 0;
2060 for (; len > 0; len -= sizeof(u32), image++) {
2061 /* read data comes through single port, auto-incr addr */
2062 /* NOTE: Use the debugless read so we don't flood kernel log
2063 * if IWL_DL_IO is set */
2064 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2065 if (val != le32_to_cpu(*image)) {
15b1687c 2066 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2067 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2068 save_len - len, val, le32_to_cpu(*image));
2069 ret = -EIO;
2070 errcnt++;
2071 if (errcnt >= 20)
2072 break;
2073 }
2074 }
2075
b0692f2f 2076 if (!errcnt)
e1623446
TW		 2077 IWL_DEBUG_INFO(priv,
2078 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2079
2080 return ret;
2081}
2082
2083/**
2084 * iwl_verify_ucode - determine which instruction image is in SRAM,
2085 * and verify its contents
2086 */
2087int iwl_verify_ucode(struct iwl_priv *priv)
2088{
2089 __le32 *image;
2090 u32 len;
2091 int ret;
2092
2093 /* Try bootstrap */
2094 image = (__le32 *)priv->ucode_boot.v_addr;
2095 len = priv->ucode_boot.len;
2096 ret = iwlcore_verify_inst_sparse(priv, image, len);
2097 if (!ret) {
e1623446 2098 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2099 return 0;
2100 }
2101
2102 /* Try initialize */
2103 image = (__le32 *)priv->ucode_init.v_addr;
2104 len = priv->ucode_init.len;
2105 ret = iwlcore_verify_inst_sparse(priv, image, len);
2106 if (!ret) {
e1623446 2107 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2108 return 0;
2109 }
2110
2111 /* Try runtime/protocol */
2112 image = (__le32 *)priv->ucode_code.v_addr;
2113 len = priv->ucode_code.len;
2114 ret = iwlcore_verify_inst_sparse(priv, image, len);
2115 if (!ret) {
e1623446 2116 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2117 return 0;
2118 }
2119
15b1687c 2120 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2121
2122 /* Since nothing seems to match, show first several data entries in
2123 * instruction SRAM, so maybe visual inspection will give a clue.
2124 * Selection of bootstrap image (vs. other images) is arbitrary. */
2125 image = (__le32 *)priv->ucode_boot.v_addr;
2126 len = priv->ucode_boot.len;
2127 ret = iwl_verify_inst_full(priv, image, len);
2128
2129 return ret;
2130}
2131EXPORT_SYMBOL(iwl_verify_ucode);
2132
56e12615 2133
47f4a587
EG		 2134void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2135{
2136 struct iwl_ct_kill_config cmd;
672639de 2137 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2138 unsigned long flags;
2139 int ret = 0;
2140
2141 spin_lock_irqsave(&priv->lock, flags);
2142 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2143 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2144 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2145 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2146
480e8407 2147 if (priv->cfg->support_ct_kill_exit) {
672639de
WYG		 2148 adv_cmd.critical_temperature_enter =
2149 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2150 adv_cmd.critical_temperature_exit =
2151 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2152
2153 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2154 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2155 if (ret)
2156 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2157 else
2158 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2159 "succeeded, "
2160 "critical temperature enter is %d,"
2161 "exit is %d\n",
2162 priv->hw_params.ct_kill_threshold,
2163 priv->hw_params.ct_kill_exit_threshold);
480e8407 2164 } else {
672639de
WYG		 2165 cmd.critical_temperature_R =
2166 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2167
672639de
WYG		 2168 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2169 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2170 if (ret)
2171 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2172 else
2173 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2174 "succeeded, "
2175 "critical temperature is %d\n",
2176 priv->hw_params.ct_kill_threshold);
672639de 2177 }
47f4a587
EG		 2178}
2179EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2180
0ad91a35 2181
14a08a7f
EG		 2182/*
2183 * CARD_STATE_CMD
2184 *
2185 * Use: Sets the device's internal card state to enable, disable, or halt
2186 *
2187 * When in the 'enable' state the card operates as normal.
2188 * When in the 'disable' state, the card enters into a low power mode.
2189 * When in the 'halt' state, the card is shut down and must be fully
2190 * restarted to come back on.
2191 */
c496294e 2192int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2193{
2194 struct iwl_host_cmd cmd = {
2195 .id = REPLY_CARD_STATE_CMD,
2196 .len = sizeof(u32),
2197 .data = &flags,
c2acea8e 2198 .flags = meta_flag,
14a08a7f
EG		 2199 };
2200
2201 return iwl_send_cmd(priv, &cmd);
2202}
2203
030f05ed
AK		 2204void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2205 struct iwl_rx_mem_buffer *rxb)
2206{
2207#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 2208 struct iwl_rx_packet *pkt = rxb_addr(rxb);
030f05ed
AK		 2209 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2210 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2211 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2212#endif
2213}
2214EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2215
2216void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2217 struct iwl_rx_mem_buffer *rxb)
2218{
2f301227 2219 struct iwl_rx_packet *pkt = rxb_addr(rxb);
396887a2 2220 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
030f05ed 2221 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
396887a2
DH		 2222 "notification for %s:\n", len,
2223 get_cmd_string(pkt->hdr.cmd));
2224 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
030f05ed
AK		 2225}
2226EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2227
2228void iwl_rx_reply_error(struct iwl_priv *priv,
2229 struct iwl_rx_mem_buffer *rxb)
2230{
2f301227 2231 struct iwl_rx_packet *pkt = rxb_addr(rxb);
261b9c33
AK		 2232
2233 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2234 "seq 0x%04X ser 0x%08X\n",
2235 le32_to_cpu(pkt->u.err_resp.error_type),
2236 get_cmd_string(pkt->u.err_resp.cmd_id),
2237 pkt->u.err_resp.cmd_id,
2238 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2239 le32_to_cpu(pkt->u.err_resp.error_info));
2240}
2241EXPORT_SYMBOL(iwl_rx_reply_error);
2242
a83b9141
WYG		 2243void iwl_clear_isr_stats(struct iwl_priv *priv)
2244{
2245 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2246}
a83b9141 2247
488829f1
AK		 2248int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2249 const struct ieee80211_tx_queue_params *params)
2250{
2251 struct iwl_priv *priv = hw->priv;
2252 unsigned long flags;
2253 int q;
2254
2255 IWL_DEBUG_MAC80211(priv, "enter\n");
2256
2257 if (!iwl_is_ready_rf(priv)) {
2258 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2259 return -EIO;
2260 }
2261
2262 if (queue >= AC_NUM) {
2263 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2264 return 0;
2265 }
2266
2267 q = AC_NUM - 1 - queue;
2268
2269 spin_lock_irqsave(&priv->lock, flags);
2270
2271 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2272 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2273 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2274 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2275 cpu_to_le16((params->txop * 32));
2276
2277 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2278 priv->qos_data.qos_active = 1;
2279
2280 if (priv->iw_mode == NL80211_IFTYPE_AP)
2281 iwl_activate_qos(priv, 1);
2282 else if (priv->assoc_id && iwl_is_associated(priv))
2283 iwl_activate_qos(priv, 0);
2284
2285 spin_unlock_irqrestore(&priv->lock, flags);
2286
2287 IWL_DEBUG_MAC80211(priv, "leave\n");
2288 return 0;
2289}
2290EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2291
2292static void iwl_ht_conf(struct iwl_priv *priv,
02bb1bea 2293 struct ieee80211_bss_conf *bss_conf)
5bbe233b 2294{
fad95bf5 2295 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
5bbe233b
AK		 2296 struct ieee80211_sta *sta;
2297
2298 IWL_DEBUG_MAC80211(priv, "enter: \n");
2299
fad95bf5 2300 if (!ht_conf->is_ht)
5bbe233b
AK		 2301 return;
2302
fad95bf5 2303 ht_conf->ht_protection =
9ed6bcce 2304 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
fad95bf5 2305 ht_conf->non_GF_STA_present =
9ed6bcce 2306 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b 2307
02bb1bea
JB		 2308 ht_conf->single_chain_sufficient = false;
2309
2310 switch (priv->iw_mode) {
2311 case NL80211_IFTYPE_STATION:
2312 rcu_read_lock();
5ed176e1 2313 sta = ieee80211_find_sta(priv->vif, priv->bssid);
02bb1bea
JB		 2314 if (sta) {
2315 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2316 int maxstreams;
2317
2318 maxstreams = (ht_cap->mcs.tx_params &
2319 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
2320 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2321 maxstreams += 1;
2322
2323 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2324 (ht_cap->mcs.rx_mask[2] == 0))
2325 ht_conf->single_chain_sufficient = true;
2326 if (maxstreams <= 1)
2327 ht_conf->single_chain_sufficient = true;
2328 } else {
2329 /*
2330 * If at all, this can only happen through a race
2331 * when the AP disconnects us while we're still
2332 * setting up the connection, in that case mac80211
2333 * will soon tell us about that.
2334 */
2335 ht_conf->single_chain_sufficient = true;
2336 }
2337 rcu_read_unlock();
2338 break;
2339 case NL80211_IFTYPE_ADHOC:
2340 ht_conf->single_chain_sufficient = true;
2341 break;
2342 default:
2343 break;
2344 }
5bbe233b
AK		 2345
2346 IWL_DEBUG_MAC80211(priv, "leave\n");
2347}
2348
2349#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2350void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2351 struct ieee80211_vif *vif,
2352 struct ieee80211_bss_conf *bss_conf,
2353 u32 changes)
5bbe233b
AK		 2354{
2355 struct iwl_priv *priv = hw->priv;
3a650292 2356 int ret;
5bbe233b
AK		 2357
2358 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2359
2d0ddec5
JB		 2360 if (!iwl_is_alive(priv))
2361 return;
2362
2363 mutex_lock(&priv->mutex);
2364
2365 if (changes & BSS_CHANGED_BEACON &&
2366 priv->iw_mode == NL80211_IFTYPE_AP) {
2367 dev_kfree_skb(priv->ibss_beacon);
2368 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2369 }
2370
d7129e19
JB		 2371 if (changes & BSS_CHANGED_BEACON_INT) {
2372 priv->beacon_int = bss_conf->beacon_int;
2373 /* TODO: in AP mode, do something to make this take effect */
2374 }
2375
2376 if (changes & BSS_CHANGED_BSSID) {
2377 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2378
2379 /*
2380 * If there is currently a HW scan going on in the
2381 * background then we need to cancel it else the RXON
2382 * below/in post_associate will fail.
2383 */
2d0ddec5 2384 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2385 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2386 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2387 mutex_unlock(&priv->mutex);
2388 return;
2389 }
2d0ddec5 2390
d7129e19
JB		 2391 /* mac80211 only sets assoc when in STATION mode */
2392 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2393 bss_conf->assoc) {
2394 memcpy(priv->staging_rxon.bssid_addr,
2395 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2396
d7129e19
JB		 2397 /* currently needed in a few places */
2398 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2399 } else {
2400 priv->staging_rxon.filter_flags &=
2401 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2402 }
d7129e19 2403
2d0ddec5
JB		 2404 }
2405
d7129e19
JB		 2406 /*
2407 * This needs to be after setting the BSSID in case
2408 * mac80211 decides to do both changes at once because
2409 * it will invoke post_associate.
2410 */
2d0ddec5
JB		 2411 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2412 changes & BSS_CHANGED_BEACON) {
2413 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2414
2415 if (beacon)
2416 iwl_mac_beacon_update(hw, beacon);
2417 }
2418
5bbe233b
AK		 2419 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2420 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2421 bss_conf->use_short_preamble);
2422 if (bss_conf->use_short_preamble)
2423 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2424 else
2425 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2426 }
2427
2428 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2429 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2430 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2431 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2432 else
2433 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2434 }
2435
d7129e19
JB		 2436 if (changes & BSS_CHANGED_BASIC_RATES) {
2437 /* XXX use this information
2438 *
2439 * To do that, remove code from iwl_set_rate() and put something
2440 * like this here:
2441 *
2442 if (A-band)
2443 priv->staging_rxon.ofdm_basic_rates =
2444 bss_conf->basic_rates;
2445 else
2446 priv->staging_rxon.ofdm_basic_rates =
2447 bss_conf->basic_rates >> 4;
2448 priv->staging_rxon.cck_basic_rates =
2449 bss_conf->basic_rates & 0xF;
2450 */
2451 }
2452
5bbe233b
AK		 2453 if (changes & BSS_CHANGED_HT) {
2454 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2455
2456 if (priv->cfg->ops->hcmd->set_rxon_chain)
2457 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2458 }
2459
2460 if (changes & BSS_CHANGED_ASSOC) {
2461 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2462 if (bss_conf->assoc) {
2463 priv->assoc_id = bss_conf->aid;
2464 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2465 priv->timestamp = bss_conf->timestamp;
2466 priv->assoc_capability = bss_conf->assoc_capability;
2467
e932a609
JB		 2468 iwl_led_associate(priv);
2469
d7129e19
JB		 2470 /*
2471 * We have just associated, don't start scan too early
2472 * leave time for EAPOL exchange to complete.
2473 *
2474 * XXX: do this in mac80211
5bbe233b
AK		 2475 */
2476 priv->next_scan_jiffies = jiffies +
2477 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2478 if (!iwl_is_rfkill(priv))
2479 priv->cfg->ops->lib->post_associate(priv);
e932a609 2480 } else {
5bbe233b 2481 priv->assoc_id = 0;
e932a609 2482 iwl_led_disassociate(priv);
644c77f0
JS		 2483
2484 /*
2485 * inform the ucode that there is no longer an
2486 * association and that no more packets should be
2487 * send
2488 */
2489 priv->staging_rxon.filter_flags &=
2490 ~RXON_FILTER_ASSOC_MSK;
2491 priv->staging_rxon.assoc_id = 0;
2492 iwlcore_commit_rxon(priv);
e932a609 2493 }
d7129e19
JB		 2494 }
2495
2496 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2497 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2498 changes);
2499 ret = iwl_send_rxon_assoc(priv);
2500 if (!ret) {
2501 /* Sync active_rxon with latest change. */
2502 memcpy((void *)&priv->active_rxon,
2503 &priv->staging_rxon,
2504 sizeof(struct iwl_rxon_cmd));
5bbe233b 2505 }
5bbe233b 2506 }
d7129e19 2507
f513dfff
DH		 2508 if ((changes & BSS_CHANGED_BEACON_ENABLED) &&
2509 vif->bss_conf.enable_beacon) {
2510 memcpy(priv->staging_rxon.bssid_addr,
2511 bss_conf->bssid, ETH_ALEN);
2512 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2513 iwlcore_config_ap(priv);
2514 }
2515
d7129e19
JB		 2516 mutex_unlock(&priv->mutex);
2517
2d0ddec5 2518 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2519}
2520EXPORT_SYMBOL(iwl_bss_info_changed);
2521
9944b938
AK		 2522int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2523{
2524 struct iwl_priv *priv = hw->priv;
2525 unsigned long flags;
2526 __le64 timestamp;
2527
2528 IWL_DEBUG_MAC80211(priv, "enter\n");
2529
2530 if (!iwl_is_ready_rf(priv)) {
2531 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2532 return -EIO;
2533 }
2534
2535 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2536 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2537 return -EIO;
2538 }
2539
2540 spin_lock_irqsave(&priv->lock, flags);
2541
2542 if (priv->ibss_beacon)
2543 dev_kfree_skb(priv->ibss_beacon);
2544
2545 priv->ibss_beacon = skb;
2546
2547 priv->assoc_id = 0;
2548 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2549 priv->timestamp = le64_to_cpu(timestamp);
2550
2551 IWL_DEBUG_MAC80211(priv, "leave\n");
2552 spin_unlock_irqrestore(&priv->lock, flags);
2553
2554 iwl_reset_qos(priv);
2555
2556 priv->cfg->ops->lib->post_associate(priv);
2557
2558
2559 return 0;
2560}
2561EXPORT_SYMBOL(iwl_mac_beacon_update);
2562
727882d6
AK		 2563int iwl_set_mode(struct iwl_priv *priv, int mode)
2564{
2565 if (mode == NL80211_IFTYPE_ADHOC) {
2566 const struct iwl_channel_info *ch_info;
2567
2568 ch_info = iwl_get_channel_info(priv,
2569 priv->band,
2570 le16_to_cpu(priv->staging_rxon.channel));
2571
2572 if (!ch_info || !is_channel_ibss(ch_info)) {
2573 IWL_ERR(priv, "channel %d not IBSS channel\n",
2574 le16_to_cpu(priv->staging_rxon.channel));
2575 return -EINVAL;
2576 }
2577 }
2578
2579 iwl_connection_init_rx_config(priv, mode);
2580
2581 if (priv->cfg->ops->hcmd->set_rxon_chain)
2582 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2583
2584 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2585
c587de0b 2586 iwl_clear_stations_table(priv);
727882d6
AK		 2587
2588 /* dont commit rxon if rf-kill is on*/
2589 if (!iwl_is_ready_rf(priv))
2590 return -EAGAIN;
2591
727882d6
AK		 2592 iwlcore_commit_rxon(priv);
2593
2594 return 0;
2595}
2596EXPORT_SYMBOL(iwl_set_mode);
2597
cbb6ab94
AK		 2598int iwl_mac_add_interface(struct ieee80211_hw *hw,
2599 struct ieee80211_if_init_conf *conf)
2600{
2601 struct iwl_priv *priv = hw->priv;
2602 unsigned long flags;
2603
2604 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2605
2606 if (priv->vif) {
2607 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2608 return -EOPNOTSUPP;
2609 }
2610
2611 spin_lock_irqsave(&priv->lock, flags);
2612 priv->vif = conf->vif;
2613 priv->iw_mode = conf->type;
2614
2615 spin_unlock_irqrestore(&priv->lock, flags);
2616
2617 mutex_lock(&priv->mutex);
2618
2619 if (conf->mac_addr) {
2620 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2621 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2622 }
2623
2624 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2625 /* we are not ready, will run again when ready */
2626 set_bit(STATUS_MODE_PENDING, &priv->status);
2627
2628 mutex_unlock(&priv->mutex);
2629
2630 IWL_DEBUG_MAC80211(priv, "leave\n");
2631 return 0;
2632}
2633EXPORT_SYMBOL(iwl_mac_add_interface);
2634
d8052319
AK		 2635void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2636 struct ieee80211_if_init_conf *conf)
2637{
2638 struct iwl_priv *priv = hw->priv;
2639
2640 IWL_DEBUG_MAC80211(priv, "enter\n");
2641
2642 mutex_lock(&priv->mutex);
2643
2644 if (iwl_is_ready_rf(priv)) {
2645 iwl_scan_cancel_timeout(priv, 100);
2646 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2647 iwlcore_commit_rxon(priv);
2648 }
2649 if (priv->vif == conf->vif) {
2650 priv->vif = NULL;
2651 memset(priv->bssid, 0, ETH_ALEN);
2652 }
2653 mutex_unlock(&priv->mutex);
2654
2655 IWL_DEBUG_MAC80211(priv, "leave\n");
2656
2657}
2658EXPORT_SYMBOL(iwl_mac_remove_interface);
2659
4808368d
AK		 2660/**
2661 * iwl_mac_config - mac80211 config callback
2662 *
2663 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2664 * be set inappropriately and the driver currently sets the hardware up to
2665 * use it whenever needed.
2666 */
2667int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2668{
2669 struct iwl_priv *priv = hw->priv;
2670 const struct iwl_channel_info *ch_info;
2671 struct ieee80211_conf *conf = &hw->conf;
fad95bf5 2672 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
4808368d
AK		 2673 unsigned long flags = 0;
2674 int ret = 0;
2675 u16 ch;
2676 int scan_active = 0;
2677
2678 mutex_lock(&priv->mutex);
2679
4808368d
AK		 2680 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2681 conf->channel->hw_value, changed);
2682
2683 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2684 test_bit(STATUS_SCANNING, &priv->status))) {
2685 scan_active = 1;
2686 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2687 }
2688
2689
2690 /* during scanning mac80211 will delay channel setting until
2691 * scan finish with changed = 0
2692 */
2693 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2694 if (scan_active)
2695 goto set_ch_out;
2696
2697 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2698 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2699 if (!is_channel_valid(ch_info)) {
2700 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2701 ret = -EINVAL;
2702 goto set_ch_out;
2703 }
2704
2705 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2706 !is_channel_ibss(ch_info)) {
2707 IWL_ERR(priv, "channel %d in band %d not "
2708 "IBSS channel\n",
2709 conf->channel->hw_value, conf->channel->band);
2710 ret = -EINVAL;
2711 goto set_ch_out;
2712 }
2713
4808368d
AK		 2714 spin_lock_irqsave(&priv->lock, flags);
2715
28bd723b
DH		 2716 /* Configure HT40 channels */
2717 ht_conf->is_ht = conf_is_ht(conf);
2718 if (ht_conf->is_ht) {
2719 if (conf_is_ht40_minus(conf)) {
2720 ht_conf->extension_chan_offset =
2721 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
c812ee24 2722 ht_conf->is_40mhz = true;
28bd723b
DH		 2723 } else if (conf_is_ht40_plus(conf)) {
2724 ht_conf->extension_chan_offset =
2725 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
c812ee24 2726 ht_conf->is_40mhz = true;
28bd723b
DH		 2727 } else {
2728 ht_conf->extension_chan_offset =
2729 IEEE80211_HT_PARAM_CHA_SEC_NONE;
c812ee24 2730 ht_conf->is_40mhz = false;
28bd723b
DH		 2731 }
2732 } else
c812ee24 2733 ht_conf->is_40mhz = false;
28bd723b
DH		 2734 /* Default to no protection. Protection mode will later be set
2735 * from BSS config in iwl_ht_conf */
2736 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2737
2738 /* if we are switching from ht to 2.4 clear flags
2739 * from any ht related info since 2.4 does not
2740 * support ht */
2741 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2742 priv->staging_rxon.flags = 0;
2743
2744 iwl_set_rxon_channel(priv, conf->channel);
2745
2746 iwl_set_flags_for_band(priv, conf->channel->band);
2747 spin_unlock_irqrestore(&priv->lock, flags);
0924e519
WYG		 2748 if (iwl_is_associated(priv) &&
2749 (le16_to_cpu(priv->active_rxon.channel) != ch) &&
2750 priv->cfg->ops->lib->set_channel_switch) {
2751 iwl_set_rate(priv);
2752 /*
2753 * at this point, staging_rxon has the
2754 * configuration for channel switch
2755 */
2756 ret = priv->cfg->ops->lib->set_channel_switch(priv,
2757 ch);
2758 if (!ret) {
2759 iwl_print_rx_config_cmd(priv);
2760 goto out;
2761 }
2762 priv->switch_rxon.switch_in_progress = false;
2763 }
4808368d
AK		 2764 set_ch_out:
2765 /* The list of supported rates and rate mask can be different
2766 * for each band; since the band may have changed, reset
2767 * the rate mask to what mac80211 lists */
2768 iwl_set_rate(priv);
2769 }
2770
78f5fb7f
JB		 2771 if (changed & (IEEE80211_CONF_CHANGE_PS |
2772 IEEE80211_CONF_CHANGE_IDLE)) {
e312c24c 2773 ret = iwl_power_update_mode(priv, false);
4808368d 2774 if (ret)
e312c24c 2775 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2776 }
2777
2778 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2779 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2780 priv->tx_power_user_lmt, conf->power_level);
2781
2782 iwl_set_tx_power(priv, conf->power_level, false);
2783 }
2784
2785 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2786 if (priv->cfg->ops->hcmd->set_rxon_chain)
2787 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2788
0cf4c01e
MA		 2789 if (!iwl_is_ready(priv)) {
2790 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2791 goto out;
2792 }
2793
4808368d
AK		 2794 if (scan_active)
2795 goto out;
2796
2797 if (memcmp(&priv->active_rxon,
2798 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2799 iwlcore_commit_rxon(priv);
2800 else
2801 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2802
2803
2804out:
2805 IWL_DEBUG_MAC80211(priv, "leave\n");
2806 mutex_unlock(&priv->mutex);
2807 return ret;
2808}
2809EXPORT_SYMBOL(iwl_mac_config);
2810
aa89f31e
AK		 2811int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2812 struct ieee80211_tx_queue_stats *stats)
2813{
2814 struct iwl_priv *priv = hw->priv;
2815 int i, avail;
2816 struct iwl_tx_queue *txq;
2817 struct iwl_queue *q;
2818 unsigned long flags;
2819
2820 IWL_DEBUG_MAC80211(priv, "enter\n");
2821
2822 if (!iwl_is_ready_rf(priv)) {
2823 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2824 return -EIO;
2825 }
2826
2827 spin_lock_irqsave(&priv->lock, flags);
2828
2829 for (i = 0; i < AC_NUM; i++) {
2830 txq = &priv->txq[i];
2831 q = &txq->q;
2832 avail = iwl_queue_space(q);
2833
2834 stats[i].len = q->n_window - avail;
2835 stats[i].limit = q->n_window - q->high_mark;
2836 stats[i].count = q->n_window;
2837
2838 }
2839 spin_unlock_irqrestore(&priv->lock, flags);
2840
2841 IWL_DEBUG_MAC80211(priv, "leave\n");
2842
2843 return 0;
2844}
2845EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2846
bd564261
AK		 2847void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2848{
2849 struct iwl_priv *priv = hw->priv;
2850 unsigned long flags;
2851
2852 mutex_lock(&priv->mutex);
2853 IWL_DEBUG_MAC80211(priv, "enter\n");
2854
2855 spin_lock_irqsave(&priv->lock, flags);
fad95bf5 2856 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
bd564261
AK		 2857 spin_unlock_irqrestore(&priv->lock, flags);
2858
2859 iwl_reset_qos(priv);
2860
2861 spin_lock_irqsave(&priv->lock, flags);
2862 priv->assoc_id = 0;
2863 priv->assoc_capability = 0;
2864 priv->assoc_station_added = 0;
2865
2866 /* new association get rid of ibss beacon skb */
2867 if (priv->ibss_beacon)
2868 dev_kfree_skb(priv->ibss_beacon);
2869
2870 priv->ibss_beacon = NULL;
2871
57c4d7b4 2872 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2873 priv->timestamp = 0;
2874 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2875 priv->beacon_int = 0;
2876
2877 spin_unlock_irqrestore(&priv->lock, flags);
2878
2879 if (!iwl_is_ready_rf(priv)) {
2880 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2881 mutex_unlock(&priv->mutex);
2882 return;
2883 }
2884
2885 /* we are restarting association process
2886 * clear RXON_FILTER_ASSOC_MSK bit
2887 */
2888 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2889 iwl_scan_cancel_timeout(priv, 100);
2890 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2891 iwlcore_commit_rxon(priv);
2892 }
2893
bd564261 2894 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2895 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2896 mutex_unlock(&priv->mutex);
2897 return;
2898 }
2899
2900 iwl_set_rate(priv);
2901
2902 mutex_unlock(&priv->mutex);
2903
2904 IWL_DEBUG_MAC80211(priv, "leave\n");
2905}
2906EXPORT_SYMBOL(iwl_mac_reset_tsf);
2907
88804e2b
WYG		 2908int iwl_alloc_txq_mem(struct iwl_priv *priv)
2909{
2910 if (!priv->txq)
2911 priv->txq = kzalloc(
2912 sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
2913 GFP_KERNEL);
2914 if (!priv->txq) {
2915 IWL_ERR(priv, "Not enough memory for txq \n");
2916 return -ENOMEM;
2917 }
2918 return 0;
2919}
2920EXPORT_SYMBOL(iwl_alloc_txq_mem);
2921
2922void iwl_free_txq_mem(struct iwl_priv *priv)
2923{
2924 kfree(priv->txq);
2925 priv->txq = NULL;
2926}
2927EXPORT_SYMBOL(iwl_free_txq_mem);
2928
1933ac4d
WYG		 2929int iwl_send_wimax_coex(struct iwl_priv *priv)
2930{
2931 struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
2932
2933 if (priv->cfg->support_wimax_coexist) {
2934 /* UnMask wake up src at associated sleep */
2935 coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
2936
2937 /* UnMask wake up src at unassociated sleep */
2938 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
2939 memcpy(coex_cmd.sta_prio, cu_priorities,
2940 sizeof(struct iwl_wimax_coex_event_entry) *
2941 COEX_NUM_OF_EVENTS);
2942
2943 /* enabling the coexistence feature */
2944 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
2945
2946 /* enabling the priorities tables */
2947 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
2948 } else {
2949 /* coexistence is disabled */
2950 memset(&coex_cmd, 0, sizeof(coex_cmd));
2951 }
2952 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
2953 sizeof(coex_cmd), &coex_cmd);
2954}
2955EXPORT_SYMBOL(iwl_send_wimax_coex);
2956
20594eb0
WYG		 2957#ifdef CONFIG_IWLWIFI_DEBUGFS
2958
2959#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2960
2961void iwl_reset_traffic_log(struct iwl_priv *priv)
2962{
2963 priv->tx_traffic_idx = 0;
2964 priv->rx_traffic_idx = 0;
2965 if (priv->tx_traffic)
2966 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2967 if (priv->rx_traffic)
2968 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2969}
2970
2971int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2972{
2973 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2974
2975 if (iwl_debug_level & IWL_DL_TX) {
2976 if (!priv->tx_traffic) {
2977 priv->tx_traffic =
2978 kzalloc(traffic_size, GFP_KERNEL);
2979 if (!priv->tx_traffic)
2980 return -ENOMEM;
2981 }
2982 }
2983 if (iwl_debug_level & IWL_DL_RX) {
2984 if (!priv->rx_traffic) {
2985 priv->rx_traffic =
2986 kzalloc(traffic_size, GFP_KERNEL);
2987 if (!priv->rx_traffic)
2988 return -ENOMEM;
2989 }
2990 }
2991 iwl_reset_traffic_log(priv);
2992 return 0;
2993}
2994EXPORT_SYMBOL(iwl_alloc_traffic_mem);
2995
2996void iwl_free_traffic_mem(struct iwl_priv *priv)
2997{
2998 kfree(priv->tx_traffic);
2999 priv->tx_traffic = NULL;
3000
3001 kfree(priv->rx_traffic);
3002 priv->rx_traffic = NULL;
3003}
3004EXPORT_SYMBOL(iwl_free_traffic_mem);
3005
3006void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
3007 u16 length, struct ieee80211_hdr *header)
3008{
3009 __le16 fc;
3010 u16 len;
3011
3012 if (likely(!(iwl_debug_level & IWL_DL_TX)))
3013 return;
3014
3015 if (!priv->tx_traffic)
3016 return;
3017
3018 fc = header->frame_control;
3019 if (ieee80211_is_data(fc)) {
3020 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3021 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3022 memcpy((priv->tx_traffic +
3023 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3024 header, len);
3025 priv->tx_traffic_idx =
3026 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3027 }
3028}
3029EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
3030
3031void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
3032 u16 length, struct ieee80211_hdr *header)
3033{
3034 __le16 fc;
3035 u16 len;
3036
3037 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3038 return;
3039
3040 if (!priv->rx_traffic)
3041 return;
3042
3043 fc = header->frame_control;
3044 if (ieee80211_is_data(fc)) {
3045 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3046 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3047 memcpy((priv->rx_traffic +
3048 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3049 header, len);
3050 priv->rx_traffic_idx =
3051 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3052 }
3053}
3054EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 3055
3056const char *get_mgmt_string(int cmd)
3057{
3058 switch (cmd) {
3059 IWL_CMD(MANAGEMENT_ASSOC_REQ);
3060 IWL_CMD(MANAGEMENT_ASSOC_RESP);
3061 IWL_CMD(MANAGEMENT_REASSOC_REQ);
3062 IWL_CMD(MANAGEMENT_REASSOC_RESP);
3063 IWL_CMD(MANAGEMENT_PROBE_REQ);
3064 IWL_CMD(MANAGEMENT_PROBE_RESP);
3065 IWL_CMD(MANAGEMENT_BEACON);
3066 IWL_CMD(MANAGEMENT_ATIM);
3067 IWL_CMD(MANAGEMENT_DISASSOC);
3068 IWL_CMD(MANAGEMENT_AUTH);
3069 IWL_CMD(MANAGEMENT_DEAUTH);
3070 IWL_CMD(MANAGEMENT_ACTION);
3071 default:
3072 return "UNKNOWN";
3073
3074 }
3075}
3076
3077const char *get_ctrl_string(int cmd)
3078{
3079 switch (cmd) {
3080 IWL_CMD(CONTROL_BACK_REQ);
3081 IWL_CMD(CONTROL_BACK);
3082 IWL_CMD(CONTROL_PSPOLL);
3083 IWL_CMD(CONTROL_RTS);
3084 IWL_CMD(CONTROL_CTS);
3085 IWL_CMD(CONTROL_ACK);
3086 IWL_CMD(CONTROL_CFEND);
3087 IWL_CMD(CONTROL_CFENDACK);
3088 default:
3089 return "UNKNOWN";
3090
3091 }
3092}
3093
7163b8a4 3094void iwl_clear_traffic_stats(struct iwl_priv *priv)
22fdf3c9
WYG		 3095{
3096 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
22fdf3c9 3097 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
7163b8a4 3098 priv->led_tpt = 0;
22fdf3c9
WYG		 3099}
3100
3101/*
3102 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3103 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3104 * Use debugFs to display the rx/rx_statistics
3105 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3106 * information will be recorded, but DATA pkt still will be recorded
3107 * for the reason of iwl_led.c need to control the led blinking based on
3108 * number of tx and rx data.
3109 *
3110 */
3111void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3112{
3113 struct traffic_stats *stats;
3114
3115 if (is_tx)
3116 stats = &priv->tx_stats;
3117 else
3118 stats = &priv->rx_stats;
3119
3120 if (ieee80211_is_mgmt(fc)) {
3121 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3122 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3123 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3124 break;
3125 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3126 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3127 break;
3128 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3129 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3130 break;
3131 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3132 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3133 break;
3134 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3135 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3136 break;
3137 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3138 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3139 break;
3140 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3141 stats->mgmt[MANAGEMENT_BEACON]++;
3142 break;
3143 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3144 stats->mgmt[MANAGEMENT_ATIM]++;
3145 break;
3146 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3147 stats->mgmt[MANAGEMENT_DISASSOC]++;
3148 break;
3149 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3150 stats->mgmt[MANAGEMENT_AUTH]++;
3151 break;
3152 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3153 stats->mgmt[MANAGEMENT_DEAUTH]++;
3154 break;
3155 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3156 stats->mgmt[MANAGEMENT_ACTION]++;
3157 break;
3158 }
3159 } else if (ieee80211_is_ctl(fc)) {
3160 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3161 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3162 stats->ctrl[CONTROL_BACK_REQ]++;
3163 break;
3164 case cpu_to_le16(IEEE80211_STYPE_BACK):
3165 stats->ctrl[CONTROL_BACK]++;
3166 break;
3167 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3168 stats->ctrl[CONTROL_PSPOLL]++;
3169 break;
3170 case cpu_to_le16(IEEE80211_STYPE_RTS):
3171 stats->ctrl[CONTROL_RTS]++;
3172 break;
3173 case cpu_to_le16(IEEE80211_STYPE_CTS):
3174 stats->ctrl[CONTROL_CTS]++;
3175 break;
3176 case cpu_to_le16(IEEE80211_STYPE_ACK):
3177 stats->ctrl[CONTROL_ACK]++;
3178 break;
3179 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3180 stats->ctrl[CONTROL_CFEND]++;
3181 break;
3182 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3183 stats->ctrl[CONTROL_CFENDACK]++;
3184 break;
3185 }
3186 } else {
3187 /* data */
3188 stats->data_cnt++;
3189 stats->data_bytes += len;
3190 }
d5f4cf71 3191 iwl_leds_background(priv);
22fdf3c9
WYG		 3192}
3193EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3194#endif
3195
696bdee3
WYG		 3196const static char *get_csr_string(int cmd)
3197{
3198 switch (cmd) {
3199 IWL_CMD(CSR_HW_IF_CONFIG_REG);
3200 IWL_CMD(CSR_INT_COALESCING);
3201 IWL_CMD(CSR_INT);
3202 IWL_CMD(CSR_INT_MASK);
3203 IWL_CMD(CSR_FH_INT_STATUS);
3204 IWL_CMD(CSR_GPIO_IN);
3205 IWL_CMD(CSR_RESET);
3206 IWL_CMD(CSR_GP_CNTRL);
3207 IWL_CMD(CSR_HW_REV);
3208 IWL_CMD(CSR_EEPROM_REG);
3209 IWL_CMD(CSR_EEPROM_GP);
3210 IWL_CMD(CSR_OTP_GP_REG);
3211 IWL_CMD(CSR_GIO_REG);
3212 IWL_CMD(CSR_GP_UCODE_REG);
3213 IWL_CMD(CSR_GP_DRIVER_REG);
3214 IWL_CMD(CSR_UCODE_DRV_GP1);
3215 IWL_CMD(CSR_UCODE_DRV_GP2);
3216 IWL_CMD(CSR_LED_REG);
3217 IWL_CMD(CSR_DRAM_INT_TBL_REG);
3218 IWL_CMD(CSR_GIO_CHICKEN_BITS);
3219 IWL_CMD(CSR_ANA_PLL_CFG);
3220 IWL_CMD(CSR_HW_REV_WA_REG);
3221 IWL_CMD(CSR_DBG_HPET_MEM_REG);
3222 default:
3223 return "UNKNOWN";
3224
3225 }
3226}
3227
3228void iwl_dump_csr(struct iwl_priv *priv)
3229{
3230 int i;
3231 u32 csr_tbl[] = {
3232 CSR_HW_IF_CONFIG_REG,
3233 CSR_INT_COALESCING,
3234 CSR_INT,
3235 CSR_INT_MASK,
3236 CSR_FH_INT_STATUS,
3237 CSR_GPIO_IN,
3238 CSR_RESET,
3239 CSR_GP_CNTRL,
3240 CSR_HW_REV,
3241 CSR_EEPROM_REG,
3242 CSR_EEPROM_GP,
3243 CSR_OTP_GP_REG,
3244 CSR_GIO_REG,
3245 CSR_GP_UCODE_REG,
3246 CSR_GP_DRIVER_REG,
3247 CSR_UCODE_DRV_GP1,
3248 CSR_UCODE_DRV_GP2,
3249 CSR_LED_REG,
3250 CSR_DRAM_INT_TBL_REG,
3251 CSR_GIO_CHICKEN_BITS,
3252 CSR_ANA_PLL_CFG,
3253 CSR_HW_REV_WA_REG,
3254 CSR_DBG_HPET_MEM_REG
3255 };
3256 IWL_ERR(priv, "CSR values:\n");
3257 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
3258 "CSR_INT_PERIODIC_REG)\n");
3259 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
3260 IWL_ERR(priv, " %25s: 0X%08x\n",
3261 get_csr_string(csr_tbl[i]),
3262 iwl_read32(priv, csr_tbl[i]));
3263 }
3264}
3265EXPORT_SYMBOL(iwl_dump_csr);
3266
6da3a13e
WYG		 3267#ifdef CONFIG_PM
3268
3269int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3270{
3271 struct iwl_priv *priv = pci_get_drvdata(pdev);
3272
3273 /*
3274 * This function is called when system goes into suspend state
3275 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3276 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3277 * it will not call apm_ops.stop() to stop the DMA operation.
3278 * Calling apm_ops.stop here to make sure we stop the DMA.
3279 */
3280 priv->cfg->ops->lib->apm_ops.stop(priv);
3281
3282 pci_save_state(pdev);
3283 pci_disable_device(pdev);
3284 pci_set_power_state(pdev, PCI_D3hot);
3285
3286 return 0;
3287}
3288EXPORT_SYMBOL(iwl_pci_suspend);
3289
3290int iwl_pci_resume(struct pci_dev *pdev)
3291{
3292 struct iwl_priv *priv = pci_get_drvdata(pdev);
3293 int ret;
3294
3295 pci_set_power_state(pdev, PCI_D0);
3296 ret = pci_enable_device(pdev);
3297 if (ret)
3298 return ret;
3299 pci_restore_state(pdev);
3300 iwl_enable_interrupts(priv);
3301
3302 return 0;
3303}
3304EXPORT_SYMBOL(iwl_pci_resume);
3305
3306#endif /* CONFIG_PM */
Linux kernel - Deliverables
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