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cfg80211: add support for custom firmware regulatory solutions
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
1d0a082d 31#include <net/mac80211.h>
df48c323 32
6bc913bd 33#include "iwl-eeprom.h"
3e0d4cb1 34#include "iwl-dev.h" /* FIXME: remove */
19335774 35#include "iwl-debug.h"
df48c323 36#include "iwl-core.h"
b661c819 37#include "iwl-io.h"
ad97edd2 38#include "iwl-rfkill.h"
5da4b55f 39#include "iwl-power.h"
df48c323 40
1d0a082d 41
df48c323
TW		 42MODULE_DESCRIPTION("iwl core");
43MODULE_VERSION(IWLWIFI_VERSION);
44MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 45MODULE_LICENSE("GPL");
df48c323 46
c7de35cd
RR		 47#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
48 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
49 IWL_RATE_SISO_##s##M_PLCP, \
50 IWL_RATE_MIMO2_##s##M_PLCP,\
51 IWL_RATE_MIMO3_##s##M_PLCP,\
52 IWL_RATE_##r##M_IEEE, \
53 IWL_RATE_##ip##M_INDEX, \
54 IWL_RATE_##in##M_INDEX, \
55 IWL_RATE_##rp##M_INDEX, \
56 IWL_RATE_##rn##M_INDEX, \
57 IWL_RATE_##pp##M_INDEX, \
58 IWL_RATE_##np##M_INDEX }
59
60/*
61 * Parameter order:
62 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
63 *
64 * If there isn't a valid next or previous rate then INV is used which
65 * maps to IWL_RATE_INVALID
66 *
67 */
1826dcc0 68const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 69 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
70 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
71 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
72 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
73 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
74 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
75 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
76 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
77 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
78 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
79 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
80 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
81 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
82 /* FIXME:RS: ^^ should be INV (legacy) */
83};
1826dcc0 84EXPORT_SYMBOL(iwl_rates);
c7de35cd 85
e7d326ac
TW		 86/**
87 * translate ucode response to mac80211 tx status control values
88 */
89void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 90 struct ieee80211_tx_info *info)
e7d326ac
TW		 91{
92 int rate_index;
e6a9854b 93 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 94
e6a9854b 95 info->antenna_sel_tx =
e7d326ac
TW		 96 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
97 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 98 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 99 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 100 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
e7d326ac 101 if (rate_n_flags & RATE_MCS_FAT_MSK)
e6a9854b 102 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 103 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 104 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 105 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 106 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 107 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 108 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 109 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 110 r->idx = rate_index;
e7d326ac
TW		 111}
112EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
113
114int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
115{
116 int idx = 0;
117
118 /* HT rate format */
119 if (rate_n_flags & RATE_MCS_HT_MSK) {
120 idx = (rate_n_flags & 0xff);
121
60d32215
DH		 122 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
123 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
124 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 125 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
126
127 idx += IWL_FIRST_OFDM_RATE;
128 /* skip 9M not supported in ht*/
129 if (idx >= IWL_RATE_9M_INDEX)
130 idx += 1;
131 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
132 return idx;
133
134 /* legacy rate format, search for match in table */
135 } else {
136 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
137 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
138 return idx;
139 }
140
141 return -1;
142}
143EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
144
76eff18b
TW		 145u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
146{
147 int i;
148 u8 ind = ant;
149 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
150 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
151 if (priv->hw_params.valid_tx_ant & BIT(ind))
152 return ind;
153 }
154 return ant;
155}
57bd1bea
TW		 156
157const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
158EXPORT_SYMBOL(iwl_bcast_addr);
159
160
1d0a082d
AK		 161/* This function both allocates and initializes hw and priv. */
162struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
163 struct ieee80211_ops *hw_ops)
164{
165 struct iwl_priv *priv;
166
167 /* mac80211 allocates memory for this device instance, including
168 * space for this driver's private structure */
169 struct ieee80211_hw *hw =
170 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
171 if (hw == NULL) {
172 IWL_ERROR("Can not allocate network device\n");
173 goto out;
174 }
175
176 priv = hw->priv;
177 priv->hw = hw;
178
179out:
180 return hw;
181}
182EXPORT_SYMBOL(iwl_alloc_all);
183
b661c819
TW		 184void iwl_hw_detect(struct iwl_priv *priv)
185{
186 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
187 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
188 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
189}
190EXPORT_SYMBOL(iwl_hw_detect);
191
1053d35f
RR		 192int iwl_hw_nic_init(struct iwl_priv *priv)
193{
194 unsigned long flags;
195 struct iwl_rx_queue *rxq = &priv->rxq;
196 int ret;
197
198 /* nic_init */
1053d35f 199 spin_lock_irqsave(&priv->lock, flags);
1b73af82 200 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 201 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
202 spin_unlock_irqrestore(&priv->lock, flags);
203
204 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
205
206 priv->cfg->ops->lib->apm_ops.config(priv);
207
208 /* Allocate the RX queue, or reset if it is already allocated */
209 if (!rxq->bd) {
210 ret = iwl_rx_queue_alloc(priv);
211 if (ret) {
212 IWL_ERROR("Unable to initialize Rx queue\n");
213 return -ENOMEM;
214 }
215 } else
216 iwl_rx_queue_reset(priv, rxq);
217
218 iwl_rx_replenish(priv);
219
220 iwl_rx_init(priv, rxq);
221
222 spin_lock_irqsave(&priv->lock, flags);
223
224 rxq->need_update = 1;
225 iwl_rx_queue_update_write_ptr(priv, rxq);
226
227 spin_unlock_irqrestore(&priv->lock, flags);
228
229 /* Allocate and init all Tx and Command queues */
230 ret = iwl_txq_ctx_reset(priv);
231 if (ret)
232 return ret;
233
234 set_bit(STATUS_INIT, &priv->status);
235
236 return 0;
237}
238EXPORT_SYMBOL(iwl_hw_nic_init);
239
bf85ea4f 240/**
37deb2a0 241 * iwl_clear_stations_table - Clear the driver's station table
bf85ea4f
AK		 242 *
243 * NOTE: This does not clear or otherwise alter the device's station table.
244 */
37deb2a0 245void iwl_clear_stations_table(struct iwl_priv *priv)
bf85ea4f
AK		 246{
247 unsigned long flags;
248
249 spin_lock_irqsave(&priv->sta_lock, flags);
250
24e5c401 251 if (iwl_is_alive(priv) &&
37deb2a0
EG		 252 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
253 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
24e5c401
EG		 254 IWL_ERROR("Couldn't clear the station table\n");
255
37deb2a0 256 priv->num_stations = 0;
bf85ea4f
AK		 257 memset(priv->stations, 0, sizeof(priv->stations));
258
259 spin_unlock_irqrestore(&priv->sta_lock, flags);
260}
37deb2a0 261EXPORT_SYMBOL(iwl_clear_stations_table);
bf85ea4f 262
c7de35cd 263void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 264{
265 u16 cw_min = 15;
266 u16 cw_max = 1023;
267 u8 aifs = 2;
268 u8 is_legacy = 0;
269 unsigned long flags;
270 int i;
271
272 spin_lock_irqsave(&priv->lock, flags);
273 priv->qos_data.qos_active = 0;
274
05c914fe 275 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
bf85ea4f
AK		 276 if (priv->qos_data.qos_enable)
277 priv->qos_data.qos_active = 1;
278 if (!(priv->active_rate & 0xfff0)) {
279 cw_min = 31;
280 is_legacy = 1;
281 }
05c914fe 282 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
bf85ea4f
AK		 283 if (priv->qos_data.qos_enable)
284 priv->qos_data.qos_active = 1;
285 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
286 cw_min = 31;
287 is_legacy = 1;
288 }
289
290 if (priv->qos_data.qos_active)
291 aifs = 3;
292
293 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
294 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
295 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
296 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
297 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
298
299 if (priv->qos_data.qos_active) {
300 i = 1;
301 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
302 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
303 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
304 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
305 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
306
307 i = 2;
308 priv->qos_data.def_qos_parm.ac[i].cw_min =
309 cpu_to_le16((cw_min + 1) / 2 - 1);
310 priv->qos_data.def_qos_parm.ac[i].cw_max =
311 cpu_to_le16(cw_max);
312 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
313 if (is_legacy)
314 priv->qos_data.def_qos_parm.ac[i].edca_txop =
315 cpu_to_le16(6016);
316 else
317 priv->qos_data.def_qos_parm.ac[i].edca_txop =
318 cpu_to_le16(3008);
319 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
320
321 i = 3;
322 priv->qos_data.def_qos_parm.ac[i].cw_min =
323 cpu_to_le16((cw_min + 1) / 4 - 1);
324 priv->qos_data.def_qos_parm.ac[i].cw_max =
325 cpu_to_le16((cw_max + 1) / 2 - 1);
326 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
327 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
328 if (is_legacy)
329 priv->qos_data.def_qos_parm.ac[i].edca_txop =
330 cpu_to_le16(3264);
331 else
332 priv->qos_data.def_qos_parm.ac[i].edca_txop =
333 cpu_to_le16(1504);
334 } else {
335 for (i = 1; i < 4; i++) {
336 priv->qos_data.def_qos_parm.ac[i].cw_min =
337 cpu_to_le16(cw_min);
338 priv->qos_data.def_qos_parm.ac[i].cw_max =
339 cpu_to_le16(cw_max);
340 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
341 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
342 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
343 }
344 }
345 IWL_DEBUG_QOS("set QoS to default \n");
346
347 spin_unlock_irqrestore(&priv->lock, flags);
348}
c7de35cd
RR		 349EXPORT_SYMBOL(iwl_reset_qos);
350
d9fe60de
JB		 351#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
352#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 353static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 354 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 355 enum ieee80211_band band)
356{
39130df3
RR		 357 u16 max_bit_rate = 0;
358 u8 rx_chains_num = priv->hw_params.rx_chains_num;
359 u8 tx_chains_num = priv->hw_params.tx_chains_num;
360
c7de35cd 361 ht_info->cap = 0;
d9fe60de 362 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 363
d9fe60de 364 ht_info->ht_supported = true;
c7de35cd 365
d9fe60de
JB		 366 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
367 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
368 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 369 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 370
371 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 372 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 373 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
374 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
375 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 376 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 377 }
c7de35cd
RR		 378
379 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 380 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 381
382 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
383 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
384
d9fe60de 385 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 386 if (rx_chains_num >= 2)
d9fe60de 387 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 388 if (rx_chains_num >= 3)
d9fe60de 389 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 390
391 /* Highest supported Rx data rate */
392 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 393 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
394 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 395
396 /* Tx MCS capabilities */
d9fe60de 397 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 398 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 399 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
400 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
401 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 402 }
c7de35cd 403}
c7de35cd
RR		 404
405static void iwlcore_init_hw_rates(struct iwl_priv *priv,
406 struct ieee80211_rate *rates)
407{
408 int i;
409
410 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 411 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 412 rates[i].hw_value = i; /* Rate scaling will work on indexes */
413 rates[i].hw_value_short = i;
414 rates[i].flags = 0;
415 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
416 /*
417 * If CCK != 1M then set short preamble rate flag.
418 */
419 rates[i].flags |=
1826dcc0 420 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 421 0 : IEEE80211_RATE_SHORT_PREAMBLE;
422 }
423 }
424}
425
426/**
427 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
428 */
429static int iwlcore_init_geos(struct iwl_priv *priv)
430{
431 struct iwl_channel_info *ch;
432 struct ieee80211_supported_band *sband;
433 struct ieee80211_channel *channels;
434 struct ieee80211_channel *geo_ch;
435 struct ieee80211_rate *rates;
436 int i = 0;
437
438 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
439 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
440 IWL_DEBUG_INFO("Geography modes already initialized.\n");
441 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
442 return 0;
443 }
444
445 channels = kzalloc(sizeof(struct ieee80211_channel) *
446 priv->channel_count, GFP_KERNEL);
447 if (!channels)
448 return -ENOMEM;
449
450 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
451 GFP_KERNEL);
452 if (!rates) {
453 kfree(channels);
454 return -ENOMEM;
455 }
456
457 /* 5.2GHz channels start after the 2.4GHz channels */
458 sband = &priv->bands[IEEE80211_BAND_5GHZ];
459 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
460 /* just OFDM */
461 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
462 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
463
49779293 464 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 465 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 466 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 467
468 sband = &priv->bands[IEEE80211_BAND_2GHZ];
469 sband->channels = channels;
470 /* OFDM & CCK */
471 sband->bitrates = rates;
472 sband->n_bitrates = IWL_RATE_COUNT;
473
49779293 474 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 475 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 476 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 477
478 priv->ieee_channels = channels;
479 priv->ieee_rates = rates;
480
481 iwlcore_init_hw_rates(priv, rates);
482
483 for (i = 0; i < priv->channel_count; i++) {
484 ch = &priv->channel_info[i];
485
486 /* FIXME: might be removed if scan is OK */
487 if (!is_channel_valid(ch))
488 continue;
489
490 if (is_channel_a_band(ch))
491 sband = &priv->bands[IEEE80211_BAND_5GHZ];
492 else
493 sband = &priv->bands[IEEE80211_BAND_2GHZ];
494
495 geo_ch = &sband->channels[sband->n_channels++];
496
497 geo_ch->center_freq =
498 ieee80211_channel_to_frequency(ch->channel);
499 geo_ch->max_power = ch->max_power_avg;
500 geo_ch->max_antenna_gain = 0xff;
501 geo_ch->hw_value = ch->channel;
502
503 if (is_channel_valid(ch)) {
504 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
505 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
506
507 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
508 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
509
510 if (ch->flags & EEPROM_CHANNEL_RADAR)
511 geo_ch->flags |= IEEE80211_CHAN_RADAR;
512
963f5517 513 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 514
630fe9b6
TW		 515 if (ch->max_power_avg > priv->tx_power_channel_lmt)
516 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 517 } else {
518 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
519 }
520
521 /* Save flags for reg domain usage */
522 geo_ch->orig_flags = geo_ch->flags;
523
963f5517 524 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 525 ch->channel, geo_ch->center_freq,
526 is_channel_a_band(ch) ? "5.2" : "2.4",
527 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
528 "restricted" : "valid",
529 geo_ch->flags);
530 }
531
532 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
533 priv->cfg->sku & IWL_SKU_A) {
534 printk(KERN_INFO DRV_NAME
535 ": Incorrectly detected BG card as ABG. Please send "
536 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
537 priv->pci_dev->device, priv->pci_dev->subsystem_device);
538 priv->cfg->sku &= ~IWL_SKU_A;
539 }
540
541 printk(KERN_INFO DRV_NAME
542 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
543 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
544 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
545
c7de35cd
RR		 546
547 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
548
549 return 0;
550}
551
552/*
553 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
554 */
6ba87956 555static void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 556{
557 kfree(priv->ieee_channels);
558 kfree(priv->ieee_rates);
559 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
560}
c7de35cd 561
28a6b07a 562static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 563{
564 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 565 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
566 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 567}
963f5517 568
47c5196e
TW		 569static u8 iwl_is_channel_extension(struct iwl_priv *priv,
570 enum ieee80211_band band,
571 u16 channel, u8 extension_chan_offset)
572{
573 const struct iwl_channel_info *ch_info;
574
575 ch_info = iwl_get_channel_info(priv, band, channel);
576 if (!is_channel_valid(ch_info))
577 return 0;
578
d9fe60de 579 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517
EG		 580 return !(ch_info->fat_extension_channel &
581 IEEE80211_CHAN_NO_FAT_ABOVE);
d9fe60de 582 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517
EG		 583 return !(ch_info->fat_extension_channel &
584 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 585
586 return 0;
587}
588
589u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 590 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 591{
592 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
593
594 if ((!iwl_ht_conf->is_ht) ||
595 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
d9fe60de 596 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
47c5196e
TW		 597 return 0;
598
599 if (sta_ht_inf) {
600 if ((!sta_ht_inf->ht_supported) ||
d9fe60de 601 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
47c5196e
TW		 602 return 0;
603 }
604
605 return iwl_is_channel_extension(priv, priv->band,
ae5eb026
JB		 606 le16_to_cpu(priv->staging_rxon.channel),
607 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 608}
609EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
610
611void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
612{
c1adf9fb 613 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 614 u32 val;
615
42eb7c64
EG		 616 if (!ht_info->is_ht) {
617 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
618 RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
619 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
620 RXON_FLG_FAT_PROT_MSK |
621 RXON_FLG_HT_PROT_MSK);
47c5196e 622 return;
42eb7c64 623 }
47c5196e
TW		 624
625 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
626 if (iwl_is_fat_tx_allowed(priv, NULL))
627 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
628 else
629 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
630 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
631
47c5196e
TW		 632 /* Note: control channel is opposite of extension channel */
633 switch (ht_info->extension_chan_offset) {
d9fe60de 634 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
47c5196e
TW		 635 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
636 break;
d9fe60de 637 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
47c5196e
TW		 638 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
639 break;
d9fe60de 640 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
47c5196e
TW		 641 default:
642 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
643 break;
644 }
645
646 val = ht_info->ht_protection;
647
648 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
649
650 iwl_set_rxon_chain(priv);
651
652 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
653 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 654 "extension channel offset 0x%x\n",
d9fe60de
JB		 655 ht_info->mcs.rx_mask[0],
656 ht_info->mcs.rx_mask[1],
657 ht_info->mcs.rx_mask[2],
47c5196e 658 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 659 ht_info->extension_chan_offset);
47c5196e
TW		 660 return;
661}
662EXPORT_SYMBOL(iwl_set_rxon_ht);
663
9e5e6c32
TW		 664#define IWL_NUM_RX_CHAINS_MULTIPLE 3
665#define IWL_NUM_RX_CHAINS_SINGLE 2
666#define IWL_NUM_IDLE_CHAINS_DUAL 2
667#define IWL_NUM_IDLE_CHAINS_SINGLE 1
668
669/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 670 * More provides better reception via diversity. Fewer saves power.
671 * MIMO (dual stream) requires at least 2, but works better with 3.
672 * This does not determine *which* chains to use, just how many.
673 */
28a6b07a 674static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 675{
28a6b07a
TW		 676 bool is_single = is_single_rx_stream(priv);
677 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 678
679 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 680 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
681 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 682 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 683 else
9e5e6c32 684 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 685}
c7de35cd 686
28a6b07a
TW		 687static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
688{
689 int idle_cnt;
690 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 691 /* # Rx chains when idling and maybe trying to save power */
12837be1 692 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 693 case WLAN_HT_CAP_SM_PS_STATIC:
694 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 695 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
696 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 697 break;
00c5ae2f 698 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 699 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 700 break;
00c5ae2f 701 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 702 default:
a96a27f9 703 IWL_ERROR("invalid mimo ps mode %d\n",
12837be1 704 priv->current_ht_config.sm_ps);
28a6b07a
TW		 705 WARN_ON(1);
706 idle_cnt = -1;
c7de35cd
RR		 707 break;
708 }
28a6b07a 709 return idle_cnt;
c7de35cd
RR		 710}
711
04816448
GE		 712/* up to 4 chains */
713static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
714{
715 u8 res;
716 res = (chain_bitmap & BIT(0)) >> 0;
717 res += (chain_bitmap & BIT(1)) >> 1;
718 res += (chain_bitmap & BIT(2)) >> 2;
719 res += (chain_bitmap & BIT(4)) >> 4;
720 return res;
721}
722
c7de35cd
RR		 723/**
724 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
725 *
726 * Selects how many and which Rx receivers/antennas/chains to use.
727 * This should not be used for scan command ... it puts data in wrong place.
728 */
729void iwl_set_rxon_chain(struct iwl_priv *priv)
730{
28a6b07a
TW		 731 bool is_single = is_single_rx_stream(priv);
732 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 733 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
734 u32 active_chains;
28a6b07a 735 u16 rx_chain;
c7de35cd
RR		 736
737 /* Tell uCode which antennas are actually connected.
738 * Before first association, we assume all antennas are connected.
739 * Just after first association, iwl_chain_noise_calibration()
740 * checks which antennas actually *are* connected. */
04816448
GE		 741 if (priv->chain_noise_data.active_chains)
742 active_chains = priv->chain_noise_data.active_chains;
743 else
744 active_chains = priv->hw_params.valid_rx_ant;
745
746 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 747
748 /* How many receivers should we use? */
28a6b07a
TW		 749 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
750 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
751
28a6b07a 752
04816448
GE		 753 /* correct rx chain count according hw settings
754 * and chain noise calibration
755 */
756 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
757 if (valid_rx_cnt < active_rx_cnt)
758 active_rx_cnt = valid_rx_cnt;
759
760 if (valid_rx_cnt < idle_rx_cnt)
761 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 762
763 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
764 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
765
766 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
767
9e5e6c32 768 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 769 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
770 else
771 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
772
a33c2f47 773 IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 774 priv->staging_rxon.rx_chain,
775 active_rx_cnt, idle_rx_cnt);
776
777 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
778 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 779}
780EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 781
782/**
17e72782 783 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 784 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
785 * @channel: Any channel valid for the requested phymode
786
787 * In addition to setting the staging RXON, priv->phymode is also set.
788 *
789 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
790 * in the staging RXON flag structure based on the phymode
791 */
17e72782 792int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 793{
17e72782
TW		 794 enum ieee80211_band band = ch->band;
795 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
796
8622e705 797 if (!iwl_get_channel_info(priv, band, channel)) {
bf85ea4f
AK		 798 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
799 channel, band);
800 return -EINVAL;
801 }
802
803 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
804 (priv->band == band))
805 return 0;
806
807 priv->staging_rxon.channel = cpu_to_le16(channel);
808 if (band == IEEE80211_BAND_5GHZ)
809 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
810 else
811 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
812
813 priv->band = band;
814
815 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
816
817 return 0;
818}
c7de35cd 819EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 820
6ba87956 821int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 822{
6ba87956 823 int ret;
bf85ea4f 824 struct ieee80211_hw *hw = priv->hw;
e227ceac 825 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 826
566bfe5a 827 /* Tell mac80211 our characteristics */
605a0bd6 828 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe
S		 829 IEEE80211_HW_NOISE_DBM |
830 IEEE80211_HW_AMPDU_AGGREGATION;
f59ac048
LR		 831 hw->wiphy->interface_modes =
832 BIT(NL80211_IFTYPE_AP) |
833 BIT(NL80211_IFTYPE_STATION) |
834 BIT(NL80211_IFTYPE_ADHOC);
bf85ea4f
AK		 835 /* Default value; 4 EDCA QOS priorities */
836 hw->queues = 4;
49779293
RR		 837 /* queues to support 11n aggregation */
838 if (priv->cfg->sku & IWL_SKU_N)
9f17b318 839 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
6ba87956
TW		 840
841 hw->conf.beacon_int = 100;
b5d7be5e 842 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 843
844 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
845 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
846 &priv->bands[IEEE80211_BAND_2GHZ];
847 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
848 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
849 &priv->bands[IEEE80211_BAND_5GHZ];
850
851 ret = ieee80211_register_hw(priv->hw);
852 if (ret) {
853 IWL_ERROR("Failed to register hw (error %d)\n", ret);
854 return ret;
855 }
856 priv->mac80211_registered = 1;
857
858 return 0;
bf85ea4f 859}
6ba87956 860EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 861
da154e30
RR		 862int iwl_set_hw_params(struct iwl_priv *priv)
863{
864 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
865 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
866 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
867 if (priv->cfg->mod_params->amsdu_size_8K)
868 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
869 else
870 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
871 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
872
49779293
RR		 873 if (priv->cfg->mod_params->disable_11n)
874 priv->cfg->sku &= ~IWL_SKU_N;
875
da154e30
RR		 876 /* Device-specific setup */
877 return priv->cfg->ops->lib->set_hw_params(priv);
878}
879EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 880
881int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 882{
883 int ret;
c7de35cd
RR		 884
885 priv->retry_rate = 1;
886 priv->ibss_beacon = NULL;
887
888 spin_lock_init(&priv->lock);
889 spin_lock_init(&priv->power_data.lock);
890 spin_lock_init(&priv->sta_lock);
891 spin_lock_init(&priv->hcmd_lock);
c7de35cd 892
c7de35cd
RR		 893 INIT_LIST_HEAD(&priv->free_frames);
894
895 mutex_init(&priv->mutex);
896
897 /* Clear the driver's (not device's) station table */
37deb2a0 898 iwl_clear_stations_table(priv);
c7de35cd
RR		 899
900 priv->data_retry_limit = -1;
901 priv->ieee_channels = NULL;
902 priv->ieee_rates = NULL;
903 priv->band = IEEE80211_BAND_2GHZ;
904
05c914fe 905 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 906
12837be1 907 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 908
909 /* Choose which receivers/antennas to use */
910 iwl_set_rxon_chain(priv);
f53696de 911 iwl_init_scan_params(priv);
c7de35cd 912
6ba87956
TW		 913 if (priv->cfg->mod_params->enable_qos)
914 priv->qos_data.qos_enable = 1;
915
c7de35cd
RR		 916 iwl_reset_qos(priv);
917
918 priv->qos_data.qos_active = 0;
919 priv->qos_data.qos_cap.val = 0;
920
c7de35cd
RR		 921 priv->rates_mask = IWL_RATES_MASK;
922 /* If power management is turned on, default to AC mode */
923 priv->power_mode = IWL_POWER_AC;
630fe9b6 924 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 925
926 ret = iwl_init_channel_map(priv);
927 if (ret) {
928 IWL_ERROR("initializing regulatory failed: %d\n", ret);
929 goto err;
930 }
931
932 ret = iwlcore_init_geos(priv);
933 if (ret) {
934 IWL_ERROR("initializing geos failed: %d\n", ret);
935 goto err_free_channel_map;
936 }
937
c7de35cd
RR		 938 return 0;
939
c7de35cd
RR		 940err_free_channel_map:
941 iwl_free_channel_map(priv);
942err:
943 return ret;
944}
6ba87956 945EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 946
630fe9b6
TW		 947int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
948{
949 int ret = 0;
950 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
951 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
952 priv->tx_power_user_lmt);
953 return -EINVAL;
954 }
955
956 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
957 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
958 priv->tx_power_user_lmt);
959 return -EINVAL;
960 }
961
962 if (priv->tx_power_user_lmt != tx_power)
963 force = true;
964
965 priv->tx_power_user_lmt = tx_power;
966
967 if (force && priv->cfg->ops->lib->send_tx_power)
968 ret = priv->cfg->ops->lib->send_tx_power(priv);
969
970 return ret;
971}
972EXPORT_SYMBOL(iwl_set_tx_power);
973
6ba87956 974void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 975{
6e21f2c1 976 iwl_calib_free_results(priv);
6ba87956
TW		 977 iwlcore_free_geos(priv);
978 iwl_free_channel_map(priv);
261415f7 979 kfree(priv->scan);
bf85ea4f 980}
6ba87956 981EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 982
49ea8596
EG		 983int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
984{
985 u32 stat_flags = 0;
986 struct iwl_host_cmd cmd = {
987 .id = REPLY_STATISTICS_CMD,
988 .meta.flags = flags,
989 .len = sizeof(stat_flags),
990 .data = (u8 *) &stat_flags,
991 };
992 return iwl_send_cmd(priv, &cmd);
993}
994EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 995
b0692f2f
EG		 996/**
997 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
998 * using sample data 100 bytes apart. If these sample points are good,
999 * it's a pretty good bet that everything between them is good, too.
1000 */
1001static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1002{
1003 u32 val;
1004 int ret = 0;
1005 u32 errcnt = 0;
1006 u32 i;
1007
1008 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1009
1010 ret = iwl_grab_nic_access(priv);
1011 if (ret)
1012 return ret;
1013
1014 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1015 /* read data comes through single port, auto-incr addr */
1016 /* NOTE: Use the debugless read so we don't flood kernel log
1017 * if IWL_DL_IO is set */
1018 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1019 i + RTC_INST_LOWER_BOUND);
1020 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1021 if (val != le32_to_cpu(*image)) {
1022 ret = -EIO;
1023 errcnt++;
1024 if (errcnt >= 3)
1025 break;
1026 }
1027 }
1028
1029 iwl_release_nic_access(priv);
1030
1031 return ret;
1032}
1033
1034/**
1035 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1036 * looking at all data.
1037 */
1038static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1039 u32 len)
1040{
1041 u32 val;
1042 u32 save_len = len;
1043 int ret = 0;
1044 u32 errcnt;
1045
1046 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1047
1048 ret = iwl_grab_nic_access(priv);
1049 if (ret)
1050 return ret;
1051
1052 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1053
1054 errcnt = 0;
1055 for (; len > 0; len -= sizeof(u32), image++) {
1056 /* read data comes through single port, auto-incr addr */
1057 /* NOTE: Use the debugless read so we don't flood kernel log
1058 * if IWL_DL_IO is set */
1059 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1060 if (val != le32_to_cpu(*image)) {
1061 IWL_ERROR("uCode INST section is invalid at "
1062 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1063 save_len - len, val, le32_to_cpu(*image));
1064 ret = -EIO;
1065 errcnt++;
1066 if (errcnt >= 20)
1067 break;
1068 }
1069 }
1070
1071 iwl_release_nic_access(priv);
1072
1073 if (!errcnt)
1074 IWL_DEBUG_INFO
1075 ("ucode image in INSTRUCTION memory is good\n");
1076
1077 return ret;
1078}
1079
1080/**
1081 * iwl_verify_ucode - determine which instruction image is in SRAM,
1082 * and verify its contents
1083 */
1084int iwl_verify_ucode(struct iwl_priv *priv)
1085{
1086 __le32 *image;
1087 u32 len;
1088 int ret;
1089
1090 /* Try bootstrap */
1091 image = (__le32 *)priv->ucode_boot.v_addr;
1092 len = priv->ucode_boot.len;
1093 ret = iwlcore_verify_inst_sparse(priv, image, len);
1094 if (!ret) {
1095 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1096 return 0;
1097 }
1098
1099 /* Try initialize */
1100 image = (__le32 *)priv->ucode_init.v_addr;
1101 len = priv->ucode_init.len;
1102 ret = iwlcore_verify_inst_sparse(priv, image, len);
1103 if (!ret) {
1104 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1105 return 0;
1106 }
1107
1108 /* Try runtime/protocol */
1109 image = (__le32 *)priv->ucode_code.v_addr;
1110 len = priv->ucode_code.len;
1111 ret = iwlcore_verify_inst_sparse(priv, image, len);
1112 if (!ret) {
1113 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1114 return 0;
1115 }
1116
1117 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1118
1119 /* Since nothing seems to match, show first several data entries in
1120 * instruction SRAM, so maybe visual inspection will give a clue.
1121 * Selection of bootstrap image (vs. other images) is arbitrary. */
1122 image = (__le32 *)priv->ucode_boot.v_addr;
1123 len = priv->ucode_boot.len;
1124 ret = iwl_verify_inst_full(priv, image, len);
1125
1126 return ret;
1127}
1128EXPORT_SYMBOL(iwl_verify_ucode);
1129
56e12615
JS		 1130
1131static const char *desc_lookup_text[] = {
1132 "OK",
1133 "FAIL",
1134 "BAD_PARAM",
1135 "BAD_CHECKSUM",
1136 "NMI_INTERRUPT_WDG",
1137 "SYSASSERT",
1138 "FATAL_ERROR",
1139 "BAD_COMMAND",
1140 "HW_ERROR_TUNE_LOCK",
1141 "HW_ERROR_TEMPERATURE",
1142 "ILLEGAL_CHAN_FREQ",
1143 "VCC_NOT_STABLE",
1144 "FH_ERROR",
1145 "NMI_INTERRUPT_HOST",
1146 "NMI_INTERRUPT_ACTION_PT",
1147 "NMI_INTERRUPT_UNKNOWN",
1148 "UCODE_VERSION_MISMATCH",
1149 "HW_ERROR_ABS_LOCK",
1150 "HW_ERROR_CAL_LOCK_FAIL",
1151 "NMI_INTERRUPT_INST_ACTION_PT",
1152 "NMI_INTERRUPT_DATA_ACTION_PT",
1153 "NMI_TRM_HW_ER",
1154 "NMI_INTERRUPT_TRM",
1155 "NMI_INTERRUPT_BREAK_POINT"
1156 "DEBUG_0",
1157 "DEBUG_1",
1158 "DEBUG_2",
1159 "DEBUG_3",
1160 "UNKNOWN"
1161};
1162
ede0cba4
EK		 1163static const char *desc_lookup(int i)
1164{
56e12615
JS		 1165 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1166
1167 if (i < 0 || i > max)
1168 i = max;
ede0cba4 1169
56e12615 1170 return desc_lookup_text[i];
ede0cba4
EK		 1171}
1172
1173#define ERROR_START_OFFSET (1 * sizeof(u32))
1174#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1175
1176void iwl_dump_nic_error_log(struct iwl_priv *priv)
1177{
1178 u32 data2, line;
1179 u32 desc, time, count, base, data1;
1180 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1181 int ret;
ede0cba4 1182
e1dfc085
GG		 1183 if (priv->ucode_type == UCODE_INIT)
1184 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1185 else
1186 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1187
1188 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1189 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1190 return;
1191 }
1192
e1dfc085
GG		 1193 ret = iwl_grab_nic_access(priv);
1194 if (ret) {
ede0cba4
EK		 1195 IWL_WARNING("Can not read from adapter at this time.\n");
1196 return;
1197 }
1198
1199 count = iwl_read_targ_mem(priv, base);
1200
1201 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1202 IWL_ERROR("Start IWL Error Log Dump:\n");
1203 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1204 }
1205
1206 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1207 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1208 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1209 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1210 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1211 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1212 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1213 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1214 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1215
56e12615 1216 IWL_ERROR("Desc Time "
ede0cba4 1217 "data1 data2 line\n");
56e12615 1218 IWL_ERROR("%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
ede0cba4
EK		 1219 desc_lookup(desc), desc, time, data1, data2, line);
1220 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1221 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1222 ilink1, ilink2);
1223
1224 iwl_release_nic_access(priv);
1225}
1226EXPORT_SYMBOL(iwl_dump_nic_error_log);
1227
189a2b59
EK		 1228#define EVENT_START_OFFSET (4 * sizeof(u32))
1229
1230/**
1231 * iwl_print_event_log - Dump error event log to syslog
1232 *
a33c2f47 1233 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
189a2b59 1234 */
a33c2f47 1235static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 1236 u32 num_events, u32 mode)
1237{
1238 u32 i;
1239 u32 base; /* SRAM byte address of event log header */
1240 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1241 u32 ptr; /* SRAM byte address of log data */
1242 u32 ev, time, data; /* event log data */
1243
1244 if (num_events == 0)
1245 return;
e1dfc085
GG		 1246 if (priv->ucode_type == UCODE_INIT)
1247 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1248 else
1249 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1250
1251 if (mode == 0)
1252 event_size = 2 * sizeof(u32);
1253 else
1254 event_size = 3 * sizeof(u32);
1255
1256 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1257
1258 /* "time" is actually "data" for mode 0 (no timestamp).
1259 * place event id # at far right for easier visual parsing. */
1260 for (i = 0; i < num_events; i++) {
1261 ev = iwl_read_targ_mem(priv, ptr);
1262 ptr += sizeof(u32);
1263 time = iwl_read_targ_mem(priv, ptr);
1264 ptr += sizeof(u32);
77c5d08e
TW		 1265 if (mode == 0) {
1266 /* data, ev */
1267 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1268 } else {
189a2b59
EK		 1269 data = iwl_read_targ_mem(priv, ptr);
1270 ptr += sizeof(u32);
77c5d08e
TW		 1271 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1272 time, data, ev);
189a2b59
EK		 1273 }
1274 }
1275}
189a2b59
EK		 1276
1277void iwl_dump_nic_event_log(struct iwl_priv *priv)
1278{
e1dfc085 1279 int ret;
189a2b59
EK		 1280 u32 base; /* SRAM byte address of event log header */
1281 u32 capacity; /* event log capacity in # entries */
1282 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1283 u32 num_wraps; /* # times uCode wrapped to top of log */
1284 u32 next_entry; /* index of next entry to be written by uCode */
1285 u32 size; /* # entries that we'll print */
1286
e1dfc085
GG		 1287 if (priv->ucode_type == UCODE_INIT)
1288 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1289 else
1290 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1291
189a2b59
EK		 1292 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1293 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1294 return;
1295 }
1296
e1dfc085
GG		 1297 ret = iwl_grab_nic_access(priv);
1298 if (ret) {
189a2b59
EK		 1299 IWL_WARNING("Can not read from adapter at this time.\n");
1300 return;
1301 }
1302
1303 /* event log header */
1304 capacity = iwl_read_targ_mem(priv, base);
1305 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1306 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1307 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1308
1309 size = num_wraps ? capacity : next_entry;
1310
1311 /* bail out if nothing in log */
1312 if (size == 0) {
1313 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1314 iwl_release_nic_access(priv);
1315 return;
1316 }
1317
1318 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1319 size, num_wraps);
1320
1321 /* if uCode has wrapped back to top of log, start at the oldest entry,
1322 * i.e the next one that uCode would fill. */
1323 if (num_wraps)
1324 iwl_print_event_log(priv, next_entry,
1325 capacity - next_entry, mode);
1326 /* (then/else) start at top of log */
1327 iwl_print_event_log(priv, 0, next_entry, mode);
1328
1329 iwl_release_nic_access(priv);
1330}
1331EXPORT_SYMBOL(iwl_dump_nic_event_log);
1332
47f4a587
EG		 1333void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1334{
1335 struct iwl_ct_kill_config cmd;
1336 unsigned long flags;
1337 int ret = 0;
1338
1339 spin_lock_irqsave(&priv->lock, flags);
1340 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1341 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1342 spin_unlock_irqrestore(&priv->lock, flags);
1343
1344 cmd.critical_temperature_R =
1345 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1346
47f4a587
EG		 1347 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1348 sizeof(cmd), &cmd);
1349 if (ret)
1350 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1351 else
1352 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1353 "critical temperature is %d\n",
1354 cmd.critical_temperature_R);
1355}
1356EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f
EG		 1357
1358/*
1359 * CARD_STATE_CMD
1360 *
1361 * Use: Sets the device's internal card state to enable, disable, or halt
1362 *
1363 * When in the 'enable' state the card operates as normal.
1364 * When in the 'disable' state, the card enters into a low power mode.
1365 * When in the 'halt' state, the card is shut down and must be fully
1366 * restarted to come back on.
1367 */
1368static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1369{
1370 struct iwl_host_cmd cmd = {
1371 .id = REPLY_CARD_STATE_CMD,
1372 .len = sizeof(u32),
1373 .data = &flags,
1374 .meta.flags = meta_flag,
1375 };
1376
1377 return iwl_send_cmd(priv, &cmd);
1378}
1379
1380void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1381{
1382 unsigned long flags;
1383
1384 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1385 return;
1386
1387 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1388
1389 iwl_scan_cancel(priv);
1390 /* FIXME: This is a workaround for AP */
05c914fe 1391 if (priv->iw_mode != NL80211_IFTYPE_AP) {
14a08a7f
EG		 1392 spin_lock_irqsave(&priv->lock, flags);
1393 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1394 CSR_UCODE_SW_BIT_RFKILL);
1395 spin_unlock_irqrestore(&priv->lock, flags);
1396 /* call the host command only if no hw rf-kill set */
1397 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1398 iwl_is_ready(priv))
1399 iwl_send_card_state(priv,
1400 CARD_STATE_CMD_DISABLE, 0);
1401 set_bit(STATUS_RF_KILL_SW, &priv->status);
1402 /* make sure mac80211 stop sending Tx frame */
1403 if (priv->mac80211_registered)
1404 ieee80211_stop_queues(priv->hw);
1405 }
1406}
1407EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1408
1409int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1410{
1411 unsigned long flags;
1412
1413 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1414 return 0;
1415
1416 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1417
1418 spin_lock_irqsave(&priv->lock, flags);
1419 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1420
a9efa652
EG		 1421 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1422 * notification where it will clear SW rfkill status.
1423 * Setting it here would break the handler. Only if the
1424 * interface is down we can set here since we don't
1425 * receive any further notification.
1426 */
1427 if (!priv->is_open)
1428 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 1429 spin_unlock_irqrestore(&priv->lock, flags);
1430
1431 /* wake up ucode */
1432 msleep(10);
1433
1434 spin_lock_irqsave(&priv->lock, flags);
1435 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1436 if (!iwl_grab_nic_access(priv))
1437 iwl_release_nic_access(priv);
1438 spin_unlock_irqrestore(&priv->lock, flags);
1439
1440 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1441 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1442 "disabled by HW switch\n");
1443 return 0;
1444 }
1445
a9efa652
EG		 1446 /* If the driver is already loaded, it will receive
1447 * CARD_STATE_NOTIFICATION notifications and the handler will
1448 * call restart to reload the driver.
1449 */
14a08a7f
EG		 1450 return 1;
1451}
1452EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
Linux kernel - Deliverables
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