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iwmc3200wifi: remove B0 hardware support
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
ef850d7c
MA		 62static irqreturn_t iwl_isr(int irq, void *data);
63
c7de35cd
RR		 64/*
65 * Parameter order:
66 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
67 *
68 * If there isn't a valid next or previous rate then INV is used which
69 * maps to IWL_RATE_INVALID
70 *
71 */
1826dcc0 72const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 73 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
74 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
75 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
76 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
77 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
78 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
79 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
80 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
81 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
82 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
83 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
84 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
85 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
86 /* FIXME:RS: ^^ should be INV (legacy) */
87};
1826dcc0 88EXPORT_SYMBOL(iwl_rates);
c7de35cd 89
e7d326ac
TW		 90/**
91 * translate ucode response to mac80211 tx status control values
92 */
93void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 94 struct ieee80211_tx_info *info)
e7d326ac
TW		 95{
96 int rate_index;
e6a9854b 97 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 98
e6a9854b 99 info->antenna_sel_tx =
e7d326ac
TW		 100 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
101 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 102 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 103 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 104 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
e7d326ac 105 if (rate_n_flags & RATE_MCS_FAT_MSK)
e6a9854b 106 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 107 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 108 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 109 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 110 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 111 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 112 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 113 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 114 r->idx = rate_index;
e7d326ac
TW		 115}
116EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
117
118int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
119{
120 int idx = 0;
121
122 /* HT rate format */
123 if (rate_n_flags & RATE_MCS_HT_MSK) {
124 idx = (rate_n_flags & 0xff);
125
60d32215
DH		 126 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
127 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
128 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 129 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
130
131 idx += IWL_FIRST_OFDM_RATE;
132 /* skip 9M not supported in ht*/
133 if (idx >= IWL_RATE_9M_INDEX)
134 idx += 1;
135 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
136 return idx;
137
138 /* legacy rate format, search for match in table */
139 } else {
140 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
141 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
142 return idx;
143 }
144
145 return -1;
146}
147EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
148
76eff18b
TW		 149u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
150{
151 int i;
152 u8 ind = ant;
153 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
154 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
155 if (priv->hw_params.valid_tx_ant & BIT(ind))
156 return ind;
157 }
158 return ant;
159}
57bd1bea
TW		 160
161const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
162EXPORT_SYMBOL(iwl_bcast_addr);
163
164
1d0a082d
AK		 165/* This function both allocates and initializes hw and priv. */
166struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
167 struct ieee80211_ops *hw_ops)
168{
169 struct iwl_priv *priv;
170
171 /* mac80211 allocates memory for this device instance, including
172 * space for this driver's private structure */
173 struct ieee80211_hw *hw =
174 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
175 if (hw == NULL) {
a3139c59
SO		 176 printk(KERN_ERR "%s: Can not allocate network device\n",
177 cfg->name);
1d0a082d
AK		 178 goto out;
179 }
180
181 priv = hw->priv;
182 priv->hw = hw;
183
184out:
185 return hw;
186}
187EXPORT_SYMBOL(iwl_alloc_all);
188
b661c819
TW		 189void iwl_hw_detect(struct iwl_priv *priv)
190{
191 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
192 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
193 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
194}
195EXPORT_SYMBOL(iwl_hw_detect);
196
1053d35f
RR		 197int iwl_hw_nic_init(struct iwl_priv *priv)
198{
199 unsigned long flags;
200 struct iwl_rx_queue *rxq = &priv->rxq;
201 int ret;
202
203 /* nic_init */
1053d35f 204 spin_lock_irqsave(&priv->lock, flags);
1b73af82 205 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 206 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
207 spin_unlock_irqrestore(&priv->lock, flags);
208
209 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
210
211 priv->cfg->ops->lib->apm_ops.config(priv);
212
213 /* Allocate the RX queue, or reset if it is already allocated */
214 if (!rxq->bd) {
215 ret = iwl_rx_queue_alloc(priv);
216 if (ret) {
15b1687c 217 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 218 return -ENOMEM;
219 }
220 } else
221 iwl_rx_queue_reset(priv, rxq);
222
223 iwl_rx_replenish(priv);
224
225 iwl_rx_init(priv, rxq);
226
227 spin_lock_irqsave(&priv->lock, flags);
228
229 rxq->need_update = 1;
230 iwl_rx_queue_update_write_ptr(priv, rxq);
231
232 spin_unlock_irqrestore(&priv->lock, flags);
233
234 /* Allocate and init all Tx and Command queues */
235 ret = iwl_txq_ctx_reset(priv);
236 if (ret)
237 return ret;
238
239 set_bit(STATUS_INIT, &priv->status);
240
241 return 0;
242}
243EXPORT_SYMBOL(iwl_hw_nic_init);
244
14d2aac5
AK		 245/*
246 * QoS support
247*/
248void iwl_activate_qos(struct iwl_priv *priv, u8 force)
249{
250 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
251 return;
252
253 priv->qos_data.def_qos_parm.qos_flags = 0;
254
255 if (priv->qos_data.qos_cap.q_AP.queue_request &&
256 !priv->qos_data.qos_cap.q_AP.txop_request)
257 priv->qos_data.def_qos_parm.qos_flags |=
258 QOS_PARAM_FLG_TXOP_TYPE_MSK;
259 if (priv->qos_data.qos_active)
260 priv->qos_data.def_qos_parm.qos_flags |=
261 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
262
263 if (priv->current_ht_config.is_ht)
264 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
265
266 if (force || iwl_is_associated(priv)) {
267 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
268 priv->qos_data.qos_active,
269 priv->qos_data.def_qos_parm.qos_flags);
270
271 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
272 sizeof(struct iwl_qosparam_cmd),
273 &priv->qos_data.def_qos_parm, NULL);
274 }
275}
276EXPORT_SYMBOL(iwl_activate_qos);
277
f2c95b04
WYG		 278/*
279 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
280 * (802.11b) (802.11a/g)
281 * AC_BK 15 1023 7 0 0
282 * AC_BE 15 1023 3 0 0
283 * AC_VI 7 15 2 6.016ms 3.008ms
284 * AC_VO 3 7 2 3.264ms 1.504ms
285 */
c7de35cd 286void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 287{
288 u16 cw_min = 15;
289 u16 cw_max = 1023;
290 u8 aifs = 2;
30dab79e 291 bool is_legacy = false;
bf85ea4f
AK		 292 unsigned long flags;
293 int i;
294
295 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 296 /* QoS always active in AP and ADHOC mode
297 * In STA mode wait for association
298 */
299 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
300 priv->iw_mode == NL80211_IFTYPE_AP)
301 priv->qos_data.qos_active = 1;
302 else
303 priv->qos_data.qos_active = 0;
bf85ea4f 304
30dab79e
WT		 305 /* check for legacy mode */
306 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
307 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
308 (priv->iw_mode == NL80211_IFTYPE_STATION &&
309 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 310 cw_min = 31;
311 is_legacy = 1;
312 }
313
314 if (priv->qos_data.qos_active)
315 aifs = 3;
316
f2c95b04 317 /* AC_BE */
bf85ea4f
AK		 318 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
319 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
320 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
321 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
322 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
323
324 if (priv->qos_data.qos_active) {
f2c95b04 325 /* AC_BK */
bf85ea4f
AK		 326 i = 1;
327 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
328 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
329 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
330 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
331 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
332
f2c95b04 333 /* AC_VI */
bf85ea4f
AK		 334 i = 2;
335 priv->qos_data.def_qos_parm.ac[i].cw_min =
336 cpu_to_le16((cw_min + 1) / 2 - 1);
337 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 338 cpu_to_le16(cw_min);
bf85ea4f
AK		 339 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
340 if (is_legacy)
341 priv->qos_data.def_qos_parm.ac[i].edca_txop =
342 cpu_to_le16(6016);
343 else
344 priv->qos_data.def_qos_parm.ac[i].edca_txop =
345 cpu_to_le16(3008);
346 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
347
f2c95b04 348 /* AC_VO */
bf85ea4f
AK		 349 i = 3;
350 priv->qos_data.def_qos_parm.ac[i].cw_min =
351 cpu_to_le16((cw_min + 1) / 4 - 1);
352 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 353 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 354 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
355 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
356 if (is_legacy)
357 priv->qos_data.def_qos_parm.ac[i].edca_txop =
358 cpu_to_le16(3264);
359 else
360 priv->qos_data.def_qos_parm.ac[i].edca_txop =
361 cpu_to_le16(1504);
362 } else {
363 for (i = 1; i < 4; i++) {
364 priv->qos_data.def_qos_parm.ac[i].cw_min =
365 cpu_to_le16(cw_min);
366 priv->qos_data.def_qos_parm.ac[i].cw_max =
367 cpu_to_le16(cw_max);
368 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
369 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
370 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
371 }
372 }
e1623446 373 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 374
375 spin_unlock_irqrestore(&priv->lock, flags);
376}
c7de35cd
RR		 377EXPORT_SYMBOL(iwl_reset_qos);
378
d9fe60de
JB		 379#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
380#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 381static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 382 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 383 enum ieee80211_band band)
384{
39130df3
RR		 385 u16 max_bit_rate = 0;
386 u8 rx_chains_num = priv->hw_params.rx_chains_num;
387 u8 tx_chains_num = priv->hw_params.tx_chains_num;
388
c7de35cd 389 ht_info->cap = 0;
d9fe60de 390 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 391
d9fe60de 392 ht_info->ht_supported = true;
c7de35cd 393
d9fe60de
JB		 394 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
395 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
396 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 397 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 398
399 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 400 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 401 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
402 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
403 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 404 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 405 }
c7de35cd
RR		 406
407 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 408 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 409
410 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
411 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
412
d9fe60de 413 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 414 if (rx_chains_num >= 2)
d9fe60de 415 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 416 if (rx_chains_num >= 3)
d9fe60de 417 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 418
419 /* Highest supported Rx data rate */
420 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 421 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
422 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 423
424 /* Tx MCS capabilities */
d9fe60de 425 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 426 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 427 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
428 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
429 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 430 }
c7de35cd 431}
c7de35cd
RR		 432
433static void iwlcore_init_hw_rates(struct iwl_priv *priv,
434 struct ieee80211_rate *rates)
435{
436 int i;
437
438 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 439 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 440 rates[i].hw_value = i; /* Rate scaling will work on indexes */
441 rates[i].hw_value_short = i;
442 rates[i].flags = 0;
443 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
444 /*
445 * If CCK != 1M then set short preamble rate flag.
446 */
447 rates[i].flags |=
1826dcc0 448 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 449 0 : IEEE80211_RATE_SHORT_PREAMBLE;
450 }
451 }
452}
453
8ccde88a 454
c7de35cd
RR		 455/**
456 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
457 */
534166de 458int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 459{
460 struct iwl_channel_info *ch;
461 struct ieee80211_supported_band *sband;
462 struct ieee80211_channel *channels;
463 struct ieee80211_channel *geo_ch;
464 struct ieee80211_rate *rates;
465 int i = 0;
466
467 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
468 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 469 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 470 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
471 return 0;
472 }
473
474 channels = kzalloc(sizeof(struct ieee80211_channel) *
475 priv->channel_count, GFP_KERNEL);
476 if (!channels)
477 return -ENOMEM;
478
479 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
480 GFP_KERNEL);
481 if (!rates) {
482 kfree(channels);
483 return -ENOMEM;
484 }
485
486 /* 5.2GHz channels start after the 2.4GHz channels */
487 sband = &priv->bands[IEEE80211_BAND_5GHZ];
488 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
489 /* just OFDM */
490 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
491 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
492
49779293 493 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 494 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 495 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 496
497 sband = &priv->bands[IEEE80211_BAND_2GHZ];
498 sband->channels = channels;
499 /* OFDM & CCK */
500 sband->bitrates = rates;
501 sband->n_bitrates = IWL_RATE_COUNT;
502
49779293 503 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 504 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 505 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 506
507 priv->ieee_channels = channels;
508 priv->ieee_rates = rates;
509
c7de35cd
RR		 510 for (i = 0; i < priv->channel_count; i++) {
511 ch = &priv->channel_info[i];
512
513 /* FIXME: might be removed if scan is OK */
514 if (!is_channel_valid(ch))
515 continue;
516
517 if (is_channel_a_band(ch))
518 sband = &priv->bands[IEEE80211_BAND_5GHZ];
519 else
520 sband = &priv->bands[IEEE80211_BAND_2GHZ];
521
522 geo_ch = &sband->channels[sband->n_channels++];
523
524 geo_ch->center_freq =
525 ieee80211_channel_to_frequency(ch->channel);
526 geo_ch->max_power = ch->max_power_avg;
527 geo_ch->max_antenna_gain = 0xff;
528 geo_ch->hw_value = ch->channel;
529
530 if (is_channel_valid(ch)) {
531 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
532 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
533
534 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
535 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
536
537 if (ch->flags & EEPROM_CHANNEL_RADAR)
538 geo_ch->flags |= IEEE80211_CHAN_RADAR;
539
963f5517 540 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 541
630fe9b6
TW		 542 if (ch->max_power_avg > priv->tx_power_channel_lmt)
543 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 544 } else {
545 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
546 }
547
548 /* Save flags for reg domain usage */
549 geo_ch->orig_flags = geo_ch->flags;
550
e1623446 551 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 552 ch->channel, geo_ch->center_freq,
553 is_channel_a_band(ch) ? "5.2" : "2.4",
554 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
555 "restricted" : "valid",
556 geo_ch->flags);
557 }
558
559 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
560 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 561 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
562 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 563 priv->pci_dev->device,
564 priv->pci_dev->subsystem_device);
c7de35cd
RR		 565 priv->cfg->sku &= ~IWL_SKU_A;
566 }
567
978785a3 568 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 569 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
570 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 571
572 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
573
574 return 0;
575}
534166de 576EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 577
578/*
579 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
580 */
534166de 581void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 582{
583 kfree(priv->ieee_channels);
584 kfree(priv->ieee_rates);
585 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
586}
534166de 587EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 588
28a6b07a 589static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 590{
591 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 592 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
593 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 594}
963f5517 595
47c5196e
TW		 596static u8 iwl_is_channel_extension(struct iwl_priv *priv,
597 enum ieee80211_band band,
598 u16 channel, u8 extension_chan_offset)
599{
600 const struct iwl_channel_info *ch_info;
601
602 ch_info = iwl_get_channel_info(priv, band, channel);
603 if (!is_channel_valid(ch_info))
604 return 0;
605
d9fe60de 606 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517 607 return !(ch_info->fat_extension_channel &
689da1b3 608 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 609 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517 610 return !(ch_info->fat_extension_channel &
689da1b3 611 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 612
613 return 0;
614}
615
616u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 617 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 618{
619 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
620
621 if ((!iwl_ht_conf->is_ht) ||
a2b0f02e 622 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ))
47c5196e
TW		 623 return 0;
624
a2b0f02e
WYG		 625 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
626 * the bit will not set if it is pure 40MHz case
627 */
47c5196e 628 if (sta_ht_inf) {
a2b0f02e 629 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 630 return 0;
631 }
611d3eb7
WYG		 632 return iwl_is_channel_extension(priv, priv->band,
633 le16_to_cpu(priv->staging_rxon.channel),
634 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 635}
636EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
637
2c2f3b33
TW		 638static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
639{
640 u16 new_val = 0;
641 u16 beacon_factor = 0;
642
643 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
644 new_val = beacon_val / beacon_factor;
645
646 if (!new_val)
647 new_val = max_beacon_val;
648
649 return new_val;
650}
651
652void iwl_setup_rxon_timing(struct iwl_priv *priv)
653{
654 u64 tsf;
655 s32 interval_tm, rem;
656 unsigned long flags;
657 struct ieee80211_conf *conf = NULL;
658 u16 beacon_int;
659
660 conf = ieee80211_get_hw_conf(priv->hw);
661
662 spin_lock_irqsave(&priv->lock, flags);
663 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
664 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
665
666 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
667 beacon_int = priv->beacon_int;
668 priv->rxon_timing.atim_window = 0;
669 } else {
670 beacon_int = priv->vif->bss_conf.beacon_int;
671
672 /* TODO: we need to get atim_window from upper stack
673 * for now we set to 0 */
674 priv->rxon_timing.atim_window = 0;
675 }
676
677 beacon_int = iwl_adjust_beacon_interval(beacon_int,
678 priv->hw_params.max_beacon_itrvl * 1024);
679 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
680
681 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
682 interval_tm = beacon_int * 1024;
683 rem = do_div(tsf, interval_tm);
684 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
685
686 spin_unlock_irqrestore(&priv->lock, flags);
687 IWL_DEBUG_ASSOC(priv,
688 "beacon interval %d beacon timer %d beacon tim %d\n",
689 le16_to_cpu(priv->rxon_timing.beacon_interval),
690 le32_to_cpu(priv->rxon_timing.beacon_init_val),
691 le16_to_cpu(priv->rxon_timing.atim_window));
692}
693EXPORT_SYMBOL(iwl_setup_rxon_timing);
694
8ccde88a
SO		 695void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
696{
697 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
698
699 if (hw_decrypt)
700 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
701 else
702 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
703
704}
705EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
706
707/**
708 * iwl_check_rxon_cmd - validate RXON structure is valid
709 *
710 * NOTE: This is really only useful during development and can eventually
711 * be #ifdef'd out once the driver is stable and folks aren't actively
712 * making changes
713 */
714int iwl_check_rxon_cmd(struct iwl_priv *priv)
715{
716 int error = 0;
717 int counter = 1;
718 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
719
720 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
721 error |= le32_to_cpu(rxon->flags &
722 (RXON_FLG_TGJ_NARROW_BAND_MSK |
723 RXON_FLG_RADAR_DETECT_MSK));
724 if (error)
725 IWL_WARN(priv, "check 24G fields %d | %d\n",
726 counter++, error);
727 } else {
728 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
729 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
730 if (error)
731 IWL_WARN(priv, "check 52 fields %d | %d\n",
732 counter++, error);
733 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
734 if (error)
735 IWL_WARN(priv, "check 52 CCK %d | %d\n",
736 counter++, error);
737 }
738 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
739 if (error)
740 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
741
742 /* make sure basic rates 6Mbps and 1Mbps are supported */
743 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
744 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
745 if (error)
746 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
747
748 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
749 if (error)
750 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
751
752 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
753 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
754 if (error)
755 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
756 counter++, error);
757
758 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
759 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
760 if (error)
761 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
762 counter++, error);
763
764 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
765 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
766 if (error)
767 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
768 counter++, error);
769
770 if (error)
771 IWL_WARN(priv, "Tuning to channel %d\n",
772 le16_to_cpu(rxon->channel));
773
774 if (error) {
775 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
776 return -1;
777 }
778 return 0;
779}
780EXPORT_SYMBOL(iwl_check_rxon_cmd);
781
782/**
783 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
784 * @priv: staging_rxon is compared to active_rxon
785 *
786 * If the RXON structure is changing enough to require a new tune,
787 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
788 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
789 */
790int iwl_full_rxon_required(struct iwl_priv *priv)
791{
792
793 /* These items are only settable from the full RXON command */
794 if (!(iwl_is_associated(priv)) ||
795 compare_ether_addr(priv->staging_rxon.bssid_addr,
796 priv->active_rxon.bssid_addr) ||
797 compare_ether_addr(priv->staging_rxon.node_addr,
798 priv->active_rxon.node_addr) ||
799 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
800 priv->active_rxon.wlap_bssid_addr) ||
801 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
802 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
803 (priv->staging_rxon.air_propagation !=
804 priv->active_rxon.air_propagation) ||
805 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
806 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
807 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
808 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 809 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
810 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 811 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
812 return 1;
813
814 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
815 * be updated with the RXON_ASSOC command -- however only some
816 * flag transitions are allowed using RXON_ASSOC */
817
818 /* Check if we are not switching bands */
819 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
820 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
821 return 1;
822
823 /* Check if we are switching association toggle */
824 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
825 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
826 return 1;
827
828 return 0;
829}
830EXPORT_SYMBOL(iwl_full_rxon_required);
831
832u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
833{
834 int i;
835 int rate_mask;
836
837 /* Set rate mask*/
838 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
839 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
840 else
841 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
842
843 /* Find lowest valid rate */
844 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
845 i = iwl_rates[i].next_ieee) {
846 if (rate_mask & (1 << i))
847 return iwl_rates[i].plcp;
848 }
849
850 /* No valid rate was found. Assign the lowest one */
851 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
852 return IWL_RATE_1M_PLCP;
853 else
854 return IWL_RATE_6M_PLCP;
855}
856EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
857
47c5196e
TW		 858void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
859{
c1adf9fb 860 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 861
42eb7c64 862 if (!ht_info->is_ht) {
a2b0f02e 863 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64
EG		 864 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
865 RXON_FLG_FAT_PROT_MSK |
866 RXON_FLG_HT_PROT_MSK);
47c5196e 867 return;
42eb7c64 868 }
47c5196e 869
a2b0f02e
WYG		 870 /* FIXME: if the definition of ht_protection changed, the "translation"
871 * will be needed for rxon->flags
872 */
873 rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
874
875 /* Set up channel bandwidth:
876 * 20 MHz only, 20/40 mixed or pure 40 if fat ok */
877 /* clear the HT channel mode before set the mode */
878 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
879 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
880 if (iwl_is_fat_tx_allowed(priv, NULL)) {
881 /* pure 40 fat */
508b08e7 882 if (ht_info->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 883 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7
WYG		 884 /* Note: control channel is opposite of extension channel */
885 switch (ht_info->extension_chan_offset) {
886 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
887 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
888 break;
889 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
890 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
891 break;
892 }
893 } else {
a2b0f02e
WYG		 894 /* Note: control channel is opposite of extension channel */
895 switch (ht_info->extension_chan_offset) {
896 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
897 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
898 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
899 break;
900 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
901 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
902 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
903 break;
904 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
905 default:
906 /* channel location only valid if in Mixed mode */
907 IWL_ERR(priv, "invalid extension channel offset\n");
908 break;
909 }
910 }
911 } else {
912 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 913 }
914
45823531
AK		 915 if (priv->cfg->ops->hcmd->set_rxon_chain)
916 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 917
e1623446 918 IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
47c5196e 919 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 920 "extension channel offset 0x%x\n",
d9fe60de
JB		 921 ht_info->mcs.rx_mask[0],
922 ht_info->mcs.rx_mask[1],
923 ht_info->mcs.rx_mask[2],
47c5196e 924 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 925 ht_info->extension_chan_offset);
47c5196e
TW		 926 return;
927}
928EXPORT_SYMBOL(iwl_set_rxon_ht);
929
9e5e6c32
TW		 930#define IWL_NUM_RX_CHAINS_MULTIPLE 3
931#define IWL_NUM_RX_CHAINS_SINGLE 2
932#define IWL_NUM_IDLE_CHAINS_DUAL 2
933#define IWL_NUM_IDLE_CHAINS_SINGLE 1
934
935/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 936 * More provides better reception via diversity. Fewer saves power.
937 * MIMO (dual stream) requires at least 2, but works better with 3.
938 * This does not determine *which* chains to use, just how many.
939 */
28a6b07a 940static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 941{
28a6b07a
TW		 942 bool is_single = is_single_rx_stream(priv);
943 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 944
945 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 946 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
947 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 948 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 949 else
9e5e6c32 950 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 951}
c7de35cd 952
28a6b07a
TW		 953static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
954{
955 int idle_cnt;
956 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 957 /* # Rx chains when idling and maybe trying to save power */
12837be1 958 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 959 case WLAN_HT_CAP_SM_PS_STATIC:
960 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 961 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
962 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 963 break;
00c5ae2f 964 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 965 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 966 break;
00c5ae2f 967 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 968 default:
15b1687c 969 IWL_ERR(priv, "invalid mimo ps mode %d\n",
12837be1 970 priv->current_ht_config.sm_ps);
28a6b07a
TW		 971 WARN_ON(1);
972 idle_cnt = -1;
c7de35cd
RR		 973 break;
974 }
28a6b07a 975 return idle_cnt;
c7de35cd
RR		 976}
977
04816448
GE		 978/* up to 4 chains */
979static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
980{
981 u8 res;
982 res = (chain_bitmap & BIT(0)) >> 0;
983 res += (chain_bitmap & BIT(1)) >> 1;
984 res += (chain_bitmap & BIT(2)) >> 2;
985 res += (chain_bitmap & BIT(4)) >> 4;
986 return res;
987}
988
4c4df78f
CR		 989/**
990 * iwl_is_monitor_mode - Determine if interface in monitor mode
991 *
992 * priv->iw_mode is set in add_interface, but add_interface is
993 * never called for monitor mode. The only way mac80211 informs us about
994 * monitor mode is through configuring filters (call to configure_filter).
995 */
279b05d4 996bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 997{
998 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
999}
279b05d4 1000EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1001
c7de35cd
RR		 1002/**
1003 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1004 *
1005 * Selects how many and which Rx receivers/antennas/chains to use.
1006 * This should not be used for scan command ... it puts data in wrong place.
1007 */
1008void iwl_set_rxon_chain(struct iwl_priv *priv)
1009{
28a6b07a
TW		 1010 bool is_single = is_single_rx_stream(priv);
1011 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1012 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1013 u32 active_chains;
28a6b07a 1014 u16 rx_chain;
c7de35cd
RR		 1015
1016 /* Tell uCode which antennas are actually connected.
1017 * Before first association, we assume all antennas are connected.
1018 * Just after first association, iwl_chain_noise_calibration()
1019 * checks which antennas actually *are* connected. */
04816448
GE		 1020 if (priv->chain_noise_data.active_chains)
1021 active_chains = priv->chain_noise_data.active_chains;
1022 else
1023 active_chains = priv->hw_params.valid_rx_ant;
1024
1025 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1026
1027 /* How many receivers should we use? */
28a6b07a
TW		 1028 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1029 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1030
28a6b07a 1031
04816448
GE		 1032 /* correct rx chain count according hw settings
1033 * and chain noise calibration
1034 */
1035 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1036 if (valid_rx_cnt < active_rx_cnt)
1037 active_rx_cnt = valid_rx_cnt;
1038
1039 if (valid_rx_cnt < idle_rx_cnt)
1040 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1041
1042 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1043 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1044
7b841727
RF		 1045 /* copied from 'iwl_bg_request_scan()' */
1046 /* Force use of chains B and C (0x6) for Rx for 4965
1047 * Avoid A (0x1) because of its off-channel reception on A-band.
1048 * MIMO is not used here, but value is required */
1049 if (iwl_is_monitor_mode(priv) &&
1050 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1051 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1052 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1053 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1054 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1055 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1056 }
1057
28a6b07a
TW		 1058 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1059
9e5e6c32 1060 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1061 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1062 else
1063 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1064
e1623446 1065 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1066 priv->staging_rxon.rx_chain,
1067 active_rx_cnt, idle_rx_cnt);
1068
1069 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1070 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1071}
1072EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1073
1074/**
17e72782 1075 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1076 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1077 * @channel: Any channel valid for the requested phymode
1078
1079 * In addition to setting the staging RXON, priv->phymode is also set.
1080 *
1081 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1082 * in the staging RXON flag structure based on the phymode
1083 */
17e72782 1084int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1085{
17e72782
TW		 1086 enum ieee80211_band band = ch->band;
1087 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1088
8622e705 1089 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1090 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1091 channel, band);
1092 return -EINVAL;
1093 }
1094
1095 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1096 (priv->band == band))
1097 return 0;
1098
1099 priv->staging_rxon.channel = cpu_to_le16(channel);
1100 if (band == IEEE80211_BAND_5GHZ)
1101 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1102 else
1103 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1104
1105 priv->band = band;
1106
e1623446 1107 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1108
1109 return 0;
1110}
c7de35cd 1111EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1112
8ccde88a
SO		 1113void iwl_set_flags_for_band(struct iwl_priv *priv,
1114 enum ieee80211_band band)
1115{
1116 if (band == IEEE80211_BAND_5GHZ) {
1117 priv->staging_rxon.flags &=
1118 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1119 | RXON_FLG_CCK_MSK);
1120 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1121 } else {
1122 /* Copied from iwl_post_associate() */
1123 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1124 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1125 else
1126 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1127
1128 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1129 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1130
1131 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1132 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1133 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1134 }
1135}
1136EXPORT_SYMBOL(iwl_set_flags_for_band);
1137
1138/*
1139 * initialize rxon structure with default values from eeprom
1140 */
1141void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1142{
1143 const struct iwl_channel_info *ch_info;
1144
1145 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1146
1147 switch (mode) {
1148 case NL80211_IFTYPE_AP:
1149 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1150 break;
1151
1152 case NL80211_IFTYPE_STATION:
1153 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1154 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1155 break;
1156
1157 case NL80211_IFTYPE_ADHOC:
1158 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1159 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1160 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1161 RXON_FILTER_ACCEPT_GRP_MSK;
1162 break;
1163
8ccde88a
SO		 1164 default:
1165 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1166 break;
1167 }
1168
1169#if 0
1170 /* TODO: Figure out when short_preamble would be set and cache from
1171 * that */
1172 if (!hw_to_local(priv->hw)->short_preamble)
1173 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1174 else
1175 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1176#endif
1177
1178 ch_info = iwl_get_channel_info(priv, priv->band,
1179 le16_to_cpu(priv->active_rxon.channel));
1180
1181 if (!ch_info)
1182 ch_info = &priv->channel_info[0];
1183
1184 /*
1185 * in some case A channels are all non IBSS
1186 * in this case force B/G channel
1187 */
1188 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1189 !(is_channel_ibss(ch_info)))
1190 ch_info = &priv->channel_info[0];
1191
1192 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1193 priv->band = ch_info->band;
1194
1195 iwl_set_flags_for_band(priv, priv->band);
1196
1197 priv->staging_rxon.ofdm_basic_rates =
1198 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1199 priv->staging_rxon.cck_basic_rates =
1200 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1201
a2b0f02e
WYG		 1202 /* clear both MIX and PURE40 mode flag */
1203 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1204 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1205 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1206 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1207 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1208 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1209 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1210}
1211EXPORT_SYMBOL(iwl_connection_init_rx_config);
1212
782571f4 1213static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1214{
1215 const struct ieee80211_supported_band *hw = NULL;
1216 struct ieee80211_rate *rate;
1217 int i;
1218
1219 hw = iwl_get_hw_mode(priv, priv->band);
1220 if (!hw) {
1221 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1222 return;
1223 }
1224
1225 priv->active_rate = 0;
1226 priv->active_rate_basic = 0;
1227
1228 for (i = 0; i < hw->n_bitrates; i++) {
1229 rate = &(hw->bitrates[i]);
1230 if (rate->hw_value < IWL_RATE_COUNT)
1231 priv->active_rate |= (1 << rate->hw_value);
1232 }
1233
e1623446 1234 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1235 priv->active_rate, priv->active_rate_basic);
1236
1237 /*
1238 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1239 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1240 * OFDM
1241 */
1242 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1243 priv->staging_rxon.cck_basic_rates =
1244 ((priv->active_rate_basic &
1245 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1246 else
1247 priv->staging_rxon.cck_basic_rates =
1248 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1249
1250 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1251 priv->staging_rxon.ofdm_basic_rates =
1252 ((priv->active_rate_basic &
1253 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1254 IWL_FIRST_OFDM_RATE) & 0xFF;
1255 else
1256 priv->staging_rxon.ofdm_basic_rates =
1257 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1258}
8ccde88a
SO		 1259
1260void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1261{
1262 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1263 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1264 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
e1623446 1265 IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
8ccde88a
SO		 1266 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
1267 rxon->channel = csa->channel;
1268 priv->staging_rxon.channel = csa->channel;
1269}
1270EXPORT_SYMBOL(iwl_rx_csa);
1271
1272#ifdef CONFIG_IWLWIFI_DEBUG
1273static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1274{
1275 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1276
e1623446 1277 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
8ccde88a 1278 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1279 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1280 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1281 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1282 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1283 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1284 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1285 rxon->ofdm_basic_rates);
e1623446
TW		 1286 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1287 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1288 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1289 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a
SO		 1290}
1291#endif
1292
1293/**
1294 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1295 */
1296void iwl_irq_handle_error(struct iwl_priv *priv)
1297{
1298 /* Set the FW error flag -- cleared on iwl_down */
1299 set_bit(STATUS_FW_ERROR, &priv->status);
1300
1301 /* Cancel currently queued command. */
1302 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1303
1304#ifdef CONFIG_IWLWIFI_DEBUG
1305 if (priv->debug_level & IWL_DL_FW_ERRORS) {
1306 iwl_dump_nic_error_log(priv);
1307 iwl_dump_nic_event_log(priv);
1308 iwl_print_rx_config_cmd(priv);
1309 }
1310#endif
1311
1312 wake_up_interruptible(&priv->wait_command_queue);
1313
1314 /* Keep the restart process from trying to send host
1315 * commands by clearing the INIT status bit */
1316 clear_bit(STATUS_READY, &priv->status);
1317
1318 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1319 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1320 "Restarting adapter due to uCode error.\n");
1321
8ccde88a
SO		 1322 if (priv->cfg->mod_params->restart_fw)
1323 queue_work(priv->workqueue, &priv->restart);
1324 }
1325}
1326EXPORT_SYMBOL(iwl_irq_handle_error);
1327
1328void iwl_configure_filter(struct ieee80211_hw *hw,
1329 unsigned int changed_flags,
1330 unsigned int *total_flags,
1331 int mc_count, struct dev_addr_list *mc_list)
1332{
1333 struct iwl_priv *priv = hw->priv;
1334 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1335
e1623446 1336 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1337 changed_flags, *total_flags);
1338
1339 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1340 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1341 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1342 else
1343 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1344 }
1345 if (changed_flags & FIF_ALLMULTI) {
1346 if (*total_flags & FIF_ALLMULTI)
1347 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1348 else
1349 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1350 }
1351 if (changed_flags & FIF_CONTROL) {
1352 if (*total_flags & FIF_CONTROL)
1353 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1354 else
1355 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1356 }
1357 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1358 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1359 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1360 else
1361 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1362 }
1363
1364 /* We avoid iwl_commit_rxon here to commit the new filter flags
1365 * since mac80211 will call ieee80211_hw_config immediately.
1366 * (mc_list is not supported at this time). Otherwise, we need to
1367 * queue a background iwl_commit_rxon work.
1368 */
1369
1370 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1371 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1372}
1373EXPORT_SYMBOL(iwl_configure_filter);
1374
6ba87956 1375int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 1376{
6ba87956 1377 int ret;
bf85ea4f 1378 struct ieee80211_hw *hw = priv->hw;
e227ceac 1379 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 1380
566bfe5a 1381 /* Tell mac80211 our characteristics */
605a0bd6 1382 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe 1383 IEEE80211_HW_NOISE_DBM |
4be8c387 1384 IEEE80211_HW_AMPDU_AGGREGATION |
286d9490 1385 IEEE80211_HW_SPECTRUM_MGMT;
f59ac048 1386 hw->wiphy->interface_modes =
f59ac048
LR		 1387 BIT(NL80211_IFTYPE_STATION) |
1388 BIT(NL80211_IFTYPE_ADHOC);
ea4a82dc 1389
2a44f911 1390 hw->wiphy->custom_regulatory = true;
1ecf9fc1
JB		 1391
1392 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
1393 /* we create the 802.11 header and a zero-length SSID element */
1394 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
ea4a82dc 1395
bf85ea4f
AK		 1396 /* Default value; 4 EDCA QOS priorities */
1397 hw->queues = 4;
6ba87956 1398
b5d7be5e 1399 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 1400
1401 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
1402 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1403 &priv->bands[IEEE80211_BAND_2GHZ];
1404 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
1405 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1406 &priv->bands[IEEE80211_BAND_5GHZ];
1407
1408 ret = ieee80211_register_hw(priv->hw);
1409 if (ret) {
15b1687c 1410 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
6ba87956
TW		 1411 return ret;
1412 }
1413 priv->mac80211_registered = 1;
1414
1415 return 0;
bf85ea4f 1416}
6ba87956 1417EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 1418
da154e30
RR		 1419int iwl_set_hw_params(struct iwl_priv *priv)
1420{
da154e30
RR		 1421 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1422 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1423 if (priv->cfg->mod_params->amsdu_size_8K)
1424 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1425 else
1426 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1427 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1428
2c2f3b33
TW		 1429 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1430
49779293
RR		 1431 if (priv->cfg->mod_params->disable_11n)
1432 priv->cfg->sku &= ~IWL_SKU_N;
1433
da154e30
RR		 1434 /* Device-specific setup */
1435 return priv->cfg->ops->lib->set_hw_params(priv);
1436}
1437EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 1438
1439int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 1440{
1441 int ret;
c7de35cd 1442
c7de35cd
RR		 1443 priv->ibss_beacon = NULL;
1444
1445 spin_lock_init(&priv->lock);
c7de35cd
RR		 1446 spin_lock_init(&priv->sta_lock);
1447 spin_lock_init(&priv->hcmd_lock);
c7de35cd 1448
c7de35cd
RR		 1449 INIT_LIST_HEAD(&priv->free_frames);
1450
1451 mutex_init(&priv->mutex);
1452
1453 /* Clear the driver's (not device's) station table */
c587de0b 1454 iwl_clear_stations_table(priv);
c7de35cd
RR		 1455
1456 priv->data_retry_limit = -1;
1457 priv->ieee_channels = NULL;
1458 priv->ieee_rates = NULL;
1459 priv->band = IEEE80211_BAND_2GHZ;
1460
05c914fe 1461 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 1462
12837be1 1463 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 1464
1465 /* Choose which receivers/antennas to use */
45823531
AK		 1466 if (priv->cfg->ops->hcmd->set_rxon_chain)
1467 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1468
f53696de 1469 iwl_init_scan_params(priv);
c7de35cd
RR		 1470
1471 iwl_reset_qos(priv);
1472
1473 priv->qos_data.qos_active = 0;
1474 priv->qos_data.qos_cap.val = 0;
1475
c7de35cd 1476 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT		 1477 /* If power management is turned on, default to CAM mode */
1478 priv->power_mode = IWL_POWER_MODE_CAM;
630fe9b6 1479 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 1480
1481 ret = iwl_init_channel_map(priv);
1482 if (ret) {
15b1687c 1483 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
c7de35cd
RR		 1484 goto err;
1485 }
1486
1487 ret = iwlcore_init_geos(priv);
1488 if (ret) {
15b1687c 1489 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
c7de35cd
RR		 1490 goto err_free_channel_map;
1491 }
534166de 1492 iwlcore_init_hw_rates(priv, priv->ieee_rates);
c7de35cd 1493
c7de35cd
RR		 1494 return 0;
1495
c7de35cd
RR		 1496err_free_channel_map:
1497 iwl_free_channel_map(priv);
1498err:
1499 return ret;
1500}
6ba87956 1501EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 1502
630fe9b6
TW		 1503int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1504{
1505 int ret = 0;
1506 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1507 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1508 tx_power,
1509 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1510 return -EINVAL;
1511 }
1512
1513 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
daf518de
WF		 1514 IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
1515 tx_power,
1516 IWL_TX_POWER_TARGET_POWER_MAX);
630fe9b6
TW		 1517 return -EINVAL;
1518 }
1519
1520 if (priv->tx_power_user_lmt != tx_power)
1521 force = true;
1522
1523 priv->tx_power_user_lmt = tx_power;
1524
019fb97d
MA		 1525 /* if nic is not up don't send command */
1526 if (!iwl_is_ready_rf(priv))
1527 return ret;
1528
630fe9b6
TW		 1529 if (force && priv->cfg->ops->lib->send_tx_power)
1530 ret = priv->cfg->ops->lib->send_tx_power(priv);
1531
1532 return ret;
1533}
1534EXPORT_SYMBOL(iwl_set_tx_power);
1535
6ba87956 1536void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1537{
6e21f2c1 1538 iwl_calib_free_results(priv);
6ba87956
TW		 1539 iwlcore_free_geos(priv);
1540 iwl_free_channel_map(priv);
261415f7 1541 kfree(priv->scan);
bf85ea4f 1542}
6ba87956 1543EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1544
0ad91a35
WT		 1545
1546void iwl_disable_interrupts(struct iwl_priv *priv)
1547{
1548 clear_bit(STATUS_INT_ENABLED, &priv->status);
1549
1550 /* disable interrupts from uCode/NIC to host */
1551 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1552
1553 /* acknowledge/clear/reset any interrupts still pending
1554 * from uCode or flow handler (Rx/Tx DMA) */
1555 iwl_write32(priv, CSR_INT, 0xffffffff);
1556 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
e1623446 1557 IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
0ad91a35
WT		 1558}
1559EXPORT_SYMBOL(iwl_disable_interrupts);
1560
1561void iwl_enable_interrupts(struct iwl_priv *priv)
1562{
e1623446 1563 IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
0ad91a35 1564 set_bit(STATUS_INT_ENABLED, &priv->status);
40cefda9 1565 iwl_write32(priv, CSR_INT_MASK, priv->inta_mask);
0ad91a35
WT		 1566}
1567EXPORT_SYMBOL(iwl_enable_interrupts);
1568
ef850d7c
MA		 1569
1570#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1571
1572/* Free dram table */
1573void iwl_free_isr_ict(struct iwl_priv *priv)
1574{
1575 if (priv->ict_tbl_vir) {
1576 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1577 PAGE_SIZE, priv->ict_tbl_vir,
1578 priv->ict_tbl_dma);
1579 priv->ict_tbl_vir = NULL;
1580 }
1581}
1582EXPORT_SYMBOL(iwl_free_isr_ict);
1583
1584
1585/* allocate dram shared table it is a PAGE_SIZE aligned
1586 * also reset all data related to ICT table interrupt.
1587 */
1588int iwl_alloc_isr_ict(struct iwl_priv *priv)
1589{
1590
1591 if (priv->cfg->use_isr_legacy)
1592 return 0;
1593 /* allocate shrared data table */
1594 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1595 ICT_COUNT) + PAGE_SIZE,
1596 &priv->ict_tbl_dma);
1597 if (!priv->ict_tbl_vir)
1598 return -ENOMEM;
1599
1600 /* align table to PAGE_SIZE boundry */
1601 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1602
1603 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1604 (unsigned long long)priv->ict_tbl_dma,
1605 (unsigned long long)priv->aligned_ict_tbl_dma,
1606 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1607
1608 priv->ict_tbl = priv->ict_tbl_vir +
1609 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1610
1611 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1612 priv->ict_tbl, priv->ict_tbl_vir,
1613 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1614
1615 /* reset table and index to all 0 */
1616 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1617 priv->ict_index = 0;
1618
40cefda9
MA		 1619 /* add periodic RX interrupt */
1620 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1621 return 0;
1622}
1623EXPORT_SYMBOL(iwl_alloc_isr_ict);
1624
1625/* Device is going up inform it about using ICT interrupt table,
1626 * also we need to tell the driver to start using ICT interrupt.
1627 */
1628int iwl_reset_ict(struct iwl_priv *priv)
1629{
1630 u32 val;
1631 unsigned long flags;
1632
1633 if (!priv->ict_tbl_vir)
1634 return 0;
1635
1636 spin_lock_irqsave(&priv->lock, flags);
1637 iwl_disable_interrupts(priv);
1638
1639 memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT);
1640
1641 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1642
1643 val |= CSR_DRAM_INT_TBL_ENABLE;
1644 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1645
1646 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1647 "aligned dma address %Lx\n",
1648 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1649
1650 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1651 priv->use_ict = true;
1652 priv->ict_index = 0;
40cefda9 1653 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1654 iwl_enable_interrupts(priv);
1655 spin_unlock_irqrestore(&priv->lock, flags);
1656
1657 return 0;
1658}
1659EXPORT_SYMBOL(iwl_reset_ict);
1660
1661/* Device is going down disable ict interrupt usage */
1662void iwl_disable_ict(struct iwl_priv *priv)
1663{
1664 unsigned long flags;
1665
1666 spin_lock_irqsave(&priv->lock, flags);
1667 priv->use_ict = false;
1668 spin_unlock_irqrestore(&priv->lock, flags);
1669}
1670EXPORT_SYMBOL(iwl_disable_ict);
1671
1672/* interrupt handler using ict table, with this interrupt driver will
1673 * stop using INTA register to get device's interrupt, reading this register
1674 * is expensive, device will write interrupts in ICT dram table, increment
1675 * index then will fire interrupt to driver, driver will OR all ICT table
1676 * entries from current index up to table entry with 0 value. the result is
1677 * the interrupt we need to service, driver will set the entries back to 0 and
1678 * set index.
1679 */
1680irqreturn_t iwl_isr_ict(int irq, void *data)
1681{
1682 struct iwl_priv *priv = data;
1683 u32 inta, inta_mask;
1684 u32 val = 0;
1685
1686 if (!priv)
1687 return IRQ_NONE;
1688
1689 /* dram interrupt table not set yet,
1690 * use legacy interrupt.
1691 */
1692 if (!priv->use_ict)
1693 return iwl_isr(irq, data);
1694
1695 spin_lock(&priv->lock);
1696
1697 /* Disable (but don't clear!) interrupts here to avoid
1698 * back-to-back ISRs and sporadic interrupts from our NIC.
1699 * If we have something to service, the tasklet will re-enable ints.
1700 * If we *don't* have something, we'll re-enable before leaving here.
1701 */
1702 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1703 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1704
1705
1706 /* Ignore interrupt if there's nothing in NIC to service.
1707 * This may be due to IRQ shared with another device,
1708 * or due to sporadic interrupts thrown from our NIC. */
1709 if (!priv->ict_tbl[priv->ict_index]) {
1710 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1711 goto none;
1712 }
1713
1714 /* read all entries that not 0 start with ict_index */
1715 while (priv->ict_tbl[priv->ict_index]) {
1716
1717 val |= priv->ict_tbl[priv->ict_index];
1718 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1719 priv->ict_index,
1720 priv->ict_tbl[priv->ict_index]);
1721 priv->ict_tbl[priv->ict_index] = 0;
1722 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1723 ICT_COUNT);
1724
1725 }
1726
1727 /* We should not get this value, just ignore it. */
1728 if (val == 0xffffffff)
1729 val = 0;
1730
1731 inta = (0xff & val) | ((0xff00 & val) << 16);
1732 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1733 inta, inta_mask, val);
1734
40cefda9 1735 inta &= priv->inta_mask;
ef850d7c
MA		 1736 priv->inta |= inta;
1737
1738 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1739 if (likely(inta))
1740 tasklet_schedule(&priv->irq_tasklet);
1741 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1742 /* Allow interrupt if was disabled by this handler and
1743 * no tasklet was schedules, We should not enable interrupt,
1744 * tasklet will enable it.
1745 */
1746 iwl_enable_interrupts(priv);
1747 }
1748
1749 spin_unlock(&priv->lock);
1750 return IRQ_HANDLED;
1751
1752 none:
1753 /* re-enable interrupts here since we don't have anything to service.
1754 * only Re-enable if disabled by irq.
1755 */
1756 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1757 iwl_enable_interrupts(priv);
1758
1759 spin_unlock(&priv->lock);
1760 return IRQ_NONE;
1761}
1762EXPORT_SYMBOL(iwl_isr_ict);
1763
1764
1765static irqreturn_t iwl_isr(int irq, void *data)
1766{
1767 struct iwl_priv *priv = data;
1768 u32 inta, inta_mask;
d651ae32 1769#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1770 u32 inta_fh;
d651ae32 1771#endif
ef850d7c
MA		 1772 if (!priv)
1773 return IRQ_NONE;
1774
1775 spin_lock(&priv->lock);
1776
1777 /* Disable (but don't clear!) interrupts here to avoid
1778 * back-to-back ISRs and sporadic interrupts from our NIC.
1779 * If we have something to service, the tasklet will re-enable ints.
1780 * If we *don't* have something, we'll re-enable before leaving here. */
1781 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1782 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1783
1784 /* Discover which interrupts are active/pending */
1785 inta = iwl_read32(priv, CSR_INT);
1786
1787 /* Ignore interrupt if there's nothing in NIC to service.
1788 * This may be due to IRQ shared with another device,
1789 * or due to sporadic interrupts thrown from our NIC. */
1790 if (!inta) {
1791 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1792 goto none;
1793 }
1794
1795 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1796 /* Hardware disappeared. It might have already raised
1797 * an interrupt */
1798 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1799 goto unplugged;
1800 }
1801
1802#ifdef CONFIG_IWLWIFI_DEBUG
1803 if (priv->debug_level & (IWL_DL_ISR)) {
1804 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1805 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1806 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1807 }
1808#endif
1809
1810 priv->inta |= inta;
1811 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1812 if (likely(inta))
1813 tasklet_schedule(&priv->irq_tasklet);
1814 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1815 iwl_enable_interrupts(priv);
1816
1817 unplugged:
1818 spin_unlock(&priv->lock);
1819 return IRQ_HANDLED;
1820
1821 none:
1822 /* re-enable interrupts here since we don't have anything to service. */
1823 /* only Re-enable if diabled by irq and no schedules tasklet. */
1824 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1825 iwl_enable_interrupts(priv);
1826
1827 spin_unlock(&priv->lock);
1828 return IRQ_NONE;
1829}
1830
1831irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1832{
1833 struct iwl_priv *priv = data;
1834 u32 inta, inta_mask;
1835 u32 inta_fh;
1836 if (!priv)
1837 return IRQ_NONE;
1838
1839 spin_lock(&priv->lock);
1840
1841 /* Disable (but don't clear!) interrupts here to avoid
1842 * back-to-back ISRs and sporadic interrupts from our NIC.
1843 * If we have something to service, the tasklet will re-enable ints.
1844 * If we *don't* have something, we'll re-enable before leaving here. */
1845 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1846 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1847
1848 /* Discover which interrupts are active/pending */
1849 inta = iwl_read32(priv, CSR_INT);
1850 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1851
1852 /* Ignore interrupt if there's nothing in NIC to service.
1853 * This may be due to IRQ shared with another device,
1854 * or due to sporadic interrupts thrown from our NIC. */
1855 if (!inta && !inta_fh) {
1856 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1857 goto none;
1858 }
1859
1860 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1861 /* Hardware disappeared. It might have already raised
1862 * an interrupt */
1863 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1864 goto unplugged;
1865 }
1866
1867 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1868 inta, inta_mask, inta_fh);
1869
1870 inta &= ~CSR_INT_BIT_SCD;
1871
1872 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1873 if (likely(inta || inta_fh))
1874 tasklet_schedule(&priv->irq_tasklet);
1875
1876 unplugged:
1877 spin_unlock(&priv->lock);
1878 return IRQ_HANDLED;
1879
1880 none:
1881 /* re-enable interrupts here since we don't have anything to service. */
1882 /* only Re-enable if diabled by irq */
1883 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1884 iwl_enable_interrupts(priv);
1885 spin_unlock(&priv->lock);
1886 return IRQ_NONE;
1887}
ef850d7c 1888EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1889
17f841cd
SO		 1890int iwl_send_bt_config(struct iwl_priv *priv)
1891{
1892 struct iwl_bt_cmd bt_cmd = {
1893 .flags = 3,
1894 .lead_time = 0xAA,
1895 .max_kill = 1,
1896 .kill_ack_mask = 0,
1897 .kill_cts_mask = 0,
1898 };
1899
1900 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1901 sizeof(struct iwl_bt_cmd), &bt_cmd);
1902}
1903EXPORT_SYMBOL(iwl_send_bt_config);
1904
49ea8596
EG		 1905int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1906{
1907 u32 stat_flags = 0;
1908 struct iwl_host_cmd cmd = {
1909 .id = REPLY_STATISTICS_CMD,
1910 .meta.flags = flags,
1911 .len = sizeof(stat_flags),
1912 .data = (u8 *) &stat_flags,
1913 };
1914 return iwl_send_cmd(priv, &cmd);
1915}
1916EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1917
b0692f2f
EG		 1918/**
1919 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1920 * using sample data 100 bytes apart. If these sample points are good,
1921 * it's a pretty good bet that everything between them is good, too.
1922 */
1923static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1924{
1925 u32 val;
1926 int ret = 0;
1927 u32 errcnt = 0;
1928 u32 i;
1929
e1623446 1930 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 1931
b0692f2f
EG		 1932 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1933 /* read data comes through single port, auto-incr addr */
1934 /* NOTE: Use the debugless read so we don't flood kernel log
1935 * if IWL_DL_IO is set */
1936 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1937 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1938 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1939 if (val != le32_to_cpu(*image)) {
1940 ret = -EIO;
1941 errcnt++;
1942 if (errcnt >= 3)
1943 break;
1944 }
1945 }
1946
b0692f2f
EG		 1947 return ret;
1948}
1949
1950/**
1951 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1952 * looking at all data.
1953 */
1954static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1955 u32 len)
1956{
1957 u32 val;
1958 u32 save_len = len;
1959 int ret = 0;
1960 u32 errcnt;
1961
e1623446 1962 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 1963
250bdd21
SO		 1964 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1965 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1966
1967 errcnt = 0;
1968 for (; len > 0; len -= sizeof(u32), image++) {
1969 /* read data comes through single port, auto-incr addr */
1970 /* NOTE: Use the debugless read so we don't flood kernel log
1971 * if IWL_DL_IO is set */
1972 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1973 if (val != le32_to_cpu(*image)) {
15b1687c 1974 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 1975 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1976 save_len - len, val, le32_to_cpu(*image));
1977 ret = -EIO;
1978 errcnt++;
1979 if (errcnt >= 20)
1980 break;
1981 }
1982 }
1983
b0692f2f 1984 if (!errcnt)
e1623446
TW		 1985 IWL_DEBUG_INFO(priv,
1986 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 1987
1988 return ret;
1989}
1990
1991/**
1992 * iwl_verify_ucode - determine which instruction image is in SRAM,
1993 * and verify its contents
1994 */
1995int iwl_verify_ucode(struct iwl_priv *priv)
1996{
1997 __le32 *image;
1998 u32 len;
1999 int ret;
2000
2001 /* Try bootstrap */
2002 image = (__le32 *)priv->ucode_boot.v_addr;
2003 len = priv->ucode_boot.len;
2004 ret = iwlcore_verify_inst_sparse(priv, image, len);
2005 if (!ret) {
e1623446 2006 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2007 return 0;
2008 }
2009
2010 /* Try initialize */
2011 image = (__le32 *)priv->ucode_init.v_addr;
2012 len = priv->ucode_init.len;
2013 ret = iwlcore_verify_inst_sparse(priv, image, len);
2014 if (!ret) {
e1623446 2015 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2016 return 0;
2017 }
2018
2019 /* Try runtime/protocol */
2020 image = (__le32 *)priv->ucode_code.v_addr;
2021 len = priv->ucode_code.len;
2022 ret = iwlcore_verify_inst_sparse(priv, image, len);
2023 if (!ret) {
e1623446 2024 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2025 return 0;
2026 }
2027
15b1687c 2028 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2029
2030 /* Since nothing seems to match, show first several data entries in
2031 * instruction SRAM, so maybe visual inspection will give a clue.
2032 * Selection of bootstrap image (vs. other images) is arbitrary. */
2033 image = (__le32 *)priv->ucode_boot.v_addr;
2034 len = priv->ucode_boot.len;
2035 ret = iwl_verify_inst_full(priv, image, len);
2036
2037 return ret;
2038}
2039EXPORT_SYMBOL(iwl_verify_ucode);
2040
56e12615
JS		 2041
2042static const char *desc_lookup_text[] = {
2043 "OK",
2044 "FAIL",
2045 "BAD_PARAM",
2046 "BAD_CHECKSUM",
2047 "NMI_INTERRUPT_WDG",
2048 "SYSASSERT",
2049 "FATAL_ERROR",
2050 "BAD_COMMAND",
2051 "HW_ERROR_TUNE_LOCK",
2052 "HW_ERROR_TEMPERATURE",
2053 "ILLEGAL_CHAN_FREQ",
2054 "VCC_NOT_STABLE",
2055 "FH_ERROR",
2056 "NMI_INTERRUPT_HOST",
2057 "NMI_INTERRUPT_ACTION_PT",
2058 "NMI_INTERRUPT_UNKNOWN",
2059 "UCODE_VERSION_MISMATCH",
2060 "HW_ERROR_ABS_LOCK",
2061 "HW_ERROR_CAL_LOCK_FAIL",
2062 "NMI_INTERRUPT_INST_ACTION_PT",
2063 "NMI_INTERRUPT_DATA_ACTION_PT",
2064 "NMI_TRM_HW_ER",
2065 "NMI_INTERRUPT_TRM",
2066 "NMI_INTERRUPT_BREAK_POINT"
2067 "DEBUG_0",
2068 "DEBUG_1",
2069 "DEBUG_2",
2070 "DEBUG_3",
2071 "UNKNOWN"
2072};
2073
ede0cba4
EK		 2074static const char *desc_lookup(int i)
2075{
56e12615
JS		 2076 int max = ARRAY_SIZE(desc_lookup_text) - 1;
2077
2078 if (i < 0 || i > max)
2079 i = max;
ede0cba4 2080
56e12615 2081 return desc_lookup_text[i];
ede0cba4
EK		 2082}
2083
2084#define ERROR_START_OFFSET (1 * sizeof(u32))
2085#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2086
2087void iwl_dump_nic_error_log(struct iwl_priv *priv)
2088{
2089 u32 data2, line;
2090 u32 desc, time, count, base, data1;
2091 u32 blink1, blink2, ilink1, ilink2;
ede0cba4 2092
e1dfc085
GG		 2093 if (priv->ucode_type == UCODE_INIT)
2094 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2095 else
2096 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 2097
2098 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 2099 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
ede0cba4
EK		 2100 return;
2101 }
2102
ede0cba4
EK		 2103 count = iwl_read_targ_mem(priv, base);
2104
2105 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT		 2106 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2107 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2108 priv->status, count);
ede0cba4
EK		 2109 }
2110
2111 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2112 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2113 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2114 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2115 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2116 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2117 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2118 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2119 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2120
15b1687c 2121 IWL_ERR(priv, "Desc Time "
ede0cba4 2122 "data1 data2 line\n");
15b1687c 2123 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
ede0cba4 2124 desc_lookup(desc), desc, time, data1, data2, line);
15b1687c
WT		 2125 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
2126 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
ede0cba4
EK		 2127 ilink1, ilink2);
2128
ede0cba4
EK		 2129}
2130EXPORT_SYMBOL(iwl_dump_nic_error_log);
2131
189a2b59
EK		 2132#define EVENT_START_OFFSET (4 * sizeof(u32))
2133
2134/**
2135 * iwl_print_event_log - Dump error event log to syslog
2136 *
189a2b59 2137 */
a33c2f47 2138static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 2139 u32 num_events, u32 mode)
2140{
2141 u32 i;
2142 u32 base; /* SRAM byte address of event log header */
2143 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2144 u32 ptr; /* SRAM byte address of log data */
2145 u32 ev, time, data; /* event log data */
2146
2147 if (num_events == 0)
2148 return;
e1dfc085
GG		 2149 if (priv->ucode_type == UCODE_INIT)
2150 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2151 else
2152 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 2153
2154 if (mode == 0)
2155 event_size = 2 * sizeof(u32);
2156 else
2157 event_size = 3 * sizeof(u32);
2158
2159 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2160
2161 /* "time" is actually "data" for mode 0 (no timestamp).
2162 * place event id # at far right for easier visual parsing. */
2163 for (i = 0; i < num_events; i++) {
2164 ev = iwl_read_targ_mem(priv, ptr);
2165 ptr += sizeof(u32);
2166 time = iwl_read_targ_mem(priv, ptr);
2167 ptr += sizeof(u32);
77c5d08e
TW		 2168 if (mode == 0) {
2169 /* data, ev */
15b1687c 2170 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
77c5d08e 2171 } else {
189a2b59
EK		 2172 data = iwl_read_targ_mem(priv, ptr);
2173 ptr += sizeof(u32);
15b1687c 2174 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
77c5d08e 2175 time, data, ev);
189a2b59
EK		 2176 }
2177 }
2178}
189a2b59
EK		 2179
2180void iwl_dump_nic_event_log(struct iwl_priv *priv)
2181{
189a2b59
EK		 2182 u32 base; /* SRAM byte address of event log header */
2183 u32 capacity; /* event log capacity in # entries */
2184 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2185 u32 num_wraps; /* # times uCode wrapped to top of log */
2186 u32 next_entry; /* index of next entry to be written by uCode */
2187 u32 size; /* # entries that we'll print */
2188
e1dfc085
GG		 2189 if (priv->ucode_type == UCODE_INIT)
2190 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2191 else
2192 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2193
189a2b59 2194 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 2195 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
189a2b59
EK		 2196 return;
2197 }
2198
189a2b59
EK		 2199 /* event log header */
2200 capacity = iwl_read_targ_mem(priv, base);
2201 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2202 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2203 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2204
2205 size = num_wraps ? capacity : next_entry;
2206
2207 /* bail out if nothing in log */
2208 if (size == 0) {
15b1687c 2209 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
189a2b59
EK		 2210 return;
2211 }
2212
15b1687c 2213 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
189a2b59
EK		 2214 size, num_wraps);
2215
2216 /* if uCode has wrapped back to top of log, start at the oldest entry,
2217 * i.e the next one that uCode would fill. */
2218 if (num_wraps)
2219 iwl_print_event_log(priv, next_entry,
2220 capacity - next_entry, mode);
2221 /* (then/else) start at top of log */
2222 iwl_print_event_log(priv, 0, next_entry, mode);
2223
189a2b59
EK		 2224}
2225EXPORT_SYMBOL(iwl_dump_nic_event_log);
2226
47f4a587
EG		 2227void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2228{
2229 struct iwl_ct_kill_config cmd;
2230 unsigned long flags;
2231 int ret = 0;
2232
2233 spin_lock_irqsave(&priv->lock, flags);
2234 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2235 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2236 spin_unlock_irqrestore(&priv->lock, flags);
2237
2238 cmd.critical_temperature_R =
2239 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2240
47f4a587
EG		 2241 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2242 sizeof(cmd), &cmd);
2243 if (ret)
15b1687c 2244 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
47f4a587 2245 else
e1623446 2246 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
47f4a587
EG		 2247 "critical temperature is %d\n",
2248 cmd.critical_temperature_R);
2249}
2250EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2251
0ad91a35 2252
14a08a7f
EG		 2253/*
2254 * CARD_STATE_CMD
2255 *
2256 * Use: Sets the device's internal card state to enable, disable, or halt
2257 *
2258 * When in the 'enable' state the card operates as normal.
2259 * When in the 'disable' state, the card enters into a low power mode.
2260 * When in the 'halt' state, the card is shut down and must be fully
2261 * restarted to come back on.
2262 */
c496294e 2263int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2264{
2265 struct iwl_host_cmd cmd = {
2266 .id = REPLY_CARD_STATE_CMD,
2267 .len = sizeof(u32),
2268 .data = &flags,
2269 .meta.flags = meta_flag,
2270 };
2271
2272 return iwl_send_cmd(priv, &cmd);
2273}
c496294e 2274EXPORT_SYMBOL(iwl_send_card_state);
14a08a7f 2275
030f05ed
AK		 2276void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2277 struct iwl_rx_mem_buffer *rxb)
2278{
2279#ifdef CONFIG_IWLWIFI_DEBUG
2280 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2281 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2282 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2283 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2284#endif
2285}
2286EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2287
2288void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2289 struct iwl_rx_mem_buffer *rxb)
2290{
2291 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2292 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
2293 "notification for %s:\n",
2294 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
2295 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
2296}
2297EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2298
2299void iwl_rx_reply_error(struct iwl_priv *priv,
2300 struct iwl_rx_mem_buffer *rxb)
2301{
2302 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2303
2304 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2305 "seq 0x%04X ser 0x%08X\n",
2306 le32_to_cpu(pkt->u.err_resp.error_type),
2307 get_cmd_string(pkt->u.err_resp.cmd_id),
2308 pkt->u.err_resp.cmd_id,
2309 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2310 le32_to_cpu(pkt->u.err_resp.error_info));
2311}
2312EXPORT_SYMBOL(iwl_rx_reply_error);
2313
a83b9141
WYG		 2314void iwl_clear_isr_stats(struct iwl_priv *priv)
2315{
2316 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2317}
2318EXPORT_SYMBOL(iwl_clear_isr_stats);
2319
488829f1
AK		 2320int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2321 const struct ieee80211_tx_queue_params *params)
2322{
2323 struct iwl_priv *priv = hw->priv;
2324 unsigned long flags;
2325 int q;
2326
2327 IWL_DEBUG_MAC80211(priv, "enter\n");
2328
2329 if (!iwl_is_ready_rf(priv)) {
2330 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2331 return -EIO;
2332 }
2333
2334 if (queue >= AC_NUM) {
2335 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2336 return 0;
2337 }
2338
2339 q = AC_NUM - 1 - queue;
2340
2341 spin_lock_irqsave(&priv->lock, flags);
2342
2343 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2344 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2345 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2346 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2347 cpu_to_le16((params->txop * 32));
2348
2349 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2350 priv->qos_data.qos_active = 1;
2351
2352 if (priv->iw_mode == NL80211_IFTYPE_AP)
2353 iwl_activate_qos(priv, 1);
2354 else if (priv->assoc_id && iwl_is_associated(priv))
2355 iwl_activate_qos(priv, 0);
2356
2357 spin_unlock_irqrestore(&priv->lock, flags);
2358
2359 IWL_DEBUG_MAC80211(priv, "leave\n");
2360 return 0;
2361}
2362EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2363
2364static void iwl_ht_conf(struct iwl_priv *priv,
2365 struct ieee80211_bss_conf *bss_conf)
2366{
2367 struct ieee80211_sta_ht_cap *ht_conf;
2368 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
2369 struct ieee80211_sta *sta;
2370
2371 IWL_DEBUG_MAC80211(priv, "enter: \n");
2372
2373 if (!iwl_conf->is_ht)
2374 return;
2375
2376
2377 /*
2378 * It is totally wrong to base global information on something
2379 * that is valid only when associated, alas, this driver works
2380 * that way and I don't know how to fix it.
2381 */
2382
2383 rcu_read_lock();
2384 sta = ieee80211_find_sta(priv->hw, priv->bssid);
2385 if (!sta) {
2386 rcu_read_unlock();
2387 return;
2388 }
2389 ht_conf = &sta->ht_cap;
2390
2391 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
2392 iwl_conf->sgf |= HT_SHORT_GI_20MHZ;
2393 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
2394 iwl_conf->sgf |= HT_SHORT_GI_40MHZ;
2395
2396 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
2397 iwl_conf->max_amsdu_size =
2398 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
2399
2400 iwl_conf->supported_chan_width =
2401 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
2402
2403 /*
2404 * XXX: The HT configuration needs to be moved into iwl_mac_config()
2405 * to be done there correctly.
2406 */
2407
2408 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
2409 if (conf_is_ht40_minus(&priv->hw->conf))
2410 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2411 else if (conf_is_ht40_plus(&priv->hw->conf))
2412 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2413
2414 /* If no above or below channel supplied disable FAT channel */
2415 if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE &&
2416 iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW)
2417 iwl_conf->supported_chan_width = 0;
2418
2419 iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
2420
2421 memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
2422
2423 iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0;
2424 iwl_conf->ht_protection =
9ed6bcce 2425 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
5bbe233b 2426 iwl_conf->non_GF_STA_present =
9ed6bcce 2427 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b
AK		 2428
2429 rcu_read_unlock();
2430
2431 IWL_DEBUG_MAC80211(priv, "leave\n");
2432}
2433
2434#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2435void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2436 struct ieee80211_vif *vif,
2437 struct ieee80211_bss_conf *bss_conf,
2438 u32 changes)
5bbe233b
AK		 2439{
2440 struct iwl_priv *priv = hw->priv;
3a650292 2441 int ret;
5bbe233b
AK		 2442
2443 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2444
2d0ddec5
JB		 2445 if (!iwl_is_alive(priv))
2446 return;
2447
2448 mutex_lock(&priv->mutex);
2449
2450 if (changes & BSS_CHANGED_BEACON &&
2451 priv->iw_mode == NL80211_IFTYPE_AP) {
2452 dev_kfree_skb(priv->ibss_beacon);
2453 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2454 }
2455
d7129e19
JB		 2456 if (changes & BSS_CHANGED_BEACON_INT) {
2457 priv->beacon_int = bss_conf->beacon_int;
2458 /* TODO: in AP mode, do something to make this take effect */
2459 }
2460
2461 if (changes & BSS_CHANGED_BSSID) {
2462 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2463
2464 /*
2465 * If there is currently a HW scan going on in the
2466 * background then we need to cancel it else the RXON
2467 * below/in post_associate will fail.
2468 */
2d0ddec5 2469 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2470 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2471 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2472 mutex_unlock(&priv->mutex);
2473 return;
2474 }
2d0ddec5 2475
d7129e19
JB		 2476 /* mac80211 only sets assoc when in STATION mode */
2477 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2478 bss_conf->assoc) {
2479 memcpy(priv->staging_rxon.bssid_addr,
2480 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2481
d7129e19
JB		 2482 /* currently needed in a few places */
2483 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2484 } else {
2485 priv->staging_rxon.filter_flags &=
2486 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2487 }
d7129e19 2488
2d0ddec5
JB		 2489 }
2490
d7129e19
JB		 2491 /*
2492 * This needs to be after setting the BSSID in case
2493 * mac80211 decides to do both changes at once because
2494 * it will invoke post_associate.
2495 */
2d0ddec5
JB		 2496 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2497 changes & BSS_CHANGED_BEACON) {
2498 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2499
2500 if (beacon)
2501 iwl_mac_beacon_update(hw, beacon);
2502 }
2503
5bbe233b
AK		 2504 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2505 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2506 bss_conf->use_short_preamble);
2507 if (bss_conf->use_short_preamble)
2508 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2509 else
2510 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2511 }
2512
2513 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2514 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2515 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2516 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2517 else
2518 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2519 }
2520
d7129e19
JB		 2521 if (changes & BSS_CHANGED_BASIC_RATES) {
2522 /* XXX use this information
2523 *
2524 * To do that, remove code from iwl_set_rate() and put something
2525 * like this here:
2526 *
2527 if (A-band)
2528 priv->staging_rxon.ofdm_basic_rates =
2529 bss_conf->basic_rates;
2530 else
2531 priv->staging_rxon.ofdm_basic_rates =
2532 bss_conf->basic_rates >> 4;
2533 priv->staging_rxon.cck_basic_rates =
2534 bss_conf->basic_rates & 0xF;
2535 */
2536 }
2537
5bbe233b
AK		 2538 if (changes & BSS_CHANGED_HT) {
2539 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2540
2541 if (priv->cfg->ops->hcmd->set_rxon_chain)
2542 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2543 }
2544
2545 if (changes & BSS_CHANGED_ASSOC) {
2546 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2547 if (bss_conf->assoc) {
2548 priv->assoc_id = bss_conf->aid;
2549 priv->beacon_int = bss_conf->beacon_int;
2550 priv->power_data.dtim_period = bss_conf->dtim_period;
2551 priv->timestamp = bss_conf->timestamp;
2552 priv->assoc_capability = bss_conf->assoc_capability;
2553
d7129e19
JB		 2554 /*
2555 * We have just associated, don't start scan too early
2556 * leave time for EAPOL exchange to complete.
2557 *
2558 * XXX: do this in mac80211
5bbe233b
AK		 2559 */
2560 priv->next_scan_jiffies = jiffies +
2561 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2562 if (!iwl_is_rfkill(priv))
2563 priv->cfg->ops->lib->post_associate(priv);
2564 } else
5bbe233b 2565 priv->assoc_id = 0;
d7129e19
JB		 2566
2567 }
2568
2569 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2570 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2571 changes);
2572 ret = iwl_send_rxon_assoc(priv);
2573 if (!ret) {
2574 /* Sync active_rxon with latest change. */
2575 memcpy((void *)&priv->active_rxon,
2576 &priv->staging_rxon,
2577 sizeof(struct iwl_rxon_cmd));
5bbe233b 2578 }
5bbe233b 2579 }
d7129e19
JB		 2580
2581 mutex_unlock(&priv->mutex);
2582
2d0ddec5 2583 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2584}
2585EXPORT_SYMBOL(iwl_bss_info_changed);
2586
9944b938
AK		 2587int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2588{
2589 struct iwl_priv *priv = hw->priv;
2590 unsigned long flags;
2591 __le64 timestamp;
2592
2593 IWL_DEBUG_MAC80211(priv, "enter\n");
2594
2595 if (!iwl_is_ready_rf(priv)) {
2596 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2597 return -EIO;
2598 }
2599
2600 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2601 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2602 return -EIO;
2603 }
2604
2605 spin_lock_irqsave(&priv->lock, flags);
2606
2607 if (priv->ibss_beacon)
2608 dev_kfree_skb(priv->ibss_beacon);
2609
2610 priv->ibss_beacon = skb;
2611
2612 priv->assoc_id = 0;
2613 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2614 priv->timestamp = le64_to_cpu(timestamp);
2615
2616 IWL_DEBUG_MAC80211(priv, "leave\n");
2617 spin_unlock_irqrestore(&priv->lock, flags);
2618
2619 iwl_reset_qos(priv);
2620
2621 priv->cfg->ops->lib->post_associate(priv);
2622
2623
2624 return 0;
2625}
2626EXPORT_SYMBOL(iwl_mac_beacon_update);
2627
727882d6
AK		 2628int iwl_set_mode(struct iwl_priv *priv, int mode)
2629{
2630 if (mode == NL80211_IFTYPE_ADHOC) {
2631 const struct iwl_channel_info *ch_info;
2632
2633 ch_info = iwl_get_channel_info(priv,
2634 priv->band,
2635 le16_to_cpu(priv->staging_rxon.channel));
2636
2637 if (!ch_info || !is_channel_ibss(ch_info)) {
2638 IWL_ERR(priv, "channel %d not IBSS channel\n",
2639 le16_to_cpu(priv->staging_rxon.channel));
2640 return -EINVAL;
2641 }
2642 }
2643
2644 iwl_connection_init_rx_config(priv, mode);
2645
2646 if (priv->cfg->ops->hcmd->set_rxon_chain)
2647 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2648
2649 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2650
c587de0b 2651 iwl_clear_stations_table(priv);
727882d6
AK		 2652
2653 /* dont commit rxon if rf-kill is on*/
2654 if (!iwl_is_ready_rf(priv))
2655 return -EAGAIN;
2656
727882d6
AK		 2657 iwlcore_commit_rxon(priv);
2658
2659 return 0;
2660}
2661EXPORT_SYMBOL(iwl_set_mode);
2662
cbb6ab94
AK		 2663int iwl_mac_add_interface(struct ieee80211_hw *hw,
2664 struct ieee80211_if_init_conf *conf)
2665{
2666 struct iwl_priv *priv = hw->priv;
2667 unsigned long flags;
2668
2669 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2670
2671 if (priv->vif) {
2672 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2673 return -EOPNOTSUPP;
2674 }
2675
2676 spin_lock_irqsave(&priv->lock, flags);
2677 priv->vif = conf->vif;
2678 priv->iw_mode = conf->type;
2679
2680 spin_unlock_irqrestore(&priv->lock, flags);
2681
2682 mutex_lock(&priv->mutex);
2683
2684 if (conf->mac_addr) {
2685 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2686 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2687 }
2688
2689 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2690 /* we are not ready, will run again when ready */
2691 set_bit(STATUS_MODE_PENDING, &priv->status);
2692
2693 mutex_unlock(&priv->mutex);
2694
2695 IWL_DEBUG_MAC80211(priv, "leave\n");
2696 return 0;
2697}
2698EXPORT_SYMBOL(iwl_mac_add_interface);
2699
d8052319
AK		 2700void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2701 struct ieee80211_if_init_conf *conf)
2702{
2703 struct iwl_priv *priv = hw->priv;
2704
2705 IWL_DEBUG_MAC80211(priv, "enter\n");
2706
2707 mutex_lock(&priv->mutex);
2708
2709 if (iwl_is_ready_rf(priv)) {
2710 iwl_scan_cancel_timeout(priv, 100);
2711 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2712 iwlcore_commit_rxon(priv);
2713 }
2714 if (priv->vif == conf->vif) {
2715 priv->vif = NULL;
2716 memset(priv->bssid, 0, ETH_ALEN);
2717 }
2718 mutex_unlock(&priv->mutex);
2719
2720 IWL_DEBUG_MAC80211(priv, "leave\n");
2721
2722}
2723EXPORT_SYMBOL(iwl_mac_remove_interface);
2724
4808368d
AK		 2725/**
2726 * iwl_mac_config - mac80211 config callback
2727 *
2728 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2729 * be set inappropriately and the driver currently sets the hardware up to
2730 * use it whenever needed.
2731 */
2732int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2733{
2734 struct iwl_priv *priv = hw->priv;
2735 const struct iwl_channel_info *ch_info;
2736 struct ieee80211_conf *conf = &hw->conf;
2737 unsigned long flags = 0;
2738 int ret = 0;
2739 u16 ch;
2740 int scan_active = 0;
2741
2742 mutex_lock(&priv->mutex);
2743
4808368d
AK		 2744 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2745 conf->channel->hw_value, changed);
2746
2747 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2748 test_bit(STATUS_SCANNING, &priv->status))) {
2749 scan_active = 1;
2750 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2751 }
2752
2753
2754 /* during scanning mac80211 will delay channel setting until
2755 * scan finish with changed = 0
2756 */
2757 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2758 if (scan_active)
2759 goto set_ch_out;
2760
2761 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2762 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2763 if (!is_channel_valid(ch_info)) {
2764 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2765 ret = -EINVAL;
2766 goto set_ch_out;
2767 }
2768
2769 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2770 !is_channel_ibss(ch_info)) {
2771 IWL_ERR(priv, "channel %d in band %d not "
2772 "IBSS channel\n",
2773 conf->channel->hw_value, conf->channel->band);
2774 ret = -EINVAL;
2775 goto set_ch_out;
2776 }
2777
2778 priv->current_ht_config.is_ht = conf_is_ht(conf);
2779
2780 spin_lock_irqsave(&priv->lock, flags);
2781
2782
2783 /* if we are switching from ht to 2.4 clear flags
2784 * from any ht related info since 2.4 does not
2785 * support ht */
2786 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2787 priv->staging_rxon.flags = 0;
2788
2789 iwl_set_rxon_channel(priv, conf->channel);
2790
2791 iwl_set_flags_for_band(priv, conf->channel->band);
2792 spin_unlock_irqrestore(&priv->lock, flags);
2793 set_ch_out:
2794 /* The list of supported rates and rate mask can be different
2795 * for each band; since the band may have changed, reset
2796 * the rate mask to what mac80211 lists */
2797 iwl_set_rate(priv);
2798 }
2799
7af2c460
JB		 2800 if (changed & IEEE80211_CONF_CHANGE_PS &&
2801 priv->iw_mode == NL80211_IFTYPE_STATION) {
2802 priv->power_data.power_disabled =
2803 !(conf->flags & IEEE80211_CONF_PS);
2804 ret = iwl_power_update_mode(priv, 0);
4808368d
AK		 2805 if (ret)
2806 IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
4808368d
AK		 2807 }
2808
2809 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2810 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2811 priv->tx_power_user_lmt, conf->power_level);
2812
2813 iwl_set_tx_power(priv, conf->power_level, false);
2814 }
2815
2816 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2817 if (priv->cfg->ops->hcmd->set_rxon_chain)
2818 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2819
0cf4c01e
MA		 2820 if (!iwl_is_ready(priv)) {
2821 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2822 goto out;
2823 }
2824
4808368d
AK		 2825 if (scan_active)
2826 goto out;
2827
2828 if (memcmp(&priv->active_rxon,
2829 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2830 iwlcore_commit_rxon(priv);
2831 else
2832 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2833
2834
2835out:
2836 IWL_DEBUG_MAC80211(priv, "leave\n");
2837 mutex_unlock(&priv->mutex);
2838 return ret;
2839}
2840EXPORT_SYMBOL(iwl_mac_config);
2841
aa89f31e
AK		 2842int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2843 struct ieee80211_tx_queue_stats *stats)
2844{
2845 struct iwl_priv *priv = hw->priv;
2846 int i, avail;
2847 struct iwl_tx_queue *txq;
2848 struct iwl_queue *q;
2849 unsigned long flags;
2850
2851 IWL_DEBUG_MAC80211(priv, "enter\n");
2852
2853 if (!iwl_is_ready_rf(priv)) {
2854 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2855 return -EIO;
2856 }
2857
2858 spin_lock_irqsave(&priv->lock, flags);
2859
2860 for (i = 0; i < AC_NUM; i++) {
2861 txq = &priv->txq[i];
2862 q = &txq->q;
2863 avail = iwl_queue_space(q);
2864
2865 stats[i].len = q->n_window - avail;
2866 stats[i].limit = q->n_window - q->high_mark;
2867 stats[i].count = q->n_window;
2868
2869 }
2870 spin_unlock_irqrestore(&priv->lock, flags);
2871
2872 IWL_DEBUG_MAC80211(priv, "leave\n");
2873
2874 return 0;
2875}
2876EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2877
bd564261
AK		 2878void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2879{
2880 struct iwl_priv *priv = hw->priv;
2881 unsigned long flags;
2882
2883 mutex_lock(&priv->mutex);
2884 IWL_DEBUG_MAC80211(priv, "enter\n");
2885
2886 spin_lock_irqsave(&priv->lock, flags);
2887 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
2888 spin_unlock_irqrestore(&priv->lock, flags);
2889
2890 iwl_reset_qos(priv);
2891
2892 spin_lock_irqsave(&priv->lock, flags);
2893 priv->assoc_id = 0;
2894 priv->assoc_capability = 0;
2895 priv->assoc_station_added = 0;
2896
2897 /* new association get rid of ibss beacon skb */
2898 if (priv->ibss_beacon)
2899 dev_kfree_skb(priv->ibss_beacon);
2900
2901 priv->ibss_beacon = NULL;
2902
57c4d7b4 2903 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2904 priv->timestamp = 0;
2905 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2906 priv->beacon_int = 0;
2907
2908 spin_unlock_irqrestore(&priv->lock, flags);
2909
2910 if (!iwl_is_ready_rf(priv)) {
2911 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2912 mutex_unlock(&priv->mutex);
2913 return;
2914 }
2915
2916 /* we are restarting association process
2917 * clear RXON_FILTER_ASSOC_MSK bit
2918 */
2919 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2920 iwl_scan_cancel_timeout(priv, 100);
2921 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2922 iwlcore_commit_rxon(priv);
2923 }
2924
bd564261 2925 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2926 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2927 mutex_unlock(&priv->mutex);
2928 return;
2929 }
2930
2931 iwl_set_rate(priv);
2932
2933 mutex_unlock(&priv->mutex);
2934
2935 IWL_DEBUG_MAC80211(priv, "leave\n");
2936}
2937EXPORT_SYMBOL(iwl_mac_reset_tsf);
2938
6da3a13e
WYG		 2939#ifdef CONFIG_PM
2940
2941int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2942{
2943 struct iwl_priv *priv = pci_get_drvdata(pdev);
2944
2945 /*
2946 * This function is called when system goes into suspend state
2947 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
2948 * first but since iwl_mac_stop() has no knowledge of who the caller is,
2949 * it will not call apm_ops.stop() to stop the DMA operation.
2950 * Calling apm_ops.stop here to make sure we stop the DMA.
2951 */
2952 priv->cfg->ops->lib->apm_ops.stop(priv);
2953
2954 pci_save_state(pdev);
2955 pci_disable_device(pdev);
2956 pci_set_power_state(pdev, PCI_D3hot);
2957
2958 return 0;
2959}
2960EXPORT_SYMBOL(iwl_pci_suspend);
2961
2962int iwl_pci_resume(struct pci_dev *pdev)
2963{
2964 struct iwl_priv *priv = pci_get_drvdata(pdev);
2965 int ret;
2966
2967 pci_set_power_state(pdev, PCI_D0);
2968 ret = pci_enable_device(pdev);
2969 if (ret)
2970 return ret;
2971 pci_restore_state(pdev);
2972 iwl_enable_interrupts(priv);
2973
2974 return 0;
2975}
2976EXPORT_SYMBOL(iwl_pci_resume);
2977
2978#endif /* CONFIG_PM */
Linux kernel - Deliverables
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