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iwlwifi: new debugging feature for dumping data traffic
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
a562a9dd
RC		 62u32 iwl_debug_level;
63EXPORT_SYMBOL(iwl_debug_level);
64
ef850d7c
MA		 65static irqreturn_t iwl_isr(int irq, void *data);
66
c7de35cd
RR		 67/*
68 * Parameter order:
69 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
1826dcc0 75const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 76 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
88 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
89 /* FIXME:RS: ^^ should be INV (legacy) */
90};
1826dcc0 91EXPORT_SYMBOL(iwl_rates);
c7de35cd 92
e7d326ac
TW		 93/**
94 * translate ucode response to mac80211 tx status control values
95 */
96void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 97 struct ieee80211_tx_info *info)
e7d326ac
TW		 98{
99 int rate_index;
e6a9854b 100 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 101
e6a9854b 102 info->antenna_sel_tx =
e7d326ac
TW		 103 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
104 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 105 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 106 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 107 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 108 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 109 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 110 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 111 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 112 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 113 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 114 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 115 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 116 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 117 r->idx = rate_index;
e7d326ac
TW		 118}
119EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
120
121int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
122{
123 int idx = 0;
124
125 /* HT rate format */
126 if (rate_n_flags & RATE_MCS_HT_MSK) {
127 idx = (rate_n_flags & 0xff);
128
60d32215
DH		 129 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
130 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
131 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 132 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
133
134 idx += IWL_FIRST_OFDM_RATE;
135 /* skip 9M not supported in ht*/
136 if (idx >= IWL_RATE_9M_INDEX)
137 idx += 1;
138 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
139 return idx;
140
141 /* legacy rate format, search for match in table */
142 } else {
143 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
144 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
145 return idx;
146 }
147
148 return -1;
149}
150EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
151
76eff18b
TW		 152u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
153{
154 int i;
155 u8 ind = ant;
156 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
157 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
158 if (priv->hw_params.valid_tx_ant & BIT(ind))
159 return ind;
160 }
161 return ant;
162}
57bd1bea
TW		 163
164const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
165EXPORT_SYMBOL(iwl_bcast_addr);
166
167
1d0a082d
AK		 168/* This function both allocates and initializes hw and priv. */
169struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
170 struct ieee80211_ops *hw_ops)
171{
172 struct iwl_priv *priv;
173
174 /* mac80211 allocates memory for this device instance, including
175 * space for this driver's private structure */
176 struct ieee80211_hw *hw =
177 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
178 if (hw == NULL) {
a3139c59
SO		 179 printk(KERN_ERR "%s: Can not allocate network device\n",
180 cfg->name);
1d0a082d
AK		 181 goto out;
182 }
183
184 priv = hw->priv;
185 priv->hw = hw;
186
187out:
188 return hw;
189}
190EXPORT_SYMBOL(iwl_alloc_all);
191
b661c819
TW		 192void iwl_hw_detect(struct iwl_priv *priv)
193{
194 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
195 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
196 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
197}
198EXPORT_SYMBOL(iwl_hw_detect);
199
1053d35f
RR		 200int iwl_hw_nic_init(struct iwl_priv *priv)
201{
202 unsigned long flags;
203 struct iwl_rx_queue *rxq = &priv->rxq;
204 int ret;
205
206 /* nic_init */
1053d35f 207 spin_lock_irqsave(&priv->lock, flags);
1b73af82 208 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 209 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
210 spin_unlock_irqrestore(&priv->lock, flags);
211
212 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
213
214 priv->cfg->ops->lib->apm_ops.config(priv);
215
216 /* Allocate the RX queue, or reset if it is already allocated */
217 if (!rxq->bd) {
218 ret = iwl_rx_queue_alloc(priv);
219 if (ret) {
15b1687c 220 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 221 return -ENOMEM;
222 }
223 } else
224 iwl_rx_queue_reset(priv, rxq);
225
226 iwl_rx_replenish(priv);
227
228 iwl_rx_init(priv, rxq);
229
230 spin_lock_irqsave(&priv->lock, flags);
231
232 rxq->need_update = 1;
233 iwl_rx_queue_update_write_ptr(priv, rxq);
234
235 spin_unlock_irqrestore(&priv->lock, flags);
236
237 /* Allocate and init all Tx and Command queues */
238 ret = iwl_txq_ctx_reset(priv);
239 if (ret)
240 return ret;
241
242 set_bit(STATUS_INIT, &priv->status);
243
244 return 0;
245}
246EXPORT_SYMBOL(iwl_hw_nic_init);
247
14d2aac5
AK		 248/*
249 * QoS support
250*/
251void iwl_activate_qos(struct iwl_priv *priv, u8 force)
252{
253 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
254 return;
255
256 priv->qos_data.def_qos_parm.qos_flags = 0;
257
258 if (priv->qos_data.qos_cap.q_AP.queue_request &&
259 !priv->qos_data.qos_cap.q_AP.txop_request)
260 priv->qos_data.def_qos_parm.qos_flags |=
261 QOS_PARAM_FLG_TXOP_TYPE_MSK;
262 if (priv->qos_data.qos_active)
263 priv->qos_data.def_qos_parm.qos_flags |=
264 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
265
266 if (priv->current_ht_config.is_ht)
267 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
268
269 if (force || iwl_is_associated(priv)) {
270 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
271 priv->qos_data.qos_active,
272 priv->qos_data.def_qos_parm.qos_flags);
273
274 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
275 sizeof(struct iwl_qosparam_cmd),
276 &priv->qos_data.def_qos_parm, NULL);
277 }
278}
279EXPORT_SYMBOL(iwl_activate_qos);
280
f2c95b04
WYG		 281/*
282 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
283 * (802.11b) (802.11a/g)
284 * AC_BK 15 1023 7 0 0
285 * AC_BE 15 1023 3 0 0
286 * AC_VI 7 15 2 6.016ms 3.008ms
287 * AC_VO 3 7 2 3.264ms 1.504ms
288 */
c7de35cd 289void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 290{
291 u16 cw_min = 15;
292 u16 cw_max = 1023;
293 u8 aifs = 2;
30dab79e 294 bool is_legacy = false;
bf85ea4f
AK		 295 unsigned long flags;
296 int i;
297
298 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 299 /* QoS always active in AP and ADHOC mode
300 * In STA mode wait for association
301 */
302 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
303 priv->iw_mode == NL80211_IFTYPE_AP)
304 priv->qos_data.qos_active = 1;
305 else
306 priv->qos_data.qos_active = 0;
bf85ea4f 307
30dab79e
WT		 308 /* check for legacy mode */
309 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
310 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
311 (priv->iw_mode == NL80211_IFTYPE_STATION &&
312 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 313 cw_min = 31;
314 is_legacy = 1;
315 }
316
317 if (priv->qos_data.qos_active)
318 aifs = 3;
319
f2c95b04 320 /* AC_BE */
bf85ea4f
AK		 321 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
322 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
323 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
324 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
325 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
326
327 if (priv->qos_data.qos_active) {
f2c95b04 328 /* AC_BK */
bf85ea4f
AK		 329 i = 1;
330 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
331 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
332 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
333 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
334 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
335
f2c95b04 336 /* AC_VI */
bf85ea4f
AK		 337 i = 2;
338 priv->qos_data.def_qos_parm.ac[i].cw_min =
339 cpu_to_le16((cw_min + 1) / 2 - 1);
340 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 341 cpu_to_le16(cw_min);
bf85ea4f
AK		 342 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
343 if (is_legacy)
344 priv->qos_data.def_qos_parm.ac[i].edca_txop =
345 cpu_to_le16(6016);
346 else
347 priv->qos_data.def_qos_parm.ac[i].edca_txop =
348 cpu_to_le16(3008);
349 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
350
f2c95b04 351 /* AC_VO */
bf85ea4f
AK		 352 i = 3;
353 priv->qos_data.def_qos_parm.ac[i].cw_min =
354 cpu_to_le16((cw_min + 1) / 4 - 1);
355 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 356 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 357 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
358 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
359 if (is_legacy)
360 priv->qos_data.def_qos_parm.ac[i].edca_txop =
361 cpu_to_le16(3264);
362 else
363 priv->qos_data.def_qos_parm.ac[i].edca_txop =
364 cpu_to_le16(1504);
365 } else {
366 for (i = 1; i < 4; i++) {
367 priv->qos_data.def_qos_parm.ac[i].cw_min =
368 cpu_to_le16(cw_min);
369 priv->qos_data.def_qos_parm.ac[i].cw_max =
370 cpu_to_le16(cw_max);
371 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
372 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
373 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
374 }
375 }
e1623446 376 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 377
378 spin_unlock_irqrestore(&priv->lock, flags);
379}
c7de35cd
RR		 380EXPORT_SYMBOL(iwl_reset_qos);
381
d9fe60de
JB		 382#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
383#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 384static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 385 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 386 enum ieee80211_band band)
387{
39130df3
RR		 388 u16 max_bit_rate = 0;
389 u8 rx_chains_num = priv->hw_params.rx_chains_num;
390 u8 tx_chains_num = priv->hw_params.tx_chains_num;
391
c7de35cd 392 ht_info->cap = 0;
d9fe60de 393 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 394
d9fe60de 395 ht_info->ht_supported = true;
c7de35cd 396
d9fe60de
JB		 397 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
398 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
399 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 400 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 401
402 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 403 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 404 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
405 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
406 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 407 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 408 }
c7de35cd
RR		 409
410 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 411 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 412
413 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
414 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
415
d9fe60de 416 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 417 if (rx_chains_num >= 2)
d9fe60de 418 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 419 if (rx_chains_num >= 3)
d9fe60de 420 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 421
422 /* Highest supported Rx data rate */
423 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 424 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
425 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 426
427 /* Tx MCS capabilities */
d9fe60de 428 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 429 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 430 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
431 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
432 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 433 }
c7de35cd 434}
c7de35cd
RR		 435
436static void iwlcore_init_hw_rates(struct iwl_priv *priv,
437 struct ieee80211_rate *rates)
438{
439 int i;
440
441 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 442 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 443 rates[i].hw_value = i; /* Rate scaling will work on indexes */
444 rates[i].hw_value_short = i;
445 rates[i].flags = 0;
446 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
447 /*
448 * If CCK != 1M then set short preamble rate flag.
449 */
450 rates[i].flags |=
1826dcc0 451 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 452 0 : IEEE80211_RATE_SHORT_PREAMBLE;
453 }
454 }
455}
456
8ccde88a 457
c7de35cd
RR		 458/**
459 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
460 */
534166de 461int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 462{
463 struct iwl_channel_info *ch;
464 struct ieee80211_supported_band *sband;
465 struct ieee80211_channel *channels;
466 struct ieee80211_channel *geo_ch;
467 struct ieee80211_rate *rates;
468 int i = 0;
469
470 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
471 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 472 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 473 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
474 return 0;
475 }
476
477 channels = kzalloc(sizeof(struct ieee80211_channel) *
478 priv->channel_count, GFP_KERNEL);
479 if (!channels)
480 return -ENOMEM;
481
482 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
483 GFP_KERNEL);
484 if (!rates) {
485 kfree(channels);
486 return -ENOMEM;
487 }
488
489 /* 5.2GHz channels start after the 2.4GHz channels */
490 sband = &priv->bands[IEEE80211_BAND_5GHZ];
491 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
492 /* just OFDM */
493 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
494 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
495
49779293 496 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 497 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 498 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 499
500 sband = &priv->bands[IEEE80211_BAND_2GHZ];
501 sband->channels = channels;
502 /* OFDM & CCK */
503 sband->bitrates = rates;
504 sband->n_bitrates = IWL_RATE_COUNT;
505
49779293 506 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 507 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 508 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 509
510 priv->ieee_channels = channels;
511 priv->ieee_rates = rates;
512
c7de35cd
RR		 513 for (i = 0; i < priv->channel_count; i++) {
514 ch = &priv->channel_info[i];
515
516 /* FIXME: might be removed if scan is OK */
517 if (!is_channel_valid(ch))
518 continue;
519
520 if (is_channel_a_band(ch))
521 sband = &priv->bands[IEEE80211_BAND_5GHZ];
522 else
523 sband = &priv->bands[IEEE80211_BAND_2GHZ];
524
525 geo_ch = &sband->channels[sband->n_channels++];
526
527 geo_ch->center_freq =
528 ieee80211_channel_to_frequency(ch->channel);
529 geo_ch->max_power = ch->max_power_avg;
530 geo_ch->max_antenna_gain = 0xff;
531 geo_ch->hw_value = ch->channel;
532
533 if (is_channel_valid(ch)) {
534 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
535 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
536
537 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
538 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
539
540 if (ch->flags & EEPROM_CHANNEL_RADAR)
541 geo_ch->flags |= IEEE80211_CHAN_RADAR;
542
7aafef1c 543 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 544
630fe9b6
TW		 545 if (ch->max_power_avg > priv->tx_power_channel_lmt)
546 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 547 } else {
548 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
549 }
550
e1623446 551 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 552 ch->channel, geo_ch->center_freq,
553 is_channel_a_band(ch) ? "5.2" : "2.4",
554 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
555 "restricted" : "valid",
556 geo_ch->flags);
557 }
558
559 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
560 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 561 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
562 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 563 priv->pci_dev->device,
564 priv->pci_dev->subsystem_device);
c7de35cd
RR		 565 priv->cfg->sku &= ~IWL_SKU_A;
566 }
567
978785a3 568 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 569 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
570 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 571
572 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
573
574 return 0;
575}
534166de 576EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 577
578/*
579 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
580 */
534166de 581void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 582{
583 kfree(priv->ieee_channels);
584 kfree(priv->ieee_rates);
585 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
586}
534166de 587EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 588
28a6b07a 589static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 590{
591 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 592 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
593 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 594}
963f5517 595
47c5196e
TW		 596static u8 iwl_is_channel_extension(struct iwl_priv *priv,
597 enum ieee80211_band band,
598 u16 channel, u8 extension_chan_offset)
599{
600 const struct iwl_channel_info *ch_info;
601
602 ch_info = iwl_get_channel_info(priv, band, channel);
603 if (!is_channel_valid(ch_info))
604 return 0;
605
d9fe60de 606 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 607 return !(ch_info->ht40_extension_channel &
689da1b3 608 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 609 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 610 return !(ch_info->ht40_extension_channel &
689da1b3 611 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 612
613 return 0;
614}
615
7aafef1c 616u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 617 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 618{
619 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
620
621 if ((!iwl_ht_conf->is_ht) ||
a2b0f02e 622 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ))
47c5196e
TW		 623 return 0;
624
a2b0f02e
WYG		 625 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
626 * the bit will not set if it is pure 40MHz case
627 */
47c5196e 628 if (sta_ht_inf) {
a2b0f02e 629 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 630 return 0;
631 }
1e4247d4
WYG		 632#ifdef CONFIG_IWLWIFI_DEBUG
633 if (priv->disable_ht40)
634 return 0;
635#endif
611d3eb7
WYG		 636 return iwl_is_channel_extension(priv, priv->band,
637 le16_to_cpu(priv->staging_rxon.channel),
638 iwl_ht_conf->extension_chan_offset);
47c5196e 639}
7aafef1c 640EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 641
2c2f3b33
TW		 642static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
643{
644 u16 new_val = 0;
645 u16 beacon_factor = 0;
646
647 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
648 new_val = beacon_val / beacon_factor;
649
650 if (!new_val)
651 new_val = max_beacon_val;
652
653 return new_val;
654}
655
656void iwl_setup_rxon_timing(struct iwl_priv *priv)
657{
658 u64 tsf;
659 s32 interval_tm, rem;
660 unsigned long flags;
661 struct ieee80211_conf *conf = NULL;
662 u16 beacon_int;
663
664 conf = ieee80211_get_hw_conf(priv->hw);
665
666 spin_lock_irqsave(&priv->lock, flags);
667 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
668 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
669
670 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
671 beacon_int = priv->beacon_int;
672 priv->rxon_timing.atim_window = 0;
673 } else {
674 beacon_int = priv->vif->bss_conf.beacon_int;
675
676 /* TODO: we need to get atim_window from upper stack
677 * for now we set to 0 */
678 priv->rxon_timing.atim_window = 0;
679 }
680
681 beacon_int = iwl_adjust_beacon_interval(beacon_int,
682 priv->hw_params.max_beacon_itrvl * 1024);
683 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
684
685 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
686 interval_tm = beacon_int * 1024;
687 rem = do_div(tsf, interval_tm);
688 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
689
690 spin_unlock_irqrestore(&priv->lock, flags);
691 IWL_DEBUG_ASSOC(priv,
692 "beacon interval %d beacon timer %d beacon tim %d\n",
693 le16_to_cpu(priv->rxon_timing.beacon_interval),
694 le32_to_cpu(priv->rxon_timing.beacon_init_val),
695 le16_to_cpu(priv->rxon_timing.atim_window));
696}
697EXPORT_SYMBOL(iwl_setup_rxon_timing);
698
8ccde88a
SO		 699void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
700{
701 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
702
703 if (hw_decrypt)
704 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
705 else
706 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
707
708}
709EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
710
711/**
712 * iwl_check_rxon_cmd - validate RXON structure is valid
713 *
714 * NOTE: This is really only useful during development and can eventually
715 * be #ifdef'd out once the driver is stable and folks aren't actively
716 * making changes
717 */
718int iwl_check_rxon_cmd(struct iwl_priv *priv)
719{
720 int error = 0;
721 int counter = 1;
722 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
723
724 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
725 error |= le32_to_cpu(rxon->flags &
726 (RXON_FLG_TGJ_NARROW_BAND_MSK |
727 RXON_FLG_RADAR_DETECT_MSK));
728 if (error)
729 IWL_WARN(priv, "check 24G fields %d | %d\n",
730 counter++, error);
731 } else {
732 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
733 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
734 if (error)
735 IWL_WARN(priv, "check 52 fields %d | %d\n",
736 counter++, error);
737 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
738 if (error)
739 IWL_WARN(priv, "check 52 CCK %d | %d\n",
740 counter++, error);
741 }
742 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
743 if (error)
744 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
745
746 /* make sure basic rates 6Mbps and 1Mbps are supported */
747 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
748 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
749 if (error)
750 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
751
752 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
753 if (error)
754 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
755
756 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
757 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
758 if (error)
759 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
760 counter++, error);
761
762 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
763 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
764 if (error)
765 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
766 counter++, error);
767
768 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
769 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
770 if (error)
771 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
772 counter++, error);
773
774 if (error)
775 IWL_WARN(priv, "Tuning to channel %d\n",
776 le16_to_cpu(rxon->channel));
777
778 if (error) {
779 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
780 return -1;
781 }
782 return 0;
783}
784EXPORT_SYMBOL(iwl_check_rxon_cmd);
785
786/**
787 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
788 * @priv: staging_rxon is compared to active_rxon
789 *
790 * If the RXON structure is changing enough to require a new tune,
791 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
792 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
793 */
794int iwl_full_rxon_required(struct iwl_priv *priv)
795{
796
797 /* These items are only settable from the full RXON command */
798 if (!(iwl_is_associated(priv)) ||
799 compare_ether_addr(priv->staging_rxon.bssid_addr,
800 priv->active_rxon.bssid_addr) ||
801 compare_ether_addr(priv->staging_rxon.node_addr,
802 priv->active_rxon.node_addr) ||
803 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
804 priv->active_rxon.wlap_bssid_addr) ||
805 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
806 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
807 (priv->staging_rxon.air_propagation !=
808 priv->active_rxon.air_propagation) ||
809 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
810 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
811 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
812 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 813 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
814 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 815 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
816 return 1;
817
818 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
819 * be updated with the RXON_ASSOC command -- however only some
820 * flag transitions are allowed using RXON_ASSOC */
821
822 /* Check if we are not switching bands */
823 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
824 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
825 return 1;
826
827 /* Check if we are switching association toggle */
828 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
829 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
830 return 1;
831
832 return 0;
833}
834EXPORT_SYMBOL(iwl_full_rxon_required);
835
836u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
837{
838 int i;
839 int rate_mask;
840
841 /* Set rate mask*/
842 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
843 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
844 else
845 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
846
847 /* Find lowest valid rate */
848 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
849 i = iwl_rates[i].next_ieee) {
850 if (rate_mask & (1 << i))
851 return iwl_rates[i].plcp;
852 }
853
854 /* No valid rate was found. Assign the lowest one */
855 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
856 return IWL_RATE_1M_PLCP;
857 else
858 return IWL_RATE_6M_PLCP;
859}
860EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
861
47c5196e
TW		 862void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
863{
c1adf9fb 864 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 865
42eb7c64 866 if (!ht_info->is_ht) {
a2b0f02e 867 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 868 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 869 RXON_FLG_HT40_PROT_MSK |
42eb7c64 870 RXON_FLG_HT_PROT_MSK);
47c5196e 871 return;
42eb7c64 872 }
47c5196e 873
a2b0f02e
WYG		 874 /* FIXME: if the definition of ht_protection changed, the "translation"
875 * will be needed for rxon->flags
876 */
877 rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
878
879 /* Set up channel bandwidth:
7aafef1c 880 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 881 /* clear the HT channel mode before set the mode */
882 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
883 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 884 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
885 /* pure ht40 */
508b08e7 886 if (ht_info->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 887 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7
WYG		 888 /* Note: control channel is opposite of extension channel */
889 switch (ht_info->extension_chan_offset) {
890 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
891 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
892 break;
893 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
894 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
895 break;
896 }
897 } else {
a2b0f02e
WYG		 898 /* Note: control channel is opposite of extension channel */
899 switch (ht_info->extension_chan_offset) {
900 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
901 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
902 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
903 break;
904 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
905 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
906 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
907 break;
908 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
909 default:
910 /* channel location only valid if in Mixed mode */
911 IWL_ERR(priv, "invalid extension channel offset\n");
912 break;
913 }
914 }
915 } else {
916 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 917 }
918
45823531
AK		 919 if (priv->cfg->ops->hcmd->set_rxon_chain)
920 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 921
e1623446 922 IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
47c5196e 923 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 924 "extension channel offset 0x%x\n",
d9fe60de
JB		 925 ht_info->mcs.rx_mask[0],
926 ht_info->mcs.rx_mask[1],
927 ht_info->mcs.rx_mask[2],
47c5196e 928 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 929 ht_info->extension_chan_offset);
47c5196e
TW		 930 return;
931}
932EXPORT_SYMBOL(iwl_set_rxon_ht);
933
9e5e6c32
TW		 934#define IWL_NUM_RX_CHAINS_MULTIPLE 3
935#define IWL_NUM_RX_CHAINS_SINGLE 2
936#define IWL_NUM_IDLE_CHAINS_DUAL 2
937#define IWL_NUM_IDLE_CHAINS_SINGLE 1
938
939/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 940 * More provides better reception via diversity. Fewer saves power.
941 * MIMO (dual stream) requires at least 2, but works better with 3.
942 * This does not determine *which* chains to use, just how many.
943 */
28a6b07a 944static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 945{
28a6b07a
TW		 946 bool is_single = is_single_rx_stream(priv);
947 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 948
949 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 950 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
951 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 952 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 953 else
9e5e6c32 954 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 955}
c7de35cd 956
28a6b07a
TW		 957static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
958{
959 int idle_cnt;
960 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 961 /* # Rx chains when idling and maybe trying to save power */
12837be1 962 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 963 case WLAN_HT_CAP_SM_PS_STATIC:
964 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 965 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
966 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 967 break;
00c5ae2f 968 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 969 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 970 break;
00c5ae2f 971 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 972 default:
15b1687c 973 IWL_ERR(priv, "invalid mimo ps mode %d\n",
12837be1 974 priv->current_ht_config.sm_ps);
28a6b07a
TW		 975 WARN_ON(1);
976 idle_cnt = -1;
c7de35cd
RR		 977 break;
978 }
28a6b07a 979 return idle_cnt;
c7de35cd
RR		 980}
981
04816448
GE		 982/* up to 4 chains */
983static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
984{
985 u8 res;
986 res = (chain_bitmap & BIT(0)) >> 0;
987 res += (chain_bitmap & BIT(1)) >> 1;
988 res += (chain_bitmap & BIT(2)) >> 2;
989 res += (chain_bitmap & BIT(4)) >> 4;
990 return res;
991}
992
4c4df78f
CR		 993/**
994 * iwl_is_monitor_mode - Determine if interface in monitor mode
995 *
996 * priv->iw_mode is set in add_interface, but add_interface is
997 * never called for monitor mode. The only way mac80211 informs us about
998 * monitor mode is through configuring filters (call to configure_filter).
999 */
279b05d4 1000bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1001{
1002 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1003}
279b05d4 1004EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1005
c7de35cd
RR		 1006/**
1007 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1008 *
1009 * Selects how many and which Rx receivers/antennas/chains to use.
1010 * This should not be used for scan command ... it puts data in wrong place.
1011 */
1012void iwl_set_rxon_chain(struct iwl_priv *priv)
1013{
28a6b07a
TW		 1014 bool is_single = is_single_rx_stream(priv);
1015 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1016 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1017 u32 active_chains;
28a6b07a 1018 u16 rx_chain;
c7de35cd
RR		 1019
1020 /* Tell uCode which antennas are actually connected.
1021 * Before first association, we assume all antennas are connected.
1022 * Just after first association, iwl_chain_noise_calibration()
1023 * checks which antennas actually *are* connected. */
04816448
GE		 1024 if (priv->chain_noise_data.active_chains)
1025 active_chains = priv->chain_noise_data.active_chains;
1026 else
1027 active_chains = priv->hw_params.valid_rx_ant;
1028
1029 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1030
1031 /* How many receivers should we use? */
28a6b07a
TW		 1032 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1033 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1034
28a6b07a 1035
04816448
GE		 1036 /* correct rx chain count according hw settings
1037 * and chain noise calibration
1038 */
1039 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1040 if (valid_rx_cnt < active_rx_cnt)
1041 active_rx_cnt = valid_rx_cnt;
1042
1043 if (valid_rx_cnt < idle_rx_cnt)
1044 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1045
1046 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1047 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1048
7b841727
RF		 1049 /* copied from 'iwl_bg_request_scan()' */
1050 /* Force use of chains B and C (0x6) for Rx for 4965
1051 * Avoid A (0x1) because of its off-channel reception on A-band.
1052 * MIMO is not used here, but value is required */
1053 if (iwl_is_monitor_mode(priv) &&
1054 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1055 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1056 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1057 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1058 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1059 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1060 }
1061
28a6b07a
TW		 1062 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1063
9e5e6c32 1064 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1065 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1066 else
1067 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1068
e1623446 1069 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1070 priv->staging_rxon.rx_chain,
1071 active_rx_cnt, idle_rx_cnt);
1072
1073 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1074 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1075}
1076EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1077
1078/**
17e72782 1079 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1080 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1081 * @channel: Any channel valid for the requested phymode
1082
1083 * In addition to setting the staging RXON, priv->phymode is also set.
1084 *
1085 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1086 * in the staging RXON flag structure based on the phymode
1087 */
17e72782 1088int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1089{
17e72782
TW		 1090 enum ieee80211_band band = ch->band;
1091 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1092
8622e705 1093 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1094 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1095 channel, band);
1096 return -EINVAL;
1097 }
1098
1099 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1100 (priv->band == band))
1101 return 0;
1102
1103 priv->staging_rxon.channel = cpu_to_le16(channel);
1104 if (band == IEEE80211_BAND_5GHZ)
1105 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1106 else
1107 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1108
1109 priv->band = band;
1110
e1623446 1111 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1112
1113 return 0;
1114}
c7de35cd 1115EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1116
8ccde88a
SO		 1117void iwl_set_flags_for_band(struct iwl_priv *priv,
1118 enum ieee80211_band band)
1119{
1120 if (band == IEEE80211_BAND_5GHZ) {
1121 priv->staging_rxon.flags &=
1122 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1123 | RXON_FLG_CCK_MSK);
1124 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1125 } else {
1126 /* Copied from iwl_post_associate() */
1127 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1128 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1129 else
1130 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1131
1132 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1133 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1134
1135 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1136 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1137 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1138 }
1139}
8ccde88a
SO		 1140
1141/*
1142 * initialize rxon structure with default values from eeprom
1143 */
1144void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1145{
1146 const struct iwl_channel_info *ch_info;
1147
1148 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1149
1150 switch (mode) {
1151 case NL80211_IFTYPE_AP:
1152 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1153 break;
1154
1155 case NL80211_IFTYPE_STATION:
1156 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1157 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1158 break;
1159
1160 case NL80211_IFTYPE_ADHOC:
1161 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1162 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1163 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1164 RXON_FILTER_ACCEPT_GRP_MSK;
1165 break;
1166
8ccde88a
SO		 1167 default:
1168 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1169 break;
1170 }
1171
1172#if 0
1173 /* TODO: Figure out when short_preamble would be set and cache from
1174 * that */
1175 if (!hw_to_local(priv->hw)->short_preamble)
1176 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1177 else
1178 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1179#endif
1180
1181 ch_info = iwl_get_channel_info(priv, priv->band,
1182 le16_to_cpu(priv->active_rxon.channel));
1183
1184 if (!ch_info)
1185 ch_info = &priv->channel_info[0];
1186
1187 /*
1188 * in some case A channels are all non IBSS
1189 * in this case force B/G channel
1190 */
1191 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1192 !(is_channel_ibss(ch_info)))
1193 ch_info = &priv->channel_info[0];
1194
1195 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1196 priv->band = ch_info->band;
1197
1198 iwl_set_flags_for_band(priv, priv->band);
1199
1200 priv->staging_rxon.ofdm_basic_rates =
1201 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1202 priv->staging_rxon.cck_basic_rates =
1203 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1204
a2b0f02e
WYG		 1205 /* clear both MIX and PURE40 mode flag */
1206 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1207 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1208 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1209 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1210 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1211 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1212 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1213}
1214EXPORT_SYMBOL(iwl_connection_init_rx_config);
1215
782571f4 1216static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1217{
1218 const struct ieee80211_supported_band *hw = NULL;
1219 struct ieee80211_rate *rate;
1220 int i;
1221
1222 hw = iwl_get_hw_mode(priv, priv->band);
1223 if (!hw) {
1224 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1225 return;
1226 }
1227
1228 priv->active_rate = 0;
1229 priv->active_rate_basic = 0;
1230
1231 for (i = 0; i < hw->n_bitrates; i++) {
1232 rate = &(hw->bitrates[i]);
1233 if (rate->hw_value < IWL_RATE_COUNT)
1234 priv->active_rate |= (1 << rate->hw_value);
1235 }
1236
e1623446 1237 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1238 priv->active_rate, priv->active_rate_basic);
1239
1240 /*
1241 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1242 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1243 * OFDM
1244 */
1245 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1246 priv->staging_rxon.cck_basic_rates =
1247 ((priv->active_rate_basic &
1248 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1249 else
1250 priv->staging_rxon.cck_basic_rates =
1251 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1252
1253 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1254 priv->staging_rxon.ofdm_basic_rates =
1255 ((priv->active_rate_basic &
1256 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1257 IWL_FIRST_OFDM_RATE) & 0xFF;
1258 else
1259 priv->staging_rxon.ofdm_basic_rates =
1260 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1261}
8ccde88a
SO		 1262
1263void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1264{
1265 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1266 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1267 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
e1623446 1268 IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
8ccde88a
SO		 1269 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
1270 rxon->channel = csa->channel;
1271 priv->staging_rxon.channel = csa->channel;
1272}
1273EXPORT_SYMBOL(iwl_rx_csa);
1274
1275#ifdef CONFIG_IWLWIFI_DEBUG
1276static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1277{
1278 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1279
e1623446 1280 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1281 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1282 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1283 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1284 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1285 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1286 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1287 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1288 rxon->ofdm_basic_rates);
e1623446
TW		 1289 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1290 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1291 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1292 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1293}
8ccde88a 1294
a94ca4e7
JB		 1295static const char *desc_lookup_text[] = {
1296 "OK",
1297 "FAIL",
1298 "BAD_PARAM",
1299 "BAD_CHECKSUM",
1300 "NMI_INTERRUPT_WDG",
1301 "SYSASSERT",
1302 "FATAL_ERROR",
1303 "BAD_COMMAND",
1304 "HW_ERROR_TUNE_LOCK",
1305 "HW_ERROR_TEMPERATURE",
1306 "ILLEGAL_CHAN_FREQ",
1307 "VCC_NOT_STABLE",
1308 "FH_ERROR",
1309 "NMI_INTERRUPT_HOST",
1310 "NMI_INTERRUPT_ACTION_PT",
1311 "NMI_INTERRUPT_UNKNOWN",
1312 "UCODE_VERSION_MISMATCH",
1313 "HW_ERROR_ABS_LOCK",
1314 "HW_ERROR_CAL_LOCK_FAIL",
1315 "NMI_INTERRUPT_INST_ACTION_PT",
1316 "NMI_INTERRUPT_DATA_ACTION_PT",
1317 "NMI_TRM_HW_ER",
1318 "NMI_INTERRUPT_TRM",
1319 "NMI_INTERRUPT_BREAK_POINT"
1320 "DEBUG_0",
1321 "DEBUG_1",
1322 "DEBUG_2",
1323 "DEBUG_3",
1324 "UNKNOWN"
1325};
1326
1327static const char *desc_lookup(int i)
1328{
1329 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1330
1331 if (i < 0 || i > max)
1332 i = max;
1333
1334 return desc_lookup_text[i];
1335}
1336
1337#define ERROR_START_OFFSET (1 * sizeof(u32))
1338#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1339
1340static void iwl_dump_nic_error_log(struct iwl_priv *priv)
1341{
1342 u32 data2, line;
1343 u32 desc, time, count, base, data1;
1344 u32 blink1, blink2, ilink1, ilink2;
1345
34a66de6
WYG		 1346 switch (priv->ucode_type) {
1347 case UCODE_RT:
a94ca4e7 1348 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
34a66de6
WYG		 1349 break;
1350 case UCODE_INIT:
1351 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1352 break;
1353 default:
1354 IWL_ERR(priv, "uCode image not available\n");
1355 return;
1356 }
a94ca4e7
JB		 1357
1358 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1359 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1360 return;
1361 }
1362
1363 count = iwl_read_targ_mem(priv, base);
1364
1365 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1366 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1367 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1368 priv->status, count);
1369 }
1370
1371 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1372 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1373 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1374 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1375 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1376 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1377 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1378 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1379 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1380
1381 IWL_ERR(priv, "Desc Time "
1382 "data1 data2 line\n");
1383 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1384 desc_lookup(desc), desc, time, data1, data2, line);
1385 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1386 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1387 ilink1, ilink2);
1388
1389}
1390
1391#define EVENT_START_OFFSET (4 * sizeof(u32))
1392
1393/**
1394 * iwl_print_event_log - Dump error event log to syslog
1395 *
1396 */
1397static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1398 u32 num_events, u32 mode)
1399{
1400 u32 i;
1401 u32 base; /* SRAM byte address of event log header */
1402 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1403 u32 ptr; /* SRAM byte address of log data */
1404 u32 ev, time, data; /* event log data */
1405
1406 if (num_events == 0)
1407 return;
34a66de6
WYG		 1408 switch (priv->ucode_type) {
1409 case UCODE_RT:
a94ca4e7 1410 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
34a66de6
WYG		 1411 break;
1412 case UCODE_INIT:
1413 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1414 break;
1415 default:
1416 IWL_ERR(priv, "uCode image not available\n");
1417 return;
1418 }
a94ca4e7
JB		 1419
1420 if (mode == 0)
1421 event_size = 2 * sizeof(u32);
1422 else
1423 event_size = 3 * sizeof(u32);
1424
1425 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1426
1427 /* "time" is actually "data" for mode 0 (no timestamp).
1428 * place event id # at far right for easier visual parsing. */
1429 for (i = 0; i < num_events; i++) {
1430 ev = iwl_read_targ_mem(priv, ptr);
1431 ptr += sizeof(u32);
1432 time = iwl_read_targ_mem(priv, ptr);
1433 ptr += sizeof(u32);
1434 if (mode == 0) {
1435 /* data, ev */
1436 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1437 } else {
1438 data = iwl_read_targ_mem(priv, ptr);
1439 ptr += sizeof(u32);
1440 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1441 time, data, ev);
1442 }
1443 }
1444}
1445
1446void iwl_dump_nic_event_log(struct iwl_priv *priv)
1447{
1448 u32 base; /* SRAM byte address of event log header */
1449 u32 capacity; /* event log capacity in # entries */
1450 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1451 u32 num_wraps; /* # times uCode wrapped to top of log */
1452 u32 next_entry; /* index of next entry to be written by uCode */
1453 u32 size; /* # entries that we'll print */
1454
34a66de6
WYG		 1455 switch (priv->ucode_type) {
1456 case UCODE_RT:
a94ca4e7 1457 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
34a66de6
WYG		 1458 break;
1459 case UCODE_INIT:
1460 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1461 break;
1462 default:
1463 IWL_ERR(priv, "uCode image not available\n");
1464 return;
1465 }
a94ca4e7
JB		 1466
1467 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1468 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1469 return;
1470 }
1471
1472 /* event log header */
1473 capacity = iwl_read_targ_mem(priv, base);
1474 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1475 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1476 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1477
1478 size = num_wraps ? capacity : next_entry;
1479
1480 /* bail out if nothing in log */
1481 if (size == 0) {
1482 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1483 return;
1484 }
1485
1486 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1487 size, num_wraps);
1488
1489 /* if uCode has wrapped back to top of log, start at the oldest entry,
1490 * i.e the next one that uCode would fill. */
1491 if (num_wraps)
1492 iwl_print_event_log(priv, next_entry,
1493 capacity - next_entry, mode);
1494 /* (then/else) start at top of log */
1495 iwl_print_event_log(priv, 0, next_entry, mode);
1496
1497}
6686d17e 1498#endif
8ccde88a
SO		 1499/**
1500 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1501 */
1502void iwl_irq_handle_error(struct iwl_priv *priv)
1503{
1504 /* Set the FW error flag -- cleared on iwl_down */
1505 set_bit(STATUS_FW_ERROR, &priv->status);
1506
1507 /* Cancel currently queued command. */
1508 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1509
1510#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1511 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
8ccde88a
SO		 1512 iwl_dump_nic_error_log(priv);
1513 iwl_dump_nic_event_log(priv);
1514 iwl_print_rx_config_cmd(priv);
1515 }
1516#endif
1517
1518 wake_up_interruptible(&priv->wait_command_queue);
1519
1520 /* Keep the restart process from trying to send host
1521 * commands by clearing the INIT status bit */
1522 clear_bit(STATUS_READY, &priv->status);
1523
1524 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1525 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1526 "Restarting adapter due to uCode error.\n");
1527
8ccde88a
SO		 1528 if (priv->cfg->mod_params->restart_fw)
1529 queue_work(priv->workqueue, &priv->restart);
1530 }
1531}
1532EXPORT_SYMBOL(iwl_irq_handle_error);
1533
1534void iwl_configure_filter(struct ieee80211_hw *hw,
1535 unsigned int changed_flags,
1536 unsigned int *total_flags,
1537 int mc_count, struct dev_addr_list *mc_list)
1538{
1539 struct iwl_priv *priv = hw->priv;
1540 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1541
e1623446 1542 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1543 changed_flags, *total_flags);
1544
1545 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1546 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1547 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1548 else
1549 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1550 }
1551 if (changed_flags & FIF_ALLMULTI) {
1552 if (*total_flags & FIF_ALLMULTI)
1553 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1554 else
1555 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1556 }
1557 if (changed_flags & FIF_CONTROL) {
1558 if (*total_flags & FIF_CONTROL)
1559 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1560 else
1561 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1562 }
1563 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1564 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1565 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1566 else
1567 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1568 }
1569
1570 /* We avoid iwl_commit_rxon here to commit the new filter flags
1571 * since mac80211 will call ieee80211_hw_config immediately.
1572 * (mc_list is not supported at this time). Otherwise, we need to
1573 * queue a background iwl_commit_rxon work.
1574 */
1575
1576 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1577 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1578}
1579EXPORT_SYMBOL(iwl_configure_filter);
1580
6ba87956 1581int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 1582{
6ba87956 1583 int ret;
bf85ea4f 1584 struct ieee80211_hw *hw = priv->hw;
e227ceac 1585 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 1586
566bfe5a 1587 /* Tell mac80211 our characteristics */
605a0bd6 1588 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe 1589 IEEE80211_HW_NOISE_DBM |
4be8c387 1590 IEEE80211_HW_AMPDU_AGGREGATION |
f55e668f
RC		 1591 IEEE80211_HW_SPECTRUM_MGMT |
1592 IEEE80211_HW_SUPPORTS_PS;
f59ac048 1593 hw->wiphy->interface_modes =
f59ac048
LR		 1594 BIT(NL80211_IFTYPE_STATION) |
1595 BIT(NL80211_IFTYPE_ADHOC);
ea4a82dc 1596
2a44f911 1597 hw->wiphy->custom_regulatory = true;
1ecf9fc1 1598
37184244
LR		 1599 /* Firmware does not support this */
1600 hw->wiphy->disable_beacon_hints = true;
1601
1ecf9fc1
JB		 1602 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
1603 /* we create the 802.11 header and a zero-length SSID element */
1604 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
ea4a82dc 1605
bf85ea4f
AK		 1606 /* Default value; 4 EDCA QOS priorities */
1607 hw->queues = 4;
6ba87956 1608
b5d7be5e 1609 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 1610
1611 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
1612 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1613 &priv->bands[IEEE80211_BAND_2GHZ];
1614 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
1615 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1616 &priv->bands[IEEE80211_BAND_5GHZ];
1617
1618 ret = ieee80211_register_hw(priv->hw);
1619 if (ret) {
15b1687c 1620 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
6ba87956
TW		 1621 return ret;
1622 }
1623 priv->mac80211_registered = 1;
1624
1625 return 0;
bf85ea4f 1626}
6ba87956 1627EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 1628
da154e30
RR		 1629int iwl_set_hw_params(struct iwl_priv *priv)
1630{
da154e30
RR		 1631 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1632 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1633 if (priv->cfg->mod_params->amsdu_size_8K)
1634 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1635 else
1636 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1637 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1638
2c2f3b33
TW		 1639 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1640
49779293
RR		 1641 if (priv->cfg->mod_params->disable_11n)
1642 priv->cfg->sku &= ~IWL_SKU_N;
1643
da154e30
RR		 1644 /* Device-specific setup */
1645 return priv->cfg->ops->lib->set_hw_params(priv);
1646}
1647EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 1648
1649int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 1650{
1651 int ret;
c7de35cd 1652
c7de35cd
RR		 1653 priv->ibss_beacon = NULL;
1654
1655 spin_lock_init(&priv->lock);
c7de35cd
RR		 1656 spin_lock_init(&priv->sta_lock);
1657 spin_lock_init(&priv->hcmd_lock);
c7de35cd 1658
c7de35cd
RR		 1659 INIT_LIST_HEAD(&priv->free_frames);
1660
1661 mutex_init(&priv->mutex);
1662
1663 /* Clear the driver's (not device's) station table */
c587de0b 1664 iwl_clear_stations_table(priv);
c7de35cd
RR		 1665
1666 priv->data_retry_limit = -1;
1667 priv->ieee_channels = NULL;
1668 priv->ieee_rates = NULL;
1669 priv->band = IEEE80211_BAND_2GHZ;
1670
05c914fe 1671 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 1672
12837be1 1673 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 1674
1675 /* Choose which receivers/antennas to use */
45823531
AK		 1676 if (priv->cfg->ops->hcmd->set_rxon_chain)
1677 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1678
f53696de 1679 iwl_init_scan_params(priv);
c7de35cd
RR		 1680
1681 iwl_reset_qos(priv);
1682
1683 priv->qos_data.qos_active = 0;
1684 priv->qos_data.qos_cap.val = 0;
1685
c7de35cd 1686 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT		 1687 /* If power management is turned on, default to CAM mode */
1688 priv->power_mode = IWL_POWER_MODE_CAM;
630fe9b6 1689 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 1690
1691 ret = iwl_init_channel_map(priv);
1692 if (ret) {
15b1687c 1693 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
c7de35cd
RR		 1694 goto err;
1695 }
1696
1697 ret = iwlcore_init_geos(priv);
1698 if (ret) {
15b1687c 1699 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
c7de35cd
RR		 1700 goto err_free_channel_map;
1701 }
534166de 1702 iwlcore_init_hw_rates(priv, priv->ieee_rates);
c7de35cd 1703
c7de35cd
RR		 1704 return 0;
1705
c7de35cd
RR		 1706err_free_channel_map:
1707 iwl_free_channel_map(priv);
1708err:
1709 return ret;
1710}
6ba87956 1711EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 1712
630fe9b6
TW		 1713int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1714{
1715 int ret = 0;
1716 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1717 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1718 tx_power,
1719 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1720 return -EINVAL;
1721 }
1722
1723 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
daf518de
WF		 1724 IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
1725 tx_power,
1726 IWL_TX_POWER_TARGET_POWER_MAX);
630fe9b6
TW		 1727 return -EINVAL;
1728 }
1729
1730 if (priv->tx_power_user_lmt != tx_power)
1731 force = true;
1732
1733 priv->tx_power_user_lmt = tx_power;
1734
019fb97d
MA		 1735 /* if nic is not up don't send command */
1736 if (!iwl_is_ready_rf(priv))
1737 return ret;
1738
630fe9b6
TW		 1739 if (force && priv->cfg->ops->lib->send_tx_power)
1740 ret = priv->cfg->ops->lib->send_tx_power(priv);
1741
1742 return ret;
1743}
1744EXPORT_SYMBOL(iwl_set_tx_power);
1745
6ba87956 1746void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1747{
6e21f2c1 1748 iwl_calib_free_results(priv);
6ba87956
TW		 1749 iwlcore_free_geos(priv);
1750 iwl_free_channel_map(priv);
261415f7 1751 kfree(priv->scan);
bf85ea4f 1752}
6ba87956 1753EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1754
ef850d7c
MA		 1755#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1756
1757/* Free dram table */
1758void iwl_free_isr_ict(struct iwl_priv *priv)
1759{
1760 if (priv->ict_tbl_vir) {
1761 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1762 PAGE_SIZE, priv->ict_tbl_vir,
1763 priv->ict_tbl_dma);
1764 priv->ict_tbl_vir = NULL;
1765 }
1766}
1767EXPORT_SYMBOL(iwl_free_isr_ict);
1768
1769
1770/* allocate dram shared table it is a PAGE_SIZE aligned
1771 * also reset all data related to ICT table interrupt.
1772 */
1773int iwl_alloc_isr_ict(struct iwl_priv *priv)
1774{
1775
1776 if (priv->cfg->use_isr_legacy)
1777 return 0;
1778 /* allocate shrared data table */
1779 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1780 ICT_COUNT) + PAGE_SIZE,
1781 &priv->ict_tbl_dma);
1782 if (!priv->ict_tbl_vir)
1783 return -ENOMEM;
1784
1785 /* align table to PAGE_SIZE boundry */
1786 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1787
1788 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1789 (unsigned long long)priv->ict_tbl_dma,
1790 (unsigned long long)priv->aligned_ict_tbl_dma,
1791 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1792
1793 priv->ict_tbl = priv->ict_tbl_vir +
1794 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1795
1796 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1797 priv->ict_tbl, priv->ict_tbl_vir,
1798 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1799
1800 /* reset table and index to all 0 */
1801 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1802 priv->ict_index = 0;
1803
40cefda9
MA		 1804 /* add periodic RX interrupt */
1805 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1806 return 0;
1807}
1808EXPORT_SYMBOL(iwl_alloc_isr_ict);
1809
1810/* Device is going up inform it about using ICT interrupt table,
1811 * also we need to tell the driver to start using ICT interrupt.
1812 */
1813int iwl_reset_ict(struct iwl_priv *priv)
1814{
1815 u32 val;
1816 unsigned long flags;
1817
1818 if (!priv->ict_tbl_vir)
1819 return 0;
1820
1821 spin_lock_irqsave(&priv->lock, flags);
1822 iwl_disable_interrupts(priv);
1823
1824 memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT);
1825
1826 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1827
1828 val |= CSR_DRAM_INT_TBL_ENABLE;
1829 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1830
1831 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1832 "aligned dma address %Lx\n",
1833 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1834
1835 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1836 priv->use_ict = true;
1837 priv->ict_index = 0;
40cefda9 1838 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1839 iwl_enable_interrupts(priv);
1840 spin_unlock_irqrestore(&priv->lock, flags);
1841
1842 return 0;
1843}
1844EXPORT_SYMBOL(iwl_reset_ict);
1845
1846/* Device is going down disable ict interrupt usage */
1847void iwl_disable_ict(struct iwl_priv *priv)
1848{
1849 unsigned long flags;
1850
1851 spin_lock_irqsave(&priv->lock, flags);
1852 priv->use_ict = false;
1853 spin_unlock_irqrestore(&priv->lock, flags);
1854}
1855EXPORT_SYMBOL(iwl_disable_ict);
1856
1857/* interrupt handler using ict table, with this interrupt driver will
1858 * stop using INTA register to get device's interrupt, reading this register
1859 * is expensive, device will write interrupts in ICT dram table, increment
1860 * index then will fire interrupt to driver, driver will OR all ICT table
1861 * entries from current index up to table entry with 0 value. the result is
1862 * the interrupt we need to service, driver will set the entries back to 0 and
1863 * set index.
1864 */
1865irqreturn_t iwl_isr_ict(int irq, void *data)
1866{
1867 struct iwl_priv *priv = data;
1868 u32 inta, inta_mask;
1869 u32 val = 0;
1870
1871 if (!priv)
1872 return IRQ_NONE;
1873
1874 /* dram interrupt table not set yet,
1875 * use legacy interrupt.
1876 */
1877 if (!priv->use_ict)
1878 return iwl_isr(irq, data);
1879
1880 spin_lock(&priv->lock);
1881
1882 /* Disable (but don't clear!) interrupts here to avoid
1883 * back-to-back ISRs and sporadic interrupts from our NIC.
1884 * If we have something to service, the tasklet will re-enable ints.
1885 * If we *don't* have something, we'll re-enable before leaving here.
1886 */
1887 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1888 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1889
1890
1891 /* Ignore interrupt if there's nothing in NIC to service.
1892 * This may be due to IRQ shared with another device,
1893 * or due to sporadic interrupts thrown from our NIC. */
1894 if (!priv->ict_tbl[priv->ict_index]) {
1895 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1896 goto none;
1897 }
1898
1899 /* read all entries that not 0 start with ict_index */
1900 while (priv->ict_tbl[priv->ict_index]) {
1901
1902 val |= priv->ict_tbl[priv->ict_index];
1903 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1904 priv->ict_index,
1905 priv->ict_tbl[priv->ict_index]);
1906 priv->ict_tbl[priv->ict_index] = 0;
1907 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1908 ICT_COUNT);
1909
1910 }
1911
1912 /* We should not get this value, just ignore it. */
1913 if (val == 0xffffffff)
1914 val = 0;
1915
1916 inta = (0xff & val) | ((0xff00 & val) << 16);
1917 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1918 inta, inta_mask, val);
1919
40cefda9 1920 inta &= priv->inta_mask;
ef850d7c
MA		 1921 priv->inta |= inta;
1922
1923 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1924 if (likely(inta))
1925 tasklet_schedule(&priv->irq_tasklet);
1926 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1927 /* Allow interrupt if was disabled by this handler and
1928 * no tasklet was schedules, We should not enable interrupt,
1929 * tasklet will enable it.
1930 */
1931 iwl_enable_interrupts(priv);
1932 }
1933
1934 spin_unlock(&priv->lock);
1935 return IRQ_HANDLED;
1936
1937 none:
1938 /* re-enable interrupts here since we don't have anything to service.
1939 * only Re-enable if disabled by irq.
1940 */
1941 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1942 iwl_enable_interrupts(priv);
1943
1944 spin_unlock(&priv->lock);
1945 return IRQ_NONE;
1946}
1947EXPORT_SYMBOL(iwl_isr_ict);
1948
1949
1950static irqreturn_t iwl_isr(int irq, void *data)
1951{
1952 struct iwl_priv *priv = data;
1953 u32 inta, inta_mask;
d651ae32 1954#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1955 u32 inta_fh;
d651ae32 1956#endif
ef850d7c
MA		 1957 if (!priv)
1958 return IRQ_NONE;
1959
1960 spin_lock(&priv->lock);
1961
1962 /* Disable (but don't clear!) interrupts here to avoid
1963 * back-to-back ISRs and sporadic interrupts from our NIC.
1964 * If we have something to service, the tasklet will re-enable ints.
1965 * If we *don't* have something, we'll re-enable before leaving here. */
1966 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1967 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1968
1969 /* Discover which interrupts are active/pending */
1970 inta = iwl_read32(priv, CSR_INT);
1971
1972 /* Ignore interrupt if there's nothing in NIC to service.
1973 * This may be due to IRQ shared with another device,
1974 * or due to sporadic interrupts thrown from our NIC. */
1975 if (!inta) {
1976 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1977 goto none;
1978 }
1979
1980 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1981 /* Hardware disappeared. It might have already raised
1982 * an interrupt */
1983 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1984 goto unplugged;
1985 }
1986
1987#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1988 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1989 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1990 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1991 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1992 }
1993#endif
1994
1995 priv->inta |= inta;
1996 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1997 if (likely(inta))
1998 tasklet_schedule(&priv->irq_tasklet);
1999 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
2000 iwl_enable_interrupts(priv);
2001
2002 unplugged:
2003 spin_unlock(&priv->lock);
2004 return IRQ_HANDLED;
2005
2006 none:
2007 /* re-enable interrupts here since we don't have anything to service. */
2008 /* only Re-enable if diabled by irq and no schedules tasklet. */
2009 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
2010 iwl_enable_interrupts(priv);
2011
2012 spin_unlock(&priv->lock);
2013 return IRQ_NONE;
2014}
2015
2016irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 2017{
2018 struct iwl_priv *priv = data;
2019 u32 inta, inta_mask;
2020 u32 inta_fh;
2021 if (!priv)
2022 return IRQ_NONE;
2023
2024 spin_lock(&priv->lock);
2025
2026 /* Disable (but don't clear!) interrupts here to avoid
2027 * back-to-back ISRs and sporadic interrupts from our NIC.
2028 * If we have something to service, the tasklet will re-enable ints.
2029 * If we *don't* have something, we'll re-enable before leaving here. */
2030 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
2031 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
2032
2033 /* Discover which interrupts are active/pending */
2034 inta = iwl_read32(priv, CSR_INT);
2035 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
2036
2037 /* Ignore interrupt if there's nothing in NIC to service.
2038 * This may be due to IRQ shared with another device,
2039 * or due to sporadic interrupts thrown from our NIC. */
2040 if (!inta && !inta_fh) {
2041 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
2042 goto none;
2043 }
2044
2045 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
2046 /* Hardware disappeared. It might have already raised
2047 * an interrupt */
2048 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
2049 goto unplugged;
2050 }
2051
2052 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
2053 inta, inta_mask, inta_fh);
2054
2055 inta &= ~CSR_INT_BIT_SCD;
2056
2057 /* iwl_irq_tasklet() will service interrupts and re-enable them */
2058 if (likely(inta || inta_fh))
2059 tasklet_schedule(&priv->irq_tasklet);
2060
2061 unplugged:
2062 spin_unlock(&priv->lock);
2063 return IRQ_HANDLED;
2064
2065 none:
2066 /* re-enable interrupts here since we don't have anything to service. */
2067 /* only Re-enable if diabled by irq */
2068 if (test_bit(STATUS_INT_ENABLED, &priv->status))
2069 iwl_enable_interrupts(priv);
2070 spin_unlock(&priv->lock);
2071 return IRQ_NONE;
2072}
ef850d7c 2073EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 2074
17f841cd
SO		 2075int iwl_send_bt_config(struct iwl_priv *priv)
2076{
2077 struct iwl_bt_cmd bt_cmd = {
2078 .flags = 3,
2079 .lead_time = 0xAA,
2080 .max_kill = 1,
2081 .kill_ack_mask = 0,
2082 .kill_cts_mask = 0,
2083 };
2084
2085 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
2086 sizeof(struct iwl_bt_cmd), &bt_cmd);
2087}
2088EXPORT_SYMBOL(iwl_send_bt_config);
2089
49ea8596
EG		 2090int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
2091{
2092 u32 stat_flags = 0;
2093 struct iwl_host_cmd cmd = {
2094 .id = REPLY_STATISTICS_CMD,
c2acea8e 2095 .flags = flags,
49ea8596
EG		 2096 .len = sizeof(stat_flags),
2097 .data = (u8 *) &stat_flags,
2098 };
2099 return iwl_send_cmd(priv, &cmd);
2100}
2101EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2102
b0692f2f
EG		 2103/**
2104 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2105 * using sample data 100 bytes apart. If these sample points are good,
2106 * it's a pretty good bet that everything between them is good, too.
2107 */
2108static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2109{
2110 u32 val;
2111 int ret = 0;
2112 u32 errcnt = 0;
2113 u32 i;
2114
e1623446 2115 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2116
b0692f2f
EG		 2117 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2118 /* read data comes through single port, auto-incr addr */
2119 /* NOTE: Use the debugless read so we don't flood kernel log
2120 * if IWL_DL_IO is set */
2121 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2122 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2123 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2124 if (val != le32_to_cpu(*image)) {
2125 ret = -EIO;
2126 errcnt++;
2127 if (errcnt >= 3)
2128 break;
2129 }
2130 }
2131
b0692f2f
EG		 2132 return ret;
2133}
2134
2135/**
2136 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2137 * looking at all data.
2138 */
2139static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2140 u32 len)
2141{
2142 u32 val;
2143 u32 save_len = len;
2144 int ret = 0;
2145 u32 errcnt;
2146
e1623446 2147 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2148
250bdd21
SO		 2149 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2150 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2151
2152 errcnt = 0;
2153 for (; len > 0; len -= sizeof(u32), image++) {
2154 /* read data comes through single port, auto-incr addr */
2155 /* NOTE: Use the debugless read so we don't flood kernel log
2156 * if IWL_DL_IO is set */
2157 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2158 if (val != le32_to_cpu(*image)) {
15b1687c 2159 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2160 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2161 save_len - len, val, le32_to_cpu(*image));
2162 ret = -EIO;
2163 errcnt++;
2164 if (errcnt >= 20)
2165 break;
2166 }
2167 }
2168
b0692f2f 2169 if (!errcnt)
e1623446
TW		 2170 IWL_DEBUG_INFO(priv,
2171 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2172
2173 return ret;
2174}
2175
2176/**
2177 * iwl_verify_ucode - determine which instruction image is in SRAM,
2178 * and verify its contents
2179 */
2180int iwl_verify_ucode(struct iwl_priv *priv)
2181{
2182 __le32 *image;
2183 u32 len;
2184 int ret;
2185
2186 /* Try bootstrap */
2187 image = (__le32 *)priv->ucode_boot.v_addr;
2188 len = priv->ucode_boot.len;
2189 ret = iwlcore_verify_inst_sparse(priv, image, len);
2190 if (!ret) {
e1623446 2191 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2192 return 0;
2193 }
2194
2195 /* Try initialize */
2196 image = (__le32 *)priv->ucode_init.v_addr;
2197 len = priv->ucode_init.len;
2198 ret = iwlcore_verify_inst_sparse(priv, image, len);
2199 if (!ret) {
e1623446 2200 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2201 return 0;
2202 }
2203
2204 /* Try runtime/protocol */
2205 image = (__le32 *)priv->ucode_code.v_addr;
2206 len = priv->ucode_code.len;
2207 ret = iwlcore_verify_inst_sparse(priv, image, len);
2208 if (!ret) {
e1623446 2209 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2210 return 0;
2211 }
2212
15b1687c 2213 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2214
2215 /* Since nothing seems to match, show first several data entries in
2216 * instruction SRAM, so maybe visual inspection will give a clue.
2217 * Selection of bootstrap image (vs. other images) is arbitrary. */
2218 image = (__le32 *)priv->ucode_boot.v_addr;
2219 len = priv->ucode_boot.len;
2220 ret = iwl_verify_inst_full(priv, image, len);
2221
2222 return ret;
2223}
2224EXPORT_SYMBOL(iwl_verify_ucode);
2225
56e12615 2226
47f4a587
EG		 2227void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2228{
2229 struct iwl_ct_kill_config cmd;
672639de 2230 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2231 unsigned long flags;
2232 int ret = 0;
2233
2234 spin_lock_irqsave(&priv->lock, flags);
2235 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2236 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2237 spin_unlock_irqrestore(&priv->lock, flags);
39b73fb1 2238 priv->power_data.ct_kill_toggle = false;
47f4a587 2239
672639de
WYG		 2240 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
2241 case CSR_HW_REV_TYPE_1000:
2242 case CSR_HW_REV_TYPE_6x00:
2243 case CSR_HW_REV_TYPE_6x50:
2244 adv_cmd.critical_temperature_enter =
2245 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2246 adv_cmd.critical_temperature_exit =
2247 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2248
2249 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2250 sizeof(adv_cmd), &adv_cmd);
2251 break;
2252 default:
2253 cmd.critical_temperature_R =
2254 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2255
672639de
WYG		 2256 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2257 sizeof(cmd), &cmd);
2258 break;
2259 }
47f4a587
EG		 2260 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2261 sizeof(cmd), &cmd);
2262 if (ret)
15b1687c 2263 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
47f4a587 2264 else
e1623446 2265 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
47f4a587
EG		 2266 "critical temperature is %d\n",
2267 cmd.critical_temperature_R);
2268}
2269EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2270
0ad91a35 2271
14a08a7f
EG		 2272/*
2273 * CARD_STATE_CMD
2274 *
2275 * Use: Sets the device's internal card state to enable, disable, or halt
2276 *
2277 * When in the 'enable' state the card operates as normal.
2278 * When in the 'disable' state, the card enters into a low power mode.
2279 * When in the 'halt' state, the card is shut down and must be fully
2280 * restarted to come back on.
2281 */
c496294e 2282int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2283{
2284 struct iwl_host_cmd cmd = {
2285 .id = REPLY_CARD_STATE_CMD,
2286 .len = sizeof(u32),
2287 .data = &flags,
c2acea8e 2288 .flags = meta_flag,
14a08a7f
EG		 2289 };
2290
2291 return iwl_send_cmd(priv, &cmd);
2292}
2293
030f05ed
AK		 2294void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2295 struct iwl_rx_mem_buffer *rxb)
2296{
2297#ifdef CONFIG_IWLWIFI_DEBUG
2298 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2299 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2300 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2301 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2302#endif
2303}
2304EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2305
2306void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2307 struct iwl_rx_mem_buffer *rxb)
2308{
2309 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2310 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
2311 "notification for %s:\n",
2312 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
3d816c77 2313 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
030f05ed
AK		 2314}
2315EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2316
2317void iwl_rx_reply_error(struct iwl_priv *priv,
2318 struct iwl_rx_mem_buffer *rxb)
2319{
2320 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2321
2322 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2323 "seq 0x%04X ser 0x%08X\n",
2324 le32_to_cpu(pkt->u.err_resp.error_type),
2325 get_cmd_string(pkt->u.err_resp.cmd_id),
2326 pkt->u.err_resp.cmd_id,
2327 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2328 le32_to_cpu(pkt->u.err_resp.error_info));
2329}
2330EXPORT_SYMBOL(iwl_rx_reply_error);
2331
a83b9141
WYG		 2332void iwl_clear_isr_stats(struct iwl_priv *priv)
2333{
2334 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2335}
a83b9141 2336
488829f1
AK		 2337int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2338 const struct ieee80211_tx_queue_params *params)
2339{
2340 struct iwl_priv *priv = hw->priv;
2341 unsigned long flags;
2342 int q;
2343
2344 IWL_DEBUG_MAC80211(priv, "enter\n");
2345
2346 if (!iwl_is_ready_rf(priv)) {
2347 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2348 return -EIO;
2349 }
2350
2351 if (queue >= AC_NUM) {
2352 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2353 return 0;
2354 }
2355
2356 q = AC_NUM - 1 - queue;
2357
2358 spin_lock_irqsave(&priv->lock, flags);
2359
2360 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2361 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2362 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2363 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2364 cpu_to_le16((params->txop * 32));
2365
2366 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2367 priv->qos_data.qos_active = 1;
2368
2369 if (priv->iw_mode == NL80211_IFTYPE_AP)
2370 iwl_activate_qos(priv, 1);
2371 else if (priv->assoc_id && iwl_is_associated(priv))
2372 iwl_activate_qos(priv, 0);
2373
2374 spin_unlock_irqrestore(&priv->lock, flags);
2375
2376 IWL_DEBUG_MAC80211(priv, "leave\n");
2377 return 0;
2378}
2379EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2380
2381static void iwl_ht_conf(struct iwl_priv *priv,
2382 struct ieee80211_bss_conf *bss_conf)
2383{
2384 struct ieee80211_sta_ht_cap *ht_conf;
2385 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
2386 struct ieee80211_sta *sta;
2387
2388 IWL_DEBUG_MAC80211(priv, "enter: \n");
2389
2390 if (!iwl_conf->is_ht)
2391 return;
2392
2393
2394 /*
2395 * It is totally wrong to base global information on something
2396 * that is valid only when associated, alas, this driver works
2397 * that way and I don't know how to fix it.
2398 */
2399
2400 rcu_read_lock();
2401 sta = ieee80211_find_sta(priv->hw, priv->bssid);
2402 if (!sta) {
2403 rcu_read_unlock();
2404 return;
2405 }
2406 ht_conf = &sta->ht_cap;
2407
2408 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
2409 iwl_conf->sgf |= HT_SHORT_GI_20MHZ;
2410 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
2411 iwl_conf->sgf |= HT_SHORT_GI_40MHZ;
2412
2413 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
2414 iwl_conf->max_amsdu_size =
2415 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
2416
2417 iwl_conf->supported_chan_width =
2418 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
2419
2420 /*
2421 * XXX: The HT configuration needs to be moved into iwl_mac_config()
2422 * to be done there correctly.
2423 */
2424
2425 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
2426 if (conf_is_ht40_minus(&priv->hw->conf))
2427 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2428 else if (conf_is_ht40_plus(&priv->hw->conf))
2429 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2430
7aafef1c 2431 /* If no above or below channel supplied disable HT40 channel */
5bbe233b
AK		 2432 if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE &&
2433 iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW)
2434 iwl_conf->supported_chan_width = 0;
2435
2436 iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
2437
2438 memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
2439
2440 iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0;
2441 iwl_conf->ht_protection =
9ed6bcce 2442 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
5bbe233b 2443 iwl_conf->non_GF_STA_present =
9ed6bcce 2444 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b
AK		 2445
2446 rcu_read_unlock();
2447
2448 IWL_DEBUG_MAC80211(priv, "leave\n");
2449}
2450
2451#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2452void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2453 struct ieee80211_vif *vif,
2454 struct ieee80211_bss_conf *bss_conf,
2455 u32 changes)
5bbe233b
AK		 2456{
2457 struct iwl_priv *priv = hw->priv;
3a650292 2458 int ret;
5bbe233b
AK		 2459
2460 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2461
2d0ddec5
JB		 2462 if (!iwl_is_alive(priv))
2463 return;
2464
2465 mutex_lock(&priv->mutex);
2466
2467 if (changes & BSS_CHANGED_BEACON &&
2468 priv->iw_mode == NL80211_IFTYPE_AP) {
2469 dev_kfree_skb(priv->ibss_beacon);
2470 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2471 }
2472
d7129e19
JB		 2473 if (changes & BSS_CHANGED_BEACON_INT) {
2474 priv->beacon_int = bss_conf->beacon_int;
2475 /* TODO: in AP mode, do something to make this take effect */
2476 }
2477
2478 if (changes & BSS_CHANGED_BSSID) {
2479 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2480
2481 /*
2482 * If there is currently a HW scan going on in the
2483 * background then we need to cancel it else the RXON
2484 * below/in post_associate will fail.
2485 */
2d0ddec5 2486 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2487 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2488 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2489 mutex_unlock(&priv->mutex);
2490 return;
2491 }
2d0ddec5 2492
d7129e19
JB		 2493 /* mac80211 only sets assoc when in STATION mode */
2494 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2495 bss_conf->assoc) {
2496 memcpy(priv->staging_rxon.bssid_addr,
2497 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2498
d7129e19
JB		 2499 /* currently needed in a few places */
2500 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2501 } else {
2502 priv->staging_rxon.filter_flags &=
2503 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2504 }
d7129e19 2505
2d0ddec5
JB		 2506 }
2507
d7129e19
JB		 2508 /*
2509 * This needs to be after setting the BSSID in case
2510 * mac80211 decides to do both changes at once because
2511 * it will invoke post_associate.
2512 */
2d0ddec5
JB		 2513 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2514 changes & BSS_CHANGED_BEACON) {
2515 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2516
2517 if (beacon)
2518 iwl_mac_beacon_update(hw, beacon);
2519 }
2520
5bbe233b
AK		 2521 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2522 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2523 bss_conf->use_short_preamble);
2524 if (bss_conf->use_short_preamble)
2525 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2526 else
2527 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2528 }
2529
2530 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2531 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2532 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2533 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2534 else
2535 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2536 }
2537
d7129e19
JB		 2538 if (changes & BSS_CHANGED_BASIC_RATES) {
2539 /* XXX use this information
2540 *
2541 * To do that, remove code from iwl_set_rate() and put something
2542 * like this here:
2543 *
2544 if (A-band)
2545 priv->staging_rxon.ofdm_basic_rates =
2546 bss_conf->basic_rates;
2547 else
2548 priv->staging_rxon.ofdm_basic_rates =
2549 bss_conf->basic_rates >> 4;
2550 priv->staging_rxon.cck_basic_rates =
2551 bss_conf->basic_rates & 0xF;
2552 */
2553 }
2554
5bbe233b
AK		 2555 if (changes & BSS_CHANGED_HT) {
2556 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2557
2558 if (priv->cfg->ops->hcmd->set_rxon_chain)
2559 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2560 }
2561
2562 if (changes & BSS_CHANGED_ASSOC) {
2563 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2564 if (bss_conf->assoc) {
2565 priv->assoc_id = bss_conf->aid;
2566 priv->beacon_int = bss_conf->beacon_int;
2567 priv->power_data.dtim_period = bss_conf->dtim_period;
2568 priv->timestamp = bss_conf->timestamp;
2569 priv->assoc_capability = bss_conf->assoc_capability;
2570
d7129e19
JB		 2571 /*
2572 * We have just associated, don't start scan too early
2573 * leave time for EAPOL exchange to complete.
2574 *
2575 * XXX: do this in mac80211
5bbe233b
AK		 2576 */
2577 priv->next_scan_jiffies = jiffies +
2578 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2579 if (!iwl_is_rfkill(priv))
2580 priv->cfg->ops->lib->post_associate(priv);
2581 } else
5bbe233b 2582 priv->assoc_id = 0;
d7129e19
JB		 2583
2584 }
2585
2586 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2587 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2588 changes);
2589 ret = iwl_send_rxon_assoc(priv);
2590 if (!ret) {
2591 /* Sync active_rxon with latest change. */
2592 memcpy((void *)&priv->active_rxon,
2593 &priv->staging_rxon,
2594 sizeof(struct iwl_rxon_cmd));
5bbe233b 2595 }
5bbe233b 2596 }
d7129e19
JB		 2597
2598 mutex_unlock(&priv->mutex);
2599
2d0ddec5 2600 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2601}
2602EXPORT_SYMBOL(iwl_bss_info_changed);
2603
9944b938
AK		 2604int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2605{
2606 struct iwl_priv *priv = hw->priv;
2607 unsigned long flags;
2608 __le64 timestamp;
2609
2610 IWL_DEBUG_MAC80211(priv, "enter\n");
2611
2612 if (!iwl_is_ready_rf(priv)) {
2613 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2614 return -EIO;
2615 }
2616
2617 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2618 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2619 return -EIO;
2620 }
2621
2622 spin_lock_irqsave(&priv->lock, flags);
2623
2624 if (priv->ibss_beacon)
2625 dev_kfree_skb(priv->ibss_beacon);
2626
2627 priv->ibss_beacon = skb;
2628
2629 priv->assoc_id = 0;
2630 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2631 priv->timestamp = le64_to_cpu(timestamp);
2632
2633 IWL_DEBUG_MAC80211(priv, "leave\n");
2634 spin_unlock_irqrestore(&priv->lock, flags);
2635
2636 iwl_reset_qos(priv);
2637
2638 priv->cfg->ops->lib->post_associate(priv);
2639
2640
2641 return 0;
2642}
2643EXPORT_SYMBOL(iwl_mac_beacon_update);
2644
727882d6
AK		 2645int iwl_set_mode(struct iwl_priv *priv, int mode)
2646{
2647 if (mode == NL80211_IFTYPE_ADHOC) {
2648 const struct iwl_channel_info *ch_info;
2649
2650 ch_info = iwl_get_channel_info(priv,
2651 priv->band,
2652 le16_to_cpu(priv->staging_rxon.channel));
2653
2654 if (!ch_info || !is_channel_ibss(ch_info)) {
2655 IWL_ERR(priv, "channel %d not IBSS channel\n",
2656 le16_to_cpu(priv->staging_rxon.channel));
2657 return -EINVAL;
2658 }
2659 }
2660
2661 iwl_connection_init_rx_config(priv, mode);
2662
2663 if (priv->cfg->ops->hcmd->set_rxon_chain)
2664 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2665
2666 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2667
c587de0b 2668 iwl_clear_stations_table(priv);
727882d6
AK		 2669
2670 /* dont commit rxon if rf-kill is on*/
2671 if (!iwl_is_ready_rf(priv))
2672 return -EAGAIN;
2673
727882d6
AK		 2674 iwlcore_commit_rxon(priv);
2675
2676 return 0;
2677}
2678EXPORT_SYMBOL(iwl_set_mode);
2679
cbb6ab94
AK		 2680int iwl_mac_add_interface(struct ieee80211_hw *hw,
2681 struct ieee80211_if_init_conf *conf)
2682{
2683 struct iwl_priv *priv = hw->priv;
2684 unsigned long flags;
2685
2686 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2687
2688 if (priv->vif) {
2689 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2690 return -EOPNOTSUPP;
2691 }
2692
2693 spin_lock_irqsave(&priv->lock, flags);
2694 priv->vif = conf->vif;
2695 priv->iw_mode = conf->type;
2696
2697 spin_unlock_irqrestore(&priv->lock, flags);
2698
2699 mutex_lock(&priv->mutex);
2700
2701 if (conf->mac_addr) {
2702 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2703 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2704 }
2705
2706 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2707 /* we are not ready, will run again when ready */
2708 set_bit(STATUS_MODE_PENDING, &priv->status);
2709
2710 mutex_unlock(&priv->mutex);
2711
2712 IWL_DEBUG_MAC80211(priv, "leave\n");
2713 return 0;
2714}
2715EXPORT_SYMBOL(iwl_mac_add_interface);
2716
d8052319
AK		 2717void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2718 struct ieee80211_if_init_conf *conf)
2719{
2720 struct iwl_priv *priv = hw->priv;
2721
2722 IWL_DEBUG_MAC80211(priv, "enter\n");
2723
2724 mutex_lock(&priv->mutex);
2725
2726 if (iwl_is_ready_rf(priv)) {
2727 iwl_scan_cancel_timeout(priv, 100);
2728 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2729 iwlcore_commit_rxon(priv);
2730 }
2731 if (priv->vif == conf->vif) {
2732 priv->vif = NULL;
2733 memset(priv->bssid, 0, ETH_ALEN);
2734 }
2735 mutex_unlock(&priv->mutex);
2736
2737 IWL_DEBUG_MAC80211(priv, "leave\n");
2738
2739}
2740EXPORT_SYMBOL(iwl_mac_remove_interface);
2741
4808368d
AK		 2742/**
2743 * iwl_mac_config - mac80211 config callback
2744 *
2745 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2746 * be set inappropriately and the driver currently sets the hardware up to
2747 * use it whenever needed.
2748 */
2749int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2750{
2751 struct iwl_priv *priv = hw->priv;
2752 const struct iwl_channel_info *ch_info;
2753 struct ieee80211_conf *conf = &hw->conf;
2754 unsigned long flags = 0;
2755 int ret = 0;
2756 u16 ch;
2757 int scan_active = 0;
2758
2759 mutex_lock(&priv->mutex);
2760
4808368d
AK		 2761 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2762 conf->channel->hw_value, changed);
2763
2764 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2765 test_bit(STATUS_SCANNING, &priv->status))) {
2766 scan_active = 1;
2767 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2768 }
2769
2770
2771 /* during scanning mac80211 will delay channel setting until
2772 * scan finish with changed = 0
2773 */
2774 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2775 if (scan_active)
2776 goto set_ch_out;
2777
2778 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2779 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2780 if (!is_channel_valid(ch_info)) {
2781 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2782 ret = -EINVAL;
2783 goto set_ch_out;
2784 }
2785
2786 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2787 !is_channel_ibss(ch_info)) {
2788 IWL_ERR(priv, "channel %d in band %d not "
2789 "IBSS channel\n",
2790 conf->channel->hw_value, conf->channel->band);
2791 ret = -EINVAL;
2792 goto set_ch_out;
2793 }
2794
2795 priv->current_ht_config.is_ht = conf_is_ht(conf);
2796
2797 spin_lock_irqsave(&priv->lock, flags);
2798
2799
2800 /* if we are switching from ht to 2.4 clear flags
2801 * from any ht related info since 2.4 does not
2802 * support ht */
2803 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2804 priv->staging_rxon.flags = 0;
2805
2806 iwl_set_rxon_channel(priv, conf->channel);
2807
2808 iwl_set_flags_for_band(priv, conf->channel->band);
2809 spin_unlock_irqrestore(&priv->lock, flags);
2810 set_ch_out:
2811 /* The list of supported rates and rate mask can be different
2812 * for each band; since the band may have changed, reset
2813 * the rate mask to what mac80211 lists */
2814 iwl_set_rate(priv);
2815 }
2816
7af2c460
JB		 2817 if (changed & IEEE80211_CONF_CHANGE_PS &&
2818 priv->iw_mode == NL80211_IFTYPE_STATION) {
2819 priv->power_data.power_disabled =
2820 !(conf->flags & IEEE80211_CONF_PS);
2821 ret = iwl_power_update_mode(priv, 0);
4808368d
AK		 2822 if (ret)
2823 IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
4808368d
AK		 2824 }
2825
2826 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2827 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2828 priv->tx_power_user_lmt, conf->power_level);
2829
2830 iwl_set_tx_power(priv, conf->power_level, false);
2831 }
2832
2833 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2834 if (priv->cfg->ops->hcmd->set_rxon_chain)
2835 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2836
0cf4c01e
MA		 2837 if (!iwl_is_ready(priv)) {
2838 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2839 goto out;
2840 }
2841
4808368d
AK		 2842 if (scan_active)
2843 goto out;
2844
2845 if (memcmp(&priv->active_rxon,
2846 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2847 iwlcore_commit_rxon(priv);
2848 else
2849 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2850
2851
2852out:
2853 IWL_DEBUG_MAC80211(priv, "leave\n");
2854 mutex_unlock(&priv->mutex);
2855 return ret;
2856}
2857EXPORT_SYMBOL(iwl_mac_config);
2858
aa89f31e
AK		 2859int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2860 struct ieee80211_tx_queue_stats *stats)
2861{
2862 struct iwl_priv *priv = hw->priv;
2863 int i, avail;
2864 struct iwl_tx_queue *txq;
2865 struct iwl_queue *q;
2866 unsigned long flags;
2867
2868 IWL_DEBUG_MAC80211(priv, "enter\n");
2869
2870 if (!iwl_is_ready_rf(priv)) {
2871 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2872 return -EIO;
2873 }
2874
2875 spin_lock_irqsave(&priv->lock, flags);
2876
2877 for (i = 0; i < AC_NUM; i++) {
2878 txq = &priv->txq[i];
2879 q = &txq->q;
2880 avail = iwl_queue_space(q);
2881
2882 stats[i].len = q->n_window - avail;
2883 stats[i].limit = q->n_window - q->high_mark;
2884 stats[i].count = q->n_window;
2885
2886 }
2887 spin_unlock_irqrestore(&priv->lock, flags);
2888
2889 IWL_DEBUG_MAC80211(priv, "leave\n");
2890
2891 return 0;
2892}
2893EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2894
bd564261
AK		 2895void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2896{
2897 struct iwl_priv *priv = hw->priv;
2898 unsigned long flags;
2899
2900 mutex_lock(&priv->mutex);
2901 IWL_DEBUG_MAC80211(priv, "enter\n");
2902
2903 spin_lock_irqsave(&priv->lock, flags);
2904 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
2905 spin_unlock_irqrestore(&priv->lock, flags);
2906
2907 iwl_reset_qos(priv);
2908
2909 spin_lock_irqsave(&priv->lock, flags);
2910 priv->assoc_id = 0;
2911 priv->assoc_capability = 0;
2912 priv->assoc_station_added = 0;
2913
2914 /* new association get rid of ibss beacon skb */
2915 if (priv->ibss_beacon)
2916 dev_kfree_skb(priv->ibss_beacon);
2917
2918 priv->ibss_beacon = NULL;
2919
57c4d7b4 2920 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2921 priv->timestamp = 0;
2922 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2923 priv->beacon_int = 0;
2924
2925 spin_unlock_irqrestore(&priv->lock, flags);
2926
2927 if (!iwl_is_ready_rf(priv)) {
2928 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2929 mutex_unlock(&priv->mutex);
2930 return;
2931 }
2932
2933 /* we are restarting association process
2934 * clear RXON_FILTER_ASSOC_MSK bit
2935 */
2936 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2937 iwl_scan_cancel_timeout(priv, 100);
2938 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2939 iwlcore_commit_rxon(priv);
2940 }
2941
bd564261 2942 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2943 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2944 mutex_unlock(&priv->mutex);
2945 return;
2946 }
2947
2948 iwl_set_rate(priv);
2949
2950 mutex_unlock(&priv->mutex);
2951
2952 IWL_DEBUG_MAC80211(priv, "leave\n");
2953}
2954EXPORT_SYMBOL(iwl_mac_reset_tsf);
2955
20594eb0
WYG		 2956#ifdef CONFIG_IWLWIFI_DEBUGFS
2957
2958#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2959
2960void iwl_reset_traffic_log(struct iwl_priv *priv)
2961{
2962 priv->tx_traffic_idx = 0;
2963 priv->rx_traffic_idx = 0;
2964 if (priv->tx_traffic)
2965 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2966 if (priv->rx_traffic)
2967 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2968}
2969
2970int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2971{
2972 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2973
2974 if (iwl_debug_level & IWL_DL_TX) {
2975 if (!priv->tx_traffic) {
2976 priv->tx_traffic =
2977 kzalloc(traffic_size, GFP_KERNEL);
2978 if (!priv->tx_traffic)
2979 return -ENOMEM;
2980 }
2981 }
2982 if (iwl_debug_level & IWL_DL_RX) {
2983 if (!priv->rx_traffic) {
2984 priv->rx_traffic =
2985 kzalloc(traffic_size, GFP_KERNEL);
2986 if (!priv->rx_traffic)
2987 return -ENOMEM;
2988 }
2989 }
2990 iwl_reset_traffic_log(priv);
2991 return 0;
2992}
2993EXPORT_SYMBOL(iwl_alloc_traffic_mem);
2994
2995void iwl_free_traffic_mem(struct iwl_priv *priv)
2996{
2997 kfree(priv->tx_traffic);
2998 priv->tx_traffic = NULL;
2999
3000 kfree(priv->rx_traffic);
3001 priv->rx_traffic = NULL;
3002}
3003EXPORT_SYMBOL(iwl_free_traffic_mem);
3004
3005void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
3006 u16 length, struct ieee80211_hdr *header)
3007{
3008 __le16 fc;
3009 u16 len;
3010
3011 if (likely(!(iwl_debug_level & IWL_DL_TX)))
3012 return;
3013
3014 if (!priv->tx_traffic)
3015 return;
3016
3017 fc = header->frame_control;
3018 if (ieee80211_is_data(fc)) {
3019 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3020 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3021 memcpy((priv->tx_traffic +
3022 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3023 header, len);
3024 priv->tx_traffic_idx =
3025 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3026 }
3027}
3028EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
3029
3030void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
3031 u16 length, struct ieee80211_hdr *header)
3032{
3033 __le16 fc;
3034 u16 len;
3035
3036 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3037 return;
3038
3039 if (!priv->rx_traffic)
3040 return;
3041
3042 fc = header->frame_control;
3043 if (ieee80211_is_data(fc)) {
3044 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3045 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3046 memcpy((priv->rx_traffic +
3047 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3048 header, len);
3049 priv->rx_traffic_idx =
3050 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3051 }
3052}
3053EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
3054#endif
3055
6da3a13e
WYG		 3056#ifdef CONFIG_PM
3057
3058int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3059{
3060 struct iwl_priv *priv = pci_get_drvdata(pdev);
3061
3062 /*
3063 * This function is called when system goes into suspend state
3064 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3065 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3066 * it will not call apm_ops.stop() to stop the DMA operation.
3067 * Calling apm_ops.stop here to make sure we stop the DMA.
3068 */
3069 priv->cfg->ops->lib->apm_ops.stop(priv);
3070
3071 pci_save_state(pdev);
3072 pci_disable_device(pdev);
3073 pci_set_power_state(pdev, PCI_D3hot);
3074
3075 return 0;
3076}
3077EXPORT_SYMBOL(iwl_pci_suspend);
3078
3079int iwl_pci_resume(struct pci_dev *pdev)
3080{
3081 struct iwl_priv *priv = pci_get_drvdata(pdev);
3082 int ret;
3083
3084 pci_set_power_state(pdev, PCI_D0);
3085 ret = pci_enable_device(pdev);
3086 if (ret)
3087 return ret;
3088 pci_restore_state(pdev);
3089 iwl_enable_interrupts(priv);
3090
3091 return 0;
3092}
3093EXPORT_SYMBOL(iwl_pci_resume);
3094
3095#endif /* CONFIG_PM */
Linux kernel - Deliverables
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