projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: filling Tx MCS set
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/version.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
712b6cf5 34struct iwl_priv; /* FIXME: remove */
0a6857e7 35#include "iwl-debug.h"
6bc913bd 36#include "iwl-eeprom.h"
3e0d4cb1 37#include "iwl-dev.h" /* FIXME: remove */
df48c323 38#include "iwl-core.h"
b661c819 39#include "iwl-io.h"
ad97edd2 40#include "iwl-rfkill.h"
5da4b55f 41#include "iwl-power.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
46MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
62/*
63 * Parameter order:
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
70const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
85};
86EXPORT_SYMBOL(iwl4965_rates);
87
1d0a082d
AK		 88/* This function both allocates and initializes hw and priv. */
89struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
90 struct ieee80211_ops *hw_ops)
91{
92 struct iwl_priv *priv;
93
94 /* mac80211 allocates memory for this device instance, including
95 * space for this driver's private structure */
96 struct ieee80211_hw *hw =
97 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
98 if (hw == NULL) {
99 IWL_ERROR("Can not allocate network device\n");
100 goto out;
101 }
102
103 priv = hw->priv;
104 priv->hw = hw;
105
106out:
107 return hw;
108}
109EXPORT_SYMBOL(iwl_alloc_all);
110
b661c819
TW		 111void iwl_hw_detect(struct iwl_priv *priv)
112{
113 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
114 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
115 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
116}
117EXPORT_SYMBOL(iwl_hw_detect);
118
1053d35f
RR		 119/* Tell nic where to find the "keep warm" buffer */
120int iwl_kw_init(struct iwl_priv *priv)
121{
122 unsigned long flags;
123 int ret;
124
125 spin_lock_irqsave(&priv->lock, flags);
126 ret = iwl_grab_nic_access(priv);
127 if (ret)
128 goto out;
129
130 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
131 priv->kw.dma_addr >> 4);
132 iwl_release_nic_access(priv);
133out:
134 spin_unlock_irqrestore(&priv->lock, flags);
135 return ret;
136}
137
138int iwl_kw_alloc(struct iwl_priv *priv)
139{
140 struct pci_dev *dev = priv->pci_dev;
16466903 141 struct iwl_kw *kw = &priv->kw;
1053d35f 142
16466903 143 kw->size = IWL_KW_SIZE;
1053d35f
RR		 144 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
145 if (!kw->v_addr)
146 return -ENOMEM;
147
148 return 0;
149}
150
151/**
152 * iwl_kw_free - Free the "keep warm" buffer
153 */
154void iwl_kw_free(struct iwl_priv *priv)
155{
156 struct pci_dev *dev = priv->pci_dev;
16466903 157 struct iwl_kw *kw = &priv->kw;
1053d35f
RR		 158
159 if (kw->v_addr) {
160 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
161 memset(kw, 0, sizeof(*kw));
162 }
163}
164
165int iwl_hw_nic_init(struct iwl_priv *priv)
166{
167 unsigned long flags;
168 struct iwl_rx_queue *rxq = &priv->rxq;
169 int ret;
170
171 /* nic_init */
1053d35f 172 spin_lock_irqsave(&priv->lock, flags);
1b73af82 173 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 174 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
175 spin_unlock_irqrestore(&priv->lock, flags);
176
177 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
178
179 priv->cfg->ops->lib->apm_ops.config(priv);
180
181 /* Allocate the RX queue, or reset if it is already allocated */
182 if (!rxq->bd) {
183 ret = iwl_rx_queue_alloc(priv);
184 if (ret) {
185 IWL_ERROR("Unable to initialize Rx queue\n");
186 return -ENOMEM;
187 }
188 } else
189 iwl_rx_queue_reset(priv, rxq);
190
191 iwl_rx_replenish(priv);
192
193 iwl_rx_init(priv, rxq);
194
195 spin_lock_irqsave(&priv->lock, flags);
196
197 rxq->need_update = 1;
198 iwl_rx_queue_update_write_ptr(priv, rxq);
199
200 spin_unlock_irqrestore(&priv->lock, flags);
201
202 /* Allocate and init all Tx and Command queues */
203 ret = iwl_txq_ctx_reset(priv);
204 if (ret)
205 return ret;
206
207 set_bit(STATUS_INIT, &priv->status);
208
209 return 0;
210}
211EXPORT_SYMBOL(iwl_hw_nic_init);
212
bf85ea4f
AK		 213/**
214 * iwlcore_clear_stations_table - Clear the driver's station table
215 *
216 * NOTE: This does not clear or otherwise alter the device's station table.
217 */
218void iwlcore_clear_stations_table(struct iwl_priv *priv)
219{
220 unsigned long flags;
221
222 spin_lock_irqsave(&priv->sta_lock, flags);
223
224 priv->num_stations = 0;
225 memset(priv->stations, 0, sizeof(priv->stations));
226
227 spin_unlock_irqrestore(&priv->sta_lock, flags);
228}
229EXPORT_SYMBOL(iwlcore_clear_stations_table);
230
c7de35cd 231void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 232{
233 u16 cw_min = 15;
234 u16 cw_max = 1023;
235 u8 aifs = 2;
236 u8 is_legacy = 0;
237 unsigned long flags;
238 int i;
239
240 spin_lock_irqsave(&priv->lock, flags);
241 priv->qos_data.qos_active = 0;
242
243 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
244 if (priv->qos_data.qos_enable)
245 priv->qos_data.qos_active = 1;
246 if (!(priv->active_rate & 0xfff0)) {
247 cw_min = 31;
248 is_legacy = 1;
249 }
250 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
251 if (priv->qos_data.qos_enable)
252 priv->qos_data.qos_active = 1;
253 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
254 cw_min = 31;
255 is_legacy = 1;
256 }
257
258 if (priv->qos_data.qos_active)
259 aifs = 3;
260
261 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
262 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
263 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
264 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
265 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
266
267 if (priv->qos_data.qos_active) {
268 i = 1;
269 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
270 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
271 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
272 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
273 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
274
275 i = 2;
276 priv->qos_data.def_qos_parm.ac[i].cw_min =
277 cpu_to_le16((cw_min + 1) / 2 - 1);
278 priv->qos_data.def_qos_parm.ac[i].cw_max =
279 cpu_to_le16(cw_max);
280 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
281 if (is_legacy)
282 priv->qos_data.def_qos_parm.ac[i].edca_txop =
283 cpu_to_le16(6016);
284 else
285 priv->qos_data.def_qos_parm.ac[i].edca_txop =
286 cpu_to_le16(3008);
287 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
288
289 i = 3;
290 priv->qos_data.def_qos_parm.ac[i].cw_min =
291 cpu_to_le16((cw_min + 1) / 4 - 1);
292 priv->qos_data.def_qos_parm.ac[i].cw_max =
293 cpu_to_le16((cw_max + 1) / 2 - 1);
294 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
295 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
296 if (is_legacy)
297 priv->qos_data.def_qos_parm.ac[i].edca_txop =
298 cpu_to_le16(3264);
299 else
300 priv->qos_data.def_qos_parm.ac[i].edca_txop =
301 cpu_to_le16(1504);
302 } else {
303 for (i = 1; i < 4; i++) {
304 priv->qos_data.def_qos_parm.ac[i].cw_min =
305 cpu_to_le16(cw_min);
306 priv->qos_data.def_qos_parm.ac[i].cw_max =
307 cpu_to_le16(cw_max);
308 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
309 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
310 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
311 }
312 }
313 IWL_DEBUG_QOS("set QoS to default \n");
314
315 spin_unlock_irqrestore(&priv->lock, flags);
316}
c7de35cd
RR		 317EXPORT_SYMBOL(iwl_reset_qos);
318
319#ifdef CONFIG_IWL4965_HT
39130df3
RR		 320#define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
321#define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
c7de35cd
RR		 322static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
323 struct ieee80211_ht_info *ht_info,
324 enum ieee80211_band band)
325{
39130df3
RR		 326 u16 max_bit_rate = 0;
327 u8 rx_chains_num = priv->hw_params.rx_chains_num;
328 u8 tx_chains_num = priv->hw_params.tx_chains_num;
329
c7de35cd
RR		 330 ht_info->cap = 0;
331 memset(ht_info->supp_mcs_set, 0, 16);
332
333 ht_info->ht_supported = 1;
334
39130df3
RR		 335 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
336 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
337 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
338 (IWL_MIMO_PS_NONE << 2));
339
340 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd
RR		 341 if (priv->hw_params.fat_channel & BIT(band)) {
342 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
343 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
344 ht_info->supp_mcs_set[4] = 0x01;
39130df3 345 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 346 }
c7de35cd
RR		 347
348 if (priv->cfg->mod_params->amsdu_size_8K)
349 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
350
351 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
352 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
353
354 ht_info->supp_mcs_set[0] = 0xFF;
39130df3 355 if (rx_chains_num >= 2)
c7de35cd 356 ht_info->supp_mcs_set[1] = 0xFF;
39130df3 357 if (rx_chains_num >= 3)
c7de35cd 358 ht_info->supp_mcs_set[2] = 0xFF;
39130df3
RR		 359
360 /* Highest supported Rx data rate */
361 max_bit_rate *= rx_chains_num;
362 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
363 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
364
365 /* Tx MCS capabilities */
366 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
367 if (tx_chains_num != rx_chains_num) {
368 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
369 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
370 }
c7de35cd 371}
88787d28
AM		 372#else
373static inline void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
374 struct ieee80211_ht_info *ht_info,
375 enum ieee80211_band band)
376{
377}
c7de35cd
RR		 378#endif /* CONFIG_IWL4965_HT */
379
380static void iwlcore_init_hw_rates(struct iwl_priv *priv,
381 struct ieee80211_rate *rates)
382{
383 int i;
384
385 for (i = 0; i < IWL_RATE_COUNT; i++) {
386 rates[i].bitrate = iwl4965_rates[i].ieee * 5;
387 rates[i].hw_value = i; /* Rate scaling will work on indexes */
388 rates[i].hw_value_short = i;
389 rates[i].flags = 0;
390 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
391 /*
392 * If CCK != 1M then set short preamble rate flag.
393 */
394 rates[i].flags |=
395 (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ?
396 0 : IEEE80211_RATE_SHORT_PREAMBLE;
397 }
398 }
399}
400
401/**
402 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
403 */
404static int iwlcore_init_geos(struct iwl_priv *priv)
405{
406 struct iwl_channel_info *ch;
407 struct ieee80211_supported_band *sband;
408 struct ieee80211_channel *channels;
409 struct ieee80211_channel *geo_ch;
410 struct ieee80211_rate *rates;
411 int i = 0;
412
413 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
414 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
415 IWL_DEBUG_INFO("Geography modes already initialized.\n");
416 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
417 return 0;
418 }
419
420 channels = kzalloc(sizeof(struct ieee80211_channel) *
421 priv->channel_count, GFP_KERNEL);
422 if (!channels)
423 return -ENOMEM;
424
425 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
426 GFP_KERNEL);
427 if (!rates) {
428 kfree(channels);
429 return -ENOMEM;
430 }
431
432 /* 5.2GHz channels start after the 2.4GHz channels */
433 sband = &priv->bands[IEEE80211_BAND_5GHZ];
434 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
435 /* just OFDM */
436 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
437 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
438
439 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
440
441 sband = &priv->bands[IEEE80211_BAND_2GHZ];
442 sband->channels = channels;
443 /* OFDM & CCK */
444 sband->bitrates = rates;
445 sband->n_bitrates = IWL_RATE_COUNT;
446
447 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
448
449 priv->ieee_channels = channels;
450 priv->ieee_rates = rates;
451
452 iwlcore_init_hw_rates(priv, rates);
453
454 for (i = 0; i < priv->channel_count; i++) {
455 ch = &priv->channel_info[i];
456
457 /* FIXME: might be removed if scan is OK */
458 if (!is_channel_valid(ch))
459 continue;
460
461 if (is_channel_a_band(ch))
462 sband = &priv->bands[IEEE80211_BAND_5GHZ];
463 else
464 sband = &priv->bands[IEEE80211_BAND_2GHZ];
465
466 geo_ch = &sband->channels[sband->n_channels++];
467
468 geo_ch->center_freq =
469 ieee80211_channel_to_frequency(ch->channel);
470 geo_ch->max_power = ch->max_power_avg;
471 geo_ch->max_antenna_gain = 0xff;
472 geo_ch->hw_value = ch->channel;
473
474 if (is_channel_valid(ch)) {
475 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
476 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
477
478 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
479 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
480
481 if (ch->flags & EEPROM_CHANNEL_RADAR)
482 geo_ch->flags |= IEEE80211_CHAN_RADAR;
483
484 if (ch->max_power_avg > priv->max_channel_txpower_limit)
485 priv->max_channel_txpower_limit =
486 ch->max_power_avg;
487 } else {
488 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
489 }
490
491 /* Save flags for reg domain usage */
492 geo_ch->orig_flags = geo_ch->flags;
493
494 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
495 ch->channel, geo_ch->center_freq,
496 is_channel_a_band(ch) ? "5.2" : "2.4",
497 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
498 "restricted" : "valid",
499 geo_ch->flags);
500 }
501
502 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
503 priv->cfg->sku & IWL_SKU_A) {
504 printk(KERN_INFO DRV_NAME
505 ": Incorrectly detected BG card as ABG. Please send "
506 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
507 priv->pci_dev->device, priv->pci_dev->subsystem_device);
508 priv->cfg->sku &= ~IWL_SKU_A;
509 }
510
511 printk(KERN_INFO DRV_NAME
512 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
513 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
514 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
515
516 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
517 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
518 &priv->bands[IEEE80211_BAND_2GHZ];
519 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
520 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
521 &priv->bands[IEEE80211_BAND_5GHZ];
522
523 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
524
525 return 0;
526}
527
528/*
529 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
530 */
531void iwlcore_free_geos(struct iwl_priv *priv)
532{
533 kfree(priv->ieee_channels);
534 kfree(priv->ieee_rates);
535 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
536}
537EXPORT_SYMBOL(iwlcore_free_geos);
538
539#ifdef CONFIG_IWL4965_HT
540static u8 is_single_rx_stream(struct iwl_priv *priv)
541{
542 return !priv->current_ht_config.is_ht ||
543 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
544 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
545 priv->ps_mode == IWL_MIMO_PS_STATIC;
546}
47c5196e
TW		 547static u8 iwl_is_channel_extension(struct iwl_priv *priv,
548 enum ieee80211_band band,
549 u16 channel, u8 extension_chan_offset)
550{
551 const struct iwl_channel_info *ch_info;
552
553 ch_info = iwl_get_channel_info(priv, band, channel);
554 if (!is_channel_valid(ch_info))
555 return 0;
556
557 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
558 return 0;
559
560 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
561 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
562 return 1;
563
564 return 0;
565}
566
567u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
568 struct ieee80211_ht_info *sta_ht_inf)
569{
570 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
571
572 if ((!iwl_ht_conf->is_ht) ||
573 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
574 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
575 return 0;
576
577 if (sta_ht_inf) {
578 if ((!sta_ht_inf->ht_supported) ||
579 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
580 return 0;
581 }
582
583 return iwl_is_channel_extension(priv, priv->band,
584 iwl_ht_conf->control_channel,
585 iwl_ht_conf->extension_chan_offset);
586}
587EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
588
589void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
590{
591 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
592 u32 val;
593
594 if (!ht_info->is_ht)
595 return;
596
597 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
598 if (iwl_is_fat_tx_allowed(priv, NULL))
599 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
600 else
601 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
602 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
603
604 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
605 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
606 le16_to_cpu(rxon->channel),
607 ht_info->control_channel);
608 rxon->channel = cpu_to_le16(ht_info->control_channel);
609 return;
610 }
611
612 /* Note: control channel is opposite of extension channel */
613 switch (ht_info->extension_chan_offset) {
614 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
615 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
616 break;
617 case IWL_EXT_CHANNEL_OFFSET_BELOW:
618 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
619 break;
620 case IWL_EXT_CHANNEL_OFFSET_NONE:
621 default:
622 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
623 break;
624 }
625
626 val = ht_info->ht_protection;
627
628 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
629
630 iwl_set_rxon_chain(priv);
631
632 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
633 "rxon flags 0x%X operation mode :0x%X "
634 "extension channel offset 0x%x "
635 "control chan %d\n",
636 ht_info->supp_mcs_set[0],
637 ht_info->supp_mcs_set[1],
638 ht_info->supp_mcs_set[2],
639 le32_to_cpu(rxon->flags), ht_info->ht_protection,
640 ht_info->extension_chan_offset,
641 ht_info->control_channel);
642 return;
643}
644EXPORT_SYMBOL(iwl_set_rxon_ht);
645
c7de35cd
RR		 646#else
647static inline u8 is_single_rx_stream(struct iwl_priv *priv)
648{
649 return 1;
650}
651#endif /*CONFIG_IWL4965_HT */
652
653/*
654 * Determine how many receiver/antenna chains to use.
655 * More provides better reception via diversity. Fewer saves power.
656 * MIMO (dual stream) requires at least 2, but works better with 3.
657 * This does not determine *which* chains to use, just how many.
658 */
659static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
660 u8 *idle_state, u8 *rx_state)
661{
662 u8 is_single = is_single_rx_stream(priv);
663 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
664
665 /* # of Rx chains to use when expecting MIMO. */
666 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
667 *rx_state = 2;
668 else
669 *rx_state = 3;
670
671 /* # Rx chains when idling and maybe trying to save power */
672 switch (priv->ps_mode) {
673 case IWL_MIMO_PS_STATIC:
674 case IWL_MIMO_PS_DYNAMIC:
675 *idle_state = (is_cam) ? 2 : 1;
676 break;
677 case IWL_MIMO_PS_NONE:
678 *idle_state = (is_cam) ? *rx_state : 1;
679 break;
680 default:
681 *idle_state = 1;
682 break;
683 }
684
685 return 0;
686}
687
688/**
689 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
690 *
691 * Selects how many and which Rx receivers/antennas/chains to use.
692 * This should not be used for scan command ... it puts data in wrong place.
693 */
694void iwl_set_rxon_chain(struct iwl_priv *priv)
695{
696 u8 is_single = is_single_rx_stream(priv);
697 u8 idle_state, rx_state;
698
699 priv->staging_rxon.rx_chain = 0;
700 rx_state = idle_state = 3;
701
702 /* Tell uCode which antennas are actually connected.
703 * Before first association, we assume all antennas are connected.
704 * Just after first association, iwl_chain_noise_calibration()
705 * checks which antennas actually *are* connected. */
706 priv->staging_rxon.rx_chain |=
707 cpu_to_le16(priv->hw_params.valid_rx_ant <<
708 RXON_RX_CHAIN_VALID_POS);
709
710 /* How many receivers should we use? */
711 iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
712 priv->staging_rxon.rx_chain |=
713 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
714 priv->staging_rxon.rx_chain |=
715 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
716
717 if (!is_single && (rx_state >= 2) &&
718 !test_bit(STATUS_POWER_PMI, &priv->status))
719 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
720 else
721 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
722
723 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
724}
725EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 726
727/**
728 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
729 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
730 * @channel: Any channel valid for the requested phymode
731
732 * In addition to setting the staging RXON, priv->phymode is also set.
733 *
734 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
735 * in the staging RXON flag structure based on the phymode
736 */
c7de35cd 737int iwl_set_rxon_channel(struct iwl_priv *priv,
bf85ea4f
AK		 738 enum ieee80211_band band,
739 u16 channel)
740{
8622e705 741 if (!iwl_get_channel_info(priv, band, channel)) {
bf85ea4f
AK		 742 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
743 channel, band);
744 return -EINVAL;
745 }
746
747 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
748 (priv->band == band))
749 return 0;
750
751 priv->staging_rxon.channel = cpu_to_le16(channel);
752 if (band == IEEE80211_BAND_5GHZ)
753 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
754 else
755 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
756
757 priv->band = band;
758
759 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
760
761 return 0;
762}
c7de35cd 763EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f
AK		 764
765static void iwlcore_init_hw(struct iwl_priv *priv)
766{
767 struct ieee80211_hw *hw = priv->hw;
768 hw->rate_control_algorithm = "iwl-4965-rs";
769
566bfe5a
BR		 770 /* Tell mac80211 our characteristics */
771 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
772 IEEE80211_HW_SIGNAL_DBM |
773 IEEE80211_HW_NOISE_DBM;
bf85ea4f
AK		 774 /* Default value; 4 EDCA QOS priorities */
775 hw->queues = 4;
776#ifdef CONFIG_IWL4965_HT
777 /* Enhanced value; more queues, to support 11n aggregation */
e100bb64 778 hw->ampdu_queues = 12;
bf85ea4f
AK		 779#endif /* CONFIG_IWL4965_HT */
780}
781
c7de35cd
RR		 782static int iwlcore_init_drv(struct iwl_priv *priv)
783{
784 int ret;
785 int i;
786
787 priv->retry_rate = 1;
788 priv->ibss_beacon = NULL;
789
790 spin_lock_init(&priv->lock);
791 spin_lock_init(&priv->power_data.lock);
792 spin_lock_init(&priv->sta_lock);
793 spin_lock_init(&priv->hcmd_lock);
794 spin_lock_init(&priv->lq_mngr.lock);
795
796 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
797 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
798
799 INIT_LIST_HEAD(&priv->free_frames);
800
801 mutex_init(&priv->mutex);
802
803 /* Clear the driver's (not device's) station table */
804 iwlcore_clear_stations_table(priv);
805
806 priv->data_retry_limit = -1;
807 priv->ieee_channels = NULL;
808 priv->ieee_rates = NULL;
809 priv->band = IEEE80211_BAND_2GHZ;
810
811 priv->iw_mode = IEEE80211_IF_TYPE_STA;
812
813 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
814 priv->ps_mode = IWL_MIMO_PS_NONE;
815
816 /* Choose which receivers/antennas to use */
817 iwl_set_rxon_chain(priv);
818
819 iwl_reset_qos(priv);
820
821 priv->qos_data.qos_active = 0;
822 priv->qos_data.qos_cap.val = 0;
823
824 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
825
826 priv->rates_mask = IWL_RATES_MASK;
827 /* If power management is turned on, default to AC mode */
828 priv->power_mode = IWL_POWER_AC;
829 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
830
831 ret = iwl_init_channel_map(priv);
832 if (ret) {
833 IWL_ERROR("initializing regulatory failed: %d\n", ret);
834 goto err;
835 }
836
837 ret = iwlcore_init_geos(priv);
838 if (ret) {
839 IWL_ERROR("initializing geos failed: %d\n", ret);
840 goto err_free_channel_map;
841 }
842
843 ret = ieee80211_register_hw(priv->hw);
844 if (ret) {
845 IWL_ERROR("Failed to register network device (error %d)\n",
846 ret);
847 goto err_free_geos;
848 }
849
850 priv->hw->conf.beacon_int = 100;
851 priv->mac80211_registered = 1;
852
853 return 0;
854
855err_free_geos:
856 iwlcore_free_geos(priv);
857err_free_channel_map:
858 iwl_free_channel_map(priv);
859err:
860 return ret;
861}
862
bf85ea4f
AK		 863int iwl_setup(struct iwl_priv *priv)
864{
865 int ret = 0;
866 iwlcore_init_hw(priv);
c7de35cd 867 ret = iwlcore_init_drv(priv);
bf85ea4f
AK		 868 return ret;
869}
870EXPORT_SYMBOL(iwl_setup);
871
c8381fdc
MA		 872/* Low level driver call this function to update iwlcore with
873 * driver status.
874 */
875int iwlcore_low_level_notify(struct iwl_priv *priv,
876 enum iwlcore_card_notify notify)
877{
03d29c68 878 int ret;
c8381fdc
MA		 879 switch (notify) {
880 case IWLCORE_INIT_EVT:
03d29c68
MA		 881 ret = iwl_rfkill_init(priv);
882 if (ret)
883 IWL_ERROR("Unable to initialize RFKILL system. "
884 "Ignoring error: %d\n", ret);
5da4b55f 885 iwl_power_initialize(priv);
c8381fdc
MA		 886 break;
887 case IWLCORE_START_EVT:
5da4b55f 888 iwl_power_update_mode(priv, 1);
c8381fdc
MA		 889 break;
890 case IWLCORE_STOP_EVT:
891 break;
892 case IWLCORE_REMOVE_EVT:
ad97edd2 893 iwl_rfkill_unregister(priv);
c8381fdc
MA		 894 break;
895 }
896
897 return 0;
898}
899EXPORT_SYMBOL(iwlcore_low_level_notify);
900
49ea8596
EG		 901int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
902{
903 u32 stat_flags = 0;
904 struct iwl_host_cmd cmd = {
905 .id = REPLY_STATISTICS_CMD,
906 .meta.flags = flags,
907 .len = sizeof(stat_flags),
908 .data = (u8 *) &stat_flags,
909 };
910 return iwl_send_cmd(priv, &cmd);
911}
912EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 913
b0692f2f
EG		 914/**
915 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
916 * using sample data 100 bytes apart. If these sample points are good,
917 * it's a pretty good bet that everything between them is good, too.
918 */
919static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
920{
921 u32 val;
922 int ret = 0;
923 u32 errcnt = 0;
924 u32 i;
925
926 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
927
928 ret = iwl_grab_nic_access(priv);
929 if (ret)
930 return ret;
931
932 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
933 /* read data comes through single port, auto-incr addr */
934 /* NOTE: Use the debugless read so we don't flood kernel log
935 * if IWL_DL_IO is set */
936 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
937 i + RTC_INST_LOWER_BOUND);
938 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
939 if (val != le32_to_cpu(*image)) {
940 ret = -EIO;
941 errcnt++;
942 if (errcnt >= 3)
943 break;
944 }
945 }
946
947 iwl_release_nic_access(priv);
948
949 return ret;
950}
951
952/**
953 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
954 * looking at all data.
955 */
956static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
957 u32 len)
958{
959 u32 val;
960 u32 save_len = len;
961 int ret = 0;
962 u32 errcnt;
963
964 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
965
966 ret = iwl_grab_nic_access(priv);
967 if (ret)
968 return ret;
969
970 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
971
972 errcnt = 0;
973 for (; len > 0; len -= sizeof(u32), image++) {
974 /* read data comes through single port, auto-incr addr */
975 /* NOTE: Use the debugless read so we don't flood kernel log
976 * if IWL_DL_IO is set */
977 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
978 if (val != le32_to_cpu(*image)) {
979 IWL_ERROR("uCode INST section is invalid at "
980 "offset 0x%x, is 0x%x, s/b 0x%x\n",
981 save_len - len, val, le32_to_cpu(*image));
982 ret = -EIO;
983 errcnt++;
984 if (errcnt >= 20)
985 break;
986 }
987 }
988
989 iwl_release_nic_access(priv);
990
991 if (!errcnt)
992 IWL_DEBUG_INFO
993 ("ucode image in INSTRUCTION memory is good\n");
994
995 return ret;
996}
997
998/**
999 * iwl_verify_ucode - determine which instruction image is in SRAM,
1000 * and verify its contents
1001 */
1002int iwl_verify_ucode(struct iwl_priv *priv)
1003{
1004 __le32 *image;
1005 u32 len;
1006 int ret;
1007
1008 /* Try bootstrap */
1009 image = (__le32 *)priv->ucode_boot.v_addr;
1010 len = priv->ucode_boot.len;
1011 ret = iwlcore_verify_inst_sparse(priv, image, len);
1012 if (!ret) {
1013 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1014 return 0;
1015 }
1016
1017 /* Try initialize */
1018 image = (__le32 *)priv->ucode_init.v_addr;
1019 len = priv->ucode_init.len;
1020 ret = iwlcore_verify_inst_sparse(priv, image, len);
1021 if (!ret) {
1022 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1023 return 0;
1024 }
1025
1026 /* Try runtime/protocol */
1027 image = (__le32 *)priv->ucode_code.v_addr;
1028 len = priv->ucode_code.len;
1029 ret = iwlcore_verify_inst_sparse(priv, image, len);
1030 if (!ret) {
1031 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1032 return 0;
1033 }
1034
1035 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1036
1037 /* Since nothing seems to match, show first several data entries in
1038 * instruction SRAM, so maybe visual inspection will give a clue.
1039 * Selection of bootstrap image (vs. other images) is arbitrary. */
1040 image = (__le32 *)priv->ucode_boot.v_addr;
1041 len = priv->ucode_boot.len;
1042 ret = iwl_verify_inst_full(priv, image, len);
1043
1044 return ret;
1045}
1046EXPORT_SYMBOL(iwl_verify_ucode);
1047
Linux kernel - Deliverables
This page took 0.131926 seconds and 5 git commands to generate.