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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groec...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
901069c7 5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
d43c36dc 32#include <linux/sched.h>
5a0e3ad6 33#include <linux/slab.h>
1d0a082d 34#include <net/mac80211.h>
df48c323 35
6bc913bd 36#include "iwl-eeprom.h"
19335774 37#include "iwl-debug.h"
df48c323 38#include "iwl-core.h"
b661c819 39#include "iwl-io.h"
5da4b55f 40#include "iwl-power.h"
c6baf7fb 41#include "iwl-agn.h"
48f20d35 42#include "iwl-shared.h"
9d143e9a 43#include "iwl-agn.h"
bdfbf092 44#include "iwl-trans.h"
df48c323 45
57bd1bea 46const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
57bd1bea 47
d9fe60de
JB		 48#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
49#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
b39488a9 50static void iwl_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 51 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 52 enum ieee80211_band band)
53{
39130df3 54 u16 max_bit_rate = 0;
d6189124
EG		 55 u8 rx_chains_num = hw_params(priv).rx_chains_num;
56 u8 tx_chains_num = hw_params(priv).tx_chains_num;
39130df3 57
c7de35cd 58 ht_info->cap = 0;
d9fe60de 59 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 60
d9fe60de 61 ht_info->ht_supported = true;
c7de35cd 62
7cb1b088
WYG		 63 if (priv->cfg->ht_params &&
64 priv->cfg->ht_params->ht_greenfield_support)
b261793d 65 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de 66 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
39130df3 67 max_bit_rate = MAX_BIT_RATE_20_MHZ;
d6189124 68 if (hw_params(priv).ht40_channel & BIT(band)) {
d9fe60de
JB		 69 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
70 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
71 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 72 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 73 }
c7de35cd 74
9d143e9a 75 if (iwlagn_mod_params.amsdu_size_8K)
d9fe60de 76 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 77
78 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
7cb1b088
WYG		 79 if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_factor)
80 ht_info->ampdu_factor = priv->cfg->bt_params->ampdu_factor;
c7de35cd 81 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
7cb1b088
WYG		 82 if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_density)
83 ht_info->ampdu_density = priv->cfg->bt_params->ampdu_density;
c7de35cd 84
d9fe60de 85 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 86 if (rx_chains_num >= 2)
d9fe60de 87 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 88 if (rx_chains_num >= 3)
d9fe60de 89 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 90
91 /* Highest supported Rx data rate */
92 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 93 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
94 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 95
96 /* Tx MCS capabilities */
d9fe60de 97 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 98 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 99 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
100 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
101 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 102 }
c7de35cd 103}
c7de35cd 104
c7de35cd 105/**
b39488a9 106 * iwl_init_geos - Initialize mac80211's geo/channel info based from eeprom
c7de35cd 107 */
b39488a9 108int iwl_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 109{
110 struct iwl_channel_info *ch;
111 struct ieee80211_supported_band *sband;
112 struct ieee80211_channel *channels;
113 struct ieee80211_channel *geo_ch;
114 struct ieee80211_rate *rates;
115 int i = 0;
75d80cad 116 s8 max_tx_power = IWLAGN_TX_POWER_TARGET_POWER_MIN;
c7de35cd
RR		 117
118 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
119 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 120 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
63013ae3 121 set_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status);
c7de35cd
RR		 122 return 0;
123 }
124
7f90dce1
EG		 125 channels = kcalloc(priv->channel_count,
126 sizeof(struct ieee80211_channel), GFP_KERNEL);
c7de35cd
RR		 127 if (!channels)
128 return -ENOMEM;
129
7f90dce1 130 rates = kcalloc(IWL_RATE_COUNT_LEGACY, sizeof(struct ieee80211_rate),
c7de35cd
RR		 131 GFP_KERNEL);
132 if (!rates) {
133 kfree(channels);
134 return -ENOMEM;
135 }
136
137 /* 5.2GHz channels start after the 2.4GHz channels */
138 sband = &priv->bands[IEEE80211_BAND_5GHZ];
139 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
140 /* just OFDM */
141 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 142 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 143
88950758 144 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
b39488a9 145 iwl_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 146 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 147
148 sband = &priv->bands[IEEE80211_BAND_2GHZ];
149 sband->channels = channels;
150 /* OFDM & CCK */
151 sband->bitrates = rates;
5027309b 152 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 153
88950758 154 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
b39488a9 155 iwl_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 156 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 157
158 priv->ieee_channels = channels;
159 priv->ieee_rates = rates;
160
c7de35cd
RR		 161 for (i = 0; i < priv->channel_count; i++) {
162 ch = &priv->channel_info[i];
163
164 /* FIXME: might be removed if scan is OK */
165 if (!is_channel_valid(ch))
166 continue;
167
5a3a0352 168 sband = &priv->bands[ch->band];
c7de35cd
RR		 169
170 geo_ch = &sband->channels[sband->n_channels++];
171
172 geo_ch->center_freq =
5a3a0352 173 ieee80211_channel_to_frequency(ch->channel, ch->band);
c7de35cd
RR		 174 geo_ch->max_power = ch->max_power_avg;
175 geo_ch->max_antenna_gain = 0xff;
176 geo_ch->hw_value = ch->channel;
177
178 if (is_channel_valid(ch)) {
179 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
180 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
181
182 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
183 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
184
185 if (ch->flags & EEPROM_CHANNEL_RADAR)
186 geo_ch->flags |= IEEE80211_CHAN_RADAR;
187
7aafef1c 188 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 189
75d80cad
SG		 190 if (ch->max_power_avg > max_tx_power)
191 max_tx_power = ch->max_power_avg;
c7de35cd
RR		 192 } else {
193 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
194 }
195
e1623446 196 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 197 ch->channel, geo_ch->center_freq,
198 is_channel_a_band(ch) ? "5.2" : "2.4",
199 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
200 "restricted" : "valid",
201 geo_ch->flags);
202 }
203
75d80cad
SG		 204 priv->tx_power_device_lmt = max_tx_power;
205 priv->tx_power_user_lmt = max_tx_power;
206 priv->tx_power_next = max_tx_power;
207
c7de35cd 208 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
88950758 209 priv->cfg->sku & EEPROM_SKU_CAP_BAND_52GHZ) {
19707bac 210 char buf[32];
26bfc0cf 211 bus_get_hw_id(bus(priv), buf, sizeof(buf));
978785a3 212 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
19707bac 213 "Please send your %s to maintainer.\n", buf);
88950758 214 priv->cfg->sku &= ~EEPROM_SKU_CAP_BAND_52GHZ;
c7de35cd
RR		 215 }
216
978785a3 217 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 218 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
219 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd 220
63013ae3 221 set_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status);
c7de35cd
RR		 222
223 return 0;
224}
225
226/*
b39488a9 227 * iwl_free_geos - undo allocations in iwl_init_geos
c7de35cd 228 */
b39488a9 229void iwl_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 230{
231 kfree(priv->ieee_channels);
232 kfree(priv->ieee_rates);
63013ae3 233 clear_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status);
c7de35cd 234}
c7de35cd 235
7e6a5886
JB		 236static bool iwl_is_channel_extension(struct iwl_priv *priv,
237 enum ieee80211_band band,
238 u16 channel, u8 extension_chan_offset)
47c5196e
TW		 239{
240 const struct iwl_channel_info *ch_info;
241
242 ch_info = iwl_get_channel_info(priv, band, channel);
243 if (!is_channel_valid(ch_info))
7e6a5886 244 return false;
47c5196e 245
d9fe60de 246 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 247 return !(ch_info->ht40_extension_channel &
689da1b3 248 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 249 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 250 return !(ch_info->ht40_extension_channel &
689da1b3 251 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e 252
7e6a5886 253 return false;
47c5196e
TW		 254}
255
7e6a5886
JB		 256bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
257 struct iwl_rxon_context *ctx,
258 struct ieee80211_sta_ht_cap *ht_cap)
47c5196e 259{
7e6a5886
JB		 260 if (!ctx->ht.enabled || !ctx->ht.is_40mhz)
261 return false;
47c5196e 262
7e6a5886
JB		 263 /*
264 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
a2b0f02e
WYG		 265 * the bit will not set if it is pure 40MHz case
266 */
7e6a5886
JB		 267 if (ht_cap && !ht_cap->ht_supported)
268 return false;
269
d73e4923 270#ifdef CONFIG_IWLWIFI_DEBUGFS
1e4247d4 271 if (priv->disable_ht40)
7e6a5886 272 return false;
1e4247d4 273#endif
7e6a5886 274
611d3eb7 275 return iwl_is_channel_extension(priv, priv->band,
246ed355 276 le16_to_cpu(ctx->staging.channel),
7e6a5886 277 ctx->ht.extension_chan_offset);
47c5196e 278}
47c5196e 279
2c2f3b33
TW		 280static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
281{
ea196fdb
JB		 282 u16 new_val;
283 u16 beacon_factor;
284
285 /*
286 * If mac80211 hasn't given us a beacon interval, program
287 * the default into the device (not checking this here
288 * would cause the adjustment below to return the maximum
289 * value, which may break PAN.)
290 */
291 if (!beacon_val)
292 return DEFAULT_BEACON_INTERVAL;
293
294 /*
295 * If the beacon interval we obtained from the peer
296 * is too large, we'll have to wake up more often
297 * (and in IBSS case, we'll beacon too much)
298 *
299 * For example, if max_beacon_val is 4096, and the
300 * requested beacon interval is 7000, we'll have to
301 * use 3500 to be able to wake up on the beacons.
302 *
303 * This could badly influence beacon detection stats.
304 */
2c2f3b33
TW		 305
306 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
307 new_val = beacon_val / beacon_factor;
308
309 if (!new_val)
310 new_val = max_beacon_val;
311
312 return new_val;
313}
314
47313e34 315int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2c2f3b33
TW		 316{
317 u64 tsf;
318 s32 interval_tm, rem;
2c2f3b33
TW		 319 struct ieee80211_conf *conf = NULL;
320 u16 beacon_int;
47313e34 321 struct ieee80211_vif *vif = ctx->vif;
2c2f3b33 322
8c222544 323 conf = &priv->hw->conf;
2c2f3b33 324
6ac2f839 325 lockdep_assert_held(&priv->shrd->mutex);
948f5a2f 326
246ed355 327 memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd));
948f5a2f 328
246ed355
JB		 329 ctx->timing.timestamp = cpu_to_le64(priv->timestamp);
330 ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval);
2c2f3b33 331
47313e34 332 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
2c2f3b33 333
47313e34
JB		 334 /*
335 * TODO: For IBSS we need to get atim_window from mac80211,
336 * for now just always use 0
337 */
338 ctx->timing.atim_window = 0;
2c2f3b33 339
bde4530e 340 if (ctx->ctxid == IWL_RXON_CTX_PAN &&
f1f270b2
JB		 341 (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) &&
342 iwl_is_associated(priv, IWL_RXON_CTX_BSS) &&
343 priv->contexts[IWL_RXON_CTX_BSS].vif &&
344 priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) {
bde4530e
JB		 345 ctx->timing.beacon_interval =
346 priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval;
347 beacon_int = le16_to_cpu(ctx->timing.beacon_interval);
f1f270b2
JB		 348 } else if (ctx->ctxid == IWL_RXON_CTX_BSS &&
349 iwl_is_associated(priv, IWL_RXON_CTX_PAN) &&
350 priv->contexts[IWL_RXON_CTX_PAN].vif &&
351 priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int &&
352 (!iwl_is_associated_ctx(ctx) || !ctx->vif ||
353 !ctx->vif->bss_conf.beacon_int)) {
354 ctx->timing.beacon_interval =
355 priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval;
356 beacon_int = le16_to_cpu(ctx->timing.beacon_interval);
bde4530e
JB		 357 } else {
358 beacon_int = iwl_adjust_beacon_interval(beacon_int,
ab9e212e 359 IWL_MAX_UCODE_BEACON_INTERVAL * TIME_UNIT);
bde4530e
JB		 360 ctx->timing.beacon_interval = cpu_to_le16(beacon_int);
361 }
2c2f3b33 362
bbb05cb5
JB		 363 ctx->beacon_int = beacon_int;
364
2c2f3b33 365 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
f8525e55 366 interval_tm = beacon_int * TIME_UNIT;
2c2f3b33 367 rem = do_div(tsf, interval_tm);
246ed355 368 ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
2c2f3b33 369
47313e34 370 ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1;
2491fa42 371
2c2f3b33
TW		 372 IWL_DEBUG_ASSOC(priv,
373 "beacon interval %d beacon timer %d beacon tim %d\n",
246ed355
JB		 374 le16_to_cpu(ctx->timing.beacon_interval),
375 le32_to_cpu(ctx->timing.beacon_init_val),
376 le16_to_cpu(ctx->timing.atim_window));
948f5a2f 377
e6bb4c9c 378 return iwl_trans_send_cmd_pdu(trans(priv), ctx->rxon_timing_cmd,
e419d62d 379 CMD_SYNC, sizeof(ctx->timing), &ctx->timing);
2c2f3b33 380}
2c2f3b33 381
246ed355
JB		 382void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
383 int hw_decrypt)
8ccde88a 384{
246ed355 385 struct iwl_rxon_cmd *rxon = &ctx->staging;
8ccde88a
SO		 386
387 if (hw_decrypt)
388 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
389 else
390 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
391
392}
8ccde88a 393
dacefedb 394/* validate RXON structure is valid */
246ed355 395int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
8ccde88a 396{
246ed355 397 struct iwl_rxon_cmd *rxon = &ctx->staging;
c914ac26 398 u32 errors = 0;
8ccde88a
SO		 399
400 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
dacefedb
JB		 401 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
402 IWL_WARN(priv, "check 2.4G: wrong narrow\n");
c914ac26 403 errors |= BIT(0);
dacefedb
JB		 404 }
405 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
406 IWL_WARN(priv, "check 2.4G: wrong radar\n");
c914ac26 407 errors |= BIT(1);
dacefedb 408 }
8ccde88a 409 } else {
dacefedb
JB		 410 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
411 IWL_WARN(priv, "check 5.2G: not short slot!\n");
c914ac26 412 errors |= BIT(2);
dacefedb
JB		 413 }
414 if (rxon->flags & RXON_FLG_CCK_MSK) {
415 IWL_WARN(priv, "check 5.2G: CCK!\n");
c914ac26 416 errors |= BIT(3);
dacefedb
JB		 417 }
418 }
419 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
420 IWL_WARN(priv, "mac/bssid mcast!\n");
c914ac26 421 errors |= BIT(4);
8ccde88a 422 }
8ccde88a
SO		 423
424 /* make sure basic rates 6Mbps and 1Mbps are supported */
dacefedb
JB		 425 if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 &&
426 (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) {
427 IWL_WARN(priv, "neither 1 nor 6 are basic\n");
c914ac26 428 errors |= BIT(5);
dacefedb 429 }
8ccde88a 430
dacefedb
JB		 431 if (le16_to_cpu(rxon->assoc_id) > 2007) {
432 IWL_WARN(priv, "aid > 2007\n");
c914ac26 433 errors |= BIT(6);
dacefedb 434 }
8ccde88a 435
dacefedb
JB		 436 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
437 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
438 IWL_WARN(priv, "CCK and short slot\n");
c914ac26 439 errors |= BIT(7);
dacefedb 440 }
8ccde88a 441
dacefedb
JB		 442 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
443 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
444 IWL_WARN(priv, "CCK and auto detect");
c914ac26 445 errors |= BIT(8);
dacefedb 446 }
8ccde88a 447
dacefedb
JB		 448 if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
449 RXON_FLG_TGG_PROTECT_MSK)) ==
450 RXON_FLG_TGG_PROTECT_MSK) {
451 IWL_WARN(priv, "TGg but no auto-detect\n");
c914ac26 452 errors |= BIT(9);
dacefedb 453 }
8ccde88a 454
c914ac26
JB		 455 if (rxon->channel == 0) {
456 IWL_WARN(priv, "zero channel is invalid\n");
457 errors |= BIT(10);
8ccde88a 458 }
c914ac26
JB		 459
460 WARN(errors, "Invalid RXON (%#x), channel %d",
461 errors, le16_to_cpu(rxon->channel));
462
463 return errors ? -EINVAL : 0;
8ccde88a 464}
8ccde88a
SO		 465
466/**
467 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
468 * @priv: staging_rxon is compared to active_rxon
469 *
470 * If the RXON structure is changing enough to require a new tune,
471 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
472 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
473 */
246ed355
JB		 474int iwl_full_rxon_required(struct iwl_priv *priv,
475 struct iwl_rxon_context *ctx)
8ccde88a 476{
246ed355
JB		 477 const struct iwl_rxon_cmd *staging = &ctx->staging;
478 const struct iwl_rxon_cmd *active = &ctx->active;
479
480#define CHK(cond) \
481 if ((cond)) { \
482 IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \
483 return 1; \
484 }
485
486#define CHK_NEQ(c1, c2) \
487 if ((c1) != (c2)) { \
488 IWL_DEBUG_INFO(priv, "need full RXON - " \
489 #c1 " != " #c2 " - %d != %d\n", \
490 (c1), (c2)); \
491 return 1; \
492 }
8ccde88a
SO		 493
494 /* These items are only settable from the full RXON command */
246ed355
JB		 495 CHK(!iwl_is_associated_ctx(ctx));
496 CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
497 CHK(compare_ether_addr(staging->node_addr, active->node_addr));
498 CHK(compare_ether_addr(staging->wlap_bssid_addr,
499 active->wlap_bssid_addr));
500 CHK_NEQ(staging->dev_type, active->dev_type);
501 CHK_NEQ(staging->channel, active->channel);
502 CHK_NEQ(staging->air_propagation, active->air_propagation);
503 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
504 active->ofdm_ht_single_stream_basic_rates);
505 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
506 active->ofdm_ht_dual_stream_basic_rates);
507 CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates,
508 active->ofdm_ht_triple_stream_basic_rates);
509 CHK_NEQ(staging->assoc_id, active->assoc_id);
8ccde88a
SO		 510
511 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
512 * be updated with the RXON_ASSOC command -- however only some
513 * flag transitions are allowed using RXON_ASSOC */
514
515 /* Check if we are not switching bands */
246ed355
JB		 516 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
517 active->flags & RXON_FLG_BAND_24G_MSK);
8ccde88a
SO		 518
519 /* Check if we are switching association toggle */
246ed355
JB		 520 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
521 active->filter_flags & RXON_FILTER_ASSOC_MSK);
522
523#undef CHK
524#undef CHK_NEQ
8ccde88a
SO		 525
526 return 0;
527}
8ccde88a 528
246ed355
JB		 529static void _iwl_set_rxon_ht(struct iwl_priv *priv,
530 struct iwl_ht_config *ht_conf,
531 struct iwl_rxon_context *ctx)
47c5196e 532{
246ed355 533 struct iwl_rxon_cmd *rxon = &ctx->staging;
47c5196e 534
7e6a5886 535 if (!ctx->ht.enabled) {
a2b0f02e 536 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 537 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 538 RXON_FLG_HT40_PROT_MSK |
42eb7c64 539 RXON_FLG_HT_PROT_MSK);
47c5196e 540 return;
42eb7c64 541 }
47c5196e 542
7e6a5886 543 /* FIXME: if the definition of ht.protection changed, the "translation"
a2b0f02e
WYG		 544 * will be needed for rxon->flags
545 */
7e6a5886 546 rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 547
548 /* Set up channel bandwidth:
7aafef1c 549 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 550 /* clear the HT channel mode before set the mode */
551 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
552 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7e6a5886 553 if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) {
7aafef1c 554 /* pure ht40 */
7e6a5886 555 if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 556 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 557 /* Note: control channel is opposite of extension channel */
7e6a5886 558 switch (ctx->ht.extension_chan_offset) {
508b08e7
WYG		 559 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
560 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
561 break;
562 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
563 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
564 break;
565 }
566 } else {
a2b0f02e 567 /* Note: control channel is opposite of extension channel */
7e6a5886 568 switch (ctx->ht.extension_chan_offset) {
a2b0f02e
WYG		 569 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
570 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
571 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
572 break;
573 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
574 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
575 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
576 break;
577 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
578 default:
579 /* channel location only valid if in Mixed mode */
580 IWL_ERR(priv, "invalid extension channel offset\n");
581 break;
582 }
583 }
584 } else {
585 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 586 }
587
e3f10cea 588 iwlagn_set_rxon_chain(priv, ctx);
47c5196e 589
02bb1bea 590 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 591 "extension channel offset 0x%x\n",
7e6a5886
JB		 592 le32_to_cpu(rxon->flags), ctx->ht.protection,
593 ctx->ht.extension_chan_offset);
47c5196e 594}
246ed355
JB		 595
596void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
597{
598 struct iwl_rxon_context *ctx;
599
600 for_each_context(priv, ctx)
601 _iwl_set_rxon_ht(priv, ht_conf, ctx);
602}
47c5196e 603
246ed355 604/* Return valid, unused, channel for a passive scan to reset the RF */
14023641 605u8 iwl_get_single_channel_number(struct iwl_priv *priv,
246ed355 606 enum ieee80211_band band)
14023641
AK		 607{
608 const struct iwl_channel_info *ch_info;
609 int i;
610 u8 channel = 0;
246ed355
JB		 611 u8 min, max;
612 struct iwl_rxon_context *ctx;
14023641 613
14023641 614 if (band == IEEE80211_BAND_5GHZ) {
246ed355
JB		 615 min = 14;
616 max = priv->channel_count;
14023641 617 } else {
246ed355
JB		 618 min = 0;
619 max = 14;
620 }
621
622 for (i = min; i < max; i++) {
623 bool busy = false;
624
625 for_each_context(priv, ctx) {
626 busy = priv->channel_info[i].channel ==
627 le16_to_cpu(ctx->staging.channel);
628 if (busy)
629 break;
14023641 630 }
246ed355
JB		 631
632 if (busy)
633 continue;
634
635 channel = priv->channel_info[i].channel;
636 ch_info = iwl_get_channel_info(priv, band, channel);
637 if (is_channel_valid(ch_info))
638 break;
14023641
AK		 639 }
640
641 return channel;
642}
14023641 643
bf85ea4f 644/**
3edb5fd6
SZ		 645 * iwl_set_rxon_channel - Set the band and channel values in staging RXON
646 * @ch: requested channel as a pointer to struct ieee80211_channel
bf85ea4f 647
bf85ea4f 648 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3edb5fd6 649 * in the staging RXON flag structure based on the ch->band
bf85ea4f 650 */
246ed355
JB		 651int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch,
652 struct iwl_rxon_context *ctx)
bf85ea4f 653{
17e72782 654 enum ieee80211_band band = ch->band;
81e95430 655 u16 channel = ch->hw_value;
17e72782 656
246ed355 657 if ((le16_to_cpu(ctx->staging.channel) == channel) &&
bf85ea4f
AK		 658 (priv->band == band))
659 return 0;
660
246ed355 661 ctx->staging.channel = cpu_to_le16(channel);
bf85ea4f 662 if (band == IEEE80211_BAND_5GHZ)
246ed355 663 ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
bf85ea4f 664 else
246ed355 665 ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
bf85ea4f
AK		 666
667 priv->band = band;
668
e1623446 669 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 670
671 return 0;
672}
bf85ea4f 673
79d07325 674void iwl_set_flags_for_band(struct iwl_priv *priv,
246ed355 675 struct iwl_rxon_context *ctx,
79d07325
WYG		 676 enum ieee80211_band band,
677 struct ieee80211_vif *vif)
8ccde88a
SO		 678{
679 if (band == IEEE80211_BAND_5GHZ) {
246ed355 680 ctx->staging.flags &=
8ccde88a
SO		 681 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
682 | RXON_FLG_CCK_MSK);
246ed355 683 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
8ccde88a
SO		 684 } else {
685 /* Copied from iwl_post_associate() */
c213d745 686 if (vif && vif->bss_conf.use_short_slot)
246ed355 687 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
8ccde88a 688 else
246ed355 689 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
8ccde88a 690
246ed355
JB		 691 ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
692 ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
693 ctx->staging.flags &= ~RXON_FLG_CCK_MSK;
8ccde88a
SO		 694 }
695}
8ccde88a
SO		 696
697/*
698 * initialize rxon structure with default values from eeprom
699 */
1dda6d28 700void iwl_connection_init_rx_config(struct iwl_priv *priv,
d0fe478c 701 struct iwl_rxon_context *ctx)
8ccde88a
SO		 702{
703 const struct iwl_channel_info *ch_info;
704
246ed355 705 memset(&ctx->staging, 0, sizeof(ctx->staging));
8ccde88a 706
d0fe478c
JB		 707 if (!ctx->vif) {
708 ctx->staging.dev_type = ctx->unused_devtype;
709 } else switch (ctx->vif->type) {
8ccde88a 710 case NL80211_IFTYPE_AP:
d0fe478c 711 ctx->staging.dev_type = ctx->ap_devtype;
8ccde88a
SO		 712 break;
713
714 case NL80211_IFTYPE_STATION:
d0fe478c 715 ctx->staging.dev_type = ctx->station_devtype;
246ed355 716 ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
8ccde88a
SO		 717 break;
718
719 case NL80211_IFTYPE_ADHOC:
d0fe478c 720 ctx->staging.dev_type = ctx->ibss_devtype;
246ed355
JB		 721 ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
722 ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
8ccde88a
SO		 723 RXON_FILTER_ACCEPT_GRP_MSK;
724 break;
725
8ccde88a 726 default:
d0fe478c
JB		 727 IWL_ERR(priv, "Unsupported interface type %d\n",
728 ctx->vif->type);
8ccde88a
SO		 729 break;
730 }
731
732#if 0
733 /* TODO: Figure out when short_preamble would be set and cache from
734 * that */
735 if (!hw_to_local(priv->hw)->short_preamble)
246ed355 736 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
8ccde88a 737 else
246ed355 738 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
8ccde88a
SO		 739#endif
740
741 ch_info = iwl_get_channel_info(priv, priv->band,
246ed355 742 le16_to_cpu(ctx->active.channel));
8ccde88a
SO		 743
744 if (!ch_info)
745 ch_info = &priv->channel_info[0];
746
246ed355 747 ctx->staging.channel = cpu_to_le16(ch_info->channel);
8ccde88a
SO		 748 priv->band = ch_info->band;
749
d0fe478c 750 iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif);
8ccde88a 751
246ed355 752 ctx->staging.ofdm_basic_rates =
8ccde88a 753 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
246ed355 754 ctx->staging.cck_basic_rates =
8ccde88a
SO		 755 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
756
a2b0f02e 757 /* clear both MIX and PURE40 mode flag */
246ed355 758 ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
a2b0f02e 759 RXON_FLG_CHANNEL_MODE_PURE_40);
d0fe478c
JB		 760 if (ctx->vif)
761 memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN);
7684c408 762
246ed355
JB		 763 ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff;
764 ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
765 ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a 766}
8ccde88a 767
79d07325 768void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 769{
770 const struct ieee80211_supported_band *hw = NULL;
771 struct ieee80211_rate *rate;
246ed355 772 struct iwl_rxon_context *ctx;
8ccde88a
SO		 773 int i;
774
775 hw = iwl_get_hw_mode(priv, priv->band);
776 if (!hw) {
777 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
778 return;
779 }
780
781 priv->active_rate = 0;
8ccde88a
SO		 782
783 for (i = 0; i < hw->n_bitrates; i++) {
784 rate = &(hw->bitrates[i]);
5027309b 785 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 786 priv->active_rate |= (1 << rate->hw_value);
787 }
788
4a02886b 789 IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate);
8ccde88a 790
246ed355
JB		 791 for_each_context(priv, ctx) {
792 ctx->staging.cck_basic_rates =
793 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
4a02886b 794
246ed355
JB		 795 ctx->staging.ofdm_basic_rates =
796 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
797 }
8ccde88a 798}
79d07325
WYG		 799
800void iwl_chswitch_done(struct iwl_priv *priv, bool is_success)
801{
8bd413e6
JB		 802 /*
803 * MULTI-FIXME
ade4c649 804 * See iwlagn_mac_channel_switch.
8bd413e6
JB		 805 */
806 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
807
63013ae3 808 if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status))
79d07325
WYG		 809 return;
810
63013ae3
EG		 811 if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING,
812 &priv->shrd->status))
8bd413e6 813 ieee80211_chswitch_done(ctx->vif, is_success);
79d07325 814}
8ccde88a 815
8ccde88a 816#ifdef CONFIG_IWLWIFI_DEBUG
14991a9d
EG		 817void iwl_print_rx_config_cmd(struct iwl_priv *priv,
818 enum iwl_rxon_context_id ctxid)
8ccde88a 819{
522376d2 820 struct iwl_rxon_context *ctx = &priv->contexts[ctxid];
246ed355 821 struct iwl_rxon_cmd *rxon = &ctx->staging;
8ccde88a 822
e1623446 823 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 824 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 825 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
826 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
827 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 828 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 829 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
830 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 831 rxon->ofdm_basic_rates);
e1623446
TW		 832 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
833 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
834 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
835 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 836}
6686d17e 837#endif
e649437f 838
e74fe233
JB		 839static void iwlagn_abort_notification_waits(struct iwl_priv *priv)
840{
841 unsigned long flags;
842 struct iwl_notification_wait *wait_entry;
843
898ed67b
WYG		 844 spin_lock_irqsave(&priv->notif_wait_lock, flags);
845 list_for_each_entry(wait_entry, &priv->notif_waits, list)
e74fe233 846 wait_entry->aborted = true;
898ed67b 847 spin_unlock_irqrestore(&priv->notif_wait_lock, flags);
e74fe233 848
898ed67b 849 wake_up_all(&priv->notif_waitq);
e74fe233
JB		 850}
851
e649437f 852void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand)
8ccde88a 853{
491bc292
WYG		 854 unsigned int reload_msec;
855 unsigned long reload_jiffies;
856
8ccde88a 857 /* Set the FW error flag -- cleared on iwl_down */
63013ae3 858 set_bit(STATUS_FW_ERROR, &priv->shrd->status);
8ccde88a
SO		 859
860 /* Cancel currently queued command. */
63013ae3 861 clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status);
8ccde88a 862
e74fe233
JB		 863 iwlagn_abort_notification_waits(priv);
864
e649437f
JB		 865 /* Keep the restart process from trying to send host
866 * commands by clearing the ready bit */
63013ae3 867 clear_bit(STATUS_READY, &priv->shrd->status);
e649437f 868
effd4d9a 869 wake_up(&priv->shrd->wait_command_queue);
e649437f
JB		 870
871 if (!ondemand) {
872 /*
873 * If firmware keep reloading, then it indicate something
874 * serious wrong and firmware having problem to recover
875 * from it. Instead of keep trying which will fill the syslog
876 * and hang the system, let's just stop it
877 */
878 reload_jiffies = jiffies;
879 reload_msec = jiffies_to_msecs((long) reload_jiffies -
880 (long) priv->reload_jiffies);
881 priv->reload_jiffies = reload_jiffies;
882 if (reload_msec <= IWL_MIN_RELOAD_DURATION) {
883 priv->reload_count++;
884 if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) {
885 IWL_ERR(priv, "BUG_ON, Stop restarting\n");
886 return;
887 }
888 } else
889 priv->reload_count = 0;
890 }
891
63013ae3 892 if (!test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) {
9d143e9a 893 if (iwlagn_mod_params.restart_fw) {
9ca06f0a 894 IWL_DEBUG_FW_ERRORS(priv,
e649437f 895 "Restarting adapter due to uCode error.\n");
74e28e44 896 queue_work(priv->shrd->workqueue, &priv->restart);
e649437f 897 } else
9ca06f0a 898 IWL_DEBUG_FW_ERRORS(priv,
e649437f
JB		 899 "Detected FW error, but not restarting\n");
900 }
901}
902
f8e200de 903static int iwl_apm_stop_master(struct iwl_priv *priv)
d68b603c 904{
5220af0c 905 int ret = 0;
d68b603c 906
5220af0c 907 /* stop device's busmaster DMA activity */
83ed9015 908 iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
d68b603c 909
83ed9015
EG		 910 ret = iwl_poll_bit(bus(priv), CSR_RESET,
911 CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c 912 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
5220af0c
BC		 913 if (ret)
914 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
d68b603c 915
d68b603c
AK		 916 IWL_DEBUG_INFO(priv, "stop master\n");
917
5220af0c 918 return ret;
d68b603c 919}
d68b603c
AK		 920
921void iwl_apm_stop(struct iwl_priv *priv)
922{
fadb3582
BC		 923 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
924
63013ae3 925 clear_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status);
9d39e5ba 926
5220af0c 927 /* Stop device's DMA activity */
d68b603c
AK		 928 iwl_apm_stop_master(priv);
929
5220af0c 930 /* Reset the entire device */
83ed9015 931 iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
d68b603c
AK		 932
933 udelay(10);
5220af0c
BC		 934
935 /*
936 * Clear "initialization complete" bit to move adapter from
937 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
938 */
83ed9015 939 iwl_clear_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
d68b603c 940}
d68b603c 941
fadb3582
BC		 942
943/*
944 * Start up NIC's basic functionality after it has been reset
945 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
946 * NOTE: This does not load uCode nor start the embedded processor
947 */
948int iwl_apm_init(struct iwl_priv *priv)
949{
950 int ret = 0;
fadb3582
BC		 951 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
952
953 /*
954 * Use "set_bit" below rather than "write", to preserve any hardware
955 * bits already set by default after reset.
956 */
957
958 /* Disable L0S exit timer (platform NMI Work/Around) */
83ed9015 959 iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS,
fadb3582
BC		 960 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
961
962 /*
963 * Disable L0s without affecting L1;
964 * don't wait for ICH L0s (ICH bug W/A)
965 */
83ed9015 966 iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS,
fadb3582
BC		 967 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
968
969 /* Set FH wait threshold to maximum (HW error during stress W/A) */
83ed9015 970 iwl_set_bit(bus(priv), CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
fadb3582
BC		 971
972 /*
973 * Enable HAP INTA (interrupt from management bus) to
974 * wake device's PCI Express link L1a -> L0s
fadb3582 975 */
83ed9015 976 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
fadb3582
BC		 977 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
978
26bfc0cf 979 bus_apm_config(bus(priv));
fadb3582
BC		 980
981 /* Configure analog phase-lock-loop before activating to D0A */
7cb1b088 982 if (priv->cfg->base_params->pll_cfg_val)
83ed9015 983 iwl_set_bit(bus(priv), CSR_ANA_PLL_CFG,
7cb1b088 984 priv->cfg->base_params->pll_cfg_val);
fadb3582
BC		 985
986 /*
987 * Set "initialization complete" bit to move adapter from
988 * D0U* --> D0A* (powered-up active) state.
989 */
83ed9015 990 iwl_set_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
fadb3582
BC		 991
992 /*
993 * Wait for clock stabilization; once stabilized, access to
994 * device-internal resources is supported, e.g. iwl_write_prph()
995 * and accesses to uCode SRAM.
996 */
83ed9015 997 ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL,
fadb3582
BC		 998 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
999 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1000 if (ret < 0) {
1001 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1002 goto out;
1003 }
1004
1005 /*
917b6777 1006 * Enable DMA clock and wait for it to stabilize.
fadb3582
BC		 1007 *
1008 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1009 * do not disable clocks. This preserves any hardware bits already
1010 * set by default in "CLK_CTRL_REG" after reset.
1011 */
83ed9015 1012 iwl_write_prph(bus(priv), APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
fadb3582
BC		 1013 udelay(20);
1014
1015 /* Disable L1-Active */
83ed9015 1016 iwl_set_bits_prph(bus(priv), APMG_PCIDEV_STT_REG,
fadb3582
BC		 1017 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1018
63013ae3 1019 set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status);
9d39e5ba 1020
fadb3582
BC		 1021out:
1022 return ret;
1023}
fadb3582
BC		 1024
1025
630fe9b6
TW		 1026int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1027{
a25a66ac
SG		 1028 int ret;
1029 s8 prev_tx_power;
f844a709
SG		 1030 bool defer;
1031 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
a25a66ac 1032
6ac2f839 1033 lockdep_assert_held(&priv->shrd->mutex);
a25a66ac
SG		 1034
1035 if (priv->tx_power_user_lmt == tx_power && !force)
1036 return 0;
1037
b744cb79
WYG		 1038 if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) {
1039 IWL_WARN(priv,
1040 "Requested user TXPOWER %d below lower limit %d.\n",
daf518de 1041 tx_power,
b744cb79 1042 IWLAGN_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1043 return -EINVAL;
1044 }
1045
dc1b0973 1046 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1047 IWL_WARN(priv,
1048 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1049 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1050 return -EINVAL;
1051 }
1052
845a9c0d 1053 if (!iwl_is_ready_rf(priv->shrd))
a25a66ac 1054 return -EIO;
630fe9b6 1055
f844a709
SG		 1056 /* scan complete and commit_rxon use tx_power_next value,
1057 * it always need to be updated for newest request */
a25a66ac 1058 priv->tx_power_next = tx_power;
f844a709
SG		 1059
1060 /* do not set tx power when scanning or channel changing */
63013ae3 1061 defer = test_bit(STATUS_SCANNING, &priv->shrd->status) ||
f844a709
SG		 1062 memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging));
1063 if (defer && !force) {
1064 IWL_DEBUG_INFO(priv, "Deferring tx power set\n");
a25a66ac 1065 return 0;
5eadd94b 1066 }
630fe9b6 1067
a25a66ac
SG		 1068 prev_tx_power = priv->tx_power_user_lmt;
1069 priv->tx_power_user_lmt = tx_power;
1070
5beaaf37 1071 ret = iwlagn_send_tx_power(priv);
a25a66ac
SG		 1072
1073 /* if fail to set tx_power, restore the orig. tx power */
1074 if (ret) {
1075 priv->tx_power_user_lmt = prev_tx_power;
1076 priv->tx_power_next = prev_tx_power;
1077 }
630fe9b6
TW		 1078 return ret;
1079}
630fe9b6 1080
65b52bde 1081void iwl_send_bt_config(struct iwl_priv *priv)
17f841cd
SO		 1082{
1083 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 1084 .lead_time = BT_LEAD_TIME_DEF,
1085 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 1086 .kill_ack_mask = 0,
1087 .kill_cts_mask = 0,
1088 };
1089
b60eec9b 1090 if (!iwlagn_mod_params.bt_coex_active)
06702a73
WYG		 1091 bt_cmd.flags = BT_COEX_DISABLE;
1092 else
1093 bt_cmd.flags = BT_COEX_ENABLE;
1094
f21dd005 1095 priv->bt_enable_flag = bt_cmd.flags;
06702a73
WYG		 1096 IWL_DEBUG_INFO(priv, "BT coex %s\n",
1097 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
1098
e6bb4c9c 1099 if (iwl_trans_send_cmd_pdu(trans(priv), REPLY_BT_CONFIG,
e419d62d 1100 CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd))
65b52bde 1101 IWL_ERR(priv, "failed to send BT Coex Config\n");
17f841cd 1102}
17f841cd 1103
ef8d5529 1104int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
49ea8596 1105{
ef8d5529
WYG		 1106 struct iwl_statistics_cmd statistics_cmd = {
1107 .configuration_flags =
1108 clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
49ea8596 1109 };
ef8d5529
WYG		 1110
1111 if (flags & CMD_ASYNC)
e6bb4c9c 1112 return iwl_trans_send_cmd_pdu(trans(priv), REPLY_STATISTICS_CMD,
e419d62d 1113 CMD_ASYNC,
ef8d5529 1114 sizeof(struct iwl_statistics_cmd),
e419d62d 1115 &statistics_cmd);
ef8d5529 1116 else
e6bb4c9c 1117 return iwl_trans_send_cmd_pdu(trans(priv), REPLY_STATISTICS_CMD,
e419d62d 1118 CMD_SYNC,
ef8d5529
WYG		 1119 sizeof(struct iwl_statistics_cmd),
1120 &statistics_cmd);
49ea8596 1121}
7e8c519e 1122
ade4c649 1123int iwlagn_mac_conf_tx(struct ieee80211_hw *hw,
8a3a3c85
EP		 1124 struct ieee80211_vif *vif, u16 queue,
1125 const struct ieee80211_tx_queue_params *params)
488829f1
AK		 1126{
1127 struct iwl_priv *priv = hw->priv;
8dfdb9d5 1128 struct iwl_rxon_context *ctx;
488829f1
AK		 1129 unsigned long flags;
1130 int q;
1131
1132 IWL_DEBUG_MAC80211(priv, "enter\n");
1133
845a9c0d 1134 if (!iwl_is_ready_rf(priv->shrd)) {
488829f1
AK		 1135 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
1136 return -EIO;
1137 }
1138
1139 if (queue >= AC_NUM) {
1140 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
1141 return 0;
1142 }
1143
1144 q = AC_NUM - 1 - queue;
1145
10b15e6f 1146 spin_lock_irqsave(&priv->shrd->lock, flags);
488829f1 1147
8dfdb9d5
JB		 1148 /*
1149 * MULTI-FIXME
1150 * This may need to be done per interface in nl80211/cfg80211/mac80211.
1151 */
1152 for_each_context(priv, ctx) {
1153 ctx->qos_data.def_qos_parm.ac[q].cw_min =
1154 cpu_to_le16(params->cw_min);
1155 ctx->qos_data.def_qos_parm.ac[q].cw_max =
1156 cpu_to_le16(params->cw_max);
1157 ctx->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
1158 ctx->qos_data.def_qos_parm.ac[q].edca_txop =
1159 cpu_to_le16((params->txop * 32));
1160
1161 ctx->qos_data.def_qos_parm.ac[q].reserved1 = 0;
1162 }
488829f1 1163
10b15e6f 1164 spin_unlock_irqrestore(&priv->shrd->lock, flags);
488829f1
AK		 1165
1166 IWL_DEBUG_MAC80211(priv, "leave\n");
1167 return 0;
1168}
5bbe233b 1169
ade4c649 1170int iwlagn_mac_tx_last_beacon(struct ieee80211_hw *hw)
a85d7cca
JB		 1171{
1172 struct iwl_priv *priv = hw->priv;
1173
1174 return priv->ibss_manager == IWL_IBSS_MANAGER;
1175}
a85d7cca 1176
d4daaea6 1177static int iwl_set_mode(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
727882d6 1178{
d0fe478c 1179 iwl_connection_init_rx_config(priv, ctx);
727882d6 1180
e3f10cea 1181 iwlagn_set_rxon_chain(priv, ctx);
727882d6 1182
805a3b81 1183 return iwlagn_commit_rxon(priv, ctx);
727882d6 1184}
727882d6 1185
d4daaea6
JB		 1186static int iwl_setup_interface(struct iwl_priv *priv,
1187 struct iwl_rxon_context *ctx)
1188{
1189 struct ieee80211_vif *vif = ctx->vif;
1190 int err;
1191
6ac2f839 1192 lockdep_assert_held(&priv->shrd->mutex);
d4daaea6
JB		 1193
1194 /*
1195 * This variable will be correct only when there's just
1196 * a single context, but all code using it is for hardware
1197 * that supports only one context.
1198 */
1199 priv->iw_mode = vif->type;
1200
1201 ctx->is_active = true;
1202
1203 err = iwl_set_mode(priv, ctx);
1204 if (err) {
1205 if (!ctx->always_active)
1206 ctx->is_active = false;
1207 return err;
1208 }
1209
1210 if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist &&
1211 vif->type == NL80211_IFTYPE_ADHOC) {
1212 /*
1213 * pretend to have high BT traffic as long as we
1214 * are operating in IBSS mode, as this will cause
1215 * the rate scaling etc. to behave as intended.
1216 */
1217 priv->bt_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1218 }
1219
1220 return 0;
1221}
1222
ade4c649
WYG		 1223int iwlagn_mac_add_interface(struct ieee80211_hw *hw,
1224 struct ieee80211_vif *vif)
cbb6ab94
AK		 1225{
1226 struct iwl_priv *priv = hw->priv;
246ed355 1227 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
d0fe478c 1228 struct iwl_rxon_context *tmp, *ctx = NULL;
d4daaea6 1229 int err;
f35c0c56 1230 enum nl80211_iftype viftype = ieee80211_vif_type_p2p(vif);
cbb6ab94 1231
3779db10 1232 IWL_DEBUG_MAC80211(priv, "enter: type %d, addr %pM\n",
f35c0c56 1233 viftype, vif->addr);
cbb6ab94 1234
c6baf7fb
JB		 1235 cancel_delayed_work_sync(&priv->hw_roc_disable_work);
1236
6ac2f839 1237 mutex_lock(&priv->shrd->mutex);
47e28f41 1238
c6baf7fb
JB		 1239 iwlagn_disable_roc(priv);
1240
845a9c0d 1241 if (!iwl_is_ready_rf(priv->shrd)) {
4bd530f3 1242 IWL_WARN(priv, "Try to add interface when device not ready\n");
b55e75ed
JB		 1243 err = -EINVAL;
1244 goto out;
1245 }
1246
d0fe478c
JB		 1247 for_each_context(priv, tmp) {
1248 u32 possible_modes =
1249 tmp->interface_modes | tmp->exclusive_interface_modes;
1250
1251 if (tmp->vif) {
1252 /* check if this busy context is exclusive */
1253 if (tmp->exclusive_interface_modes &
1254 BIT(tmp->vif->type)) {
1255 err = -EINVAL;
1256 goto out;
1257 }
1258 continue;
1259 }
1260
f35c0c56 1261 if (!(possible_modes & BIT(viftype)))
d0fe478c
JB		 1262 continue;
1263
1264 /* have maybe usable context w/o interface */
1265 ctx = tmp;
1266 break;
1267 }
1268
1269 if (!ctx) {
47e28f41
JB		 1270 err = -EOPNOTSUPP;
1271 goto out;
cbb6ab94
AK		 1272 }
1273
d0fe478c 1274 vif_priv->ctx = ctx;
8bd413e6 1275 ctx->vif = vif;
59079949 1276
d4daaea6
JB		 1277 err = iwl_setup_interface(priv, ctx);
1278 if (!err)
1279 goto out;
cbb6ab94 1280
8bd413e6 1281 ctx->vif = NULL;
b55e75ed 1282 priv->iw_mode = NL80211_IFTYPE_STATION;
47e28f41 1283 out:
6ac2f839 1284 mutex_unlock(&priv->shrd->mutex);
cbb6ab94
AK		 1285
1286 IWL_DEBUG_MAC80211(priv, "leave\n");
47e28f41 1287 return err;
cbb6ab94 1288}
cbb6ab94 1289
d4daaea6
JB		 1290static void iwl_teardown_interface(struct iwl_priv *priv,
1291 struct ieee80211_vif *vif,
1292 bool mode_change)
d8052319 1293{
246ed355 1294 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
d8052319 1295
6ac2f839 1296 lockdep_assert_held(&priv->shrd->mutex);
d0fe478c 1297
e7e16b90
SG		 1298 if (priv->scan_vif == vif) {
1299 iwl_scan_cancel_timeout(priv, 200);
1300 iwl_force_scan_end(priv);
1301 }
8bd413e6 1302
d4daaea6
JB		 1303 if (!mode_change) {
1304 iwl_set_mode(priv, ctx);
1305 if (!ctx->always_active)
1306 ctx->is_active = false;
1307 }
763cc3bf 1308
59079949
JB		 1309 /*
1310 * When removing the IBSS interface, overwrite the
1311 * BT traffic load with the stored one from the last
1312 * notification, if any. If this is a device that
1313 * doesn't implement this, this has no effect since
1314 * both values are the same and zero.
1315 */
1316 if (vif->type == NL80211_IFTYPE_ADHOC)
66e863a5 1317 priv->bt_traffic_load = priv->last_bt_traffic_load;
d4daaea6
JB		 1318}
1319
ade4c649 1320void iwlagn_mac_remove_interface(struct ieee80211_hw *hw,
d4daaea6
JB		 1321 struct ieee80211_vif *vif)
1322{
1323 struct iwl_priv *priv = hw->priv;
1324 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
1325
1326 IWL_DEBUG_MAC80211(priv, "enter\n");
1327
6ac2f839 1328 mutex_lock(&priv->shrd->mutex);
d4daaea6 1329
1dd9124e
EG		 1330 if (WARN_ON(ctx->vif != vif)) {
1331 struct iwl_rxon_context *tmp;
1332 IWL_ERR(priv, "ctx->vif = %p, vif = %p\n", ctx->vif, vif);
1333 for_each_context(priv, tmp)
1334 IWL_ERR(priv, "\tID = %d:\tctx = %p\tctx->vif = %p\n",
1335 tmp->ctxid, tmp, tmp->vif);
1336 }
d4daaea6
JB		 1337 ctx->vif = NULL;
1338
1339 iwl_teardown_interface(priv, vif, false);
59079949 1340
6ac2f839 1341 mutex_unlock(&priv->shrd->mutex);
d8052319
AK		 1342
1343 IWL_DEBUG_MAC80211(priv, "leave\n");
1344
1345}
d8052319 1346
20594eb0
WYG		 1347#ifdef CONFIG_IWLWIFI_DEBUGFS
1348
1349#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
1350
1351void iwl_reset_traffic_log(struct iwl_priv *priv)
1352{
1353 priv->tx_traffic_idx = 0;
1354 priv->rx_traffic_idx = 0;
1355 if (priv->tx_traffic)
1356 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
1357 if (priv->rx_traffic)
1358 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
1359}
1360
1361int iwl_alloc_traffic_mem(struct iwl_priv *priv)
1362{
1363 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
1364
8f470ce3 1365 if (iwl_get_debug_level(priv->shrd) & IWL_DL_TX) {
20594eb0
WYG		 1366 if (!priv->tx_traffic) {
1367 priv->tx_traffic =
1368 kzalloc(traffic_size, GFP_KERNEL);
1369 if (!priv->tx_traffic)
1370 return -ENOMEM;
1371 }
1372 }
8f470ce3 1373 if (iwl_get_debug_level(priv->shrd) & IWL_DL_RX) {
20594eb0
WYG		 1374 if (!priv->rx_traffic) {
1375 priv->rx_traffic =
1376 kzalloc(traffic_size, GFP_KERNEL);
1377 if (!priv->rx_traffic)
1378 return -ENOMEM;
1379 }
1380 }
1381 iwl_reset_traffic_log(priv);
1382 return 0;
1383}
20594eb0
WYG		 1384
1385void iwl_free_traffic_mem(struct iwl_priv *priv)
1386{
1387 kfree(priv->tx_traffic);
1388 priv->tx_traffic = NULL;
1389
1390 kfree(priv->rx_traffic);
1391 priv->rx_traffic = NULL;
1392}
20594eb0
WYG		 1393
1394void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
1395 u16 length, struct ieee80211_hdr *header)
1396{
1397 __le16 fc;
1398 u16 len;
1399
8f470ce3 1400 if (likely(!(iwl_get_debug_level(priv->shrd) & IWL_DL_TX)))
20594eb0
WYG		 1401 return;
1402
1403 if (!priv->tx_traffic)
1404 return;
1405
1406 fc = header->frame_control;
1407 if (ieee80211_is_data(fc)) {
1408 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
1409 ? IWL_TRAFFIC_ENTRY_SIZE : length;
1410 memcpy((priv->tx_traffic +
1411 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
1412 header, len);
1413 priv->tx_traffic_idx =
1414 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
1415 }
1416}
20594eb0
WYG		 1417
1418void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
1419 u16 length, struct ieee80211_hdr *header)
1420{
1421 __le16 fc;
1422 u16 len;
1423
8f470ce3 1424 if (likely(!(iwl_get_debug_level(priv->shrd) & IWL_DL_RX)))
20594eb0
WYG		 1425 return;
1426
1427 if (!priv->rx_traffic)
1428 return;
1429
1430 fc = header->frame_control;
1431 if (ieee80211_is_data(fc)) {
1432 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
1433 ? IWL_TRAFFIC_ENTRY_SIZE : length;
1434 memcpy((priv->rx_traffic +
1435 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
1436 header, len);
1437 priv->rx_traffic_idx =
1438 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
1439 }
1440}
22fdf3c9
WYG		 1441
1442const char *get_mgmt_string(int cmd)
1443{
1444 switch (cmd) {
1445 IWL_CMD(MANAGEMENT_ASSOC_REQ);
1446 IWL_CMD(MANAGEMENT_ASSOC_RESP);
1447 IWL_CMD(MANAGEMENT_REASSOC_REQ);
1448 IWL_CMD(MANAGEMENT_REASSOC_RESP);
1449 IWL_CMD(MANAGEMENT_PROBE_REQ);
1450 IWL_CMD(MANAGEMENT_PROBE_RESP);
1451 IWL_CMD(MANAGEMENT_BEACON);
1452 IWL_CMD(MANAGEMENT_ATIM);
1453 IWL_CMD(MANAGEMENT_DISASSOC);
1454 IWL_CMD(MANAGEMENT_AUTH);
1455 IWL_CMD(MANAGEMENT_DEAUTH);
1456 IWL_CMD(MANAGEMENT_ACTION);
1457 default:
1458 return "UNKNOWN";
1459
1460 }
1461}
1462
1463const char *get_ctrl_string(int cmd)
1464{
1465 switch (cmd) {
1466 IWL_CMD(CONTROL_BACK_REQ);
1467 IWL_CMD(CONTROL_BACK);
1468 IWL_CMD(CONTROL_PSPOLL);
1469 IWL_CMD(CONTROL_RTS);
1470 IWL_CMD(CONTROL_CTS);
1471 IWL_CMD(CONTROL_ACK);
1472 IWL_CMD(CONTROL_CFEND);
1473 IWL_CMD(CONTROL_CFENDACK);
1474 default:
1475 return "UNKNOWN";
1476
1477 }
1478}
1479
7163b8a4 1480void iwl_clear_traffic_stats(struct iwl_priv *priv)
22fdf3c9
WYG		 1481{
1482 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
22fdf3c9
WYG		 1483 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
1484}
1485
1486/*
1487 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
1488 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
1489 * Use debugFs to display the rx/rx_statistics
1490 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
1491 * information will be recorded, but DATA pkt still will be recorded
1492 * for the reason of iwl_led.c need to control the led blinking based on
1493 * number of tx and rx data.
1494 *
1495 */
1496void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
1497{
1498 struct traffic_stats *stats;
1499
1500 if (is_tx)
1501 stats = &priv->tx_stats;
1502 else
1503 stats = &priv->rx_stats;
1504
1505 if (ieee80211_is_mgmt(fc)) {
1506 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
1507 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
1508 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
1509 break;
1510 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
1511 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
1512 break;
1513 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
1514 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
1515 break;
1516 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
1517 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
1518 break;
1519 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
1520 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
1521 break;
1522 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
1523 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
1524 break;
1525 case cpu_to_le16(IEEE80211_STYPE_BEACON):
1526 stats->mgmt[MANAGEMENT_BEACON]++;
1527 break;
1528 case cpu_to_le16(IEEE80211_STYPE_ATIM):
1529 stats->mgmt[MANAGEMENT_ATIM]++;
1530 break;
1531 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
1532 stats->mgmt[MANAGEMENT_DISASSOC]++;
1533 break;
1534 case cpu_to_le16(IEEE80211_STYPE_AUTH):
1535 stats->mgmt[MANAGEMENT_AUTH]++;
1536 break;
1537 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
1538 stats->mgmt[MANAGEMENT_DEAUTH]++;
1539 break;
1540 case cpu_to_le16(IEEE80211_STYPE_ACTION):
1541 stats->mgmt[MANAGEMENT_ACTION]++;
1542 break;
1543 }
1544 } else if (ieee80211_is_ctl(fc)) {
1545 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
1546 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
1547 stats->ctrl[CONTROL_BACK_REQ]++;
1548 break;
1549 case cpu_to_le16(IEEE80211_STYPE_BACK):
1550 stats->ctrl[CONTROL_BACK]++;
1551 break;
1552 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
1553 stats->ctrl[CONTROL_PSPOLL]++;
1554 break;
1555 case cpu_to_le16(IEEE80211_STYPE_RTS):
1556 stats->ctrl[CONTROL_RTS]++;
1557 break;
1558 case cpu_to_le16(IEEE80211_STYPE_CTS):
1559 stats->ctrl[CONTROL_CTS]++;
1560 break;
1561 case cpu_to_le16(IEEE80211_STYPE_ACK):
1562 stats->ctrl[CONTROL_ACK]++;
1563 break;
1564 case cpu_to_le16(IEEE80211_STYPE_CFEND):
1565 stats->ctrl[CONTROL_CFEND]++;
1566 break;
1567 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
1568 stats->ctrl[CONTROL_CFENDACK]++;
1569 break;
1570 }
1571 } else {
1572 /* data */
1573 stats->data_cnt++;
1574 stats->data_bytes += len;
1575 }
1576}
20594eb0
WYG		 1577#endif
1578
a93e7973 1579static void iwl_force_rf_reset(struct iwl_priv *priv)
afbdd69a 1580{
63013ae3 1581 if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status))
afbdd69a
WYG		 1582 return;
1583
246ed355 1584 if (!iwl_is_any_associated(priv)) {
afbdd69a
WYG		 1585 IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n");
1586 return;
1587 }
1588 /*
1589 * There is no easy and better way to force reset the radio,
1590 * the only known method is switching channel which will force to
1591 * reset and tune the radio.
1592 * Use internal short scan (single channel) operation to should
1593 * achieve this objective.
1594 * Driver should reset the radio when number of consecutive missed
1595 * beacon, or any other uCode error condition detected.
1596 */
1597 IWL_DEBUG_INFO(priv, "perform radio reset.\n");
1598 iwl_internal_short_hw_scan(priv);
afbdd69a 1599}
a93e7973 1600
a93e7973 1601
c04f9f22 1602int iwl_force_reset(struct iwl_priv *priv, int mode, bool external)
a93e7973 1603{
8a472da4
WYG		 1604 struct iwl_force_reset *force_reset;
1605
63013ae3 1606 if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status))
a93e7973
WYG		 1607 return -EINVAL;
1608
8a472da4
WYG		 1609 if (mode >= IWL_MAX_FORCE_RESET) {
1610 IWL_DEBUG_INFO(priv, "invalid reset request.\n");
1611 return -EINVAL;
1612 }
1613 force_reset = &priv->force_reset[mode];
1614 force_reset->reset_request_count++;
c04f9f22
WYG		 1615 if (!external) {
1616 if (force_reset->last_force_reset_jiffies &&
1617 time_after(force_reset->last_force_reset_jiffies +
1618 force_reset->reset_duration, jiffies)) {
1619 IWL_DEBUG_INFO(priv, "force reset rejected\n");
1620 force_reset->reset_reject_count++;
1621 return -EAGAIN;
1622 }
a93e7973 1623 }
8a472da4
WYG		 1624 force_reset->reset_success_count++;
1625 force_reset->last_force_reset_jiffies = jiffies;
a93e7973 1626 IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode);
a93e7973
WYG		 1627 switch (mode) {
1628 case IWL_RF_RESET:
1629 iwl_force_rf_reset(priv);
1630 break;
1631 case IWL_FW_RESET:
c04f9f22
WYG		 1632 /*
1633 * if the request is from external(ex: debugfs),
1634 * then always perform the request in regardless the module
1635 * parameter setting
1636 * if the request is from internal (uCode error or driver
1637 * detect failure), then fw_restart module parameter
1638 * need to be check before performing firmware reload
1639 */
9d143e9a 1640 if (!external && !iwlagn_mod_params.restart_fw) {
c04f9f22
WYG		 1641 IWL_DEBUG_INFO(priv, "Cancel firmware reload based on "
1642 "module parameter setting\n");
1643 break;
1644 }
a93e7973 1645 IWL_ERR(priv, "On demand firmware reload\n");
e649437f 1646 iwlagn_fw_error(priv, true);
a93e7973 1647 break;
a93e7973 1648 }
a93e7973
WYG		 1649 return 0;
1650}
b74e31a9 1651
ade4c649
WYG		 1652int iwlagn_mac_change_interface(struct ieee80211_hw *hw,
1653 struct ieee80211_vif *vif,
1654 enum nl80211_iftype newtype, bool newp2p)
d4daaea6
JB		 1655{
1656 struct iwl_priv *priv = hw->priv;
1657 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
ebf8dc80 1658 struct iwl_rxon_context *bss_ctx = &priv->contexts[IWL_RXON_CTX_BSS];
d4daaea6 1659 struct iwl_rxon_context *tmp;
5306c080 1660 enum nl80211_iftype newviftype = newtype;
d4daaea6
JB		 1661 u32 interface_modes;
1662 int err;
1663
770c72c4
WYG		 1664 IWL_DEBUG_MAC80211(priv, "enter\n");
1665
d4daaea6
JB		 1666 newtype = ieee80211_iftype_p2p(newtype, newp2p);
1667
6ac2f839 1668 mutex_lock(&priv->shrd->mutex);
d4daaea6 1669
845a9c0d 1670 if (!ctx->vif || !iwl_is_ready_rf(priv->shrd)) {
a2b76b3b
JB		 1671 /*
1672 * Huh? But wait ... this can maybe happen when
1673 * we're in the middle of a firmware restart!
1674 */
1675 err = -EBUSY;
1676 goto out;
1677 }
1678
d4daaea6
JB		 1679 interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes;
1680
1681 if (!(interface_modes & BIT(newtype))) {
1682 err = -EBUSY;
1683 goto out;
1684 }
1685
ebf8dc80
JB		 1686 /*
1687 * Refuse a change that should be done by moving from the PAN
1688 * context to the BSS context instead, if the BSS context is
1689 * available and can support the new interface type.
1690 */
1691 if (ctx->ctxid == IWL_RXON_CTX_PAN && !bss_ctx->vif &&
1692 (bss_ctx->interface_modes & BIT(newtype) ||
1693 bss_ctx->exclusive_interface_modes & BIT(newtype))) {
1694 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
1695 err = -EBUSY;
1696 goto out;
1697 }
1698
d4daaea6
JB		 1699 if (ctx->exclusive_interface_modes & BIT(newtype)) {
1700 for_each_context(priv, tmp) {
1701 if (ctx == tmp)
1702 continue;
1703
1704 if (!tmp->vif)
1705 continue;
1706
1707 /*
1708 * The current mode switch would be exclusive, but
1709 * another context is active ... refuse the switch.
1710 */
1711 err = -EBUSY;
1712 goto out;
1713 }
1714 }
1715
1716 /* success */
1717 iwl_teardown_interface(priv, vif, true);
5306c080 1718 vif->type = newviftype;
a2b76b3b 1719 vif->p2p = newp2p;
d4daaea6
JB		 1720 err = iwl_setup_interface(priv, ctx);
1721 WARN_ON(err);
1722 /*
1723 * We've switched internally, but submitting to the
1724 * device may have failed for some reason. Mask this
1725 * error, because otherwise mac80211 will not switch
1726 * (and set the interface type back) and we'll be
1727 * out of sync with it.
1728 */
1729 err = 0;
1730
1731 out:
6ac2f839 1732 mutex_unlock(&priv->shrd->mutex);
770c72c4
WYG		 1733 IWL_DEBUG_MAC80211(priv, "leave\n");
1734
d4daaea6
JB		 1735 return err;
1736}
d4daaea6 1737
317d09f7
WYG		 1738int iwl_cmd_echo_test(struct iwl_priv *priv)
1739{
7e4005cc 1740 int ret;
317d09f7
WYG		 1741 struct iwl_host_cmd cmd = {
1742 .id = REPLY_ECHO,
1743 .flags = CMD_SYNC,
1744 };
1745
7e4005cc
WYG		 1746 ret = iwl_trans_send_cmd(trans(priv), &cmd);
1747 if (ret)
1748 IWL_ERR(priv, "echo testing fail: 0X%x\n", ret);
1749 else
1750 IWL_DEBUG_INFO(priv, "echo testing pass\n");
1751 return ret;
317d09f7
WYG		 1752}
1753
f22be624 1754static inline int iwl_check_stuck_queue(struct iwl_priv *priv, int txq)
b74e31a9 1755{
f22be624 1756 if (iwl_trans_check_stuck_queue(trans(priv), txq)) {
317d09f7
WYG		 1757 int ret;
1758 if (txq == priv->shrd->cmd_queue) {
1759 /*
1760 * validate command queue still working
1761 * by sending "ECHO" command
1762 */
1763 if (!iwl_cmd_echo_test(priv))
1764 return 0;
1765 else
1766 IWL_DEBUG_HC(priv, "echo testing fail\n");
1767 }
1768 ret = iwl_force_reset(priv, IWL_FW_RESET, false);
22de94de 1769 return (ret == -EAGAIN) ? 0 : 1;
b74e31a9
WYG		 1770 }
1771 return 0;
1772}
1773
22de94de
SG		 1774/*
1775 * Making watchdog tick be a quarter of timeout assure we will
1776 * discover the queue hung between timeout and 1.25*timeout
1777 */
1778#define IWL_WD_TICK(timeout) ((timeout) / 4)
1779
1780/*
1781 * Watchdog timer callback, we check each tx queue for stuck, if if hung
1782 * we reset the firmware. If everything is fine just rearm the timer.
1783 */
1784void iwl_bg_watchdog(unsigned long data)
b74e31a9
WYG		 1785{
1786 struct iwl_priv *priv = (struct iwl_priv *)data;
1787 int cnt;
22de94de 1788 unsigned long timeout;
b74e31a9 1789
63013ae3 1790 if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status))
b74e31a9
WYG		 1791 return;
1792
46e7741e
WYG		 1793 if (iwl_is_rfkill(priv->shrd))
1794 return;
1795
22de94de
SG		 1796 timeout = priv->cfg->base_params->wd_timeout;
1797 if (timeout == 0)
1798 return;
1799
b74e31a9 1800 /* monitor and check for stuck cmd queue */
cefeaa5f 1801 if (iwl_check_stuck_queue(priv, priv->shrd->cmd_queue))
b74e31a9
WYG		 1802 return;
1803
1804 /* monitor and check for other stuck queues */
246ed355 1805 if (iwl_is_any_associated(priv)) {
d6189124 1806 for (cnt = 0; cnt < hw_params(priv).max_txq_num; cnt++) {
b74e31a9 1807 /* skip as we already checked the command queue */
cefeaa5f 1808 if (cnt == priv->shrd->cmd_queue)
b74e31a9
WYG		 1809 continue;
1810 if (iwl_check_stuck_queue(priv, cnt))
1811 return;
1812 }
1813 }
22de94de
SG		 1814
1815 mod_timer(&priv->watchdog, jiffies +
1816 msecs_to_jiffies(IWL_WD_TICK(timeout)));
b74e31a9 1817}
22de94de
SG		 1818
1819void iwl_setup_watchdog(struct iwl_priv *priv)
1820{
1821 unsigned int timeout = priv->cfg->base_params->wd_timeout;
afbdd69a 1822
300d0834 1823 if (timeout && !iwlagn_mod_params.wd_disable)
22de94de
SG		 1824 mod_timer(&priv->watchdog,
1825 jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout)));
1826 else
1827 del_timer(&priv->watchdog);
1828}
a0ee74cf 1829
8c222544
EG		 1830/**
1831 * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time
1832 * @priv -- pointer to iwl_priv data structure
1833 * @tsf_bits -- number of bits need to shift for masking)
1834 */
1835static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv,
1836 u16 tsf_bits)
1837{
1838 return (1 << tsf_bits) - 1;
1839}
1840
1841/**
1842 * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time
1843 * @priv -- pointer to iwl_priv data structure
1844 * @tsf_bits -- number of bits need to shift for masking)
1845 */
1846static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv,
1847 u16 tsf_bits)
1848{
1849 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
1850}
1851
a0ee74cf
WYG		 1852/*
1853 * extended beacon time format
1854 * time in usec will be changed into a 32-bit value in extended:internal format
1855 * the extended part is the beacon counts
1856 * the internal part is the time in usec within one beacon interval
1857 */
1858u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval)
1859{
1860 u32 quot;
1861 u32 rem;
1862 u32 interval = beacon_interval * TIME_UNIT;
1863
1864 if (!interval || !usec)
1865 return 0;
1866
1867 quot = (usec / interval) &
403ba56a
DF		 1868 (iwl_beacon_time_mask_high(priv, IWLAGN_EXT_BEACON_TIME_POS) >>
1869 IWLAGN_EXT_BEACON_TIME_POS);
a0ee74cf 1870 rem = (usec % interval) & iwl_beacon_time_mask_low(priv,
403ba56a 1871 IWLAGN_EXT_BEACON_TIME_POS);
a0ee74cf 1872
403ba56a 1873 return (quot << IWLAGN_EXT_BEACON_TIME_POS) + rem;
a0ee74cf 1874}
a0ee74cf
WYG		 1875
1876/* base is usually what we get from ucode with each received frame,
1877 * the same as HW timer counter counting down
1878 */
1879__le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
1880 u32 addon, u32 beacon_interval)
1881{
1882 u32 base_low = base & iwl_beacon_time_mask_low(priv,
403ba56a 1883 IWLAGN_EXT_BEACON_TIME_POS);
a0ee74cf 1884 u32 addon_low = addon & iwl_beacon_time_mask_low(priv,
403ba56a 1885 IWLAGN_EXT_BEACON_TIME_POS);
a0ee74cf
WYG		 1886 u32 interval = beacon_interval * TIME_UNIT;
1887 u32 res = (base & iwl_beacon_time_mask_high(priv,
403ba56a 1888 IWLAGN_EXT_BEACON_TIME_POS)) +
a0ee74cf 1889 (addon & iwl_beacon_time_mask_high(priv,
403ba56a 1890 IWLAGN_EXT_BEACON_TIME_POS));
a0ee74cf
WYG		 1891
1892 if (base_low > addon_low)
1893 res += base_low - addon_low;
1894 else if (base_low < addon_low) {
1895 res += interval + base_low - addon_low;
403ba56a 1896 res += (1 << IWLAGN_EXT_BEACON_TIME_POS);
a0ee74cf 1897 } else
403ba56a 1898 res += (1 << IWLAGN_EXT_BEACON_TIME_POS);
a0ee74cf
WYG		 1899
1900 return cpu_to_le32(res);
1901}
a0ee74cf 1902
464021ff
EG		 1903void iwl_start_tx_ba_trans_ready(struct iwl_priv *priv,
1904 enum iwl_rxon_context_id ctx,
288712a6
EG		 1905 u8 sta_id, u8 tid)
1906{
427977ab 1907 struct ieee80211_vif *vif;
288712a6
EG		 1908 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1909
464021ff
EG		 1910 if (ctx == NUM_IWL_RXON_CTX)
1911 ctx = priv->stations[sta_id].ctxid;
1912 vif = priv->contexts[ctx].vif;
1913
288712a6
EG		 1914 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
1915}
464021ff
EG		 1916
1917void iwl_stop_tx_ba_trans_ready(struct iwl_priv *priv,
1918 enum iwl_rxon_context_id ctx,
1919 u8 sta_id, u8 tid)
1920{
1921 struct ieee80211_vif *vif;
1922 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1923
1924 if (ctx == NUM_IWL_RXON_CTX)
1925 ctx = priv->stations[sta_id].ctxid;
1926 vif = priv->contexts[ctx].vif;
1927
1928 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
1929}
3e10caeb
EG		 1930
1931void iwl_set_hw_rfkill_state(struct iwl_priv *priv, bool state)
1932{
1933 wiphy_rfkill_set_hw_state(priv->hw->wiphy, state);
1934}
7a10e3e4
EG		 1935
1936void iwl_nic_config(struct iwl_priv *priv)
1937{
1938 priv->cfg->lib->nic_config(priv);
1939
1940}
909e9b23
EG		 1941
1942void iwl_free_skb(struct iwl_priv *priv, struct sk_buff *skb)
1943{
1944 struct ieee80211_tx_info *info;
1945
1946 info = IEEE80211_SKB_CB(skb);
1947 kmem_cache_free(priv->tx_cmd_pool, (info->driver_data[1]));
1948 dev_kfree_skb_any(skb);
1949}
859cfb0a
EG		 1950
1951void iwl_stop_sw_queue(struct iwl_priv *priv, u8 ac)
1952{
1953 ieee80211_stop_queue(priv->hw, ac);
1954}
1955
1956void iwl_wake_sw_queue(struct iwl_priv *priv, u8 ac)
1957{
1958 ieee80211_wake_queue(priv->hw, ac);
1959}
Linux kernel - Deliverables
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