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iwlwifi: add SM PS support for 6x50 series
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
a562a9dd
RC		 62u32 iwl_debug_level;
63EXPORT_SYMBOL(iwl_debug_level);
64
ef850d7c
MA		 65static irqreturn_t iwl_isr(int irq, void *data);
66
c7de35cd
RR		 67/*
68 * Parameter order:
69 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
1826dcc0 75const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 76 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
88 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
89 /* FIXME:RS: ^^ should be INV (legacy) */
90};
1826dcc0 91EXPORT_SYMBOL(iwl_rates);
c7de35cd 92
e7d326ac
TW		 93/**
94 * translate ucode response to mac80211 tx status control values
95 */
96void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 97 struct ieee80211_tx_info *info)
e7d326ac 98{
e6a9854b 99 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 100
e6a9854b 101 info->antenna_sel_tx =
e7d326ac
TW		 102 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
103 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 104 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 105 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 106 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 107 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 108 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 109 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 110 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 111 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 112 r->flags |= IEEE80211_TX_RC_SHORT_GI;
31513be8 113 r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
e7d326ac
TW		 114}
115EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
116
117int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
118{
119 int idx = 0;
120
121 /* HT rate format */
122 if (rate_n_flags & RATE_MCS_HT_MSK) {
123 idx = (rate_n_flags & 0xff);
124
60d32215
DH		 125 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
126 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
127 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 128 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
129
130 idx += IWL_FIRST_OFDM_RATE;
131 /* skip 9M not supported in ht*/
132 if (idx >= IWL_RATE_9M_INDEX)
133 idx += 1;
134 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
135 return idx;
136
137 /* legacy rate format, search for match in table */
138 } else {
139 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
140 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
141 return idx;
142 }
143
144 return -1;
145}
146EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
147
31513be8
DH		 148int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
149{
150 int idx = 0;
151 int band_offset = 0;
152
153 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
154 if (rate_n_flags & RATE_MCS_HT_MSK) {
155 idx = (rate_n_flags & 0xff);
156 return idx;
157 /* Legacy rate format, search for match in table */
158 } else {
159 if (band == IEEE80211_BAND_5GHZ)
160 band_offset = IWL_FIRST_OFDM_RATE;
161 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
162 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
163 return idx - band_offset;
164 }
165
166 return -1;
167}
168
76eff18b
TW		 169u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
170{
171 int i;
172 u8 ind = ant;
173 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
174 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
175 if (priv->hw_params.valid_tx_ant & BIT(ind))
176 return ind;
177 }
178 return ant;
179}
57bd1bea
TW		 180
181const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
182EXPORT_SYMBOL(iwl_bcast_addr);
183
184
1d0a082d
AK		 185/* This function both allocates and initializes hw and priv. */
186struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
187 struct ieee80211_ops *hw_ops)
188{
189 struct iwl_priv *priv;
190
191 /* mac80211 allocates memory for this device instance, including
192 * space for this driver's private structure */
193 struct ieee80211_hw *hw =
194 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
195 if (hw == NULL) {
a3139c59
SO		 196 printk(KERN_ERR "%s: Can not allocate network device\n",
197 cfg->name);
1d0a082d
AK		 198 goto out;
199 }
200
201 priv = hw->priv;
202 priv->hw = hw;
203
204out:
205 return hw;
206}
207EXPORT_SYMBOL(iwl_alloc_all);
208
b661c819
TW		 209void iwl_hw_detect(struct iwl_priv *priv)
210{
211 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
212 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
213 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
214}
215EXPORT_SYMBOL(iwl_hw_detect);
216
1053d35f
RR		 217int iwl_hw_nic_init(struct iwl_priv *priv)
218{
219 unsigned long flags;
220 struct iwl_rx_queue *rxq = &priv->rxq;
221 int ret;
222
223 /* nic_init */
1053d35f 224 spin_lock_irqsave(&priv->lock, flags);
1b73af82 225 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 226 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
227 spin_unlock_irqrestore(&priv->lock, flags);
228
229 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
230
231 priv->cfg->ops->lib->apm_ops.config(priv);
232
233 /* Allocate the RX queue, or reset if it is already allocated */
234 if (!rxq->bd) {
235 ret = iwl_rx_queue_alloc(priv);
236 if (ret) {
15b1687c 237 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 238 return -ENOMEM;
239 }
240 } else
241 iwl_rx_queue_reset(priv, rxq);
242
243 iwl_rx_replenish(priv);
244
245 iwl_rx_init(priv, rxq);
246
247 spin_lock_irqsave(&priv->lock, flags);
248
249 rxq->need_update = 1;
250 iwl_rx_queue_update_write_ptr(priv, rxq);
251
252 spin_unlock_irqrestore(&priv->lock, flags);
253
254 /* Allocate and init all Tx and Command queues */
255 ret = iwl_txq_ctx_reset(priv);
256 if (ret)
257 return ret;
258
259 set_bit(STATUS_INIT, &priv->status);
260
261 return 0;
262}
263EXPORT_SYMBOL(iwl_hw_nic_init);
264
14d2aac5
AK		 265/*
266 * QoS support
267*/
268void iwl_activate_qos(struct iwl_priv *priv, u8 force)
269{
270 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
271 return;
272
273 priv->qos_data.def_qos_parm.qos_flags = 0;
274
275 if (priv->qos_data.qos_cap.q_AP.queue_request &&
276 !priv->qos_data.qos_cap.q_AP.txop_request)
277 priv->qos_data.def_qos_parm.qos_flags |=
278 QOS_PARAM_FLG_TXOP_TYPE_MSK;
279 if (priv->qos_data.qos_active)
280 priv->qos_data.def_qos_parm.qos_flags |=
281 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
282
283 if (priv->current_ht_config.is_ht)
284 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
285
286 if (force || iwl_is_associated(priv)) {
287 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
288 priv->qos_data.qos_active,
289 priv->qos_data.def_qos_parm.qos_flags);
290
291 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
292 sizeof(struct iwl_qosparam_cmd),
293 &priv->qos_data.def_qos_parm, NULL);
294 }
295}
296EXPORT_SYMBOL(iwl_activate_qos);
297
f2c95b04
WYG		 298/*
299 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
300 * (802.11b) (802.11a/g)
301 * AC_BK 15 1023 7 0 0
302 * AC_BE 15 1023 3 0 0
303 * AC_VI 7 15 2 6.016ms 3.008ms
304 * AC_VO 3 7 2 3.264ms 1.504ms
305 */
c7de35cd 306void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 307{
308 u16 cw_min = 15;
309 u16 cw_max = 1023;
310 u8 aifs = 2;
30dab79e 311 bool is_legacy = false;
bf85ea4f
AK		 312 unsigned long flags;
313 int i;
314
315 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 316 /* QoS always active in AP and ADHOC mode
317 * In STA mode wait for association
318 */
319 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
320 priv->iw_mode == NL80211_IFTYPE_AP)
321 priv->qos_data.qos_active = 1;
322 else
323 priv->qos_data.qos_active = 0;
bf85ea4f 324
30dab79e
WT		 325 /* check for legacy mode */
326 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
327 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
328 (priv->iw_mode == NL80211_IFTYPE_STATION &&
329 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 330 cw_min = 31;
331 is_legacy = 1;
332 }
333
334 if (priv->qos_data.qos_active)
335 aifs = 3;
336
f2c95b04 337 /* AC_BE */
bf85ea4f
AK		 338 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
339 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
340 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
341 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
342 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
343
344 if (priv->qos_data.qos_active) {
f2c95b04 345 /* AC_BK */
bf85ea4f
AK		 346 i = 1;
347 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
348 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
349 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
350 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
351 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
352
f2c95b04 353 /* AC_VI */
bf85ea4f
AK		 354 i = 2;
355 priv->qos_data.def_qos_parm.ac[i].cw_min =
356 cpu_to_le16((cw_min + 1) / 2 - 1);
357 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 358 cpu_to_le16(cw_min);
bf85ea4f
AK		 359 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
360 if (is_legacy)
361 priv->qos_data.def_qos_parm.ac[i].edca_txop =
362 cpu_to_le16(6016);
363 else
364 priv->qos_data.def_qos_parm.ac[i].edca_txop =
365 cpu_to_le16(3008);
366 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
367
f2c95b04 368 /* AC_VO */
bf85ea4f
AK		 369 i = 3;
370 priv->qos_data.def_qos_parm.ac[i].cw_min =
371 cpu_to_le16((cw_min + 1) / 4 - 1);
372 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 373 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 374 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
375 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
376 if (is_legacy)
377 priv->qos_data.def_qos_parm.ac[i].edca_txop =
378 cpu_to_le16(3264);
379 else
380 priv->qos_data.def_qos_parm.ac[i].edca_txop =
381 cpu_to_le16(1504);
382 } else {
383 for (i = 1; i < 4; i++) {
384 priv->qos_data.def_qos_parm.ac[i].cw_min =
385 cpu_to_le16(cw_min);
386 priv->qos_data.def_qos_parm.ac[i].cw_max =
387 cpu_to_le16(cw_max);
388 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
389 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
390 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
391 }
392 }
e1623446 393 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 394
395 spin_unlock_irqrestore(&priv->lock, flags);
396}
c7de35cd
RR		 397EXPORT_SYMBOL(iwl_reset_qos);
398
d9fe60de
JB		 399#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
400#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 401static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 402 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 403 enum ieee80211_band band)
404{
39130df3
RR		 405 u16 max_bit_rate = 0;
406 u8 rx_chains_num = priv->hw_params.rx_chains_num;
407 u8 tx_chains_num = priv->hw_params.tx_chains_num;
408
c7de35cd 409 ht_info->cap = 0;
d9fe60de 410 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 411
d9fe60de 412 ht_info->ht_supported = true;
c7de35cd 413
b261793d
DH		 414 if (priv->cfg->ht_greenfield_support)
415 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de 416 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3f3e0376
WYG		 417 if (priv->cfg->support_sm_ps)
418 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
419 (WLAN_HT_CAP_SM_PS_DYNAMIC << 2));
420 else
421 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
422 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 423
424 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 425 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 426 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
427 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
428 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 429 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 430 }
c7de35cd
RR		 431
432 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 433 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 434
435 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
436 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
437
d9fe60de 438 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 439 if (rx_chains_num >= 2)
d9fe60de 440 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 441 if (rx_chains_num >= 3)
d9fe60de 442 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 443
444 /* Highest supported Rx data rate */
445 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 446 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
447 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 448
449 /* Tx MCS capabilities */
d9fe60de 450 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 451 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 452 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
453 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
454 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 455 }
c7de35cd 456}
c7de35cd 457
c7de35cd
RR		 458/**
459 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
460 */
534166de 461int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 462{
463 struct iwl_channel_info *ch;
464 struct ieee80211_supported_band *sband;
465 struct ieee80211_channel *channels;
466 struct ieee80211_channel *geo_ch;
467 struct ieee80211_rate *rates;
468 int i = 0;
469
470 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
471 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 472 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 473 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
474 return 0;
475 }
476
477 channels = kzalloc(sizeof(struct ieee80211_channel) *
478 priv->channel_count, GFP_KERNEL);
479 if (!channels)
480 return -ENOMEM;
481
5027309b 482 rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
c7de35cd
RR		 483 GFP_KERNEL);
484 if (!rates) {
485 kfree(channels);
486 return -ENOMEM;
487 }
488
489 /* 5.2GHz channels start after the 2.4GHz channels */
490 sband = &priv->bands[IEEE80211_BAND_5GHZ];
491 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
492 /* just OFDM */
493 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 494 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 495
49779293 496 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 497 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 498 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 499
500 sband = &priv->bands[IEEE80211_BAND_2GHZ];
501 sband->channels = channels;
502 /* OFDM & CCK */
503 sband->bitrates = rates;
5027309b 504 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 505
49779293 506 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 507 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 508 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 509
510 priv->ieee_channels = channels;
511 priv->ieee_rates = rates;
512
c7de35cd
RR		 513 for (i = 0; i < priv->channel_count; i++) {
514 ch = &priv->channel_info[i];
515
516 /* FIXME: might be removed if scan is OK */
517 if (!is_channel_valid(ch))
518 continue;
519
520 if (is_channel_a_band(ch))
521 sband = &priv->bands[IEEE80211_BAND_5GHZ];
522 else
523 sband = &priv->bands[IEEE80211_BAND_2GHZ];
524
525 geo_ch = &sband->channels[sband->n_channels++];
526
527 geo_ch->center_freq =
528 ieee80211_channel_to_frequency(ch->channel);
529 geo_ch->max_power = ch->max_power_avg;
530 geo_ch->max_antenna_gain = 0xff;
531 geo_ch->hw_value = ch->channel;
532
533 if (is_channel_valid(ch)) {
534 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
535 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
536
537 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
538 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
539
540 if (ch->flags & EEPROM_CHANNEL_RADAR)
541 geo_ch->flags |= IEEE80211_CHAN_RADAR;
542
7aafef1c 543 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 544
dc1b0973
WYG		 545 if (ch->max_power_avg > priv->tx_power_device_lmt)
546 priv->tx_power_device_lmt = ch->max_power_avg;
c7de35cd
RR		 547 } else {
548 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
549 }
550
e1623446 551 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 552 ch->channel, geo_ch->center_freq,
553 is_channel_a_band(ch) ? "5.2" : "2.4",
554 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
555 "restricted" : "valid",
556 geo_ch->flags);
557 }
558
559 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
560 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 561 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
562 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 563 priv->pci_dev->device,
564 priv->pci_dev->subsystem_device);
c7de35cd
RR		 565 priv->cfg->sku &= ~IWL_SKU_A;
566 }
567
978785a3 568 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 569 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
570 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 571
572 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
573
574 return 0;
575}
534166de 576EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 577
578/*
579 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
580 */
534166de 581void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 582{
583 kfree(priv->ieee_channels);
584 kfree(priv->ieee_rates);
585 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
586}
534166de 587EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 588
37dc70fe
AK		 589/*
590 * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
591 * function.
592 */
593void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
594 __le32 *tx_flags)
595{
596 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
597 *tx_flags |= TX_CMD_FLG_RTS_MSK;
598 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
599 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
600 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
601 *tx_flags |= TX_CMD_FLG_CTS_MSK;
602 }
603}
604EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
605
28a6b07a 606static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 607{
608 return !priv->current_ht_config.is_ht ||
02bb1bea 609 priv->current_ht_config.single_chain_sufficient;
c7de35cd 610}
963f5517 611
47c5196e
TW		 612static u8 iwl_is_channel_extension(struct iwl_priv *priv,
613 enum ieee80211_band band,
614 u16 channel, u8 extension_chan_offset)
615{
616 const struct iwl_channel_info *ch_info;
617
618 ch_info = iwl_get_channel_info(priv, band, channel);
619 if (!is_channel_valid(ch_info))
620 return 0;
621
d9fe60de 622 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 623 return !(ch_info->ht40_extension_channel &
689da1b3 624 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 625 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 626 return !(ch_info->ht40_extension_channel &
689da1b3 627 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 628
629 return 0;
630}
631
7aafef1c 632u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 633 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e 634{
fad95bf5 635 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
47c5196e 636
fad95bf5 637 if (!ht_conf->is_ht || !ht_conf->is_40mhz)
47c5196e
TW		 638 return 0;
639
a2b0f02e
WYG		 640 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
641 * the bit will not set if it is pure 40MHz case
642 */
47c5196e 643 if (sta_ht_inf) {
a2b0f02e 644 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 645 return 0;
646 }
1e4247d4
WYG		 647#ifdef CONFIG_IWLWIFI_DEBUG
648 if (priv->disable_ht40)
649 return 0;
650#endif
611d3eb7
WYG		 651 return iwl_is_channel_extension(priv, priv->band,
652 le16_to_cpu(priv->staging_rxon.channel),
fad95bf5 653 ht_conf->extension_chan_offset);
47c5196e 654}
7aafef1c 655EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 656
2c2f3b33
TW		 657static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
658{
659 u16 new_val = 0;
660 u16 beacon_factor = 0;
661
662 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
663 new_val = beacon_val / beacon_factor;
664
665 if (!new_val)
666 new_val = max_beacon_val;
667
668 return new_val;
669}
670
671void iwl_setup_rxon_timing(struct iwl_priv *priv)
672{
673 u64 tsf;
674 s32 interval_tm, rem;
675 unsigned long flags;
676 struct ieee80211_conf *conf = NULL;
677 u16 beacon_int;
678
679 conf = ieee80211_get_hw_conf(priv->hw);
680
681 spin_lock_irqsave(&priv->lock, flags);
682 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
683 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
684
685 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
686 beacon_int = priv->beacon_int;
687 priv->rxon_timing.atim_window = 0;
688 } else {
689 beacon_int = priv->vif->bss_conf.beacon_int;
690
691 /* TODO: we need to get atim_window from upper stack
692 * for now we set to 0 */
693 priv->rxon_timing.atim_window = 0;
694 }
695
696 beacon_int = iwl_adjust_beacon_interval(beacon_int,
697 priv->hw_params.max_beacon_itrvl * 1024);
698 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
699
700 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
701 interval_tm = beacon_int * 1024;
702 rem = do_div(tsf, interval_tm);
703 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
704
705 spin_unlock_irqrestore(&priv->lock, flags);
706 IWL_DEBUG_ASSOC(priv,
707 "beacon interval %d beacon timer %d beacon tim %d\n",
708 le16_to_cpu(priv->rxon_timing.beacon_interval),
709 le32_to_cpu(priv->rxon_timing.beacon_init_val),
710 le16_to_cpu(priv->rxon_timing.atim_window));
711}
712EXPORT_SYMBOL(iwl_setup_rxon_timing);
713
8ccde88a
SO		 714void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
715{
716 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
717
718 if (hw_decrypt)
719 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
720 else
721 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
722
723}
724EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
725
726/**
727 * iwl_check_rxon_cmd - validate RXON structure is valid
728 *
729 * NOTE: This is really only useful during development and can eventually
730 * be #ifdef'd out once the driver is stable and folks aren't actively
731 * making changes
732 */
733int iwl_check_rxon_cmd(struct iwl_priv *priv)
734{
735 int error = 0;
736 int counter = 1;
737 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
738
739 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
740 error |= le32_to_cpu(rxon->flags &
741 (RXON_FLG_TGJ_NARROW_BAND_MSK |
742 RXON_FLG_RADAR_DETECT_MSK));
743 if (error)
744 IWL_WARN(priv, "check 24G fields %d | %d\n",
745 counter++, error);
746 } else {
747 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
748 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
749 if (error)
750 IWL_WARN(priv, "check 52 fields %d | %d\n",
751 counter++, error);
752 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
753 if (error)
754 IWL_WARN(priv, "check 52 CCK %d | %d\n",
755 counter++, error);
756 }
757 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
758 if (error)
759 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
760
761 /* make sure basic rates 6Mbps and 1Mbps are supported */
762 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
763 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
764 if (error)
765 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
766
767 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
768 if (error)
769 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
770
771 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
772 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
773 if (error)
774 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
775 counter++, error);
776
777 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
778 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
779 if (error)
780 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
781 counter++, error);
782
783 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
784 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
785 if (error)
786 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
787 counter++, error);
788
789 if (error)
790 IWL_WARN(priv, "Tuning to channel %d\n",
791 le16_to_cpu(rxon->channel));
792
793 if (error) {
794 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
795 return -1;
796 }
797 return 0;
798}
799EXPORT_SYMBOL(iwl_check_rxon_cmd);
800
801/**
802 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
803 * @priv: staging_rxon is compared to active_rxon
804 *
805 * If the RXON structure is changing enough to require a new tune,
806 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
807 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
808 */
809int iwl_full_rxon_required(struct iwl_priv *priv)
810{
811
812 /* These items are only settable from the full RXON command */
813 if (!(iwl_is_associated(priv)) ||
814 compare_ether_addr(priv->staging_rxon.bssid_addr,
815 priv->active_rxon.bssid_addr) ||
816 compare_ether_addr(priv->staging_rxon.node_addr,
817 priv->active_rxon.node_addr) ||
818 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
819 priv->active_rxon.wlap_bssid_addr) ||
820 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
821 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
822 (priv->staging_rxon.air_propagation !=
823 priv->active_rxon.air_propagation) ||
824 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
825 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
826 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
827 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 828 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
829 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 830 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
831 return 1;
832
833 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
834 * be updated with the RXON_ASSOC command -- however only some
835 * flag transitions are allowed using RXON_ASSOC */
836
837 /* Check if we are not switching bands */
838 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
839 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
840 return 1;
841
842 /* Check if we are switching association toggle */
843 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
844 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
845 return 1;
846
847 return 0;
848}
849EXPORT_SYMBOL(iwl_full_rxon_required);
850
851u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
852{
853 int i;
854 int rate_mask;
855
856 /* Set rate mask*/
857 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
858 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
859 else
860 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
861
862 /* Find lowest valid rate */
863 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
864 i = iwl_rates[i].next_ieee) {
865 if (rate_mask & (1 << i))
866 return iwl_rates[i].plcp;
867 }
868
869 /* No valid rate was found. Assign the lowest one */
870 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
871 return IWL_RATE_1M_PLCP;
872 else
873 return IWL_RATE_6M_PLCP;
874}
875EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
876
fad95bf5 877void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
47c5196e 878{
c1adf9fb 879 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 880
fad95bf5 881 if (!ht_conf->is_ht) {
a2b0f02e 882 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 883 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 884 RXON_FLG_HT40_PROT_MSK |
42eb7c64 885 RXON_FLG_HT_PROT_MSK);
47c5196e 886 return;
42eb7c64 887 }
47c5196e 888
a2b0f02e
WYG		 889 /* FIXME: if the definition of ht_protection changed, the "translation"
890 * will be needed for rxon->flags
891 */
fad95bf5 892 rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 893
894 /* Set up channel bandwidth:
7aafef1c 895 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 896 /* clear the HT channel mode before set the mode */
897 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
898 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 899 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
900 /* pure ht40 */
fad95bf5 901 if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 902 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 903 /* Note: control channel is opposite of extension channel */
fad95bf5 904 switch (ht_conf->extension_chan_offset) {
508b08e7
WYG		 905 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
906 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
907 break;
908 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
909 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
910 break;
911 }
912 } else {
a2b0f02e 913 /* Note: control channel is opposite of extension channel */
fad95bf5 914 switch (ht_conf->extension_chan_offset) {
a2b0f02e
WYG		 915 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
916 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
917 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
918 break;
919 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
920 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
921 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
922 break;
923 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
924 default:
925 /* channel location only valid if in Mixed mode */
926 IWL_ERR(priv, "invalid extension channel offset\n");
927 break;
928 }
929 }
930 } else {
931 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 932 }
933
45823531
AK		 934 if (priv->cfg->ops->hcmd->set_rxon_chain)
935 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 936
02bb1bea 937 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 938 "extension channel offset 0x%x\n",
fad95bf5
JB		 939 le32_to_cpu(rxon->flags), ht_conf->ht_protection,
940 ht_conf->extension_chan_offset);
47c5196e
TW		 941 return;
942}
943EXPORT_SYMBOL(iwl_set_rxon_ht);
944
9e5e6c32
TW		 945#define IWL_NUM_RX_CHAINS_MULTIPLE 3
946#define IWL_NUM_RX_CHAINS_SINGLE 2
947#define IWL_NUM_IDLE_CHAINS_DUAL 2
948#define IWL_NUM_IDLE_CHAINS_SINGLE 1
949
2b396a12
JB		 950/*
951 * Determine how many receiver/antenna chains to use.
952 *
953 * More provides better reception via diversity. Fewer saves power
954 * at the expense of throughput, but only when not in powersave to
955 * start with.
956 *
c7de35cd
RR		 957 * MIMO (dual stream) requires at least 2, but works better with 3.
958 * This does not determine *which* chains to use, just how many.
959 */
28a6b07a 960static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 961{
c7de35cd 962 /* # of Rx chains to use when expecting MIMO. */
02bb1bea 963 if (is_single_rx_stream(priv))
9e5e6c32 964 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 965 else
9e5e6c32 966 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 967}
c7de35cd 968
2b396a12 969/*
3f3e0376
WYG		 970 * When we are in power saving mode, unless device support spatial
971 * multiplexing power save, use the active count for rx chain count.
2b396a12 972 */
28a6b07a
TW		 973static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
974{
3f3e0376
WYG		 975 int idle_cnt = active_cnt;
976 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
977
978 if (priv->cfg->support_sm_ps) {
979 /* # Rx chains when idling and maybe trying to save power */
980 switch (priv->current_ht_config.sm_ps) {
981 case WLAN_HT_CAP_SM_PS_STATIC:
982 case WLAN_HT_CAP_SM_PS_DYNAMIC:
983 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
984 IWL_NUM_IDLE_CHAINS_SINGLE;
985 break;
986 case WLAN_HT_CAP_SM_PS_DISABLED:
987 idle_cnt = (is_cam) ? active_cnt :
988 IWL_NUM_IDLE_CHAINS_SINGLE;
989 break;
990 case WLAN_HT_CAP_SM_PS_INVALID:
991 default:
992 IWL_ERR(priv, "invalid sm_ps mode %d\n",
993 priv->current_ht_config.sm_ps);
994 WARN_ON(1);
995 break;
996 }
997 }
998 return idle_cnt;
c7de35cd
RR		 999}
1000
04816448
GE		 1001/* up to 4 chains */
1002static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1003{
1004 u8 res;
1005 res = (chain_bitmap & BIT(0)) >> 0;
1006 res += (chain_bitmap & BIT(1)) >> 1;
1007 res += (chain_bitmap & BIT(2)) >> 2;
9bddbab3 1008 res += (chain_bitmap & BIT(3)) >> 3;
04816448
GE		 1009 return res;
1010}
1011
4c4df78f
CR		 1012/**
1013 * iwl_is_monitor_mode - Determine if interface in monitor mode
1014 *
1015 * priv->iw_mode is set in add_interface, but add_interface is
1016 * never called for monitor mode. The only way mac80211 informs us about
1017 * monitor mode is through configuring filters (call to configure_filter).
1018 */
279b05d4 1019bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1020{
1021 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1022}
279b05d4 1023EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1024
c7de35cd
RR		 1025/**
1026 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1027 *
1028 * Selects how many and which Rx receivers/antennas/chains to use.
1029 * This should not be used for scan command ... it puts data in wrong place.
1030 */
1031void iwl_set_rxon_chain(struct iwl_priv *priv)
1032{
28a6b07a
TW		 1033 bool is_single = is_single_rx_stream(priv);
1034 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1035 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1036 u32 active_chains;
28a6b07a 1037 u16 rx_chain;
c7de35cd
RR		 1038
1039 /* Tell uCode which antennas are actually connected.
1040 * Before first association, we assume all antennas are connected.
1041 * Just after first association, iwl_chain_noise_calibration()
1042 * checks which antennas actually *are* connected. */
04816448
GE		 1043 if (priv->chain_noise_data.active_chains)
1044 active_chains = priv->chain_noise_data.active_chains;
1045 else
1046 active_chains = priv->hw_params.valid_rx_ant;
1047
1048 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1049
1050 /* How many receivers should we use? */
28a6b07a
TW		 1051 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1052 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1053
28a6b07a 1054
04816448
GE		 1055 /* correct rx chain count according hw settings
1056 * and chain noise calibration
1057 */
1058 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1059 if (valid_rx_cnt < active_rx_cnt)
1060 active_rx_cnt = valid_rx_cnt;
1061
1062 if (valid_rx_cnt < idle_rx_cnt)
1063 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1064
1065 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1066 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1067
7b841727
RF		 1068 /* copied from 'iwl_bg_request_scan()' */
1069 /* Force use of chains B and C (0x6) for Rx for 4965
1070 * Avoid A (0x1) because of its off-channel reception on A-band.
1071 * MIMO is not used here, but value is required */
1072 if (iwl_is_monitor_mode(priv) &&
1073 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1074 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1075 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1076 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1077 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1078 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1079 }
1080
28a6b07a
TW		 1081 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1082
9e5e6c32 1083 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1084 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1085 else
1086 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1087
e1623446 1088 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1089 priv->staging_rxon.rx_chain,
1090 active_rx_cnt, idle_rx_cnt);
1091
1092 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1093 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1094}
1095EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1096
1097/**
17e72782 1098 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1099 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1100 * @channel: Any channel valid for the requested phymode
1101
1102 * In addition to setting the staging RXON, priv->phymode is also set.
1103 *
1104 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1105 * in the staging RXON flag structure based on the phymode
1106 */
17e72782 1107int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1108{
17e72782
TW		 1109 enum ieee80211_band band = ch->band;
1110 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1111
8622e705 1112 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1113 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1114 channel, band);
1115 return -EINVAL;
1116 }
1117
1118 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1119 (priv->band == band))
1120 return 0;
1121
1122 priv->staging_rxon.channel = cpu_to_le16(channel);
1123 if (band == IEEE80211_BAND_5GHZ)
1124 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1125 else
1126 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1127
1128 priv->band = band;
1129
e1623446 1130 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1131
1132 return 0;
1133}
c7de35cd 1134EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1135
8ccde88a
SO		 1136void iwl_set_flags_for_band(struct iwl_priv *priv,
1137 enum ieee80211_band band)
1138{
1139 if (band == IEEE80211_BAND_5GHZ) {
1140 priv->staging_rxon.flags &=
1141 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1142 | RXON_FLG_CCK_MSK);
1143 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1144 } else {
1145 /* Copied from iwl_post_associate() */
1146 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1147 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1148 else
1149 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1150
1151 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1152 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1153
1154 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1155 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1156 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1157 }
1158}
8ccde88a
SO		 1159
1160/*
1161 * initialize rxon structure with default values from eeprom
1162 */
1163void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1164{
1165 const struct iwl_channel_info *ch_info;
1166
1167 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1168
1169 switch (mode) {
1170 case NL80211_IFTYPE_AP:
1171 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1172 break;
1173
1174 case NL80211_IFTYPE_STATION:
1175 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1176 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1177 break;
1178
1179 case NL80211_IFTYPE_ADHOC:
1180 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1181 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1182 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1183 RXON_FILTER_ACCEPT_GRP_MSK;
1184 break;
1185
8ccde88a
SO		 1186 default:
1187 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1188 break;
1189 }
1190
1191#if 0
1192 /* TODO: Figure out when short_preamble would be set and cache from
1193 * that */
1194 if (!hw_to_local(priv->hw)->short_preamble)
1195 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1196 else
1197 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1198#endif
1199
1200 ch_info = iwl_get_channel_info(priv, priv->band,
1201 le16_to_cpu(priv->active_rxon.channel));
1202
1203 if (!ch_info)
1204 ch_info = &priv->channel_info[0];
1205
1206 /*
1207 * in some case A channels are all non IBSS
1208 * in this case force B/G channel
1209 */
1210 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1211 !(is_channel_ibss(ch_info)))
1212 ch_info = &priv->channel_info[0];
1213
1214 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1215 priv->band = ch_info->band;
1216
1217 iwl_set_flags_for_band(priv, priv->band);
1218
1219 priv->staging_rxon.ofdm_basic_rates =
1220 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1221 priv->staging_rxon.cck_basic_rates =
1222 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1223
a2b0f02e
WYG		 1224 /* clear both MIX and PURE40 mode flag */
1225 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1226 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1227 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1228 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1229 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1230 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1231 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1232}
1233EXPORT_SYMBOL(iwl_connection_init_rx_config);
1234
782571f4 1235static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1236{
1237 const struct ieee80211_supported_band *hw = NULL;
1238 struct ieee80211_rate *rate;
1239 int i;
1240
1241 hw = iwl_get_hw_mode(priv, priv->band);
1242 if (!hw) {
1243 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1244 return;
1245 }
1246
1247 priv->active_rate = 0;
1248 priv->active_rate_basic = 0;
1249
1250 for (i = 0; i < hw->n_bitrates; i++) {
1251 rate = &(hw->bitrates[i]);
5027309b 1252 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 1253 priv->active_rate |= (1 << rate->hw_value);
1254 }
1255
e1623446 1256 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1257 priv->active_rate, priv->active_rate_basic);
1258
1259 /*
1260 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1261 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1262 * OFDM
1263 */
1264 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1265 priv->staging_rxon.cck_basic_rates =
1266 ((priv->active_rate_basic &
1267 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1268 else
1269 priv->staging_rxon.cck_basic_rates =
1270 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1271
1272 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1273 priv->staging_rxon.ofdm_basic_rates =
1274 ((priv->active_rate_basic &
1275 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1276 IWL_FIRST_OFDM_RATE) & 0xFF;
1277 else
1278 priv->staging_rxon.ofdm_basic_rates =
1279 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1280}
8ccde88a
SO		 1281
1282void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1283{
2f301227 1284 struct iwl_rx_packet *pkt = rxb_addr(rxb);
8ccde88a
SO		 1285 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1286 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
4a56e965
WYG		 1287
1288 if (!le32_to_cpu(csa->status)) {
1289 rxon->channel = csa->channel;
1290 priv->staging_rxon.channel = csa->channel;
1291 IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
1292 le16_to_cpu(csa->channel));
1293 } else
1294 IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
1295 le16_to_cpu(csa->channel));
8ccde88a
SO		 1296}
1297EXPORT_SYMBOL(iwl_rx_csa);
1298
1299#ifdef CONFIG_IWLWIFI_DEBUG
1300static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1301{
1302 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1303
e1623446 1304 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1305 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1306 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1307 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1308 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1309 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1310 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1311 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1312 rxon->ofdm_basic_rates);
e1623446
TW		 1313 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1314 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1315 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1316 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1317}
6686d17e 1318#endif
8ccde88a
SO		 1319/**
1320 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1321 */
1322void iwl_irq_handle_error(struct iwl_priv *priv)
1323{
1324 /* Set the FW error flag -- cleared on iwl_down */
1325 set_bit(STATUS_FW_ERROR, &priv->status);
1326
1327 /* Cancel currently queued command. */
1328 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1329
1330#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1331 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
b7a79404
RC		 1332 priv->cfg->ops->lib->dump_nic_error_log(priv);
1333 priv->cfg->ops->lib->dump_nic_event_log(priv);
8ccde88a
SO		 1334 iwl_print_rx_config_cmd(priv);
1335 }
1336#endif
1337
1338 wake_up_interruptible(&priv->wait_command_queue);
1339
1340 /* Keep the restart process from trying to send host
1341 * commands by clearing the INIT status bit */
1342 clear_bit(STATUS_READY, &priv->status);
1343
1344 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1345 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1346 "Restarting adapter due to uCode error.\n");
1347
8ccde88a
SO		 1348 if (priv->cfg->mod_params->restart_fw)
1349 queue_work(priv->workqueue, &priv->restart);
1350 }
1351}
1352EXPORT_SYMBOL(iwl_irq_handle_error);
1353
d68b603c
AK		 1354int iwl_apm_stop_master(struct iwl_priv *priv)
1355{
5220af0c 1356 int ret = 0;
d68b603c 1357
5220af0c 1358 /* stop device's busmaster DMA activity */
d68b603c
AK		 1359 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1360
5220af0c 1361 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c 1362 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
5220af0c
BC		 1363 if (ret)
1364 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
d68b603c 1365
d68b603c
AK		 1366 IWL_DEBUG_INFO(priv, "stop master\n");
1367
5220af0c 1368 return ret;
d68b603c
AK		 1369}
1370EXPORT_SYMBOL(iwl_apm_stop_master);
1371
1372void iwl_apm_stop(struct iwl_priv *priv)
1373{
fadb3582
BC		 1374 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1375
5220af0c 1376 /* Stop device's DMA activity */
d68b603c
AK		 1377 iwl_apm_stop_master(priv);
1378
5220af0c 1379 /* Reset the entire device */
d68b603c
AK		 1380 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1381
1382 udelay(10);
5220af0c
BC		 1383
1384 /*
1385 * Clear "initialization complete" bit to move adapter from
1386 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
1387 */
d68b603c 1388 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
d68b603c
AK		 1389}
1390EXPORT_SYMBOL(iwl_apm_stop);
1391
fadb3582
BC		 1392
1393/*
1394 * Start up NIC's basic functionality after it has been reset
1395 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1396 * NOTE: This does not load uCode nor start the embedded processor
1397 */
1398int iwl_apm_init(struct iwl_priv *priv)
1399{
1400 int ret = 0;
1401 u16 lctl;
1402
1403 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1404
1405 /*
1406 * Use "set_bit" below rather than "write", to preserve any hardware
1407 * bits already set by default after reset.
1408 */
1409
1410 /* Disable L0S exit timer (platform NMI Work/Around) */
1411 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1412 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1413
1414 /*
1415 * Disable L0s without affecting L1;
1416 * don't wait for ICH L0s (ICH bug W/A)
1417 */
1418 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1419 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1420
1421 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1422 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1423
1424 /*
1425 * Enable HAP INTA (interrupt from management bus) to
1426 * wake device's PCI Express link L1a -> L0s
1427 * NOTE: This is no-op for 3945 (non-existant bit)
1428 */
1429 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1430 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1431
1432 /*
a6c5c731
BC		 1433 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1434 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1435 * If so (likely), disable L0S, so device moves directly L0->L1;
1436 * costs negligible amount of power savings.
1437 * If not (unlikely), enable L0S, so there is at least some
1438 * power savings, even without L1.
fadb3582
BC		 1439 */
1440 if (priv->cfg->set_l0s) {
1441 lctl = iwl_pcie_link_ctl(priv);
1442 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1443 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1444 /* L1-ASPM enabled; disable(!) L0S */
1445 iwl_set_bit(priv, CSR_GIO_REG,
1446 CSR_GIO_REG_VAL_L0S_ENABLED);
1447 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1448 } else {
1449 /* L1-ASPM disabled; enable(!) L0S */
1450 iwl_clear_bit(priv, CSR_GIO_REG,
1451 CSR_GIO_REG_VAL_L0S_ENABLED);
1452 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1453 }
1454 }
1455
1456 /* Configure analog phase-lock-loop before activating to D0A */
1457 if (priv->cfg->pll_cfg_val)
1458 iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
1459
1460 /*
1461 * Set "initialization complete" bit to move adapter from
1462 * D0U* --> D0A* (powered-up active) state.
1463 */
1464 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1465
1466 /*
1467 * Wait for clock stabilization; once stabilized, access to
1468 * device-internal resources is supported, e.g. iwl_write_prph()
1469 * and accesses to uCode SRAM.
1470 */
1471 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1472 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1473 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1474 if (ret < 0) {
1475 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1476 goto out;
1477 }
1478
1479 /*
1480 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
1481 * BSM (Boostrap State Machine) is only in 3945 and 4965;
1482 * later devices (i.e. 5000 and later) have non-volatile SRAM,
1483 * and don't need BSM to restore data after power-saving sleep.
1484 *
1485 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1486 * do not disable clocks. This preserves any hardware bits already
1487 * set by default in "CLK_CTRL_REG" after reset.
1488 */
1489 if (priv->cfg->use_bsm)
1490 iwl_write_prph(priv, APMG_CLK_EN_REG,
1491 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
1492 else
1493 iwl_write_prph(priv, APMG_CLK_EN_REG,
1494 APMG_CLK_VAL_DMA_CLK_RQT);
1495 udelay(20);
1496
1497 /* Disable L1-Active */
1498 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1499 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1500
1501out:
1502 return ret;
1503}
1504EXPORT_SYMBOL(iwl_apm_init);
1505
1506
1507
8ccde88a
SO		 1508void iwl_configure_filter(struct ieee80211_hw *hw,
1509 unsigned int changed_flags,
1510 unsigned int *total_flags,
3ac64bee 1511 u64 multicast)
8ccde88a
SO		 1512{
1513 struct iwl_priv *priv = hw->priv;
1514 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1515
e1623446 1516 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1517 changed_flags, *total_flags);
1518
1519 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1520 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1521 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1522 else
1523 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1524 }
1525 if (changed_flags & FIF_ALLMULTI) {
1526 if (*total_flags & FIF_ALLMULTI)
1527 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1528 else
1529 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1530 }
1531 if (changed_flags & FIF_CONTROL) {
1532 if (*total_flags & FIF_CONTROL)
1533 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1534 else
1535 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1536 }
1537 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1538 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1539 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1540 else
1541 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1542 }
1543
1544 /* We avoid iwl_commit_rxon here to commit the new filter flags
1545 * since mac80211 will call ieee80211_hw_config immediately.
1546 * (mc_list is not supported at this time). Otherwise, we need to
1547 * queue a background iwl_commit_rxon work.
1548 */
1549
1550 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1551 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1552}
1553EXPORT_SYMBOL(iwl_configure_filter);
1554
da154e30
RR		 1555int iwl_set_hw_params(struct iwl_priv *priv)
1556{
da154e30
RR		 1557 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1558 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1559 if (priv->cfg->mod_params->amsdu_size_8K)
2f301227 1560 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
da154e30 1561 else
2f301227 1562 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
da154e30 1563
2c2f3b33
TW		 1564 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1565
49779293
RR		 1566 if (priv->cfg->mod_params->disable_11n)
1567 priv->cfg->sku &= ~IWL_SKU_N;
1568
da154e30
RR		 1569 /* Device-specific setup */
1570 return priv->cfg->ops->lib->set_hw_params(priv);
1571}
1572EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956 1573
630fe9b6
TW		 1574int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1575{
1576 int ret = 0;
5eadd94b
WYG		 1577 s8 prev_tx_power = priv->tx_power_user_lmt;
1578
630fe9b6 1579 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1580 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1581 tx_power,
1582 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1583 return -EINVAL;
1584 }
1585
dc1b0973 1586 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1587 IWL_WARN(priv,
1588 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1589 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1590 return -EINVAL;
1591 }
1592
1593 if (priv->tx_power_user_lmt != tx_power)
1594 force = true;
1595
019fb97d 1596 /* if nic is not up don't send command */
5eadd94b
WYG		 1597 if (iwl_is_ready_rf(priv)) {
1598 priv->tx_power_user_lmt = tx_power;
1599 if (force && priv->cfg->ops->lib->send_tx_power)
1600 ret = priv->cfg->ops->lib->send_tx_power(priv);
1601 else if (!priv->cfg->ops->lib->send_tx_power)
1602 ret = -EOPNOTSUPP;
1603 /*
1604 * if fail to set tx_power, restore the orig. tx power
1605 */
1606 if (ret)
1607 priv->tx_power_user_lmt = prev_tx_power;
1608 }
630fe9b6 1609
5eadd94b
WYG		 1610 /*
1611 * Even this is an async host command, the command
1612 * will always report success from uCode
1613 * So once driver can placing the command into the queue
1614 * successfully, driver can use priv->tx_power_user_lmt
1615 * to reflect the current tx power
1616 */
630fe9b6
TW		 1617 return ret;
1618}
1619EXPORT_SYMBOL(iwl_set_tx_power);
1620
ef850d7c
MA		 1621#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1622
1623/* Free dram table */
1624void iwl_free_isr_ict(struct iwl_priv *priv)
1625{
1626 if (priv->ict_tbl_vir) {
1627 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1628 PAGE_SIZE, priv->ict_tbl_vir,
1629 priv->ict_tbl_dma);
1630 priv->ict_tbl_vir = NULL;
1631 }
1632}
1633EXPORT_SYMBOL(iwl_free_isr_ict);
1634
1635
1636/* allocate dram shared table it is a PAGE_SIZE aligned
1637 * also reset all data related to ICT table interrupt.
1638 */
1639int iwl_alloc_isr_ict(struct iwl_priv *priv)
1640{
1641
1642 if (priv->cfg->use_isr_legacy)
1643 return 0;
1644 /* allocate shrared data table */
1645 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1646 ICT_COUNT) + PAGE_SIZE,
1647 &priv->ict_tbl_dma);
1648 if (!priv->ict_tbl_vir)
1649 return -ENOMEM;
1650
1651 /* align table to PAGE_SIZE boundry */
1652 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1653
1654 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1655 (unsigned long long)priv->ict_tbl_dma,
1656 (unsigned long long)priv->aligned_ict_tbl_dma,
1657 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1658
1659 priv->ict_tbl = priv->ict_tbl_vir +
1660 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1661
1662 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1663 priv->ict_tbl, priv->ict_tbl_vir,
1664 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1665
1666 /* reset table and index to all 0 */
1667 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1668 priv->ict_index = 0;
1669
40cefda9
MA		 1670 /* add periodic RX interrupt */
1671 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1672 return 0;
1673}
1674EXPORT_SYMBOL(iwl_alloc_isr_ict);
1675
1676/* Device is going up inform it about using ICT interrupt table,
1677 * also we need to tell the driver to start using ICT interrupt.
1678 */
1679int iwl_reset_ict(struct iwl_priv *priv)
1680{
1681 u32 val;
1682 unsigned long flags;
1683
1684 if (!priv->ict_tbl_vir)
1685 return 0;
1686
1687 spin_lock_irqsave(&priv->lock, flags);
1688 iwl_disable_interrupts(priv);
1689
1303dcfd 1690 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
ef850d7c
MA		 1691
1692 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1693
1694 val |= CSR_DRAM_INT_TBL_ENABLE;
1695 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1696
1697 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1698 "aligned dma address %Lx\n",
1699 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1700
1701 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1702 priv->use_ict = true;
1703 priv->ict_index = 0;
40cefda9 1704 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1705 iwl_enable_interrupts(priv);
1706 spin_unlock_irqrestore(&priv->lock, flags);
1707
1708 return 0;
1709}
1710EXPORT_SYMBOL(iwl_reset_ict);
1711
1712/* Device is going down disable ict interrupt usage */
1713void iwl_disable_ict(struct iwl_priv *priv)
1714{
1715 unsigned long flags;
1716
1717 spin_lock_irqsave(&priv->lock, flags);
1718 priv->use_ict = false;
1719 spin_unlock_irqrestore(&priv->lock, flags);
1720}
1721EXPORT_SYMBOL(iwl_disable_ict);
1722
1723/* interrupt handler using ict table, with this interrupt driver will
1724 * stop using INTA register to get device's interrupt, reading this register
1725 * is expensive, device will write interrupts in ICT dram table, increment
1726 * index then will fire interrupt to driver, driver will OR all ICT table
1727 * entries from current index up to table entry with 0 value. the result is
1728 * the interrupt we need to service, driver will set the entries back to 0 and
1729 * set index.
1730 */
1731irqreturn_t iwl_isr_ict(int irq, void *data)
1732{
1733 struct iwl_priv *priv = data;
1734 u32 inta, inta_mask;
1735 u32 val = 0;
1736
1737 if (!priv)
1738 return IRQ_NONE;
1739
1740 /* dram interrupt table not set yet,
1741 * use legacy interrupt.
1742 */
1743 if (!priv->use_ict)
1744 return iwl_isr(irq, data);
1745
1746 spin_lock(&priv->lock);
1747
1748 /* Disable (but don't clear!) interrupts here to avoid
1749 * back-to-back ISRs and sporadic interrupts from our NIC.
1750 * If we have something to service, the tasklet will re-enable ints.
1751 * If we *don't* have something, we'll re-enable before leaving here.
1752 */
1753 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1754 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1755
1756
1757 /* Ignore interrupt if there's nothing in NIC to service.
1758 * This may be due to IRQ shared with another device,
1759 * or due to sporadic interrupts thrown from our NIC. */
1760 if (!priv->ict_tbl[priv->ict_index]) {
1761 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1762 goto none;
1763 }
1764
1765 /* read all entries that not 0 start with ict_index */
1766 while (priv->ict_tbl[priv->ict_index]) {
1767
1303dcfd 1768 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
ef850d7c 1769 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1303dcfd
JB		 1770 priv->ict_index,
1771 le32_to_cpu(priv->ict_tbl[priv->ict_index]));
ef850d7c
MA		 1772 priv->ict_tbl[priv->ict_index] = 0;
1773 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1303dcfd 1774 ICT_COUNT);
ef850d7c
MA		 1775
1776 }
1777
1778 /* We should not get this value, just ignore it. */
1779 if (val == 0xffffffff)
1780 val = 0;
1781
1782 inta = (0xff & val) | ((0xff00 & val) << 16);
1783 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1784 inta, inta_mask, val);
1785
40cefda9 1786 inta &= priv->inta_mask;
ef850d7c
MA		 1787 priv->inta |= inta;
1788
1789 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1790 if (likely(inta))
1791 tasklet_schedule(&priv->irq_tasklet);
1792 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1793 /* Allow interrupt if was disabled by this handler and
1794 * no tasklet was schedules, We should not enable interrupt,
1795 * tasklet will enable it.
1796 */
1797 iwl_enable_interrupts(priv);
1798 }
1799
1800 spin_unlock(&priv->lock);
1801 return IRQ_HANDLED;
1802
1803 none:
1804 /* re-enable interrupts here since we don't have anything to service.
1805 * only Re-enable if disabled by irq.
1806 */
1807 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1808 iwl_enable_interrupts(priv);
1809
1810 spin_unlock(&priv->lock);
1811 return IRQ_NONE;
1812}
1813EXPORT_SYMBOL(iwl_isr_ict);
1814
1815
1816static irqreturn_t iwl_isr(int irq, void *data)
1817{
1818 struct iwl_priv *priv = data;
1819 u32 inta, inta_mask;
d651ae32 1820#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1821 u32 inta_fh;
d651ae32 1822#endif
ef850d7c
MA		 1823 if (!priv)
1824 return IRQ_NONE;
1825
1826 spin_lock(&priv->lock);
1827
1828 /* Disable (but don't clear!) interrupts here to avoid
1829 * back-to-back ISRs and sporadic interrupts from our NIC.
1830 * If we have something to service, the tasklet will re-enable ints.
1831 * If we *don't* have something, we'll re-enable before leaving here. */
1832 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1833 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1834
1835 /* Discover which interrupts are active/pending */
1836 inta = iwl_read32(priv, CSR_INT);
1837
1838 /* Ignore interrupt if there's nothing in NIC to service.
1839 * This may be due to IRQ shared with another device,
1840 * or due to sporadic interrupts thrown from our NIC. */
1841 if (!inta) {
1842 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1843 goto none;
1844 }
1845
1846 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1847 /* Hardware disappeared. It might have already raised
1848 * an interrupt */
1849 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1850 goto unplugged;
1851 }
1852
1853#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1854 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1855 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1856 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1857 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1858 }
1859#endif
1860
1861 priv->inta |= inta;
1862 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1863 if (likely(inta))
1864 tasklet_schedule(&priv->irq_tasklet);
1865 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1866 iwl_enable_interrupts(priv);
1867
1868 unplugged:
1869 spin_unlock(&priv->lock);
1870 return IRQ_HANDLED;
1871
1872 none:
1873 /* re-enable interrupts here since we don't have anything to service. */
1874 /* only Re-enable if diabled by irq and no schedules tasklet. */
1875 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1876 iwl_enable_interrupts(priv);
1877
1878 spin_unlock(&priv->lock);
1879 return IRQ_NONE;
1880}
1881
1882irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1883{
1884 struct iwl_priv *priv = data;
1885 u32 inta, inta_mask;
1886 u32 inta_fh;
1887 if (!priv)
1888 return IRQ_NONE;
1889
1890 spin_lock(&priv->lock);
1891
1892 /* Disable (but don't clear!) interrupts here to avoid
1893 * back-to-back ISRs and sporadic interrupts from our NIC.
1894 * If we have something to service, the tasklet will re-enable ints.
1895 * If we *don't* have something, we'll re-enable before leaving here. */
1896 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1897 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1898
1899 /* Discover which interrupts are active/pending */
1900 inta = iwl_read32(priv, CSR_INT);
1901 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1902
1903 /* Ignore interrupt if there's nothing in NIC to service.
1904 * This may be due to IRQ shared with another device,
1905 * or due to sporadic interrupts thrown from our NIC. */
1906 if (!inta && !inta_fh) {
1907 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1908 goto none;
1909 }
1910
1911 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1912 /* Hardware disappeared. It might have already raised
1913 * an interrupt */
1914 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1915 goto unplugged;
1916 }
1917
1918 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1919 inta, inta_mask, inta_fh);
1920
1921 inta &= ~CSR_INT_BIT_SCD;
1922
1923 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1924 if (likely(inta || inta_fh))
1925 tasklet_schedule(&priv->irq_tasklet);
1926
1927 unplugged:
1928 spin_unlock(&priv->lock);
1929 return IRQ_HANDLED;
1930
1931 none:
1932 /* re-enable interrupts here since we don't have anything to service. */
1933 /* only Re-enable if diabled by irq */
1934 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1935 iwl_enable_interrupts(priv);
1936 spin_unlock(&priv->lock);
1937 return IRQ_NONE;
1938}
ef850d7c 1939EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1940
17f841cd
SO		 1941int iwl_send_bt_config(struct iwl_priv *priv)
1942{
1943 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 1944 .flags = BT_COEX_MODE_4W,
1945 .lead_time = BT_LEAD_TIME_DEF,
1946 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 1947 .kill_ack_mask = 0,
1948 .kill_cts_mask = 0,
1949 };
1950
1951 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1952 sizeof(struct iwl_bt_cmd), &bt_cmd);
1953}
1954EXPORT_SYMBOL(iwl_send_bt_config);
1955
49ea8596
EG		 1956int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1957{
1958 u32 stat_flags = 0;
1959 struct iwl_host_cmd cmd = {
1960 .id = REPLY_STATISTICS_CMD,
c2acea8e 1961 .flags = flags,
49ea8596
EG		 1962 .len = sizeof(stat_flags),
1963 .data = (u8 *) &stat_flags,
1964 };
1965 return iwl_send_cmd(priv, &cmd);
1966}
1967EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1968
b0692f2f
EG		 1969/**
1970 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1971 * using sample data 100 bytes apart. If these sample points are good,
1972 * it's a pretty good bet that everything between them is good, too.
1973 */
1974static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1975{
1976 u32 val;
1977 int ret = 0;
1978 u32 errcnt = 0;
1979 u32 i;
1980
e1623446 1981 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 1982
b0692f2f
EG		 1983 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1984 /* read data comes through single port, auto-incr addr */
1985 /* NOTE: Use the debugless read so we don't flood kernel log
1986 * if IWL_DL_IO is set */
1987 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1988 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1989 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1990 if (val != le32_to_cpu(*image)) {
1991 ret = -EIO;
1992 errcnt++;
1993 if (errcnt >= 3)
1994 break;
1995 }
1996 }
1997
b0692f2f
EG		 1998 return ret;
1999}
2000
2001/**
2002 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2003 * looking at all data.
2004 */
2005static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2006 u32 len)
2007{
2008 u32 val;
2009 u32 save_len = len;
2010 int ret = 0;
2011 u32 errcnt;
2012
e1623446 2013 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2014
250bdd21
SO		 2015 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2016 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2017
2018 errcnt = 0;
2019 for (; len > 0; len -= sizeof(u32), image++) {
2020 /* read data comes through single port, auto-incr addr */
2021 /* NOTE: Use the debugless read so we don't flood kernel log
2022 * if IWL_DL_IO is set */
2023 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2024 if (val != le32_to_cpu(*image)) {
15b1687c 2025 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2026 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2027 save_len - len, val, le32_to_cpu(*image));
2028 ret = -EIO;
2029 errcnt++;
2030 if (errcnt >= 20)
2031 break;
2032 }
2033 }
2034
b0692f2f 2035 if (!errcnt)
e1623446
TW		 2036 IWL_DEBUG_INFO(priv,
2037 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2038
2039 return ret;
2040}
2041
2042/**
2043 * iwl_verify_ucode - determine which instruction image is in SRAM,
2044 * and verify its contents
2045 */
2046int iwl_verify_ucode(struct iwl_priv *priv)
2047{
2048 __le32 *image;
2049 u32 len;
2050 int ret;
2051
2052 /* Try bootstrap */
2053 image = (__le32 *)priv->ucode_boot.v_addr;
2054 len = priv->ucode_boot.len;
2055 ret = iwlcore_verify_inst_sparse(priv, image, len);
2056 if (!ret) {
e1623446 2057 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2058 return 0;
2059 }
2060
2061 /* Try initialize */
2062 image = (__le32 *)priv->ucode_init.v_addr;
2063 len = priv->ucode_init.len;
2064 ret = iwlcore_verify_inst_sparse(priv, image, len);
2065 if (!ret) {
e1623446 2066 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2067 return 0;
2068 }
2069
2070 /* Try runtime/protocol */
2071 image = (__le32 *)priv->ucode_code.v_addr;
2072 len = priv->ucode_code.len;
2073 ret = iwlcore_verify_inst_sparse(priv, image, len);
2074 if (!ret) {
e1623446 2075 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2076 return 0;
2077 }
2078
15b1687c 2079 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2080
2081 /* Since nothing seems to match, show first several data entries in
2082 * instruction SRAM, so maybe visual inspection will give a clue.
2083 * Selection of bootstrap image (vs. other images) is arbitrary. */
2084 image = (__le32 *)priv->ucode_boot.v_addr;
2085 len = priv->ucode_boot.len;
2086 ret = iwl_verify_inst_full(priv, image, len);
2087
2088 return ret;
2089}
2090EXPORT_SYMBOL(iwl_verify_ucode);
2091
56e12615 2092
47f4a587
EG		 2093void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2094{
2095 struct iwl_ct_kill_config cmd;
672639de 2096 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2097 unsigned long flags;
2098 int ret = 0;
2099
2100 spin_lock_irqsave(&priv->lock, flags);
2101 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2102 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2103 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2104 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2105
480e8407 2106 if (priv->cfg->support_ct_kill_exit) {
672639de
WYG		 2107 adv_cmd.critical_temperature_enter =
2108 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2109 adv_cmd.critical_temperature_exit =
2110 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2111
2112 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2113 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2114 if (ret)
2115 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2116 else
2117 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2118 "succeeded, "
2119 "critical temperature enter is %d,"
2120 "exit is %d\n",
2121 priv->hw_params.ct_kill_threshold,
2122 priv->hw_params.ct_kill_exit_threshold);
480e8407 2123 } else {
672639de
WYG		 2124 cmd.critical_temperature_R =
2125 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2126
672639de
WYG		 2127 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2128 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2129 if (ret)
2130 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2131 else
2132 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2133 "succeeded, "
2134 "critical temperature is %d\n",
2135 priv->hw_params.ct_kill_threshold);
672639de 2136 }
47f4a587
EG		 2137}
2138EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2139
0ad91a35 2140
14a08a7f
EG		 2141/*
2142 * CARD_STATE_CMD
2143 *
2144 * Use: Sets the device's internal card state to enable, disable, or halt
2145 *
2146 * When in the 'enable' state the card operates as normal.
2147 * When in the 'disable' state, the card enters into a low power mode.
2148 * When in the 'halt' state, the card is shut down and must be fully
2149 * restarted to come back on.
2150 */
c496294e 2151int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2152{
2153 struct iwl_host_cmd cmd = {
2154 .id = REPLY_CARD_STATE_CMD,
2155 .len = sizeof(u32),
2156 .data = &flags,
c2acea8e 2157 .flags = meta_flag,
14a08a7f
EG		 2158 };
2159
2160 return iwl_send_cmd(priv, &cmd);
2161}
2162
030f05ed
AK		 2163void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2164 struct iwl_rx_mem_buffer *rxb)
2165{
2166#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 2167 struct iwl_rx_packet *pkt = rxb_addr(rxb);
030f05ed
AK		 2168 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2169 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2170 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2171#endif
2172}
2173EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2174
2175void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2176 struct iwl_rx_mem_buffer *rxb)
2177{
2f301227 2178 struct iwl_rx_packet *pkt = rxb_addr(rxb);
396887a2 2179 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
030f05ed 2180 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
396887a2
DH		 2181 "notification for %s:\n", len,
2182 get_cmd_string(pkt->hdr.cmd));
2183 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
030f05ed
AK		 2184}
2185EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2186
2187void iwl_rx_reply_error(struct iwl_priv *priv,
2188 struct iwl_rx_mem_buffer *rxb)
2189{
2f301227 2190 struct iwl_rx_packet *pkt = rxb_addr(rxb);
261b9c33
AK		 2191
2192 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2193 "seq 0x%04X ser 0x%08X\n",
2194 le32_to_cpu(pkt->u.err_resp.error_type),
2195 get_cmd_string(pkt->u.err_resp.cmd_id),
2196 pkt->u.err_resp.cmd_id,
2197 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2198 le32_to_cpu(pkt->u.err_resp.error_info));
2199}
2200EXPORT_SYMBOL(iwl_rx_reply_error);
2201
a83b9141
WYG		 2202void iwl_clear_isr_stats(struct iwl_priv *priv)
2203{
2204 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2205}
a83b9141 2206
488829f1
AK		 2207int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2208 const struct ieee80211_tx_queue_params *params)
2209{
2210 struct iwl_priv *priv = hw->priv;
2211 unsigned long flags;
2212 int q;
2213
2214 IWL_DEBUG_MAC80211(priv, "enter\n");
2215
2216 if (!iwl_is_ready_rf(priv)) {
2217 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2218 return -EIO;
2219 }
2220
2221 if (queue >= AC_NUM) {
2222 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2223 return 0;
2224 }
2225
2226 q = AC_NUM - 1 - queue;
2227
2228 spin_lock_irqsave(&priv->lock, flags);
2229
2230 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2231 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2232 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2233 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2234 cpu_to_le16((params->txop * 32));
2235
2236 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2237 priv->qos_data.qos_active = 1;
2238
2239 if (priv->iw_mode == NL80211_IFTYPE_AP)
2240 iwl_activate_qos(priv, 1);
2241 else if (priv->assoc_id && iwl_is_associated(priv))
2242 iwl_activate_qos(priv, 0);
2243
2244 spin_unlock_irqrestore(&priv->lock, flags);
2245
2246 IWL_DEBUG_MAC80211(priv, "leave\n");
2247 return 0;
2248}
2249EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2250
2251static void iwl_ht_conf(struct iwl_priv *priv,
02bb1bea 2252 struct ieee80211_bss_conf *bss_conf)
5bbe233b 2253{
fad95bf5 2254 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
5bbe233b
AK		 2255 struct ieee80211_sta *sta;
2256
2257 IWL_DEBUG_MAC80211(priv, "enter: \n");
2258
fad95bf5 2259 if (!ht_conf->is_ht)
5bbe233b
AK		 2260 return;
2261
fad95bf5 2262 ht_conf->ht_protection =
9ed6bcce 2263 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
fad95bf5 2264 ht_conf->non_GF_STA_present =
9ed6bcce 2265 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b 2266
02bb1bea
JB		 2267 ht_conf->single_chain_sufficient = false;
2268
2269 switch (priv->iw_mode) {
2270 case NL80211_IFTYPE_STATION:
2271 rcu_read_lock();
2272 sta = ieee80211_find_sta(priv->hw, priv->bssid);
2273 if (sta) {
2274 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2275 int maxstreams;
2276
2277 maxstreams = (ht_cap->mcs.tx_params &
2278 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
2279 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2280 maxstreams += 1;
2281
3f3e0376
WYG		 2282 ht_conf->sm_ps =
2283 (u8)((ht_cap->cap & IEEE80211_HT_CAP_SM_PS)
2284 >> 2);
2285 IWL_DEBUG_MAC80211(priv, "sm_ps: 0x%x\n",
2286 ht_conf->sm_ps);
2287
02bb1bea
JB		 2288 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2289 (ht_cap->mcs.rx_mask[2] == 0))
2290 ht_conf->single_chain_sufficient = true;
2291 if (maxstreams <= 1)
2292 ht_conf->single_chain_sufficient = true;
2293 } else {
2294 /*
2295 * If at all, this can only happen through a race
2296 * when the AP disconnects us while we're still
2297 * setting up the connection, in that case mac80211
2298 * will soon tell us about that.
2299 */
2300 ht_conf->single_chain_sufficient = true;
2301 }
2302 rcu_read_unlock();
2303 break;
2304 case NL80211_IFTYPE_ADHOC:
2305 ht_conf->single_chain_sufficient = true;
2306 break;
2307 default:
2308 break;
2309 }
5bbe233b
AK		 2310
2311 IWL_DEBUG_MAC80211(priv, "leave\n");
2312}
2313
2314#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2315void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2316 struct ieee80211_vif *vif,
2317 struct ieee80211_bss_conf *bss_conf,
2318 u32 changes)
5bbe233b
AK		 2319{
2320 struct iwl_priv *priv = hw->priv;
3a650292 2321 int ret;
5bbe233b
AK		 2322
2323 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2324
2d0ddec5
JB		 2325 if (!iwl_is_alive(priv))
2326 return;
2327
2328 mutex_lock(&priv->mutex);
2329
2330 if (changes & BSS_CHANGED_BEACON &&
2331 priv->iw_mode == NL80211_IFTYPE_AP) {
2332 dev_kfree_skb(priv->ibss_beacon);
2333 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2334 }
2335
d7129e19
JB		 2336 if (changes & BSS_CHANGED_BEACON_INT) {
2337 priv->beacon_int = bss_conf->beacon_int;
2338 /* TODO: in AP mode, do something to make this take effect */
2339 }
2340
2341 if (changes & BSS_CHANGED_BSSID) {
2342 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2343
2344 /*
2345 * If there is currently a HW scan going on in the
2346 * background then we need to cancel it else the RXON
2347 * below/in post_associate will fail.
2348 */
2d0ddec5 2349 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2350 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2351 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2352 mutex_unlock(&priv->mutex);
2353 return;
2354 }
2d0ddec5 2355
d7129e19
JB		 2356 /* mac80211 only sets assoc when in STATION mode */
2357 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2358 bss_conf->assoc) {
2359 memcpy(priv->staging_rxon.bssid_addr,
2360 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2361
d7129e19
JB		 2362 /* currently needed in a few places */
2363 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2364 } else {
2365 priv->staging_rxon.filter_flags &=
2366 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2367 }
d7129e19 2368
2d0ddec5
JB		 2369 }
2370
d7129e19
JB		 2371 /*
2372 * This needs to be after setting the BSSID in case
2373 * mac80211 decides to do both changes at once because
2374 * it will invoke post_associate.
2375 */
2d0ddec5
JB		 2376 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2377 changes & BSS_CHANGED_BEACON) {
2378 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2379
2380 if (beacon)
2381 iwl_mac_beacon_update(hw, beacon);
2382 }
2383
5bbe233b
AK		 2384 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2385 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2386 bss_conf->use_short_preamble);
2387 if (bss_conf->use_short_preamble)
2388 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2389 else
2390 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2391 }
2392
2393 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2394 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2395 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2396 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2397 else
2398 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2399 }
2400
d7129e19
JB		 2401 if (changes & BSS_CHANGED_BASIC_RATES) {
2402 /* XXX use this information
2403 *
2404 * To do that, remove code from iwl_set_rate() and put something
2405 * like this here:
2406 *
2407 if (A-band)
2408 priv->staging_rxon.ofdm_basic_rates =
2409 bss_conf->basic_rates;
2410 else
2411 priv->staging_rxon.ofdm_basic_rates =
2412 bss_conf->basic_rates >> 4;
2413 priv->staging_rxon.cck_basic_rates =
2414 bss_conf->basic_rates & 0xF;
2415 */
2416 }
2417
5bbe233b
AK		 2418 if (changes & BSS_CHANGED_HT) {
2419 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2420
2421 if (priv->cfg->ops->hcmd->set_rxon_chain)
2422 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2423 }
2424
2425 if (changes & BSS_CHANGED_ASSOC) {
2426 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2427 if (bss_conf->assoc) {
2428 priv->assoc_id = bss_conf->aid;
2429 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2430 priv->timestamp = bss_conf->timestamp;
2431 priv->assoc_capability = bss_conf->assoc_capability;
2432
e932a609
JB		 2433 iwl_led_associate(priv);
2434
d7129e19
JB		 2435 /*
2436 * We have just associated, don't start scan too early
2437 * leave time for EAPOL exchange to complete.
2438 *
2439 * XXX: do this in mac80211
5bbe233b
AK		 2440 */
2441 priv->next_scan_jiffies = jiffies +
2442 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2443 if (!iwl_is_rfkill(priv))
2444 priv->cfg->ops->lib->post_associate(priv);
e932a609 2445 } else {
5bbe233b 2446 priv->assoc_id = 0;
e932a609
JB		 2447 iwl_led_disassociate(priv);
2448 }
d7129e19
JB		 2449 }
2450
2451 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2452 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2453 changes);
2454 ret = iwl_send_rxon_assoc(priv);
2455 if (!ret) {
2456 /* Sync active_rxon with latest change. */
2457 memcpy((void *)&priv->active_rxon,
2458 &priv->staging_rxon,
2459 sizeof(struct iwl_rxon_cmd));
5bbe233b 2460 }
5bbe233b 2461 }
d7129e19
JB		 2462
2463 mutex_unlock(&priv->mutex);
2464
2d0ddec5 2465 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2466}
2467EXPORT_SYMBOL(iwl_bss_info_changed);
2468
9944b938
AK		 2469int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2470{
2471 struct iwl_priv *priv = hw->priv;
2472 unsigned long flags;
2473 __le64 timestamp;
2474
2475 IWL_DEBUG_MAC80211(priv, "enter\n");
2476
2477 if (!iwl_is_ready_rf(priv)) {
2478 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2479 return -EIO;
2480 }
2481
2482 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2483 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2484 return -EIO;
2485 }
2486
2487 spin_lock_irqsave(&priv->lock, flags);
2488
2489 if (priv->ibss_beacon)
2490 dev_kfree_skb(priv->ibss_beacon);
2491
2492 priv->ibss_beacon = skb;
2493
2494 priv->assoc_id = 0;
2495 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2496 priv->timestamp = le64_to_cpu(timestamp);
2497
2498 IWL_DEBUG_MAC80211(priv, "leave\n");
2499 spin_unlock_irqrestore(&priv->lock, flags);
2500
2501 iwl_reset_qos(priv);
2502
2503 priv->cfg->ops->lib->post_associate(priv);
2504
2505
2506 return 0;
2507}
2508EXPORT_SYMBOL(iwl_mac_beacon_update);
2509
727882d6
AK		 2510int iwl_set_mode(struct iwl_priv *priv, int mode)
2511{
2512 if (mode == NL80211_IFTYPE_ADHOC) {
2513 const struct iwl_channel_info *ch_info;
2514
2515 ch_info = iwl_get_channel_info(priv,
2516 priv->band,
2517 le16_to_cpu(priv->staging_rxon.channel));
2518
2519 if (!ch_info || !is_channel_ibss(ch_info)) {
2520 IWL_ERR(priv, "channel %d not IBSS channel\n",
2521 le16_to_cpu(priv->staging_rxon.channel));
2522 return -EINVAL;
2523 }
2524 }
2525
2526 iwl_connection_init_rx_config(priv, mode);
2527
2528 if (priv->cfg->ops->hcmd->set_rxon_chain)
2529 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2530
2531 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2532
c587de0b 2533 iwl_clear_stations_table(priv);
727882d6
AK		 2534
2535 /* dont commit rxon if rf-kill is on*/
2536 if (!iwl_is_ready_rf(priv))
2537 return -EAGAIN;
2538
727882d6
AK		 2539 iwlcore_commit_rxon(priv);
2540
2541 return 0;
2542}
2543EXPORT_SYMBOL(iwl_set_mode);
2544
cbb6ab94
AK		 2545int iwl_mac_add_interface(struct ieee80211_hw *hw,
2546 struct ieee80211_if_init_conf *conf)
2547{
2548 struct iwl_priv *priv = hw->priv;
2549 unsigned long flags;
2550
2551 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2552
2553 if (priv->vif) {
2554 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2555 return -EOPNOTSUPP;
2556 }
2557
2558 spin_lock_irqsave(&priv->lock, flags);
2559 priv->vif = conf->vif;
2560 priv->iw_mode = conf->type;
2561
2562 spin_unlock_irqrestore(&priv->lock, flags);
2563
2564 mutex_lock(&priv->mutex);
2565
2566 if (conf->mac_addr) {
2567 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2568 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2569 }
2570
2571 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2572 /* we are not ready, will run again when ready */
2573 set_bit(STATUS_MODE_PENDING, &priv->status);
2574
2575 mutex_unlock(&priv->mutex);
2576
2577 IWL_DEBUG_MAC80211(priv, "leave\n");
2578 return 0;
2579}
2580EXPORT_SYMBOL(iwl_mac_add_interface);
2581
d8052319
AK		 2582void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2583 struct ieee80211_if_init_conf *conf)
2584{
2585 struct iwl_priv *priv = hw->priv;
2586
2587 IWL_DEBUG_MAC80211(priv, "enter\n");
2588
2589 mutex_lock(&priv->mutex);
2590
2591 if (iwl_is_ready_rf(priv)) {
2592 iwl_scan_cancel_timeout(priv, 100);
2593 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2594 iwlcore_commit_rxon(priv);
2595 }
2596 if (priv->vif == conf->vif) {
2597 priv->vif = NULL;
2598 memset(priv->bssid, 0, ETH_ALEN);
2599 }
2600 mutex_unlock(&priv->mutex);
2601
2602 IWL_DEBUG_MAC80211(priv, "leave\n");
2603
2604}
2605EXPORT_SYMBOL(iwl_mac_remove_interface);
2606
4808368d
AK		 2607/**
2608 * iwl_mac_config - mac80211 config callback
2609 *
2610 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2611 * be set inappropriately and the driver currently sets the hardware up to
2612 * use it whenever needed.
2613 */
2614int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2615{
2616 struct iwl_priv *priv = hw->priv;
2617 const struct iwl_channel_info *ch_info;
2618 struct ieee80211_conf *conf = &hw->conf;
fad95bf5 2619 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
4808368d
AK		 2620 unsigned long flags = 0;
2621 int ret = 0;
2622 u16 ch;
2623 int scan_active = 0;
2624
2625 mutex_lock(&priv->mutex);
2626
4808368d
AK		 2627 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2628 conf->channel->hw_value, changed);
2629
2630 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2631 test_bit(STATUS_SCANNING, &priv->status))) {
2632 scan_active = 1;
2633 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2634 }
2635
2636
2637 /* during scanning mac80211 will delay channel setting until
2638 * scan finish with changed = 0
2639 */
2640 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2641 if (scan_active)
2642 goto set_ch_out;
2643
2644 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2645 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2646 if (!is_channel_valid(ch_info)) {
2647 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2648 ret = -EINVAL;
2649 goto set_ch_out;
2650 }
2651
2652 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2653 !is_channel_ibss(ch_info)) {
2654 IWL_ERR(priv, "channel %d in band %d not "
2655 "IBSS channel\n",
2656 conf->channel->hw_value, conf->channel->band);
2657 ret = -EINVAL;
2658 goto set_ch_out;
2659 }
2660
4a56e965
WYG		 2661 if (iwl_is_associated(priv) &&
2662 (le16_to_cpu(priv->active_rxon.channel) != ch) &&
2663 priv->cfg->ops->lib->set_channel_switch) {
2664 ret = priv->cfg->ops->lib->set_channel_switch(priv,
2665 ch);
2666 goto out;
2667 }
2668
4808368d
AK		 2669 spin_lock_irqsave(&priv->lock, flags);
2670
28bd723b
DH		 2671 /* Configure HT40 channels */
2672 ht_conf->is_ht = conf_is_ht(conf);
2673 if (ht_conf->is_ht) {
2674 if (conf_is_ht40_minus(conf)) {
2675 ht_conf->extension_chan_offset =
2676 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
c812ee24 2677 ht_conf->is_40mhz = true;
28bd723b
DH		 2678 } else if (conf_is_ht40_plus(conf)) {
2679 ht_conf->extension_chan_offset =
2680 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
c812ee24 2681 ht_conf->is_40mhz = true;
28bd723b
DH		 2682 } else {
2683 ht_conf->extension_chan_offset =
2684 IEEE80211_HT_PARAM_CHA_SEC_NONE;
c812ee24 2685 ht_conf->is_40mhz = false;
28bd723b
DH		 2686 }
2687 } else
c812ee24 2688 ht_conf->is_40mhz = false;
28bd723b
DH		 2689 /* Default to no protection. Protection mode will later be set
2690 * from BSS config in iwl_ht_conf */
2691 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2692
2693 /* if we are switching from ht to 2.4 clear flags
2694 * from any ht related info since 2.4 does not
2695 * support ht */
2696 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2697 priv->staging_rxon.flags = 0;
2698
2699 iwl_set_rxon_channel(priv, conf->channel);
2700
2701 iwl_set_flags_for_band(priv, conf->channel->band);
2702 spin_unlock_irqrestore(&priv->lock, flags);
2703 set_ch_out:
2704 /* The list of supported rates and rate mask can be different
2705 * for each band; since the band may have changed, reset
2706 * the rate mask to what mac80211 lists */
2707 iwl_set_rate(priv);
2708 }
2709
78f5fb7f
JB		 2710 if (changed & (IEEE80211_CONF_CHANGE_PS |
2711 IEEE80211_CONF_CHANGE_IDLE)) {
e312c24c 2712 ret = iwl_power_update_mode(priv, false);
4808368d 2713 if (ret)
e312c24c 2714 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2715 }
2716
2717 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2718 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2719 priv->tx_power_user_lmt, conf->power_level);
2720
2721 iwl_set_tx_power(priv, conf->power_level, false);
2722 }
2723
2724 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2725 if (priv->cfg->ops->hcmd->set_rxon_chain)
2726 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2727
0cf4c01e
MA		 2728 if (!iwl_is_ready(priv)) {
2729 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2730 goto out;
2731 }
2732
4808368d
AK		 2733 if (scan_active)
2734 goto out;
2735
2736 if (memcmp(&priv->active_rxon,
2737 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2738 iwlcore_commit_rxon(priv);
2739 else
2740 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2741
2742
2743out:
2744 IWL_DEBUG_MAC80211(priv, "leave\n");
2745 mutex_unlock(&priv->mutex);
2746 return ret;
2747}
2748EXPORT_SYMBOL(iwl_mac_config);
2749
aa89f31e
AK		 2750int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2751 struct ieee80211_tx_queue_stats *stats)
2752{
2753 struct iwl_priv *priv = hw->priv;
2754 int i, avail;
2755 struct iwl_tx_queue *txq;
2756 struct iwl_queue *q;
2757 unsigned long flags;
2758
2759 IWL_DEBUG_MAC80211(priv, "enter\n");
2760
2761 if (!iwl_is_ready_rf(priv)) {
2762 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2763 return -EIO;
2764 }
2765
2766 spin_lock_irqsave(&priv->lock, flags);
2767
2768 for (i = 0; i < AC_NUM; i++) {
2769 txq = &priv->txq[i];
2770 q = &txq->q;
2771 avail = iwl_queue_space(q);
2772
2773 stats[i].len = q->n_window - avail;
2774 stats[i].limit = q->n_window - q->high_mark;
2775 stats[i].count = q->n_window;
2776
2777 }
2778 spin_unlock_irqrestore(&priv->lock, flags);
2779
2780 IWL_DEBUG_MAC80211(priv, "leave\n");
2781
2782 return 0;
2783}
2784EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2785
bd564261
AK		 2786void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2787{
2788 struct iwl_priv *priv = hw->priv;
2789 unsigned long flags;
2790
2791 mutex_lock(&priv->mutex);
2792 IWL_DEBUG_MAC80211(priv, "enter\n");
2793
2794 spin_lock_irqsave(&priv->lock, flags);
fad95bf5 2795 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
bd564261
AK		 2796 spin_unlock_irqrestore(&priv->lock, flags);
2797
2798 iwl_reset_qos(priv);
2799
2800 spin_lock_irqsave(&priv->lock, flags);
2801 priv->assoc_id = 0;
2802 priv->assoc_capability = 0;
2803 priv->assoc_station_added = 0;
2804
2805 /* new association get rid of ibss beacon skb */
2806 if (priv->ibss_beacon)
2807 dev_kfree_skb(priv->ibss_beacon);
2808
2809 priv->ibss_beacon = NULL;
2810
57c4d7b4 2811 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2812 priv->timestamp = 0;
2813 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2814 priv->beacon_int = 0;
2815
2816 spin_unlock_irqrestore(&priv->lock, flags);
2817
2818 if (!iwl_is_ready_rf(priv)) {
2819 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2820 mutex_unlock(&priv->mutex);
2821 return;
2822 }
2823
2824 /* we are restarting association process
2825 * clear RXON_FILTER_ASSOC_MSK bit
2826 */
2827 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2828 iwl_scan_cancel_timeout(priv, 100);
2829 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2830 iwlcore_commit_rxon(priv);
2831 }
2832
bd564261 2833 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2834 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2835 mutex_unlock(&priv->mutex);
2836 return;
2837 }
2838
2839 iwl_set_rate(priv);
2840
2841 mutex_unlock(&priv->mutex);
2842
2843 IWL_DEBUG_MAC80211(priv, "leave\n");
2844}
2845EXPORT_SYMBOL(iwl_mac_reset_tsf);
2846
88804e2b
WYG		 2847int iwl_alloc_txq_mem(struct iwl_priv *priv)
2848{
2849 if (!priv->txq)
2850 priv->txq = kzalloc(
2851 sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
2852 GFP_KERNEL);
2853 if (!priv->txq) {
2854 IWL_ERR(priv, "Not enough memory for txq \n");
2855 return -ENOMEM;
2856 }
2857 return 0;
2858}
2859EXPORT_SYMBOL(iwl_alloc_txq_mem);
2860
2861void iwl_free_txq_mem(struct iwl_priv *priv)
2862{
2863 kfree(priv->txq);
2864 priv->txq = NULL;
2865}
2866EXPORT_SYMBOL(iwl_free_txq_mem);
2867
20594eb0
WYG		 2868#ifdef CONFIG_IWLWIFI_DEBUGFS
2869
2870#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2871
2872void iwl_reset_traffic_log(struct iwl_priv *priv)
2873{
2874 priv->tx_traffic_idx = 0;
2875 priv->rx_traffic_idx = 0;
2876 if (priv->tx_traffic)
2877 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2878 if (priv->rx_traffic)
2879 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2880}
2881
2882int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2883{
2884 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2885
2886 if (iwl_debug_level & IWL_DL_TX) {
2887 if (!priv->tx_traffic) {
2888 priv->tx_traffic =
2889 kzalloc(traffic_size, GFP_KERNEL);
2890 if (!priv->tx_traffic)
2891 return -ENOMEM;
2892 }
2893 }
2894 if (iwl_debug_level & IWL_DL_RX) {
2895 if (!priv->rx_traffic) {
2896 priv->rx_traffic =
2897 kzalloc(traffic_size, GFP_KERNEL);
2898 if (!priv->rx_traffic)
2899 return -ENOMEM;
2900 }
2901 }
2902 iwl_reset_traffic_log(priv);
2903 return 0;
2904}
2905EXPORT_SYMBOL(iwl_alloc_traffic_mem);
2906
2907void iwl_free_traffic_mem(struct iwl_priv *priv)
2908{
2909 kfree(priv->tx_traffic);
2910 priv->tx_traffic = NULL;
2911
2912 kfree(priv->rx_traffic);
2913 priv->rx_traffic = NULL;
2914}
2915EXPORT_SYMBOL(iwl_free_traffic_mem);
2916
2917void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
2918 u16 length, struct ieee80211_hdr *header)
2919{
2920 __le16 fc;
2921 u16 len;
2922
2923 if (likely(!(iwl_debug_level & IWL_DL_TX)))
2924 return;
2925
2926 if (!priv->tx_traffic)
2927 return;
2928
2929 fc = header->frame_control;
2930 if (ieee80211_is_data(fc)) {
2931 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
2932 ? IWL_TRAFFIC_ENTRY_SIZE : length;
2933 memcpy((priv->tx_traffic +
2934 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
2935 header, len);
2936 priv->tx_traffic_idx =
2937 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
2938 }
2939}
2940EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
2941
2942void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
2943 u16 length, struct ieee80211_hdr *header)
2944{
2945 __le16 fc;
2946 u16 len;
2947
2948 if (likely(!(iwl_debug_level & IWL_DL_RX)))
2949 return;
2950
2951 if (!priv->rx_traffic)
2952 return;
2953
2954 fc = header->frame_control;
2955 if (ieee80211_is_data(fc)) {
2956 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
2957 ? IWL_TRAFFIC_ENTRY_SIZE : length;
2958 memcpy((priv->rx_traffic +
2959 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
2960 header, len);
2961 priv->rx_traffic_idx =
2962 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
2963 }
2964}
2965EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 2966
2967const char *get_mgmt_string(int cmd)
2968{
2969 switch (cmd) {
2970 IWL_CMD(MANAGEMENT_ASSOC_REQ);
2971 IWL_CMD(MANAGEMENT_ASSOC_RESP);
2972 IWL_CMD(MANAGEMENT_REASSOC_REQ);
2973 IWL_CMD(MANAGEMENT_REASSOC_RESP);
2974 IWL_CMD(MANAGEMENT_PROBE_REQ);
2975 IWL_CMD(MANAGEMENT_PROBE_RESP);
2976 IWL_CMD(MANAGEMENT_BEACON);
2977 IWL_CMD(MANAGEMENT_ATIM);
2978 IWL_CMD(MANAGEMENT_DISASSOC);
2979 IWL_CMD(MANAGEMENT_AUTH);
2980 IWL_CMD(MANAGEMENT_DEAUTH);
2981 IWL_CMD(MANAGEMENT_ACTION);
2982 default:
2983 return "UNKNOWN";
2984
2985 }
2986}
2987
2988const char *get_ctrl_string(int cmd)
2989{
2990 switch (cmd) {
2991 IWL_CMD(CONTROL_BACK_REQ);
2992 IWL_CMD(CONTROL_BACK);
2993 IWL_CMD(CONTROL_PSPOLL);
2994 IWL_CMD(CONTROL_RTS);
2995 IWL_CMD(CONTROL_CTS);
2996 IWL_CMD(CONTROL_ACK);
2997 IWL_CMD(CONTROL_CFEND);
2998 IWL_CMD(CONTROL_CFENDACK);
2999 default:
3000 return "UNKNOWN";
3001
3002 }
3003}
3004
3005void iwl_clear_tx_stats(struct iwl_priv *priv)
3006{
3007 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
3008
3009}
3010
3011void iwl_clear_rx_stats(struct iwl_priv *priv)
3012{
3013 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
3014}
3015
3016/*
3017 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3018 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3019 * Use debugFs to display the rx/rx_statistics
3020 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3021 * information will be recorded, but DATA pkt still will be recorded
3022 * for the reason of iwl_led.c need to control the led blinking based on
3023 * number of tx and rx data.
3024 *
3025 */
3026void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3027{
3028 struct traffic_stats *stats;
3029
3030 if (is_tx)
3031 stats = &priv->tx_stats;
3032 else
3033 stats = &priv->rx_stats;
3034
3035 if (ieee80211_is_mgmt(fc)) {
3036 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3037 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3038 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3039 break;
3040 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3041 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3042 break;
3043 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3044 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3045 break;
3046 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3047 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3048 break;
3049 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3050 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3051 break;
3052 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3053 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3054 break;
3055 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3056 stats->mgmt[MANAGEMENT_BEACON]++;
3057 break;
3058 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3059 stats->mgmt[MANAGEMENT_ATIM]++;
3060 break;
3061 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3062 stats->mgmt[MANAGEMENT_DISASSOC]++;
3063 break;
3064 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3065 stats->mgmt[MANAGEMENT_AUTH]++;
3066 break;
3067 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3068 stats->mgmt[MANAGEMENT_DEAUTH]++;
3069 break;
3070 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3071 stats->mgmt[MANAGEMENT_ACTION]++;
3072 break;
3073 }
3074 } else if (ieee80211_is_ctl(fc)) {
3075 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3076 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3077 stats->ctrl[CONTROL_BACK_REQ]++;
3078 break;
3079 case cpu_to_le16(IEEE80211_STYPE_BACK):
3080 stats->ctrl[CONTROL_BACK]++;
3081 break;
3082 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3083 stats->ctrl[CONTROL_PSPOLL]++;
3084 break;
3085 case cpu_to_le16(IEEE80211_STYPE_RTS):
3086 stats->ctrl[CONTROL_RTS]++;
3087 break;
3088 case cpu_to_le16(IEEE80211_STYPE_CTS):
3089 stats->ctrl[CONTROL_CTS]++;
3090 break;
3091 case cpu_to_le16(IEEE80211_STYPE_ACK):
3092 stats->ctrl[CONTROL_ACK]++;
3093 break;
3094 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3095 stats->ctrl[CONTROL_CFEND]++;
3096 break;
3097 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3098 stats->ctrl[CONTROL_CFENDACK]++;
3099 break;
3100 }
3101 } else {
3102 /* data */
3103 stats->data_cnt++;
3104 stats->data_bytes += len;
3105 }
3106}
3107EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3108#endif
3109
6da3a13e
WYG		 3110#ifdef CONFIG_PM
3111
3112int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3113{
3114 struct iwl_priv *priv = pci_get_drvdata(pdev);
3115
3116 /*
3117 * This function is called when system goes into suspend state
3118 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3119 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3120 * it will not call apm_ops.stop() to stop the DMA operation.
3121 * Calling apm_ops.stop here to make sure we stop the DMA.
3122 */
3123 priv->cfg->ops->lib->apm_ops.stop(priv);
3124
3125 pci_save_state(pdev);
3126 pci_disable_device(pdev);
3127 pci_set_power_state(pdev, PCI_D3hot);
3128
3129 return 0;
3130}
3131EXPORT_SYMBOL(iwl_pci_suspend);
3132
3133int iwl_pci_resume(struct pci_dev *pdev)
3134{
3135 struct iwl_priv *priv = pci_get_drvdata(pdev);
3136 int ret;
3137
3138 pci_set_power_state(pdev, PCI_D0);
3139 ret = pci_enable_device(pdev);
3140 if (ret)
3141 return ret;
3142 pci_restore_state(pdev);
3143 iwl_enable_interrupts(priv);
3144
3145 return 0;
3146}
3147EXPORT_SYMBOL(iwl_pci_resume);
3148
3149#endif /* CONFIG_PM */
Linux kernel - Deliverables
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