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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
5 | * Copyright(c) 2008 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Tomas Winkler <tomas.winkler@intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/version.h> | |
1d0a082d | 32 | #include <net/mac80211.h> |
df48c323 | 33 | |
712b6cf5 | 34 | struct iwl_priv; /* FIXME: remove */ |
0a6857e7 | 35 | #include "iwl-debug.h" |
6bc913bd | 36 | #include "iwl-eeprom.h" |
3e0d4cb1 | 37 | #include "iwl-dev.h" /* FIXME: remove */ |
df48c323 | 38 | #include "iwl-core.h" |
b661c819 | 39 | #include "iwl-io.h" |
ad97edd2 | 40 | #include "iwl-rfkill.h" |
5da4b55f | 41 | #include "iwl-power.h" |
df48c323 | 42 | |
1d0a082d | 43 | |
df48c323 TW |
44 | MODULE_DESCRIPTION("iwl core"); |
45 | MODULE_VERSION(IWLWIFI_VERSION); | |
46 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
712b6cf5 | 47 | MODULE_LICENSE("GPL"); |
df48c323 | 48 | |
c7de35cd RR |
49 | #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ |
50 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ | |
51 | IWL_RATE_SISO_##s##M_PLCP, \ | |
52 | IWL_RATE_MIMO2_##s##M_PLCP,\ | |
53 | IWL_RATE_MIMO3_##s##M_PLCP,\ | |
54 | IWL_RATE_##r##M_IEEE, \ | |
55 | IWL_RATE_##ip##M_INDEX, \ | |
56 | IWL_RATE_##in##M_INDEX, \ | |
57 | IWL_RATE_##rp##M_INDEX, \ | |
58 | IWL_RATE_##rn##M_INDEX, \ | |
59 | IWL_RATE_##pp##M_INDEX, \ | |
60 | IWL_RATE_##np##M_INDEX } | |
61 | ||
62 | /* | |
63 | * Parameter order: | |
64 | * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate | |
65 | * | |
66 | * If there isn't a valid next or previous rate then INV is used which | |
67 | * maps to IWL_RATE_INVALID | |
68 | * | |
69 | */ | |
1826dcc0 | 70 | const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { |
c7de35cd RR |
71 | IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
72 | IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */ | |
73 | IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */ | |
74 | IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */ | |
75 | IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */ | |
76 | IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */ | |
77 | IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */ | |
78 | IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */ | |
79 | IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */ | |
80 | IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */ | |
81 | IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */ | |
82 | IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */ | |
83 | IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */ | |
84 | /* FIXME:RS: ^^ should be INV (legacy) */ | |
85 | }; | |
1826dcc0 | 86 | EXPORT_SYMBOL(iwl_rates); |
c7de35cd | 87 | |
57bd1bea TW |
88 | |
89 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; | |
90 | EXPORT_SYMBOL(iwl_bcast_addr); | |
91 | ||
92 | ||
1d0a082d AK |
93 | /* This function both allocates and initializes hw and priv. */ |
94 | struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, | |
95 | struct ieee80211_ops *hw_ops) | |
96 | { | |
97 | struct iwl_priv *priv; | |
98 | ||
99 | /* mac80211 allocates memory for this device instance, including | |
100 | * space for this driver's private structure */ | |
101 | struct ieee80211_hw *hw = | |
102 | ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops); | |
103 | if (hw == NULL) { | |
104 | IWL_ERROR("Can not allocate network device\n"); | |
105 | goto out; | |
106 | } | |
107 | ||
108 | priv = hw->priv; | |
109 | priv->hw = hw; | |
110 | ||
111 | out: | |
112 | return hw; | |
113 | } | |
114 | EXPORT_SYMBOL(iwl_alloc_all); | |
115 | ||
b661c819 TW |
116 | void iwl_hw_detect(struct iwl_priv *priv) |
117 | { | |
118 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); | |
119 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); | |
120 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); | |
121 | } | |
122 | EXPORT_SYMBOL(iwl_hw_detect); | |
123 | ||
1053d35f RR |
124 | /* Tell nic where to find the "keep warm" buffer */ |
125 | int iwl_kw_init(struct iwl_priv *priv) | |
126 | { | |
127 | unsigned long flags; | |
128 | int ret; | |
129 | ||
130 | spin_lock_irqsave(&priv->lock, flags); | |
131 | ret = iwl_grab_nic_access(priv); | |
132 | if (ret) | |
133 | goto out; | |
134 | ||
135 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, | |
136 | priv->kw.dma_addr >> 4); | |
137 | iwl_release_nic_access(priv); | |
138 | out: | |
139 | spin_unlock_irqrestore(&priv->lock, flags); | |
140 | return ret; | |
141 | } | |
142 | ||
143 | int iwl_kw_alloc(struct iwl_priv *priv) | |
144 | { | |
145 | struct pci_dev *dev = priv->pci_dev; | |
16466903 | 146 | struct iwl_kw *kw = &priv->kw; |
1053d35f | 147 | |
16466903 | 148 | kw->size = IWL_KW_SIZE; |
1053d35f RR |
149 | kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr); |
150 | if (!kw->v_addr) | |
151 | return -ENOMEM; | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | /** | |
157 | * iwl_kw_free - Free the "keep warm" buffer | |
158 | */ | |
159 | void iwl_kw_free(struct iwl_priv *priv) | |
160 | { | |
161 | struct pci_dev *dev = priv->pci_dev; | |
16466903 | 162 | struct iwl_kw *kw = &priv->kw; |
1053d35f RR |
163 | |
164 | if (kw->v_addr) { | |
165 | pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr); | |
166 | memset(kw, 0, sizeof(*kw)); | |
167 | } | |
168 | } | |
169 | ||
170 | int iwl_hw_nic_init(struct iwl_priv *priv) | |
171 | { | |
172 | unsigned long flags; | |
173 | struct iwl_rx_queue *rxq = &priv->rxq; | |
174 | int ret; | |
175 | ||
176 | /* nic_init */ | |
1053d35f | 177 | spin_lock_irqsave(&priv->lock, flags); |
1b73af82 | 178 | priv->cfg->ops->lib->apm_ops.init(priv); |
1053d35f RR |
179 | iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); |
180 | spin_unlock_irqrestore(&priv->lock, flags); | |
181 | ||
182 | ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); | |
183 | ||
184 | priv->cfg->ops->lib->apm_ops.config(priv); | |
185 | ||
186 | /* Allocate the RX queue, or reset if it is already allocated */ | |
187 | if (!rxq->bd) { | |
188 | ret = iwl_rx_queue_alloc(priv); | |
189 | if (ret) { | |
190 | IWL_ERROR("Unable to initialize Rx queue\n"); | |
191 | return -ENOMEM; | |
192 | } | |
193 | } else | |
194 | iwl_rx_queue_reset(priv, rxq); | |
195 | ||
196 | iwl_rx_replenish(priv); | |
197 | ||
198 | iwl_rx_init(priv, rxq); | |
199 | ||
200 | spin_lock_irqsave(&priv->lock, flags); | |
201 | ||
202 | rxq->need_update = 1; | |
203 | iwl_rx_queue_update_write_ptr(priv, rxq); | |
204 | ||
205 | spin_unlock_irqrestore(&priv->lock, flags); | |
206 | ||
207 | /* Allocate and init all Tx and Command queues */ | |
208 | ret = iwl_txq_ctx_reset(priv); | |
209 | if (ret) | |
210 | return ret; | |
211 | ||
212 | set_bit(STATUS_INIT, &priv->status); | |
213 | ||
214 | return 0; | |
215 | } | |
216 | EXPORT_SYMBOL(iwl_hw_nic_init); | |
217 | ||
bf85ea4f AK |
218 | /** |
219 | * iwlcore_clear_stations_table - Clear the driver's station table | |
220 | * | |
221 | * NOTE: This does not clear or otherwise alter the device's station table. | |
222 | */ | |
223 | void iwlcore_clear_stations_table(struct iwl_priv *priv) | |
224 | { | |
225 | unsigned long flags; | |
226 | ||
227 | spin_lock_irqsave(&priv->sta_lock, flags); | |
228 | ||
229 | priv->num_stations = 0; | |
230 | memset(priv->stations, 0, sizeof(priv->stations)); | |
231 | ||
232 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
233 | } | |
234 | EXPORT_SYMBOL(iwlcore_clear_stations_table); | |
235 | ||
c7de35cd | 236 | void iwl_reset_qos(struct iwl_priv *priv) |
bf85ea4f AK |
237 | { |
238 | u16 cw_min = 15; | |
239 | u16 cw_max = 1023; | |
240 | u8 aifs = 2; | |
241 | u8 is_legacy = 0; | |
242 | unsigned long flags; | |
243 | int i; | |
244 | ||
245 | spin_lock_irqsave(&priv->lock, flags); | |
246 | priv->qos_data.qos_active = 0; | |
247 | ||
248 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) { | |
249 | if (priv->qos_data.qos_enable) | |
250 | priv->qos_data.qos_active = 1; | |
251 | if (!(priv->active_rate & 0xfff0)) { | |
252 | cw_min = 31; | |
253 | is_legacy = 1; | |
254 | } | |
255 | } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
256 | if (priv->qos_data.qos_enable) | |
257 | priv->qos_data.qos_active = 1; | |
258 | } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) { | |
259 | cw_min = 31; | |
260 | is_legacy = 1; | |
261 | } | |
262 | ||
263 | if (priv->qos_data.qos_active) | |
264 | aifs = 3; | |
265 | ||
266 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); | |
267 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
268 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
269 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
270 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
271 | ||
272 | if (priv->qos_data.qos_active) { | |
273 | i = 1; | |
274 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
275 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
276 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
277 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
278 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
279 | ||
280 | i = 2; | |
281 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
282 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
283 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
284 | cpu_to_le16(cw_max); | |
285 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
286 | if (is_legacy) | |
287 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
288 | cpu_to_le16(6016); | |
289 | else | |
290 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
291 | cpu_to_le16(3008); | |
292 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
293 | ||
294 | i = 3; | |
295 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
296 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
297 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
298 | cpu_to_le16((cw_max + 1) / 2 - 1); | |
299 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
300 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
301 | if (is_legacy) | |
302 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
303 | cpu_to_le16(3264); | |
304 | else | |
305 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
306 | cpu_to_le16(1504); | |
307 | } else { | |
308 | for (i = 1; i < 4; i++) { | |
309 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
310 | cpu_to_le16(cw_min); | |
311 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
312 | cpu_to_le16(cw_max); | |
313 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
314 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
315 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
316 | } | |
317 | } | |
318 | IWL_DEBUG_QOS("set QoS to default \n"); | |
319 | ||
320 | spin_unlock_irqrestore(&priv->lock, flags); | |
321 | } | |
c7de35cd RR |
322 | EXPORT_SYMBOL(iwl_reset_qos); |
323 | ||
324 | #ifdef CONFIG_IWL4965_HT | |
39130df3 RR |
325 | #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */ |
326 | #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */ | |
c7de35cd RR |
327 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
328 | struct ieee80211_ht_info *ht_info, | |
329 | enum ieee80211_band band) | |
330 | { | |
39130df3 RR |
331 | u16 max_bit_rate = 0; |
332 | u8 rx_chains_num = priv->hw_params.rx_chains_num; | |
333 | u8 tx_chains_num = priv->hw_params.tx_chains_num; | |
334 | ||
c7de35cd RR |
335 | ht_info->cap = 0; |
336 | memset(ht_info->supp_mcs_set, 0, 16); | |
337 | ||
338 | ht_info->ht_supported = 1; | |
339 | ||
39130df3 RR |
340 | ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD; |
341 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20; | |
342 | ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS & | |
343 | (IWL_MIMO_PS_NONE << 2)); | |
344 | ||
345 | max_bit_rate = MAX_BIT_RATE_20_MHZ; | |
c7de35cd RR |
346 | if (priv->hw_params.fat_channel & BIT(band)) { |
347 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH; | |
348 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40; | |
349 | ht_info->supp_mcs_set[4] = 0x01; | |
39130df3 | 350 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 351 | } |
c7de35cd RR |
352 | |
353 | if (priv->cfg->mod_params->amsdu_size_8K) | |
354 | ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU; | |
355 | ||
356 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
357 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
358 | ||
359 | ht_info->supp_mcs_set[0] = 0xFF; | |
39130df3 | 360 | if (rx_chains_num >= 2) |
c7de35cd | 361 | ht_info->supp_mcs_set[1] = 0xFF; |
39130df3 | 362 | if (rx_chains_num >= 3) |
c7de35cd | 363 | ht_info->supp_mcs_set[2] = 0xFF; |
39130df3 RR |
364 | |
365 | /* Highest supported Rx data rate */ | |
366 | max_bit_rate *= rx_chains_num; | |
367 | ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF); | |
368 | ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8); | |
369 | ||
370 | /* Tx MCS capabilities */ | |
371 | ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED; | |
372 | if (tx_chains_num != rx_chains_num) { | |
373 | ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF; | |
374 | ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2); | |
375 | } | |
c7de35cd | 376 | } |
88787d28 AM |
377 | #else |
378 | static inline void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, | |
379 | struct ieee80211_ht_info *ht_info, | |
380 | enum ieee80211_band band) | |
381 | { | |
382 | } | |
c7de35cd RR |
383 | #endif /* CONFIG_IWL4965_HT */ |
384 | ||
385 | static void iwlcore_init_hw_rates(struct iwl_priv *priv, | |
386 | struct ieee80211_rate *rates) | |
387 | { | |
388 | int i; | |
389 | ||
390 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
1826dcc0 | 391 | rates[i].bitrate = iwl_rates[i].ieee * 5; |
c7de35cd RR |
392 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ |
393 | rates[i].hw_value_short = i; | |
394 | rates[i].flags = 0; | |
395 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
396 | /* | |
397 | * If CCK != 1M then set short preamble rate flag. | |
398 | */ | |
399 | rates[i].flags |= | |
1826dcc0 | 400 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? |
c7de35cd RR |
401 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
402 | } | |
403 | } | |
404 | } | |
405 | ||
406 | /** | |
407 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom | |
408 | */ | |
409 | static int iwlcore_init_geos(struct iwl_priv *priv) | |
410 | { | |
411 | struct iwl_channel_info *ch; | |
412 | struct ieee80211_supported_band *sband; | |
413 | struct ieee80211_channel *channels; | |
414 | struct ieee80211_channel *geo_ch; | |
415 | struct ieee80211_rate *rates; | |
416 | int i = 0; | |
417 | ||
418 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
419 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
420 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); | |
421 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
422 | return 0; | |
423 | } | |
424 | ||
425 | channels = kzalloc(sizeof(struct ieee80211_channel) * | |
426 | priv->channel_count, GFP_KERNEL); | |
427 | if (!channels) | |
428 | return -ENOMEM; | |
429 | ||
430 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), | |
431 | GFP_KERNEL); | |
432 | if (!rates) { | |
433 | kfree(channels); | |
434 | return -ENOMEM; | |
435 | } | |
436 | ||
437 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
438 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
439 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
440 | /* just OFDM */ | |
441 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
442 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
443 | ||
444 | iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ); | |
445 | ||
446 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
447 | sband->channels = channels; | |
448 | /* OFDM & CCK */ | |
449 | sband->bitrates = rates; | |
450 | sband->n_bitrates = IWL_RATE_COUNT; | |
451 | ||
452 | iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ); | |
453 | ||
454 | priv->ieee_channels = channels; | |
455 | priv->ieee_rates = rates; | |
456 | ||
457 | iwlcore_init_hw_rates(priv, rates); | |
458 | ||
459 | for (i = 0; i < priv->channel_count; i++) { | |
460 | ch = &priv->channel_info[i]; | |
461 | ||
462 | /* FIXME: might be removed if scan is OK */ | |
463 | if (!is_channel_valid(ch)) | |
464 | continue; | |
465 | ||
466 | if (is_channel_a_band(ch)) | |
467 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
468 | else | |
469 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
470 | ||
471 | geo_ch = &sband->channels[sband->n_channels++]; | |
472 | ||
473 | geo_ch->center_freq = | |
474 | ieee80211_channel_to_frequency(ch->channel); | |
475 | geo_ch->max_power = ch->max_power_avg; | |
476 | geo_ch->max_antenna_gain = 0xff; | |
477 | geo_ch->hw_value = ch->channel; | |
478 | ||
479 | if (is_channel_valid(ch)) { | |
480 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
481 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
482 | ||
483 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
484 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
485 | ||
486 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
487 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
488 | ||
489 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
490 | priv->max_channel_txpower_limit = | |
491 | ch->max_power_avg; | |
492 | } else { | |
493 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
494 | } | |
495 | ||
496 | /* Save flags for reg domain usage */ | |
497 | geo_ch->orig_flags = geo_ch->flags; | |
498 | ||
499 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
500 | ch->channel, geo_ch->center_freq, | |
501 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
502 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
503 | "restricted" : "valid", | |
504 | geo_ch->flags); | |
505 | } | |
506 | ||
507 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && | |
508 | priv->cfg->sku & IWL_SKU_A) { | |
509 | printk(KERN_INFO DRV_NAME | |
510 | ": Incorrectly detected BG card as ABG. Please send " | |
511 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
512 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
513 | priv->cfg->sku &= ~IWL_SKU_A; | |
514 | } | |
515 | ||
516 | printk(KERN_INFO DRV_NAME | |
517 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
518 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, | |
519 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
520 | ||
521 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
522 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
523 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
524 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
525 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
526 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
527 | ||
528 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
533 | /* | |
534 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos | |
535 | */ | |
536 | void iwlcore_free_geos(struct iwl_priv *priv) | |
537 | { | |
538 | kfree(priv->ieee_channels); | |
539 | kfree(priv->ieee_rates); | |
540 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
541 | } | |
542 | EXPORT_SYMBOL(iwlcore_free_geos); | |
543 | ||
544 | #ifdef CONFIG_IWL4965_HT | |
545 | static u8 is_single_rx_stream(struct iwl_priv *priv) | |
546 | { | |
547 | return !priv->current_ht_config.is_ht || | |
548 | ((priv->current_ht_config.supp_mcs_set[1] == 0) && | |
549 | (priv->current_ht_config.supp_mcs_set[2] == 0)) || | |
550 | priv->ps_mode == IWL_MIMO_PS_STATIC; | |
551 | } | |
47c5196e TW |
552 | static u8 iwl_is_channel_extension(struct iwl_priv *priv, |
553 | enum ieee80211_band band, | |
554 | u16 channel, u8 extension_chan_offset) | |
555 | { | |
556 | const struct iwl_channel_info *ch_info; | |
557 | ||
558 | ch_info = iwl_get_channel_info(priv, band, channel); | |
559 | if (!is_channel_valid(ch_info)) | |
560 | return 0; | |
561 | ||
562 | if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE) | |
563 | return 0; | |
564 | ||
565 | if ((ch_info->fat_extension_channel == extension_chan_offset) || | |
566 | (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX)) | |
567 | return 1; | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv, | |
573 | struct ieee80211_ht_info *sta_ht_inf) | |
574 | { | |
575 | struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config; | |
576 | ||
577 | if ((!iwl_ht_conf->is_ht) || | |
578 | (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) || | |
579 | (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)) | |
580 | return 0; | |
581 | ||
582 | if (sta_ht_inf) { | |
583 | if ((!sta_ht_inf->ht_supported) || | |
584 | (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH))) | |
585 | return 0; | |
586 | } | |
587 | ||
588 | return iwl_is_channel_extension(priv, priv->band, | |
589 | iwl_ht_conf->control_channel, | |
590 | iwl_ht_conf->extension_chan_offset); | |
591 | } | |
592 | EXPORT_SYMBOL(iwl_is_fat_tx_allowed); | |
593 | ||
594 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info) | |
595 | { | |
c1adf9fb | 596 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
47c5196e TW |
597 | u32 val; |
598 | ||
599 | if (!ht_info->is_ht) | |
600 | return; | |
601 | ||
602 | /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */ | |
603 | if (iwl_is_fat_tx_allowed(priv, NULL)) | |
604 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK; | |
605 | else | |
606 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | | |
607 | RXON_FLG_CHANNEL_MODE_PURE_40_MSK); | |
608 | ||
609 | if (le16_to_cpu(rxon->channel) != ht_info->control_channel) { | |
610 | IWL_DEBUG_ASSOC("control diff than current %d %d\n", | |
611 | le16_to_cpu(rxon->channel), | |
612 | ht_info->control_channel); | |
613 | rxon->channel = cpu_to_le16(ht_info->control_channel); | |
614 | return; | |
615 | } | |
616 | ||
617 | /* Note: control channel is opposite of extension channel */ | |
618 | switch (ht_info->extension_chan_offset) { | |
619 | case IWL_EXT_CHANNEL_OFFSET_ABOVE: | |
620 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
621 | break; | |
622 | case IWL_EXT_CHANNEL_OFFSET_BELOW: | |
623 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
624 | break; | |
625 | case IWL_EXT_CHANNEL_OFFSET_NONE: | |
626 | default: | |
627 | rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK; | |
628 | break; | |
629 | } | |
630 | ||
631 | val = ht_info->ht_protection; | |
632 | ||
633 | rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS); | |
634 | ||
635 | iwl_set_rxon_chain(priv); | |
636 | ||
637 | IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X " | |
638 | "rxon flags 0x%X operation mode :0x%X " | |
639 | "extension channel offset 0x%x " | |
640 | "control chan %d\n", | |
641 | ht_info->supp_mcs_set[0], | |
642 | ht_info->supp_mcs_set[1], | |
643 | ht_info->supp_mcs_set[2], | |
644 | le32_to_cpu(rxon->flags), ht_info->ht_protection, | |
645 | ht_info->extension_chan_offset, | |
646 | ht_info->control_channel); | |
647 | return; | |
648 | } | |
649 | EXPORT_SYMBOL(iwl_set_rxon_ht); | |
650 | ||
c7de35cd RR |
651 | #else |
652 | static inline u8 is_single_rx_stream(struct iwl_priv *priv) | |
653 | { | |
654 | return 1; | |
655 | } | |
656 | #endif /*CONFIG_IWL4965_HT */ | |
657 | ||
658 | /* | |
659 | * Determine how many receiver/antenna chains to use. | |
660 | * More provides better reception via diversity. Fewer saves power. | |
661 | * MIMO (dual stream) requires at least 2, but works better with 3. | |
662 | * This does not determine *which* chains to use, just how many. | |
663 | */ | |
664 | static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv, | |
665 | u8 *idle_state, u8 *rx_state) | |
666 | { | |
667 | u8 is_single = is_single_rx_stream(priv); | |
668 | u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1; | |
669 | ||
670 | /* # of Rx chains to use when expecting MIMO. */ | |
671 | if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC))) | |
672 | *rx_state = 2; | |
673 | else | |
674 | *rx_state = 3; | |
675 | ||
676 | /* # Rx chains when idling and maybe trying to save power */ | |
677 | switch (priv->ps_mode) { | |
678 | case IWL_MIMO_PS_STATIC: | |
679 | case IWL_MIMO_PS_DYNAMIC: | |
680 | *idle_state = (is_cam) ? 2 : 1; | |
681 | break; | |
682 | case IWL_MIMO_PS_NONE: | |
683 | *idle_state = (is_cam) ? *rx_state : 1; | |
684 | break; | |
685 | default: | |
686 | *idle_state = 1; | |
687 | break; | |
688 | } | |
689 | ||
690 | return 0; | |
691 | } | |
692 | ||
693 | /** | |
694 | * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image | |
695 | * | |
696 | * Selects how many and which Rx receivers/antennas/chains to use. | |
697 | * This should not be used for scan command ... it puts data in wrong place. | |
698 | */ | |
699 | void iwl_set_rxon_chain(struct iwl_priv *priv) | |
700 | { | |
701 | u8 is_single = is_single_rx_stream(priv); | |
702 | u8 idle_state, rx_state; | |
703 | ||
704 | priv->staging_rxon.rx_chain = 0; | |
705 | rx_state = idle_state = 3; | |
706 | ||
707 | /* Tell uCode which antennas are actually connected. | |
708 | * Before first association, we assume all antennas are connected. | |
709 | * Just after first association, iwl_chain_noise_calibration() | |
710 | * checks which antennas actually *are* connected. */ | |
711 | priv->staging_rxon.rx_chain |= | |
712 | cpu_to_le16(priv->hw_params.valid_rx_ant << | |
713 | RXON_RX_CHAIN_VALID_POS); | |
714 | ||
715 | /* How many receivers should we use? */ | |
716 | iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state); | |
717 | priv->staging_rxon.rx_chain |= | |
718 | cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS); | |
719 | priv->staging_rxon.rx_chain |= | |
720 | cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS); | |
721 | ||
722 | if (!is_single && (rx_state >= 2) && | |
723 | !test_bit(STATUS_POWER_PMI, &priv->status)) | |
724 | priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
725 | else | |
726 | priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
727 | ||
728 | IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain); | |
729 | } | |
730 | EXPORT_SYMBOL(iwl_set_rxon_chain); | |
bf85ea4f AK |
731 | |
732 | /** | |
733 | * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON | |
734 | * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz | |
735 | * @channel: Any channel valid for the requested phymode | |
736 | ||
737 | * In addition to setting the staging RXON, priv->phymode is also set. | |
738 | * | |
739 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
740 | * in the staging RXON flag structure based on the phymode | |
741 | */ | |
c7de35cd | 742 | int iwl_set_rxon_channel(struct iwl_priv *priv, |
bf85ea4f AK |
743 | enum ieee80211_band band, |
744 | u16 channel) | |
745 | { | |
8622e705 | 746 | if (!iwl_get_channel_info(priv, band, channel)) { |
bf85ea4f AK |
747 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
748 | channel, band); | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && | |
753 | (priv->band == band)) | |
754 | return 0; | |
755 | ||
756 | priv->staging_rxon.channel = cpu_to_le16(channel); | |
757 | if (band == IEEE80211_BAND_5GHZ) | |
758 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; | |
759 | else | |
760 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
761 | ||
762 | priv->band = band; | |
763 | ||
764 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); | |
765 | ||
766 | return 0; | |
767 | } | |
c7de35cd | 768 | EXPORT_SYMBOL(iwl_set_rxon_channel); |
bf85ea4f AK |
769 | |
770 | static void iwlcore_init_hw(struct iwl_priv *priv) | |
771 | { | |
772 | struct ieee80211_hw *hw = priv->hw; | |
773 | hw->rate_control_algorithm = "iwl-4965-rs"; | |
774 | ||
566bfe5a BR |
775 | /* Tell mac80211 our characteristics */ |
776 | hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | | |
777 | IEEE80211_HW_SIGNAL_DBM | | |
778 | IEEE80211_HW_NOISE_DBM; | |
bf85ea4f AK |
779 | /* Default value; 4 EDCA QOS priorities */ |
780 | hw->queues = 4; | |
781 | #ifdef CONFIG_IWL4965_HT | |
782 | /* Enhanced value; more queues, to support 11n aggregation */ | |
e100bb64 | 783 | hw->ampdu_queues = 12; |
bf85ea4f AK |
784 | #endif /* CONFIG_IWL4965_HT */ |
785 | } | |
786 | ||
c7de35cd RR |
787 | static int iwlcore_init_drv(struct iwl_priv *priv) |
788 | { | |
789 | int ret; | |
790 | int i; | |
791 | ||
792 | priv->retry_rate = 1; | |
793 | priv->ibss_beacon = NULL; | |
794 | ||
795 | spin_lock_init(&priv->lock); | |
796 | spin_lock_init(&priv->power_data.lock); | |
797 | spin_lock_init(&priv->sta_lock); | |
798 | spin_lock_init(&priv->hcmd_lock); | |
799 | spin_lock_init(&priv->lq_mngr.lock); | |
800 | ||
801 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) | |
802 | INIT_LIST_HEAD(&priv->ibss_mac_hash[i]); | |
803 | ||
804 | INIT_LIST_HEAD(&priv->free_frames); | |
805 | ||
806 | mutex_init(&priv->mutex); | |
807 | ||
808 | /* Clear the driver's (not device's) station table */ | |
809 | iwlcore_clear_stations_table(priv); | |
810 | ||
811 | priv->data_retry_limit = -1; | |
812 | priv->ieee_channels = NULL; | |
813 | priv->ieee_rates = NULL; | |
814 | priv->band = IEEE80211_BAND_2GHZ; | |
815 | ||
816 | priv->iw_mode = IEEE80211_IF_TYPE_STA; | |
817 | ||
818 | priv->use_ant_b_for_management_frame = 1; /* start with ant B */ | |
819 | priv->ps_mode = IWL_MIMO_PS_NONE; | |
820 | ||
821 | /* Choose which receivers/antennas to use */ | |
822 | iwl_set_rxon_chain(priv); | |
823 | ||
824 | iwl_reset_qos(priv); | |
825 | ||
826 | priv->qos_data.qos_active = 0; | |
827 | priv->qos_data.qos_cap.val = 0; | |
828 | ||
829 | iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); | |
830 | ||
831 | priv->rates_mask = IWL_RATES_MASK; | |
832 | /* If power management is turned on, default to AC mode */ | |
833 | priv->power_mode = IWL_POWER_AC; | |
834 | priv->user_txpower_limit = IWL_DEFAULT_TX_POWER; | |
835 | ||
836 | ret = iwl_init_channel_map(priv); | |
837 | if (ret) { | |
838 | IWL_ERROR("initializing regulatory failed: %d\n", ret); | |
839 | goto err; | |
840 | } | |
841 | ||
842 | ret = iwlcore_init_geos(priv); | |
843 | if (ret) { | |
844 | IWL_ERROR("initializing geos failed: %d\n", ret); | |
845 | goto err_free_channel_map; | |
846 | } | |
847 | ||
848 | ret = ieee80211_register_hw(priv->hw); | |
849 | if (ret) { | |
850 | IWL_ERROR("Failed to register network device (error %d)\n", | |
851 | ret); | |
852 | goto err_free_geos; | |
853 | } | |
854 | ||
855 | priv->hw->conf.beacon_int = 100; | |
856 | priv->mac80211_registered = 1; | |
857 | ||
858 | return 0; | |
859 | ||
860 | err_free_geos: | |
861 | iwlcore_free_geos(priv); | |
862 | err_free_channel_map: | |
863 | iwl_free_channel_map(priv); | |
864 | err: | |
865 | return ret; | |
866 | } | |
867 | ||
bf85ea4f AK |
868 | int iwl_setup(struct iwl_priv *priv) |
869 | { | |
870 | int ret = 0; | |
871 | iwlcore_init_hw(priv); | |
c7de35cd | 872 | ret = iwlcore_init_drv(priv); |
bf85ea4f AK |
873 | return ret; |
874 | } | |
875 | EXPORT_SYMBOL(iwl_setup); | |
876 | ||
c8381fdc MA |
877 | /* Low level driver call this function to update iwlcore with |
878 | * driver status. | |
879 | */ | |
880 | int iwlcore_low_level_notify(struct iwl_priv *priv, | |
881 | enum iwlcore_card_notify notify) | |
882 | { | |
03d29c68 | 883 | int ret; |
c8381fdc MA |
884 | switch (notify) { |
885 | case IWLCORE_INIT_EVT: | |
03d29c68 MA |
886 | ret = iwl_rfkill_init(priv); |
887 | if (ret) | |
888 | IWL_ERROR("Unable to initialize RFKILL system. " | |
889 | "Ignoring error: %d\n", ret); | |
5da4b55f | 890 | iwl_power_initialize(priv); |
c8381fdc MA |
891 | break; |
892 | case IWLCORE_START_EVT: | |
5da4b55f | 893 | iwl_power_update_mode(priv, 1); |
c8381fdc MA |
894 | break; |
895 | case IWLCORE_STOP_EVT: | |
896 | break; | |
897 | case IWLCORE_REMOVE_EVT: | |
ad97edd2 | 898 | iwl_rfkill_unregister(priv); |
c8381fdc MA |
899 | break; |
900 | } | |
901 | ||
902 | return 0; | |
903 | } | |
904 | EXPORT_SYMBOL(iwlcore_low_level_notify); | |
905 | ||
49ea8596 EG |
906 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags) |
907 | { | |
908 | u32 stat_flags = 0; | |
909 | struct iwl_host_cmd cmd = { | |
910 | .id = REPLY_STATISTICS_CMD, | |
911 | .meta.flags = flags, | |
912 | .len = sizeof(stat_flags), | |
913 | .data = (u8 *) &stat_flags, | |
914 | }; | |
915 | return iwl_send_cmd(priv, &cmd); | |
916 | } | |
917 | EXPORT_SYMBOL(iwl_send_statistics_request); | |
7e8c519e | 918 | |
b0692f2f EG |
919 | /** |
920 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
921 | * using sample data 100 bytes apart. If these sample points are good, | |
922 | * it's a pretty good bet that everything between them is good, too. | |
923 | */ | |
924 | static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) | |
925 | { | |
926 | u32 val; | |
927 | int ret = 0; | |
928 | u32 errcnt = 0; | |
929 | u32 i; | |
930 | ||
931 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
932 | ||
933 | ret = iwl_grab_nic_access(priv); | |
934 | if (ret) | |
935 | return ret; | |
936 | ||
937 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
938 | /* read data comes through single port, auto-incr addr */ | |
939 | /* NOTE: Use the debugless read so we don't flood kernel log | |
940 | * if IWL_DL_IO is set */ | |
941 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, | |
942 | i + RTC_INST_LOWER_BOUND); | |
943 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
944 | if (val != le32_to_cpu(*image)) { | |
945 | ret = -EIO; | |
946 | errcnt++; | |
947 | if (errcnt >= 3) | |
948 | break; | |
949 | } | |
950 | } | |
951 | ||
952 | iwl_release_nic_access(priv); | |
953 | ||
954 | return ret; | |
955 | } | |
956 | ||
957 | /** | |
958 | * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host, | |
959 | * looking at all data. | |
960 | */ | |
961 | static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image, | |
962 | u32 len) | |
963 | { | |
964 | u32 val; | |
965 | u32 save_len = len; | |
966 | int ret = 0; | |
967 | u32 errcnt; | |
968 | ||
969 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
970 | ||
971 | ret = iwl_grab_nic_access(priv); | |
972 | if (ret) | |
973 | return ret; | |
974 | ||
975 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); | |
976 | ||
977 | errcnt = 0; | |
978 | for (; len > 0; len -= sizeof(u32), image++) { | |
979 | /* read data comes through single port, auto-incr addr */ | |
980 | /* NOTE: Use the debugless read so we don't flood kernel log | |
981 | * if IWL_DL_IO is set */ | |
982 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
983 | if (val != le32_to_cpu(*image)) { | |
984 | IWL_ERROR("uCode INST section is invalid at " | |
985 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
986 | save_len - len, val, le32_to_cpu(*image)); | |
987 | ret = -EIO; | |
988 | errcnt++; | |
989 | if (errcnt >= 20) | |
990 | break; | |
991 | } | |
992 | } | |
993 | ||
994 | iwl_release_nic_access(priv); | |
995 | ||
996 | if (!errcnt) | |
997 | IWL_DEBUG_INFO | |
998 | ("ucode image in INSTRUCTION memory is good\n"); | |
999 | ||
1000 | return ret; | |
1001 | } | |
1002 | ||
1003 | /** | |
1004 | * iwl_verify_ucode - determine which instruction image is in SRAM, | |
1005 | * and verify its contents | |
1006 | */ | |
1007 | int iwl_verify_ucode(struct iwl_priv *priv) | |
1008 | { | |
1009 | __le32 *image; | |
1010 | u32 len; | |
1011 | int ret; | |
1012 | ||
1013 | /* Try bootstrap */ | |
1014 | image = (__le32 *)priv->ucode_boot.v_addr; | |
1015 | len = priv->ucode_boot.len; | |
1016 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1017 | if (!ret) { | |
1018 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | /* Try initialize */ | |
1023 | image = (__le32 *)priv->ucode_init.v_addr; | |
1024 | len = priv->ucode_init.len; | |
1025 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1026 | if (!ret) { | |
1027 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | /* Try runtime/protocol */ | |
1032 | image = (__le32 *)priv->ucode_code.v_addr; | |
1033 | len = priv->ucode_code.len; | |
1034 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1035 | if (!ret) { | |
1036 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
1041 | ||
1042 | /* Since nothing seems to match, show first several data entries in | |
1043 | * instruction SRAM, so maybe visual inspection will give a clue. | |
1044 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
1045 | image = (__le32 *)priv->ucode_boot.v_addr; | |
1046 | len = priv->ucode_boot.len; | |
1047 | ret = iwl_verify_inst_full(priv, image, len); | |
1048 | ||
1049 | return ret; | |
1050 | } | |
1051 | EXPORT_SYMBOL(iwl_verify_ucode); | |
1052 |