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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
901069c7 | 5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
d43c36dc | 32 | #include <linux/sched.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
1d0a082d | 34 | #include <net/mac80211.h> |
df48c323 | 35 | |
6bc913bd | 36 | #include "iwl-eeprom.h" |
3e0d4cb1 | 37 | #include "iwl-dev.h" /* FIXME: remove */ |
19335774 | 38 | #include "iwl-debug.h" |
df48c323 | 39 | #include "iwl-core.h" |
b661c819 | 40 | #include "iwl-io.h" |
5da4b55f | 41 | #include "iwl-power.h" |
83dde8c9 | 42 | #include "iwl-sta.h" |
c6baf7fb | 43 | #include "iwl-agn.h" |
ef850d7c | 44 | #include "iwl-helpers.h" |
48f20d35 | 45 | #include "iwl-shared.h" |
9d143e9a | 46 | #include "iwl-agn.h" |
bdfbf092 | 47 | #include "iwl-trans.h" |
df48c323 | 48 | |
57bd1bea | 49 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
57bd1bea | 50 | |
d9fe60de JB |
51 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
52 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
b39488a9 | 53 | static void iwl_init_ht_hw_capab(const struct iwl_priv *priv, |
d9fe60de | 54 | struct ieee80211_sta_ht_cap *ht_info, |
c7de35cd RR |
55 | enum ieee80211_band band) |
56 | { | |
39130df3 | 57 | u16 max_bit_rate = 0; |
d6189124 EG |
58 | u8 rx_chains_num = hw_params(priv).rx_chains_num; |
59 | u8 tx_chains_num = hw_params(priv).tx_chains_num; | |
39130df3 | 60 | |
c7de35cd | 61 | ht_info->cap = 0; |
d9fe60de | 62 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
c7de35cd | 63 | |
d9fe60de | 64 | ht_info->ht_supported = true; |
c7de35cd | 65 | |
7cb1b088 WYG |
66 | if (priv->cfg->ht_params && |
67 | priv->cfg->ht_params->ht_greenfield_support) | |
b261793d | 68 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; |
d9fe60de | 69 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; |
39130df3 | 70 | max_bit_rate = MAX_BIT_RATE_20_MHZ; |
d6189124 | 71 | if (hw_params(priv).ht40_channel & BIT(band)) { |
d9fe60de JB |
72 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
73 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
74 | ht_info->mcs.rx_mask[4] = 0x01; | |
39130df3 | 75 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 76 | } |
c7de35cd | 77 | |
9d143e9a | 78 | if (iwlagn_mod_params.amsdu_size_8K) |
d9fe60de | 79 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
c7de35cd RR |
80 | |
81 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
7cb1b088 WYG |
82 | if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_factor) |
83 | ht_info->ampdu_factor = priv->cfg->bt_params->ampdu_factor; | |
c7de35cd | 84 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; |
7cb1b088 WYG |
85 | if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_density) |
86 | ht_info->ampdu_density = priv->cfg->bt_params->ampdu_density; | |
c7de35cd | 87 | |
d9fe60de | 88 | ht_info->mcs.rx_mask[0] = 0xFF; |
39130df3 | 89 | if (rx_chains_num >= 2) |
d9fe60de | 90 | ht_info->mcs.rx_mask[1] = 0xFF; |
39130df3 | 91 | if (rx_chains_num >= 3) |
d9fe60de | 92 | ht_info->mcs.rx_mask[2] = 0xFF; |
39130df3 RR |
93 | |
94 | /* Highest supported Rx data rate */ | |
95 | max_bit_rate *= rx_chains_num; | |
d9fe60de JB |
96 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
97 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
39130df3 RR |
98 | |
99 | /* Tx MCS capabilities */ | |
d9fe60de | 100 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
39130df3 | 101 | if (tx_chains_num != rx_chains_num) { |
d9fe60de JB |
102 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
103 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << | |
104 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
39130df3 | 105 | } |
c7de35cd | 106 | } |
c7de35cd | 107 | |
c7de35cd | 108 | /** |
b39488a9 | 109 | * iwl_init_geos - Initialize mac80211's geo/channel info based from eeprom |
c7de35cd | 110 | */ |
b39488a9 | 111 | int iwl_init_geos(struct iwl_priv *priv) |
c7de35cd RR |
112 | { |
113 | struct iwl_channel_info *ch; | |
114 | struct ieee80211_supported_band *sband; | |
115 | struct ieee80211_channel *channels; | |
116 | struct ieee80211_channel *geo_ch; | |
117 | struct ieee80211_rate *rates; | |
118 | int i = 0; | |
75d80cad | 119 | s8 max_tx_power = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
c7de35cd RR |
120 | |
121 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
122 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
e1623446 | 123 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
63013ae3 | 124 | set_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status); |
c7de35cd RR |
125 | return 0; |
126 | } | |
127 | ||
128 | channels = kzalloc(sizeof(struct ieee80211_channel) * | |
129 | priv->channel_count, GFP_KERNEL); | |
130 | if (!channels) | |
131 | return -ENOMEM; | |
132 | ||
5027309b | 133 | rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY), |
c7de35cd RR |
134 | GFP_KERNEL); |
135 | if (!rates) { | |
136 | kfree(channels); | |
137 | return -ENOMEM; | |
138 | } | |
139 | ||
140 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
141 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
142 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
143 | /* just OFDM */ | |
144 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
5027309b | 145 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE; |
c7de35cd | 146 | |
88950758 | 147 | if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE) |
b39488a9 | 148 | iwl_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 149 | IEEE80211_BAND_5GHZ); |
c7de35cd RR |
150 | |
151 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
152 | sband->channels = channels; | |
153 | /* OFDM & CCK */ | |
154 | sband->bitrates = rates; | |
5027309b | 155 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY; |
c7de35cd | 156 | |
88950758 | 157 | if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE) |
b39488a9 | 158 | iwl_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 159 | IEEE80211_BAND_2GHZ); |
c7de35cd RR |
160 | |
161 | priv->ieee_channels = channels; | |
162 | priv->ieee_rates = rates; | |
163 | ||
c7de35cd RR |
164 | for (i = 0; i < priv->channel_count; i++) { |
165 | ch = &priv->channel_info[i]; | |
166 | ||
167 | /* FIXME: might be removed if scan is OK */ | |
168 | if (!is_channel_valid(ch)) | |
169 | continue; | |
170 | ||
5a3a0352 | 171 | sband = &priv->bands[ch->band]; |
c7de35cd RR |
172 | |
173 | geo_ch = &sband->channels[sband->n_channels++]; | |
174 | ||
175 | geo_ch->center_freq = | |
5a3a0352 | 176 | ieee80211_channel_to_frequency(ch->channel, ch->band); |
c7de35cd RR |
177 | geo_ch->max_power = ch->max_power_avg; |
178 | geo_ch->max_antenna_gain = 0xff; | |
179 | geo_ch->hw_value = ch->channel; | |
180 | ||
181 | if (is_channel_valid(ch)) { | |
182 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
183 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
184 | ||
185 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
186 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
187 | ||
188 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
189 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
190 | ||
7aafef1c | 191 | geo_ch->flags |= ch->ht40_extension_channel; |
4d38c2e8 | 192 | |
75d80cad SG |
193 | if (ch->max_power_avg > max_tx_power) |
194 | max_tx_power = ch->max_power_avg; | |
c7de35cd RR |
195 | } else { |
196 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
197 | } | |
198 | ||
e1623446 | 199 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
200 | ch->channel, geo_ch->center_freq, |
201 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
202 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
203 | "restricted" : "valid", | |
204 | geo_ch->flags); | |
205 | } | |
206 | ||
75d80cad SG |
207 | priv->tx_power_device_lmt = max_tx_power; |
208 | priv->tx_power_user_lmt = max_tx_power; | |
209 | priv->tx_power_next = max_tx_power; | |
210 | ||
c7de35cd | 211 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
88950758 | 212 | priv->cfg->sku & EEPROM_SKU_CAP_BAND_52GHZ) { |
19707bac | 213 | char buf[32]; |
d5934110 | 214 | bus_get_hw_id(priv->bus, buf, sizeof(buf)); |
978785a3 | 215 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
19707bac | 216 | "Please send your %s to maintainer.\n", buf); |
88950758 | 217 | priv->cfg->sku &= ~EEPROM_SKU_CAP_BAND_52GHZ; |
c7de35cd RR |
218 | } |
219 | ||
978785a3 | 220 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
a3139c59 SO |
221 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
222 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
c7de35cd | 223 | |
63013ae3 | 224 | set_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status); |
c7de35cd RR |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
229 | /* | |
b39488a9 | 230 | * iwl_free_geos - undo allocations in iwl_init_geos |
c7de35cd | 231 | */ |
b39488a9 | 232 | void iwl_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
233 | { |
234 | kfree(priv->ieee_channels); | |
235 | kfree(priv->ieee_rates); | |
63013ae3 | 236 | clear_bit(STATUS_GEO_CONFIGURED, &priv->shrd->status); |
c7de35cd | 237 | } |
c7de35cd | 238 | |
7e6a5886 JB |
239 | static bool iwl_is_channel_extension(struct iwl_priv *priv, |
240 | enum ieee80211_band band, | |
241 | u16 channel, u8 extension_chan_offset) | |
47c5196e TW |
242 | { |
243 | const struct iwl_channel_info *ch_info; | |
244 | ||
245 | ch_info = iwl_get_channel_info(priv, band, channel); | |
246 | if (!is_channel_valid(ch_info)) | |
7e6a5886 | 247 | return false; |
47c5196e | 248 | |
d9fe60de | 249 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
7aafef1c | 250 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 251 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 252 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
7aafef1c | 253 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 254 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e | 255 | |
7e6a5886 | 256 | return false; |
47c5196e TW |
257 | } |
258 | ||
7e6a5886 JB |
259 | bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
260 | struct iwl_rxon_context *ctx, | |
261 | struct ieee80211_sta_ht_cap *ht_cap) | |
47c5196e | 262 | { |
7e6a5886 JB |
263 | if (!ctx->ht.enabled || !ctx->ht.is_40mhz) |
264 | return false; | |
47c5196e | 265 | |
7e6a5886 JB |
266 | /* |
267 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
a2b0f02e WYG |
268 | * the bit will not set if it is pure 40MHz case |
269 | */ | |
7e6a5886 JB |
270 | if (ht_cap && !ht_cap->ht_supported) |
271 | return false; | |
272 | ||
d73e4923 | 273 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1e4247d4 | 274 | if (priv->disable_ht40) |
7e6a5886 | 275 | return false; |
1e4247d4 | 276 | #endif |
7e6a5886 | 277 | |
611d3eb7 | 278 | return iwl_is_channel_extension(priv, priv->band, |
246ed355 | 279 | le16_to_cpu(ctx->staging.channel), |
7e6a5886 | 280 | ctx->ht.extension_chan_offset); |
47c5196e | 281 | } |
47c5196e | 282 | |
2c2f3b33 TW |
283 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
284 | { | |
ea196fdb JB |
285 | u16 new_val; |
286 | u16 beacon_factor; | |
287 | ||
288 | /* | |
289 | * If mac80211 hasn't given us a beacon interval, program | |
290 | * the default into the device (not checking this here | |
291 | * would cause the adjustment below to return the maximum | |
292 | * value, which may break PAN.) | |
293 | */ | |
294 | if (!beacon_val) | |
295 | return DEFAULT_BEACON_INTERVAL; | |
296 | ||
297 | /* | |
298 | * If the beacon interval we obtained from the peer | |
299 | * is too large, we'll have to wake up more often | |
300 | * (and in IBSS case, we'll beacon too much) | |
301 | * | |
302 | * For example, if max_beacon_val is 4096, and the | |
303 | * requested beacon interval is 7000, we'll have to | |
304 | * use 3500 to be able to wake up on the beacons. | |
305 | * | |
306 | * This could badly influence beacon detection stats. | |
307 | */ | |
2c2f3b33 TW |
308 | |
309 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
310 | new_val = beacon_val / beacon_factor; | |
311 | ||
312 | if (!new_val) | |
313 | new_val = max_beacon_val; | |
314 | ||
315 | return new_val; | |
316 | } | |
317 | ||
47313e34 | 318 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
2c2f3b33 TW |
319 | { |
320 | u64 tsf; | |
321 | s32 interval_tm, rem; | |
2c2f3b33 TW |
322 | struct ieee80211_conf *conf = NULL; |
323 | u16 beacon_int; | |
47313e34 | 324 | struct ieee80211_vif *vif = ctx->vif; |
2c2f3b33 TW |
325 | |
326 | conf = ieee80211_get_hw_conf(priv->hw); | |
327 | ||
6ac2f839 | 328 | lockdep_assert_held(&priv->shrd->mutex); |
948f5a2f | 329 | |
246ed355 | 330 | memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
948f5a2f | 331 | |
246ed355 JB |
332 | ctx->timing.timestamp = cpu_to_le64(priv->timestamp); |
333 | ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
2c2f3b33 | 334 | |
47313e34 | 335 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; |
2c2f3b33 | 336 | |
47313e34 JB |
337 | /* |
338 | * TODO: For IBSS we need to get atim_window from mac80211, | |
339 | * for now just always use 0 | |
340 | */ | |
341 | ctx->timing.atim_window = 0; | |
2c2f3b33 | 342 | |
bde4530e | 343 | if (ctx->ctxid == IWL_RXON_CTX_PAN && |
f1f270b2 JB |
344 | (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) && |
345 | iwl_is_associated(priv, IWL_RXON_CTX_BSS) && | |
346 | priv->contexts[IWL_RXON_CTX_BSS].vif && | |
347 | priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) { | |
bde4530e JB |
348 | ctx->timing.beacon_interval = |
349 | priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; | |
350 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
f1f270b2 JB |
351 | } else if (ctx->ctxid == IWL_RXON_CTX_BSS && |
352 | iwl_is_associated(priv, IWL_RXON_CTX_PAN) && | |
353 | priv->contexts[IWL_RXON_CTX_PAN].vif && | |
354 | priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int && | |
355 | (!iwl_is_associated_ctx(ctx) || !ctx->vif || | |
356 | !ctx->vif->bss_conf.beacon_int)) { | |
357 | ctx->timing.beacon_interval = | |
358 | priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; | |
359 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
bde4530e JB |
360 | } else { |
361 | beacon_int = iwl_adjust_beacon_interval(beacon_int, | |
d6189124 | 362 | hw_params(priv).max_beacon_itrvl * TIME_UNIT); |
bde4530e JB |
363 | ctx->timing.beacon_interval = cpu_to_le16(beacon_int); |
364 | } | |
2c2f3b33 | 365 | |
bbb05cb5 JB |
366 | ctx->beacon_int = beacon_int; |
367 | ||
2c2f3b33 | 368 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
f8525e55 | 369 | interval_tm = beacon_int * TIME_UNIT; |
2c2f3b33 | 370 | rem = do_div(tsf, interval_tm); |
246ed355 | 371 | ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
2c2f3b33 | 372 | |
47313e34 | 373 | ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; |
2491fa42 | 374 | |
2c2f3b33 TW |
375 | IWL_DEBUG_ASSOC(priv, |
376 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
246ed355 JB |
377 | le16_to_cpu(ctx->timing.beacon_interval), |
378 | le32_to_cpu(ctx->timing.beacon_init_val), | |
379 | le16_to_cpu(ctx->timing.atim_window)); | |
948f5a2f | 380 | |
e6bb4c9c | 381 | return iwl_trans_send_cmd_pdu(trans(priv), ctx->rxon_timing_cmd, |
e419d62d | 382 | CMD_SYNC, sizeof(ctx->timing), &ctx->timing); |
2c2f3b33 | 383 | } |
2c2f3b33 | 384 | |
246ed355 JB |
385 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx, |
386 | int hw_decrypt) | |
8ccde88a | 387 | { |
246ed355 | 388 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a SO |
389 | |
390 | if (hw_decrypt) | |
391 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
392 | else | |
393 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
394 | ||
395 | } | |
8ccde88a | 396 | |
dacefedb | 397 | /* validate RXON structure is valid */ |
246ed355 | 398 | int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
8ccde88a | 399 | { |
246ed355 | 400 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
c914ac26 | 401 | u32 errors = 0; |
8ccde88a SO |
402 | |
403 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
dacefedb JB |
404 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { |
405 | IWL_WARN(priv, "check 2.4G: wrong narrow\n"); | |
c914ac26 | 406 | errors |= BIT(0); |
dacefedb JB |
407 | } |
408 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
409 | IWL_WARN(priv, "check 2.4G: wrong radar\n"); | |
c914ac26 | 410 | errors |= BIT(1); |
dacefedb | 411 | } |
8ccde88a | 412 | } else { |
dacefedb JB |
413 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { |
414 | IWL_WARN(priv, "check 5.2G: not short slot!\n"); | |
c914ac26 | 415 | errors |= BIT(2); |
dacefedb JB |
416 | } |
417 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
418 | IWL_WARN(priv, "check 5.2G: CCK!\n"); | |
c914ac26 | 419 | errors |= BIT(3); |
dacefedb JB |
420 | } |
421 | } | |
422 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
423 | IWL_WARN(priv, "mac/bssid mcast!\n"); | |
c914ac26 | 424 | errors |= BIT(4); |
8ccde88a | 425 | } |
8ccde88a SO |
426 | |
427 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
dacefedb JB |
428 | if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 && |
429 | (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) { | |
430 | IWL_WARN(priv, "neither 1 nor 6 are basic\n"); | |
c914ac26 | 431 | errors |= BIT(5); |
dacefedb | 432 | } |
8ccde88a | 433 | |
dacefedb JB |
434 | if (le16_to_cpu(rxon->assoc_id) > 2007) { |
435 | IWL_WARN(priv, "aid > 2007\n"); | |
c914ac26 | 436 | errors |= BIT(6); |
dacefedb | 437 | } |
8ccde88a | 438 | |
dacefedb JB |
439 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) |
440 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
441 | IWL_WARN(priv, "CCK and short slot\n"); | |
c914ac26 | 442 | errors |= BIT(7); |
dacefedb | 443 | } |
8ccde88a | 444 | |
dacefedb JB |
445 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) |
446 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
447 | IWL_WARN(priv, "CCK and auto detect"); | |
c914ac26 | 448 | errors |= BIT(8); |
dacefedb | 449 | } |
8ccde88a | 450 | |
dacefedb JB |
451 | if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | |
452 | RXON_FLG_TGG_PROTECT_MSK)) == | |
453 | RXON_FLG_TGG_PROTECT_MSK) { | |
454 | IWL_WARN(priv, "TGg but no auto-detect\n"); | |
c914ac26 | 455 | errors |= BIT(9); |
dacefedb | 456 | } |
8ccde88a | 457 | |
c914ac26 JB |
458 | if (rxon->channel == 0) { |
459 | IWL_WARN(priv, "zero channel is invalid\n"); | |
460 | errors |= BIT(10); | |
8ccde88a | 461 | } |
c914ac26 JB |
462 | |
463 | WARN(errors, "Invalid RXON (%#x), channel %d", | |
464 | errors, le16_to_cpu(rxon->channel)); | |
465 | ||
466 | return errors ? -EINVAL : 0; | |
8ccde88a | 467 | } |
8ccde88a SO |
468 | |
469 | /** | |
470 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
471 | * @priv: staging_rxon is compared to active_rxon | |
472 | * | |
473 | * If the RXON structure is changing enough to require a new tune, | |
474 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
475 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
476 | */ | |
246ed355 JB |
477 | int iwl_full_rxon_required(struct iwl_priv *priv, |
478 | struct iwl_rxon_context *ctx) | |
8ccde88a | 479 | { |
246ed355 JB |
480 | const struct iwl_rxon_cmd *staging = &ctx->staging; |
481 | const struct iwl_rxon_cmd *active = &ctx->active; | |
482 | ||
483 | #define CHK(cond) \ | |
484 | if ((cond)) { \ | |
485 | IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \ | |
486 | return 1; \ | |
487 | } | |
488 | ||
489 | #define CHK_NEQ(c1, c2) \ | |
490 | if ((c1) != (c2)) { \ | |
491 | IWL_DEBUG_INFO(priv, "need full RXON - " \ | |
492 | #c1 " != " #c2 " - %d != %d\n", \ | |
493 | (c1), (c2)); \ | |
494 | return 1; \ | |
495 | } | |
8ccde88a SO |
496 | |
497 | /* These items are only settable from the full RXON command */ | |
246ed355 JB |
498 | CHK(!iwl_is_associated_ctx(ctx)); |
499 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); | |
500 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
501 | CHK(compare_ether_addr(staging->wlap_bssid_addr, | |
502 | active->wlap_bssid_addr)); | |
503 | CHK_NEQ(staging->dev_type, active->dev_type); | |
504 | CHK_NEQ(staging->channel, active->channel); | |
505 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
506 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
507 | active->ofdm_ht_single_stream_basic_rates); | |
508 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
509 | active->ofdm_ht_dual_stream_basic_rates); | |
510 | CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates, | |
511 | active->ofdm_ht_triple_stream_basic_rates); | |
512 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
8ccde88a SO |
513 | |
514 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
515 | * be updated with the RXON_ASSOC command -- however only some | |
516 | * flag transitions are allowed using RXON_ASSOC */ | |
517 | ||
518 | /* Check if we are not switching bands */ | |
246ed355 JB |
519 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, |
520 | active->flags & RXON_FLG_BAND_24G_MSK); | |
8ccde88a SO |
521 | |
522 | /* Check if we are switching association toggle */ | |
246ed355 JB |
523 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, |
524 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
525 | ||
526 | #undef CHK | |
527 | #undef CHK_NEQ | |
8ccde88a SO |
528 | |
529 | return 0; | |
530 | } | |
8ccde88a | 531 | |
246ed355 JB |
532 | static void _iwl_set_rxon_ht(struct iwl_priv *priv, |
533 | struct iwl_ht_config *ht_conf, | |
534 | struct iwl_rxon_context *ctx) | |
47c5196e | 535 | { |
246ed355 | 536 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
47c5196e | 537 | |
7e6a5886 | 538 | if (!ctx->ht.enabled) { |
a2b0f02e | 539 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 | 540 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
7aafef1c | 541 | RXON_FLG_HT40_PROT_MSK | |
42eb7c64 | 542 | RXON_FLG_HT_PROT_MSK); |
47c5196e | 543 | return; |
42eb7c64 | 544 | } |
47c5196e | 545 | |
7e6a5886 | 546 | /* FIXME: if the definition of ht.protection changed, the "translation" |
a2b0f02e WYG |
547 | * will be needed for rxon->flags |
548 | */ | |
7e6a5886 | 549 | rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); |
a2b0f02e WYG |
550 | |
551 | /* Set up channel bandwidth: | |
7aafef1c | 552 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
a2b0f02e WYG |
553 | /* clear the HT channel mode before set the mode */ |
554 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
555 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
7e6a5886 | 556 | if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) { |
7aafef1c | 557 | /* pure ht40 */ |
7e6a5886 | 558 | if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
a2b0f02e | 559 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
508b08e7 | 560 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 561 | switch (ctx->ht.extension_chan_offset) { |
508b08e7 WYG |
562 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
563 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
564 | break; | |
565 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
566 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
567 | break; | |
568 | } | |
569 | } else { | |
a2b0f02e | 570 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 571 | switch (ctx->ht.extension_chan_offset) { |
a2b0f02e WYG |
572 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
573 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
574 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
575 | break; | |
576 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
577 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
578 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
579 | break; | |
580 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
581 | default: | |
582 | /* channel location only valid if in Mixed mode */ | |
583 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
584 | break; | |
585 | } | |
586 | } | |
587 | } else { | |
588 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
589 | } |
590 | ||
e3f10cea | 591 | iwlagn_set_rxon_chain(priv, ctx); |
47c5196e | 592 | |
02bb1bea | 593 | IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 594 | "extension channel offset 0x%x\n", |
7e6a5886 JB |
595 | le32_to_cpu(rxon->flags), ctx->ht.protection, |
596 | ctx->ht.extension_chan_offset); | |
47c5196e | 597 | } |
246ed355 JB |
598 | |
599 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf) | |
600 | { | |
601 | struct iwl_rxon_context *ctx; | |
602 | ||
603 | for_each_context(priv, ctx) | |
604 | _iwl_set_rxon_ht(priv, ht_conf, ctx); | |
605 | } | |
47c5196e | 606 | |
246ed355 | 607 | /* Return valid, unused, channel for a passive scan to reset the RF */ |
14023641 | 608 | u8 iwl_get_single_channel_number(struct iwl_priv *priv, |
246ed355 | 609 | enum ieee80211_band band) |
14023641 AK |
610 | { |
611 | const struct iwl_channel_info *ch_info; | |
612 | int i; | |
613 | u8 channel = 0; | |
246ed355 JB |
614 | u8 min, max; |
615 | struct iwl_rxon_context *ctx; | |
14023641 | 616 | |
14023641 | 617 | if (band == IEEE80211_BAND_5GHZ) { |
246ed355 JB |
618 | min = 14; |
619 | max = priv->channel_count; | |
14023641 | 620 | } else { |
246ed355 JB |
621 | min = 0; |
622 | max = 14; | |
623 | } | |
624 | ||
625 | for (i = min; i < max; i++) { | |
626 | bool busy = false; | |
627 | ||
628 | for_each_context(priv, ctx) { | |
629 | busy = priv->channel_info[i].channel == | |
630 | le16_to_cpu(ctx->staging.channel); | |
631 | if (busy) | |
632 | break; | |
14023641 | 633 | } |
246ed355 JB |
634 | |
635 | if (busy) | |
636 | continue; | |
637 | ||
638 | channel = priv->channel_info[i].channel; | |
639 | ch_info = iwl_get_channel_info(priv, band, channel); | |
640 | if (is_channel_valid(ch_info)) | |
641 | break; | |
14023641 AK |
642 | } |
643 | ||
644 | return channel; | |
645 | } | |
14023641 | 646 | |
bf85ea4f | 647 | /** |
3edb5fd6 SZ |
648 | * iwl_set_rxon_channel - Set the band and channel values in staging RXON |
649 | * @ch: requested channel as a pointer to struct ieee80211_channel | |
bf85ea4f | 650 | |
bf85ea4f | 651 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
3edb5fd6 | 652 | * in the staging RXON flag structure based on the ch->band |
bf85ea4f | 653 | */ |
246ed355 JB |
654 | int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch, |
655 | struct iwl_rxon_context *ctx) | |
bf85ea4f | 656 | { |
17e72782 | 657 | enum ieee80211_band band = ch->band; |
81e95430 | 658 | u16 channel = ch->hw_value; |
17e72782 | 659 | |
246ed355 | 660 | if ((le16_to_cpu(ctx->staging.channel) == channel) && |
bf85ea4f AK |
661 | (priv->band == band)) |
662 | return 0; | |
663 | ||
246ed355 | 664 | ctx->staging.channel = cpu_to_le16(channel); |
bf85ea4f | 665 | if (band == IEEE80211_BAND_5GHZ) |
246ed355 | 666 | ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK; |
bf85ea4f | 667 | else |
246ed355 | 668 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
bf85ea4f AK |
669 | |
670 | priv->band = band; | |
671 | ||
e1623446 | 672 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f AK |
673 | |
674 | return 0; | |
675 | } | |
bf85ea4f | 676 | |
79d07325 | 677 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
246ed355 | 678 | struct iwl_rxon_context *ctx, |
79d07325 WYG |
679 | enum ieee80211_band band, |
680 | struct ieee80211_vif *vif) | |
8ccde88a SO |
681 | { |
682 | if (band == IEEE80211_BAND_5GHZ) { | |
246ed355 | 683 | ctx->staging.flags &= |
8ccde88a SO |
684 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
685 | | RXON_FLG_CCK_MSK); | |
246ed355 | 686 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a SO |
687 | } else { |
688 | /* Copied from iwl_post_associate() */ | |
c213d745 | 689 | if (vif && vif->bss_conf.use_short_slot) |
246ed355 | 690 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 691 | else |
246ed355 | 692 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 693 | |
246ed355 JB |
694 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
695 | ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
696 | ctx->staging.flags &= ~RXON_FLG_CCK_MSK; | |
8ccde88a SO |
697 | } |
698 | } | |
8ccde88a SO |
699 | |
700 | /* | |
701 | * initialize rxon structure with default values from eeprom | |
702 | */ | |
1dda6d28 | 703 | void iwl_connection_init_rx_config(struct iwl_priv *priv, |
d0fe478c | 704 | struct iwl_rxon_context *ctx) |
8ccde88a SO |
705 | { |
706 | const struct iwl_channel_info *ch_info; | |
707 | ||
246ed355 | 708 | memset(&ctx->staging, 0, sizeof(ctx->staging)); |
8ccde88a | 709 | |
d0fe478c JB |
710 | if (!ctx->vif) { |
711 | ctx->staging.dev_type = ctx->unused_devtype; | |
712 | } else switch (ctx->vif->type) { | |
8ccde88a | 713 | case NL80211_IFTYPE_AP: |
d0fe478c | 714 | ctx->staging.dev_type = ctx->ap_devtype; |
8ccde88a SO |
715 | break; |
716 | ||
717 | case NL80211_IFTYPE_STATION: | |
d0fe478c | 718 | ctx->staging.dev_type = ctx->station_devtype; |
246ed355 | 719 | ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; |
8ccde88a SO |
720 | break; |
721 | ||
722 | case NL80211_IFTYPE_ADHOC: | |
d0fe478c | 723 | ctx->staging.dev_type = ctx->ibss_devtype; |
246ed355 JB |
724 | ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; |
725 | ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
8ccde88a SO |
726 | RXON_FILTER_ACCEPT_GRP_MSK; |
727 | break; | |
728 | ||
8ccde88a | 729 | default: |
d0fe478c JB |
730 | IWL_ERR(priv, "Unsupported interface type %d\n", |
731 | ctx->vif->type); | |
8ccde88a SO |
732 | break; |
733 | } | |
734 | ||
735 | #if 0 | |
736 | /* TODO: Figure out when short_preamble would be set and cache from | |
737 | * that */ | |
738 | if (!hw_to_local(priv->hw)->short_preamble) | |
246ed355 | 739 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a | 740 | else |
246ed355 | 741 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a SO |
742 | #endif |
743 | ||
744 | ch_info = iwl_get_channel_info(priv, priv->band, | |
246ed355 | 745 | le16_to_cpu(ctx->active.channel)); |
8ccde88a SO |
746 | |
747 | if (!ch_info) | |
748 | ch_info = &priv->channel_info[0]; | |
749 | ||
246ed355 | 750 | ctx->staging.channel = cpu_to_le16(ch_info->channel); |
8ccde88a SO |
751 | priv->band = ch_info->band; |
752 | ||
d0fe478c | 753 | iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif); |
8ccde88a | 754 | |
246ed355 | 755 | ctx->staging.ofdm_basic_rates = |
8ccde88a | 756 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
246ed355 | 757 | ctx->staging.cck_basic_rates = |
8ccde88a SO |
758 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
759 | ||
a2b0f02e | 760 | /* clear both MIX and PURE40 mode flag */ |
246ed355 | 761 | ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | |
a2b0f02e | 762 | RXON_FLG_CHANNEL_MODE_PURE_40); |
d0fe478c JB |
763 | if (ctx->vif) |
764 | memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN); | |
7684c408 | 765 | |
246ed355 JB |
766 | ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff; |
767 | ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
768 | ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff; | |
8ccde88a | 769 | } |
8ccde88a | 770 | |
79d07325 | 771 | void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
772 | { |
773 | const struct ieee80211_supported_band *hw = NULL; | |
774 | struct ieee80211_rate *rate; | |
246ed355 | 775 | struct iwl_rxon_context *ctx; |
8ccde88a SO |
776 | int i; |
777 | ||
778 | hw = iwl_get_hw_mode(priv, priv->band); | |
779 | if (!hw) { | |
780 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
781 | return; | |
782 | } | |
783 | ||
784 | priv->active_rate = 0; | |
8ccde88a SO |
785 | |
786 | for (i = 0; i < hw->n_bitrates; i++) { | |
787 | rate = &(hw->bitrates[i]); | |
5027309b | 788 | if (rate->hw_value < IWL_RATE_COUNT_LEGACY) |
8ccde88a SO |
789 | priv->active_rate |= (1 << rate->hw_value); |
790 | } | |
791 | ||
4a02886b | 792 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate); |
8ccde88a | 793 | |
246ed355 JB |
794 | for_each_context(priv, ctx) { |
795 | ctx->staging.cck_basic_rates = | |
796 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
4a02886b | 797 | |
246ed355 JB |
798 | ctx->staging.ofdm_basic_rates = |
799 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
800 | } | |
8ccde88a | 801 | } |
79d07325 WYG |
802 | |
803 | void iwl_chswitch_done(struct iwl_priv *priv, bool is_success) | |
804 | { | |
8bd413e6 JB |
805 | /* |
806 | * MULTI-FIXME | |
807 | * See iwl_mac_channel_switch. | |
808 | */ | |
809 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
810 | ||
63013ae3 | 811 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
79d07325 WYG |
812 | return; |
813 | ||
63013ae3 EG |
814 | if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, |
815 | &priv->shrd->status)) | |
8bd413e6 | 816 | ieee80211_chswitch_done(ctx->vif, is_success); |
79d07325 | 817 | } |
8ccde88a | 818 | |
8ccde88a | 819 | #ifdef CONFIG_IWLWIFI_DEBUG |
246ed355 JB |
820 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, |
821 | struct iwl_rxon_context *ctx) | |
8ccde88a | 822 | { |
246ed355 | 823 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a | 824 | |
e1623446 | 825 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
3d816c77 | 826 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
827 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
828 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
829 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 830 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
831 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
832 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 833 | rxon->ofdm_basic_rates); |
e1623446 TW |
834 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
835 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
836 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
837 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a | 838 | } |
6686d17e | 839 | #endif |
e649437f | 840 | |
e74fe233 JB |
841 | static void iwlagn_abort_notification_waits(struct iwl_priv *priv) |
842 | { | |
843 | unsigned long flags; | |
844 | struct iwl_notification_wait *wait_entry; | |
845 | ||
898ed67b WYG |
846 | spin_lock_irqsave(&priv->notif_wait_lock, flags); |
847 | list_for_each_entry(wait_entry, &priv->notif_waits, list) | |
e74fe233 | 848 | wait_entry->aborted = true; |
898ed67b | 849 | spin_unlock_irqrestore(&priv->notif_wait_lock, flags); |
e74fe233 | 850 | |
898ed67b | 851 | wake_up_all(&priv->notif_waitq); |
e74fe233 JB |
852 | } |
853 | ||
e649437f | 854 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) |
8ccde88a | 855 | { |
491bc292 WYG |
856 | unsigned int reload_msec; |
857 | unsigned long reload_jiffies; | |
858 | ||
8ccde88a | 859 | /* Set the FW error flag -- cleared on iwl_down */ |
63013ae3 | 860 | set_bit(STATUS_FW_ERROR, &priv->shrd->status); |
8ccde88a SO |
861 | |
862 | /* Cancel currently queued command. */ | |
63013ae3 | 863 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
8ccde88a | 864 | |
e74fe233 JB |
865 | iwlagn_abort_notification_waits(priv); |
866 | ||
e649437f JB |
867 | /* Keep the restart process from trying to send host |
868 | * commands by clearing the ready bit */ | |
63013ae3 | 869 | clear_bit(STATUS_READY, &priv->shrd->status); |
e649437f JB |
870 | |
871 | wake_up_interruptible(&priv->wait_command_queue); | |
872 | ||
873 | if (!ondemand) { | |
874 | /* | |
875 | * If firmware keep reloading, then it indicate something | |
876 | * serious wrong and firmware having problem to recover | |
877 | * from it. Instead of keep trying which will fill the syslog | |
878 | * and hang the system, let's just stop it | |
879 | */ | |
880 | reload_jiffies = jiffies; | |
881 | reload_msec = jiffies_to_msecs((long) reload_jiffies - | |
882 | (long) priv->reload_jiffies); | |
883 | priv->reload_jiffies = reload_jiffies; | |
884 | if (reload_msec <= IWL_MIN_RELOAD_DURATION) { | |
885 | priv->reload_count++; | |
886 | if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) { | |
887 | IWL_ERR(priv, "BUG_ON, Stop restarting\n"); | |
888 | return; | |
889 | } | |
890 | } else | |
891 | priv->reload_count = 0; | |
892 | } | |
893 | ||
63013ae3 | 894 | if (!test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) { |
9d143e9a | 895 | if (iwlagn_mod_params.restart_fw) { |
9ca06f0a | 896 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f | 897 | "Restarting adapter due to uCode error.\n"); |
74e28e44 | 898 | queue_work(priv->shrd->workqueue, &priv->restart); |
e649437f | 899 | } else |
9ca06f0a | 900 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f JB |
901 | "Detected FW error, but not restarting\n"); |
902 | } | |
903 | } | |
904 | ||
f8e200de | 905 | static int iwl_apm_stop_master(struct iwl_priv *priv) |
d68b603c | 906 | { |
5220af0c | 907 | int ret = 0; |
d68b603c | 908 | |
5220af0c | 909 | /* stop device's busmaster DMA activity */ |
d68b603c AK |
910 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
911 | ||
5220af0c | 912 | ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, |
d68b603c | 913 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
5220af0c BC |
914 | if (ret) |
915 | IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n"); | |
d68b603c | 916 | |
d68b603c AK |
917 | IWL_DEBUG_INFO(priv, "stop master\n"); |
918 | ||
5220af0c | 919 | return ret; |
d68b603c | 920 | } |
d68b603c AK |
921 | |
922 | void iwl_apm_stop(struct iwl_priv *priv) | |
923 | { | |
fadb3582 BC |
924 | IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n"); |
925 | ||
63013ae3 | 926 | clear_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status); |
9d39e5ba | 927 | |
5220af0c | 928 | /* Stop device's DMA activity */ |
d68b603c AK |
929 | iwl_apm_stop_master(priv); |
930 | ||
5220af0c | 931 | /* Reset the entire device */ |
d68b603c AK |
932 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
933 | ||
934 | udelay(10); | |
5220af0c BC |
935 | |
936 | /* | |
937 | * Clear "initialization complete" bit to move adapter from | |
938 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
939 | */ | |
d68b603c | 940 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
d68b603c | 941 | } |
d68b603c | 942 | |
fadb3582 BC |
943 | |
944 | /* | |
945 | * Start up NIC's basic functionality after it has been reset | |
946 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
947 | * NOTE: This does not load uCode nor start the embedded processor | |
948 | */ | |
949 | int iwl_apm_init(struct iwl_priv *priv) | |
950 | { | |
951 | int ret = 0; | |
fadb3582 BC |
952 | IWL_DEBUG_INFO(priv, "Init card's basic functions\n"); |
953 | ||
954 | /* | |
955 | * Use "set_bit" below rather than "write", to preserve any hardware | |
956 | * bits already set by default after reset. | |
957 | */ | |
958 | ||
959 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
960 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
961 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
962 | ||
963 | /* | |
964 | * Disable L0s without affecting L1; | |
965 | * don't wait for ICH L0s (ICH bug W/A) | |
966 | */ | |
967 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
968 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
969 | ||
970 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
971 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
972 | ||
973 | /* | |
974 | * Enable HAP INTA (interrupt from management bus) to | |
975 | * wake device's PCI Express link L1a -> L0s | |
fadb3582 BC |
976 | */ |
977 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
978 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
979 | ||
d5934110 | 980 | bus_apm_config(priv->bus); |
fadb3582 BC |
981 | |
982 | /* Configure analog phase-lock-loop before activating to D0A */ | |
7cb1b088 WYG |
983 | if (priv->cfg->base_params->pll_cfg_val) |
984 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, | |
985 | priv->cfg->base_params->pll_cfg_val); | |
fadb3582 BC |
986 | |
987 | /* | |
988 | * Set "initialization complete" bit to move adapter from | |
989 | * D0U* --> D0A* (powered-up active) state. | |
990 | */ | |
991 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
992 | ||
993 | /* | |
994 | * Wait for clock stabilization; once stabilized, access to | |
995 | * device-internal resources is supported, e.g. iwl_write_prph() | |
996 | * and accesses to uCode SRAM. | |
997 | */ | |
998 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
999 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1000 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
1001 | if (ret < 0) { | |
1002 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); | |
1003 | goto out; | |
1004 | } | |
1005 | ||
1006 | /* | |
917b6777 | 1007 | * Enable DMA clock and wait for it to stabilize. |
fadb3582 BC |
1008 | * |
1009 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
1010 | * do not disable clocks. This preserves any hardware bits already | |
1011 | * set by default in "CLK_CTRL_REG" after reset. | |
1012 | */ | |
917b6777 | 1013 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
fadb3582 BC |
1014 | udelay(20); |
1015 | ||
1016 | /* Disable L1-Active */ | |
1017 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
1018 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
1019 | ||
63013ae3 | 1020 | set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status); |
9d39e5ba | 1021 | |
fadb3582 BC |
1022 | out: |
1023 | return ret; | |
1024 | } | |
fadb3582 BC |
1025 | |
1026 | ||
630fe9b6 TW |
1027 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
1028 | { | |
a25a66ac SG |
1029 | int ret; |
1030 | s8 prev_tx_power; | |
f844a709 SG |
1031 | bool defer; |
1032 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
a25a66ac | 1033 | |
6ac2f839 | 1034 | lockdep_assert_held(&priv->shrd->mutex); |
a25a66ac SG |
1035 | |
1036 | if (priv->tx_power_user_lmt == tx_power && !force) | |
1037 | return 0; | |
1038 | ||
b744cb79 WYG |
1039 | if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) { |
1040 | IWL_WARN(priv, | |
1041 | "Requested user TXPOWER %d below lower limit %d.\n", | |
daf518de | 1042 | tx_power, |
b744cb79 | 1043 | IWLAGN_TX_POWER_TARGET_POWER_MIN); |
630fe9b6 TW |
1044 | return -EINVAL; |
1045 | } | |
1046 | ||
dc1b0973 | 1047 | if (tx_power > priv->tx_power_device_lmt) { |
08f2d58d WYG |
1048 | IWL_WARN(priv, |
1049 | "Requested user TXPOWER %d above upper limit %d.\n", | |
dc1b0973 | 1050 | tx_power, priv->tx_power_device_lmt); |
630fe9b6 TW |
1051 | return -EINVAL; |
1052 | } | |
1053 | ||
a25a66ac SG |
1054 | if (!iwl_is_ready_rf(priv)) |
1055 | return -EIO; | |
630fe9b6 | 1056 | |
f844a709 SG |
1057 | /* scan complete and commit_rxon use tx_power_next value, |
1058 | * it always need to be updated for newest request */ | |
a25a66ac | 1059 | priv->tx_power_next = tx_power; |
f844a709 SG |
1060 | |
1061 | /* do not set tx power when scanning or channel changing */ | |
63013ae3 | 1062 | defer = test_bit(STATUS_SCANNING, &priv->shrd->status) || |
f844a709 SG |
1063 | memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)); |
1064 | if (defer && !force) { | |
1065 | IWL_DEBUG_INFO(priv, "Deferring tx power set\n"); | |
a25a66ac | 1066 | return 0; |
5eadd94b | 1067 | } |
630fe9b6 | 1068 | |
a25a66ac SG |
1069 | prev_tx_power = priv->tx_power_user_lmt; |
1070 | priv->tx_power_user_lmt = tx_power; | |
1071 | ||
5beaaf37 | 1072 | ret = iwlagn_send_tx_power(priv); |
a25a66ac SG |
1073 | |
1074 | /* if fail to set tx_power, restore the orig. tx power */ | |
1075 | if (ret) { | |
1076 | priv->tx_power_user_lmt = prev_tx_power; | |
1077 | priv->tx_power_next = prev_tx_power; | |
1078 | } | |
630fe9b6 TW |
1079 | return ret; |
1080 | } | |
630fe9b6 | 1081 | |
65b52bde | 1082 | void iwl_send_bt_config(struct iwl_priv *priv) |
17f841cd SO |
1083 | { |
1084 | struct iwl_bt_cmd bt_cmd = { | |
456d0f76 WYG |
1085 | .lead_time = BT_LEAD_TIME_DEF, |
1086 | .max_kill = BT_MAX_KILL_DEF, | |
17f841cd SO |
1087 | .kill_ack_mask = 0, |
1088 | .kill_cts_mask = 0, | |
1089 | }; | |
1090 | ||
b60eec9b | 1091 | if (!iwlagn_mod_params.bt_coex_active) |
06702a73 WYG |
1092 | bt_cmd.flags = BT_COEX_DISABLE; |
1093 | else | |
1094 | bt_cmd.flags = BT_COEX_ENABLE; | |
1095 | ||
f21dd005 | 1096 | priv->bt_enable_flag = bt_cmd.flags; |
06702a73 WYG |
1097 | IWL_DEBUG_INFO(priv, "BT coex %s\n", |
1098 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); | |
1099 | ||
e6bb4c9c | 1100 | if (iwl_trans_send_cmd_pdu(trans(priv), REPLY_BT_CONFIG, |
e419d62d | 1101 | CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd)) |
65b52bde | 1102 | IWL_ERR(priv, "failed to send BT Coex Config\n"); |
17f841cd | 1103 | } |
17f841cd | 1104 | |
ef8d5529 | 1105 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear) |
49ea8596 | 1106 | { |
ef8d5529 WYG |
1107 | struct iwl_statistics_cmd statistics_cmd = { |
1108 | .configuration_flags = | |
1109 | clear ? IWL_STATS_CONF_CLEAR_STATS : 0, | |
49ea8596 | 1110 | }; |
ef8d5529 WYG |
1111 | |
1112 | if (flags & CMD_ASYNC) | |
e6bb4c9c | 1113 | return iwl_trans_send_cmd_pdu(trans(priv), REPLY_STATISTICS_CMD, |
e419d62d | 1114 | CMD_ASYNC, |
ef8d5529 | 1115 | sizeof(struct iwl_statistics_cmd), |
e419d62d | 1116 | &statistics_cmd); |
ef8d5529 | 1117 | else |
e6bb4c9c | 1118 | return iwl_trans_send_cmd_pdu(trans(priv), REPLY_STATISTICS_CMD, |
e419d62d | 1119 | CMD_SYNC, |
ef8d5529 WYG |
1120 | sizeof(struct iwl_statistics_cmd), |
1121 | &statistics_cmd); | |
49ea8596 | 1122 | } |
7e8c519e | 1123 | |
a83b9141 WYG |
1124 | void iwl_clear_isr_stats(struct iwl_priv *priv) |
1125 | { | |
1126 | memset(&priv->isr_stats, 0, sizeof(priv->isr_stats)); | |
1127 | } | |
a83b9141 | 1128 | |
488829f1 AK |
1129 | int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
1130 | const struct ieee80211_tx_queue_params *params) | |
1131 | { | |
1132 | struct iwl_priv *priv = hw->priv; | |
8dfdb9d5 | 1133 | struct iwl_rxon_context *ctx; |
488829f1 AK |
1134 | unsigned long flags; |
1135 | int q; | |
1136 | ||
1137 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
1138 | ||
1139 | if (!iwl_is_ready_rf(priv)) { | |
1140 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
1141 | return -EIO; | |
1142 | } | |
1143 | ||
1144 | if (queue >= AC_NUM) { | |
1145 | IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue); | |
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | q = AC_NUM - 1 - queue; | |
1150 | ||
10b15e6f | 1151 | spin_lock_irqsave(&priv->shrd->lock, flags); |
488829f1 | 1152 | |
8dfdb9d5 JB |
1153 | /* |
1154 | * MULTI-FIXME | |
1155 | * This may need to be done per interface in nl80211/cfg80211/mac80211. | |
1156 | */ | |
1157 | for_each_context(priv, ctx) { | |
1158 | ctx->qos_data.def_qos_parm.ac[q].cw_min = | |
1159 | cpu_to_le16(params->cw_min); | |
1160 | ctx->qos_data.def_qos_parm.ac[q].cw_max = | |
1161 | cpu_to_le16(params->cw_max); | |
1162 | ctx->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
1163 | ctx->qos_data.def_qos_parm.ac[q].edca_txop = | |
1164 | cpu_to_le16((params->txop * 32)); | |
1165 | ||
1166 | ctx->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
1167 | } | |
488829f1 | 1168 | |
10b15e6f | 1169 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
488829f1 AK |
1170 | |
1171 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
1172 | return 0; | |
1173 | } | |
5bbe233b | 1174 | |
a85d7cca JB |
1175 | int iwl_mac_tx_last_beacon(struct ieee80211_hw *hw) |
1176 | { | |
1177 | struct iwl_priv *priv = hw->priv; | |
1178 | ||
1179 | return priv->ibss_manager == IWL_IBSS_MANAGER; | |
1180 | } | |
a85d7cca | 1181 | |
d4daaea6 | 1182 | static int iwl_set_mode(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
727882d6 | 1183 | { |
d0fe478c | 1184 | iwl_connection_init_rx_config(priv, ctx); |
727882d6 | 1185 | |
e3f10cea | 1186 | iwlagn_set_rxon_chain(priv, ctx); |
727882d6 | 1187 | |
805a3b81 | 1188 | return iwlagn_commit_rxon(priv, ctx); |
727882d6 | 1189 | } |
727882d6 | 1190 | |
d4daaea6 JB |
1191 | static int iwl_setup_interface(struct iwl_priv *priv, |
1192 | struct iwl_rxon_context *ctx) | |
1193 | { | |
1194 | struct ieee80211_vif *vif = ctx->vif; | |
1195 | int err; | |
1196 | ||
6ac2f839 | 1197 | lockdep_assert_held(&priv->shrd->mutex); |
d4daaea6 JB |
1198 | |
1199 | /* | |
1200 | * This variable will be correct only when there's just | |
1201 | * a single context, but all code using it is for hardware | |
1202 | * that supports only one context. | |
1203 | */ | |
1204 | priv->iw_mode = vif->type; | |
1205 | ||
1206 | ctx->is_active = true; | |
1207 | ||
1208 | err = iwl_set_mode(priv, ctx); | |
1209 | if (err) { | |
1210 | if (!ctx->always_active) | |
1211 | ctx->is_active = false; | |
1212 | return err; | |
1213 | } | |
1214 | ||
1215 | if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist && | |
1216 | vif->type == NL80211_IFTYPE_ADHOC) { | |
1217 | /* | |
1218 | * pretend to have high BT traffic as long as we | |
1219 | * are operating in IBSS mode, as this will cause | |
1220 | * the rate scaling etc. to behave as intended. | |
1221 | */ | |
1222 | priv->bt_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_HIGH; | |
1223 | } | |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | ||
b55e75ed | 1228 | int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
cbb6ab94 AK |
1229 | { |
1230 | struct iwl_priv *priv = hw->priv; | |
246ed355 | 1231 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
d0fe478c | 1232 | struct iwl_rxon_context *tmp, *ctx = NULL; |
d4daaea6 | 1233 | int err; |
f35c0c56 | 1234 | enum nl80211_iftype viftype = ieee80211_vif_type_p2p(vif); |
cbb6ab94 | 1235 | |
3779db10 | 1236 | IWL_DEBUG_MAC80211(priv, "enter: type %d, addr %pM\n", |
f35c0c56 | 1237 | viftype, vif->addr); |
cbb6ab94 | 1238 | |
c6baf7fb JB |
1239 | cancel_delayed_work_sync(&priv->hw_roc_disable_work); |
1240 | ||
6ac2f839 | 1241 | mutex_lock(&priv->shrd->mutex); |
47e28f41 | 1242 | |
c6baf7fb JB |
1243 | iwlagn_disable_roc(priv); |
1244 | ||
4bd530f3 SG |
1245 | if (!iwl_is_ready_rf(priv)) { |
1246 | IWL_WARN(priv, "Try to add interface when device not ready\n"); | |
b55e75ed JB |
1247 | err = -EINVAL; |
1248 | goto out; | |
1249 | } | |
1250 | ||
d0fe478c JB |
1251 | for_each_context(priv, tmp) { |
1252 | u32 possible_modes = | |
1253 | tmp->interface_modes | tmp->exclusive_interface_modes; | |
1254 | ||
1255 | if (tmp->vif) { | |
1256 | /* check if this busy context is exclusive */ | |
1257 | if (tmp->exclusive_interface_modes & | |
1258 | BIT(tmp->vif->type)) { | |
1259 | err = -EINVAL; | |
1260 | goto out; | |
1261 | } | |
1262 | continue; | |
1263 | } | |
1264 | ||
f35c0c56 | 1265 | if (!(possible_modes & BIT(viftype))) |
d0fe478c JB |
1266 | continue; |
1267 | ||
1268 | /* have maybe usable context w/o interface */ | |
1269 | ctx = tmp; | |
1270 | break; | |
1271 | } | |
1272 | ||
1273 | if (!ctx) { | |
47e28f41 JB |
1274 | err = -EOPNOTSUPP; |
1275 | goto out; | |
cbb6ab94 AK |
1276 | } |
1277 | ||
d0fe478c | 1278 | vif_priv->ctx = ctx; |
8bd413e6 | 1279 | ctx->vif = vif; |
59079949 | 1280 | |
d4daaea6 JB |
1281 | err = iwl_setup_interface(priv, ctx); |
1282 | if (!err) | |
1283 | goto out; | |
cbb6ab94 | 1284 | |
8bd413e6 | 1285 | ctx->vif = NULL; |
b55e75ed | 1286 | priv->iw_mode = NL80211_IFTYPE_STATION; |
47e28f41 | 1287 | out: |
6ac2f839 | 1288 | mutex_unlock(&priv->shrd->mutex); |
cbb6ab94 AK |
1289 | |
1290 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
47e28f41 | 1291 | return err; |
cbb6ab94 | 1292 | } |
cbb6ab94 | 1293 | |
d4daaea6 JB |
1294 | static void iwl_teardown_interface(struct iwl_priv *priv, |
1295 | struct ieee80211_vif *vif, | |
1296 | bool mode_change) | |
d8052319 | 1297 | { |
246ed355 | 1298 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); |
d8052319 | 1299 | |
6ac2f839 | 1300 | lockdep_assert_held(&priv->shrd->mutex); |
d0fe478c | 1301 | |
e7e16b90 SG |
1302 | if (priv->scan_vif == vif) { |
1303 | iwl_scan_cancel_timeout(priv, 200); | |
1304 | iwl_force_scan_end(priv); | |
1305 | } | |
8bd413e6 | 1306 | |
d4daaea6 JB |
1307 | if (!mode_change) { |
1308 | iwl_set_mode(priv, ctx); | |
1309 | if (!ctx->always_active) | |
1310 | ctx->is_active = false; | |
1311 | } | |
763cc3bf | 1312 | |
59079949 JB |
1313 | /* |
1314 | * When removing the IBSS interface, overwrite the | |
1315 | * BT traffic load with the stored one from the last | |
1316 | * notification, if any. If this is a device that | |
1317 | * doesn't implement this, this has no effect since | |
1318 | * both values are the same and zero. | |
1319 | */ | |
1320 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
66e863a5 | 1321 | priv->bt_traffic_load = priv->last_bt_traffic_load; |
d4daaea6 JB |
1322 | } |
1323 | ||
1324 | void iwl_mac_remove_interface(struct ieee80211_hw *hw, | |
1325 | struct ieee80211_vif *vif) | |
1326 | { | |
1327 | struct iwl_priv *priv = hw->priv; | |
1328 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); | |
1329 | ||
1330 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
1331 | ||
6ac2f839 | 1332 | mutex_lock(&priv->shrd->mutex); |
d4daaea6 JB |
1333 | |
1334 | WARN_ON(ctx->vif != vif); | |
1335 | ctx->vif = NULL; | |
1336 | ||
1337 | iwl_teardown_interface(priv, vif, false); | |
59079949 | 1338 | |
6ac2f839 | 1339 | mutex_unlock(&priv->shrd->mutex); |
d8052319 AK |
1340 | |
1341 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
1342 | ||
1343 | } | |
d8052319 | 1344 | |
20594eb0 WYG |
1345 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1346 | ||
1347 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) | |
1348 | ||
1349 | void iwl_reset_traffic_log(struct iwl_priv *priv) | |
1350 | { | |
1351 | priv->tx_traffic_idx = 0; | |
1352 | priv->rx_traffic_idx = 0; | |
1353 | if (priv->tx_traffic) | |
1354 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1355 | if (priv->rx_traffic) | |
1356 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1357 | } | |
1358 | ||
1359 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) | |
1360 | { | |
1361 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; | |
1362 | ||
8f470ce3 | 1363 | if (iwl_get_debug_level(priv->shrd) & IWL_DL_TX) { |
20594eb0 WYG |
1364 | if (!priv->tx_traffic) { |
1365 | priv->tx_traffic = | |
1366 | kzalloc(traffic_size, GFP_KERNEL); | |
1367 | if (!priv->tx_traffic) | |
1368 | return -ENOMEM; | |
1369 | } | |
1370 | } | |
8f470ce3 | 1371 | if (iwl_get_debug_level(priv->shrd) & IWL_DL_RX) { |
20594eb0 WYG |
1372 | if (!priv->rx_traffic) { |
1373 | priv->rx_traffic = | |
1374 | kzalloc(traffic_size, GFP_KERNEL); | |
1375 | if (!priv->rx_traffic) | |
1376 | return -ENOMEM; | |
1377 | } | |
1378 | } | |
1379 | iwl_reset_traffic_log(priv); | |
1380 | return 0; | |
1381 | } | |
20594eb0 WYG |
1382 | |
1383 | void iwl_free_traffic_mem(struct iwl_priv *priv) | |
1384 | { | |
1385 | kfree(priv->tx_traffic); | |
1386 | priv->tx_traffic = NULL; | |
1387 | ||
1388 | kfree(priv->rx_traffic); | |
1389 | priv->rx_traffic = NULL; | |
1390 | } | |
20594eb0 WYG |
1391 | |
1392 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | |
1393 | u16 length, struct ieee80211_hdr *header) | |
1394 | { | |
1395 | __le16 fc; | |
1396 | u16 len; | |
1397 | ||
8f470ce3 | 1398 | if (likely(!(iwl_get_debug_level(priv->shrd) & IWL_DL_TX))) |
20594eb0 WYG |
1399 | return; |
1400 | ||
1401 | if (!priv->tx_traffic) | |
1402 | return; | |
1403 | ||
1404 | fc = header->frame_control; | |
1405 | if (ieee80211_is_data(fc)) { | |
1406 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1407 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1408 | memcpy((priv->tx_traffic + | |
1409 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1410 | header, len); | |
1411 | priv->tx_traffic_idx = | |
1412 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1413 | } | |
1414 | } | |
20594eb0 WYG |
1415 | |
1416 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | |
1417 | u16 length, struct ieee80211_hdr *header) | |
1418 | { | |
1419 | __le16 fc; | |
1420 | u16 len; | |
1421 | ||
8f470ce3 | 1422 | if (likely(!(iwl_get_debug_level(priv->shrd) & IWL_DL_RX))) |
20594eb0 WYG |
1423 | return; |
1424 | ||
1425 | if (!priv->rx_traffic) | |
1426 | return; | |
1427 | ||
1428 | fc = header->frame_control; | |
1429 | if (ieee80211_is_data(fc)) { | |
1430 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1431 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1432 | memcpy((priv->rx_traffic + | |
1433 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1434 | header, len); | |
1435 | priv->rx_traffic_idx = | |
1436 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1437 | } | |
1438 | } | |
22fdf3c9 WYG |
1439 | |
1440 | const char *get_mgmt_string(int cmd) | |
1441 | { | |
1442 | switch (cmd) { | |
1443 | IWL_CMD(MANAGEMENT_ASSOC_REQ); | |
1444 | IWL_CMD(MANAGEMENT_ASSOC_RESP); | |
1445 | IWL_CMD(MANAGEMENT_REASSOC_REQ); | |
1446 | IWL_CMD(MANAGEMENT_REASSOC_RESP); | |
1447 | IWL_CMD(MANAGEMENT_PROBE_REQ); | |
1448 | IWL_CMD(MANAGEMENT_PROBE_RESP); | |
1449 | IWL_CMD(MANAGEMENT_BEACON); | |
1450 | IWL_CMD(MANAGEMENT_ATIM); | |
1451 | IWL_CMD(MANAGEMENT_DISASSOC); | |
1452 | IWL_CMD(MANAGEMENT_AUTH); | |
1453 | IWL_CMD(MANAGEMENT_DEAUTH); | |
1454 | IWL_CMD(MANAGEMENT_ACTION); | |
1455 | default: | |
1456 | return "UNKNOWN"; | |
1457 | ||
1458 | } | |
1459 | } | |
1460 | ||
1461 | const char *get_ctrl_string(int cmd) | |
1462 | { | |
1463 | switch (cmd) { | |
1464 | IWL_CMD(CONTROL_BACK_REQ); | |
1465 | IWL_CMD(CONTROL_BACK); | |
1466 | IWL_CMD(CONTROL_PSPOLL); | |
1467 | IWL_CMD(CONTROL_RTS); | |
1468 | IWL_CMD(CONTROL_CTS); | |
1469 | IWL_CMD(CONTROL_ACK); | |
1470 | IWL_CMD(CONTROL_CFEND); | |
1471 | IWL_CMD(CONTROL_CFENDACK); | |
1472 | default: | |
1473 | return "UNKNOWN"; | |
1474 | ||
1475 | } | |
1476 | } | |
1477 | ||
7163b8a4 | 1478 | void iwl_clear_traffic_stats(struct iwl_priv *priv) |
22fdf3c9 WYG |
1479 | { |
1480 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); | |
22fdf3c9 WYG |
1481 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); |
1482 | } | |
1483 | ||
1484 | /* | |
1485 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will | |
1486 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. | |
1487 | * Use debugFs to display the rx/rx_statistics | |
1488 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL | |
1489 | * information will be recorded, but DATA pkt still will be recorded | |
1490 | * for the reason of iwl_led.c need to control the led blinking based on | |
1491 | * number of tx and rx data. | |
1492 | * | |
1493 | */ | |
1494 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) | |
1495 | { | |
1496 | struct traffic_stats *stats; | |
1497 | ||
1498 | if (is_tx) | |
1499 | stats = &priv->tx_stats; | |
1500 | else | |
1501 | stats = &priv->rx_stats; | |
1502 | ||
1503 | if (ieee80211_is_mgmt(fc)) { | |
1504 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1505 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
1506 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
1507 | break; | |
1508 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
1509 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
1510 | break; | |
1511 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
1512 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
1513 | break; | |
1514 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
1515 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
1516 | break; | |
1517 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
1518 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
1519 | break; | |
1520 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
1521 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
1522 | break; | |
1523 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
1524 | stats->mgmt[MANAGEMENT_BEACON]++; | |
1525 | break; | |
1526 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
1527 | stats->mgmt[MANAGEMENT_ATIM]++; | |
1528 | break; | |
1529 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
1530 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
1531 | break; | |
1532 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
1533 | stats->mgmt[MANAGEMENT_AUTH]++; | |
1534 | break; | |
1535 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
1536 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
1537 | break; | |
1538 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
1539 | stats->mgmt[MANAGEMENT_ACTION]++; | |
1540 | break; | |
1541 | } | |
1542 | } else if (ieee80211_is_ctl(fc)) { | |
1543 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1544 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
1545 | stats->ctrl[CONTROL_BACK_REQ]++; | |
1546 | break; | |
1547 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
1548 | stats->ctrl[CONTROL_BACK]++; | |
1549 | break; | |
1550 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
1551 | stats->ctrl[CONTROL_PSPOLL]++; | |
1552 | break; | |
1553 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
1554 | stats->ctrl[CONTROL_RTS]++; | |
1555 | break; | |
1556 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
1557 | stats->ctrl[CONTROL_CTS]++; | |
1558 | break; | |
1559 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
1560 | stats->ctrl[CONTROL_ACK]++; | |
1561 | break; | |
1562 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
1563 | stats->ctrl[CONTROL_CFEND]++; | |
1564 | break; | |
1565 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
1566 | stats->ctrl[CONTROL_CFENDACK]++; | |
1567 | break; | |
1568 | } | |
1569 | } else { | |
1570 | /* data */ | |
1571 | stats->data_cnt++; | |
1572 | stats->data_bytes += len; | |
1573 | } | |
1574 | } | |
20594eb0 WYG |
1575 | #endif |
1576 | ||
a93e7973 | 1577 | static void iwl_force_rf_reset(struct iwl_priv *priv) |
afbdd69a | 1578 | { |
63013ae3 | 1579 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
afbdd69a WYG |
1580 | return; |
1581 | ||
246ed355 | 1582 | if (!iwl_is_any_associated(priv)) { |
afbdd69a WYG |
1583 | IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n"); |
1584 | return; | |
1585 | } | |
1586 | /* | |
1587 | * There is no easy and better way to force reset the radio, | |
1588 | * the only known method is switching channel which will force to | |
1589 | * reset and tune the radio. | |
1590 | * Use internal short scan (single channel) operation to should | |
1591 | * achieve this objective. | |
1592 | * Driver should reset the radio when number of consecutive missed | |
1593 | * beacon, or any other uCode error condition detected. | |
1594 | */ | |
1595 | IWL_DEBUG_INFO(priv, "perform radio reset.\n"); | |
1596 | iwl_internal_short_hw_scan(priv); | |
afbdd69a | 1597 | } |
a93e7973 | 1598 | |
a93e7973 | 1599 | |
c04f9f22 | 1600 | int iwl_force_reset(struct iwl_priv *priv, int mode, bool external) |
a93e7973 | 1601 | { |
8a472da4 WYG |
1602 | struct iwl_force_reset *force_reset; |
1603 | ||
63013ae3 | 1604 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
a93e7973 WYG |
1605 | return -EINVAL; |
1606 | ||
8a472da4 WYG |
1607 | if (mode >= IWL_MAX_FORCE_RESET) { |
1608 | IWL_DEBUG_INFO(priv, "invalid reset request.\n"); | |
1609 | return -EINVAL; | |
1610 | } | |
1611 | force_reset = &priv->force_reset[mode]; | |
1612 | force_reset->reset_request_count++; | |
c04f9f22 WYG |
1613 | if (!external) { |
1614 | if (force_reset->last_force_reset_jiffies && | |
1615 | time_after(force_reset->last_force_reset_jiffies + | |
1616 | force_reset->reset_duration, jiffies)) { | |
1617 | IWL_DEBUG_INFO(priv, "force reset rejected\n"); | |
1618 | force_reset->reset_reject_count++; | |
1619 | return -EAGAIN; | |
1620 | } | |
a93e7973 | 1621 | } |
8a472da4 WYG |
1622 | force_reset->reset_success_count++; |
1623 | force_reset->last_force_reset_jiffies = jiffies; | |
a93e7973 | 1624 | IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode); |
a93e7973 WYG |
1625 | switch (mode) { |
1626 | case IWL_RF_RESET: | |
1627 | iwl_force_rf_reset(priv); | |
1628 | break; | |
1629 | case IWL_FW_RESET: | |
c04f9f22 WYG |
1630 | /* |
1631 | * if the request is from external(ex: debugfs), | |
1632 | * then always perform the request in regardless the module | |
1633 | * parameter setting | |
1634 | * if the request is from internal (uCode error or driver | |
1635 | * detect failure), then fw_restart module parameter | |
1636 | * need to be check before performing firmware reload | |
1637 | */ | |
9d143e9a | 1638 | if (!external && !iwlagn_mod_params.restart_fw) { |
c04f9f22 WYG |
1639 | IWL_DEBUG_INFO(priv, "Cancel firmware reload based on " |
1640 | "module parameter setting\n"); | |
1641 | break; | |
1642 | } | |
a93e7973 | 1643 | IWL_ERR(priv, "On demand firmware reload\n"); |
e649437f | 1644 | iwlagn_fw_error(priv, true); |
a93e7973 | 1645 | break; |
a93e7973 | 1646 | } |
a93e7973 WYG |
1647 | return 0; |
1648 | } | |
b74e31a9 | 1649 | |
d4daaea6 JB |
1650 | int iwl_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1651 | enum nl80211_iftype newtype, bool newp2p) | |
1652 | { | |
1653 | struct iwl_priv *priv = hw->priv; | |
1654 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); | |
ebf8dc80 | 1655 | struct iwl_rxon_context *bss_ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
d4daaea6 | 1656 | struct iwl_rxon_context *tmp; |
5306c080 | 1657 | enum nl80211_iftype newviftype = newtype; |
d4daaea6 JB |
1658 | u32 interface_modes; |
1659 | int err; | |
1660 | ||
1661 | newtype = ieee80211_iftype_p2p(newtype, newp2p); | |
1662 | ||
6ac2f839 | 1663 | mutex_lock(&priv->shrd->mutex); |
d4daaea6 | 1664 | |
a2b76b3b JB |
1665 | if (!ctx->vif || !iwl_is_ready_rf(priv)) { |
1666 | /* | |
1667 | * Huh? But wait ... this can maybe happen when | |
1668 | * we're in the middle of a firmware restart! | |
1669 | */ | |
1670 | err = -EBUSY; | |
1671 | goto out; | |
1672 | } | |
1673 | ||
d4daaea6 JB |
1674 | interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes; |
1675 | ||
1676 | if (!(interface_modes & BIT(newtype))) { | |
1677 | err = -EBUSY; | |
1678 | goto out; | |
1679 | } | |
1680 | ||
ebf8dc80 JB |
1681 | /* |
1682 | * Refuse a change that should be done by moving from the PAN | |
1683 | * context to the BSS context instead, if the BSS context is | |
1684 | * available and can support the new interface type. | |
1685 | */ | |
1686 | if (ctx->ctxid == IWL_RXON_CTX_PAN && !bss_ctx->vif && | |
1687 | (bss_ctx->interface_modes & BIT(newtype) || | |
1688 | bss_ctx->exclusive_interface_modes & BIT(newtype))) { | |
1689 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | |
1690 | err = -EBUSY; | |
1691 | goto out; | |
1692 | } | |
1693 | ||
d4daaea6 JB |
1694 | if (ctx->exclusive_interface_modes & BIT(newtype)) { |
1695 | for_each_context(priv, tmp) { | |
1696 | if (ctx == tmp) | |
1697 | continue; | |
1698 | ||
1699 | if (!tmp->vif) | |
1700 | continue; | |
1701 | ||
1702 | /* | |
1703 | * The current mode switch would be exclusive, but | |
1704 | * another context is active ... refuse the switch. | |
1705 | */ | |
1706 | err = -EBUSY; | |
1707 | goto out; | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | /* success */ | |
1712 | iwl_teardown_interface(priv, vif, true); | |
5306c080 | 1713 | vif->type = newviftype; |
a2b76b3b | 1714 | vif->p2p = newp2p; |
d4daaea6 JB |
1715 | err = iwl_setup_interface(priv, ctx); |
1716 | WARN_ON(err); | |
1717 | /* | |
1718 | * We've switched internally, but submitting to the | |
1719 | * device may have failed for some reason. Mask this | |
1720 | * error, because otherwise mac80211 will not switch | |
1721 | * (and set the interface type back) and we'll be | |
1722 | * out of sync with it. | |
1723 | */ | |
1724 | err = 0; | |
1725 | ||
1726 | out: | |
6ac2f839 | 1727 | mutex_unlock(&priv->shrd->mutex); |
d4daaea6 JB |
1728 | return err; |
1729 | } | |
d4daaea6 | 1730 | |
b74e31a9 | 1731 | /* |
22de94de SG |
1732 | * On every watchdog tick we check (latest) time stamp. If it does not |
1733 | * change during timeout period and queue is not empty we reset firmware. | |
b74e31a9 | 1734 | */ |
b74e31a9 WYG |
1735 | static int iwl_check_stuck_queue(struct iwl_priv *priv, int cnt) |
1736 | { | |
22de94de SG |
1737 | struct iwl_tx_queue *txq = &priv->txq[cnt]; |
1738 | struct iwl_queue *q = &txq->q; | |
1739 | unsigned long timeout; | |
1740 | int ret; | |
b74e31a9 | 1741 | |
22de94de SG |
1742 | if (q->read_ptr == q->write_ptr) { |
1743 | txq->time_stamp = jiffies; | |
7cb1b088 | 1744 | return 0; |
22de94de | 1745 | } |
7cb1b088 | 1746 | |
22de94de SG |
1747 | timeout = txq->time_stamp + |
1748 | msecs_to_jiffies(priv->cfg->base_params->wd_timeout); | |
1749 | ||
1750 | if (time_after(jiffies, timeout)) { | |
1751 | IWL_ERR(priv, "Queue %d stuck for %u ms.\n", | |
1752 | q->id, priv->cfg->base_params->wd_timeout); | |
1753 | ret = iwl_force_reset(priv, IWL_FW_RESET, false); | |
1754 | return (ret == -EAGAIN) ? 0 : 1; | |
b74e31a9 | 1755 | } |
22de94de | 1756 | |
b74e31a9 WYG |
1757 | return 0; |
1758 | } | |
1759 | ||
22de94de SG |
1760 | /* |
1761 | * Making watchdog tick be a quarter of timeout assure we will | |
1762 | * discover the queue hung between timeout and 1.25*timeout | |
1763 | */ | |
1764 | #define IWL_WD_TICK(timeout) ((timeout) / 4) | |
1765 | ||
1766 | /* | |
1767 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
1768 | * we reset the firmware. If everything is fine just rearm the timer. | |
1769 | */ | |
1770 | void iwl_bg_watchdog(unsigned long data) | |
b74e31a9 WYG |
1771 | { |
1772 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
1773 | int cnt; | |
22de94de | 1774 | unsigned long timeout; |
b74e31a9 | 1775 | |
63013ae3 | 1776 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
b74e31a9 WYG |
1777 | return; |
1778 | ||
22de94de SG |
1779 | timeout = priv->cfg->base_params->wd_timeout; |
1780 | if (timeout == 0) | |
1781 | return; | |
1782 | ||
b74e31a9 | 1783 | /* monitor and check for stuck cmd queue */ |
cefeaa5f | 1784 | if (iwl_check_stuck_queue(priv, priv->shrd->cmd_queue)) |
b74e31a9 WYG |
1785 | return; |
1786 | ||
1787 | /* monitor and check for other stuck queues */ | |
246ed355 | 1788 | if (iwl_is_any_associated(priv)) { |
d6189124 | 1789 | for (cnt = 0; cnt < hw_params(priv).max_txq_num; cnt++) { |
b74e31a9 | 1790 | /* skip as we already checked the command queue */ |
cefeaa5f | 1791 | if (cnt == priv->shrd->cmd_queue) |
b74e31a9 WYG |
1792 | continue; |
1793 | if (iwl_check_stuck_queue(priv, cnt)) | |
1794 | return; | |
1795 | } | |
1796 | } | |
22de94de SG |
1797 | |
1798 | mod_timer(&priv->watchdog, jiffies + | |
1799 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
b74e31a9 | 1800 | } |
22de94de SG |
1801 | |
1802 | void iwl_setup_watchdog(struct iwl_priv *priv) | |
1803 | { | |
1804 | unsigned int timeout = priv->cfg->base_params->wd_timeout; | |
afbdd69a | 1805 | |
300d0834 | 1806 | if (timeout && !iwlagn_mod_params.wd_disable) |
22de94de SG |
1807 | mod_timer(&priv->watchdog, |
1808 | jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1809 | else | |
1810 | del_timer(&priv->watchdog); | |
1811 | } | |
a0ee74cf WYG |
1812 | |
1813 | /* | |
1814 | * extended beacon time format | |
1815 | * time in usec will be changed into a 32-bit value in extended:internal format | |
1816 | * the extended part is the beacon counts | |
1817 | * the internal part is the time in usec within one beacon interval | |
1818 | */ | |
1819 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval) | |
1820 | { | |
1821 | u32 quot; | |
1822 | u32 rem; | |
1823 | u32 interval = beacon_interval * TIME_UNIT; | |
1824 | ||
1825 | if (!interval || !usec) | |
1826 | return 0; | |
1827 | ||
1828 | quot = (usec / interval) & | |
1829 | (iwl_beacon_time_mask_high(priv, | |
d6189124 EG |
1830 | hw_params(priv).beacon_time_tsf_bits) >> |
1831 | hw_params(priv).beacon_time_tsf_bits); | |
a0ee74cf | 1832 | rem = (usec % interval) & iwl_beacon_time_mask_low(priv, |
d6189124 | 1833 | hw_params(priv).beacon_time_tsf_bits); |
a0ee74cf | 1834 | |
d6189124 | 1835 | return (quot << hw_params(priv).beacon_time_tsf_bits) + rem; |
a0ee74cf | 1836 | } |
a0ee74cf WYG |
1837 | |
1838 | /* base is usually what we get from ucode with each received frame, | |
1839 | * the same as HW timer counter counting down | |
1840 | */ | |
1841 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | |
1842 | u32 addon, u32 beacon_interval) | |
1843 | { | |
1844 | u32 base_low = base & iwl_beacon_time_mask_low(priv, | |
d6189124 | 1845 | hw_params(priv).beacon_time_tsf_bits); |
a0ee74cf | 1846 | u32 addon_low = addon & iwl_beacon_time_mask_low(priv, |
d6189124 | 1847 | hw_params(priv).beacon_time_tsf_bits); |
a0ee74cf WYG |
1848 | u32 interval = beacon_interval * TIME_UNIT; |
1849 | u32 res = (base & iwl_beacon_time_mask_high(priv, | |
d6189124 | 1850 | hw_params(priv).beacon_time_tsf_bits)) + |
a0ee74cf | 1851 | (addon & iwl_beacon_time_mask_high(priv, |
d6189124 | 1852 | hw_params(priv).beacon_time_tsf_bits)); |
a0ee74cf WYG |
1853 | |
1854 | if (base_low > addon_low) | |
1855 | res += base_low - addon_low; | |
1856 | else if (base_low < addon_low) { | |
1857 | res += interval + base_low - addon_low; | |
d6189124 | 1858 | res += (1 << hw_params(priv).beacon_time_tsf_bits); |
a0ee74cf | 1859 | } else |
d6189124 | 1860 | res += (1 << hw_params(priv).beacon_time_tsf_bits); |
a0ee74cf WYG |
1861 | |
1862 | return cpu_to_le32(res); | |
1863 | } | |
a0ee74cf | 1864 |