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net/libertas: don't recursive spin lock in if_spi_e2h()
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
ef850d7c
MA		 62static irqreturn_t iwl_isr(int irq, void *data);
63
c7de35cd
RR		 64/*
65 * Parameter order:
66 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
67 *
68 * If there isn't a valid next or previous rate then INV is used which
69 * maps to IWL_RATE_INVALID
70 *
71 */
1826dcc0 72const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 73 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
74 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
75 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
76 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
77 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
78 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
79 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
80 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
81 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
82 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
83 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
84 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
85 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
86 /* FIXME:RS: ^^ should be INV (legacy) */
87};
1826dcc0 88EXPORT_SYMBOL(iwl_rates);
c7de35cd 89
e7d326ac
TW		 90/**
91 * translate ucode response to mac80211 tx status control values
92 */
93void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 94 struct ieee80211_tx_info *info)
e7d326ac
TW		 95{
96 int rate_index;
e6a9854b 97 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 98
e6a9854b 99 info->antenna_sel_tx =
e7d326ac
TW		 100 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
101 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 102 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 103 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 104 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
e7d326ac 105 if (rate_n_flags & RATE_MCS_FAT_MSK)
e6a9854b 106 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 107 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 108 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 109 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 110 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 111 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 112 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 113 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 114 r->idx = rate_index;
e7d326ac
TW		 115}
116EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
117
118int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
119{
120 int idx = 0;
121
122 /* HT rate format */
123 if (rate_n_flags & RATE_MCS_HT_MSK) {
124 idx = (rate_n_flags & 0xff);
125
60d32215
DH		 126 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
127 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
128 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 129 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
130
131 idx += IWL_FIRST_OFDM_RATE;
132 /* skip 9M not supported in ht*/
133 if (idx >= IWL_RATE_9M_INDEX)
134 idx += 1;
135 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
136 return idx;
137
138 /* legacy rate format, search for match in table */
139 } else {
140 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
141 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
142 return idx;
143 }
144
145 return -1;
146}
147EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
148
76eff18b
TW		 149u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
150{
151 int i;
152 u8 ind = ant;
153 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
154 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
155 if (priv->hw_params.valid_tx_ant & BIT(ind))
156 return ind;
157 }
158 return ant;
159}
57bd1bea
TW		 160
161const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
162EXPORT_SYMBOL(iwl_bcast_addr);
163
164
1d0a082d
AK		 165/* This function both allocates and initializes hw and priv. */
166struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
167 struct ieee80211_ops *hw_ops)
168{
169 struct iwl_priv *priv;
170
171 /* mac80211 allocates memory for this device instance, including
172 * space for this driver's private structure */
173 struct ieee80211_hw *hw =
174 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
175 if (hw == NULL) {
a3139c59
SO		 176 printk(KERN_ERR "%s: Can not allocate network device\n",
177 cfg->name);
1d0a082d
AK		 178 goto out;
179 }
180
181 priv = hw->priv;
182 priv->hw = hw;
183
184out:
185 return hw;
186}
187EXPORT_SYMBOL(iwl_alloc_all);
188
b661c819
TW		 189void iwl_hw_detect(struct iwl_priv *priv)
190{
191 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
192 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
193 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
194}
195EXPORT_SYMBOL(iwl_hw_detect);
196
1053d35f
RR		 197int iwl_hw_nic_init(struct iwl_priv *priv)
198{
199 unsigned long flags;
200 struct iwl_rx_queue *rxq = &priv->rxq;
201 int ret;
202
203 /* nic_init */
1053d35f 204 spin_lock_irqsave(&priv->lock, flags);
1b73af82 205 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 206 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
207 spin_unlock_irqrestore(&priv->lock, flags);
208
209 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
210
211 priv->cfg->ops->lib->apm_ops.config(priv);
212
213 /* Allocate the RX queue, or reset if it is already allocated */
214 if (!rxq->bd) {
215 ret = iwl_rx_queue_alloc(priv);
216 if (ret) {
15b1687c 217 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 218 return -ENOMEM;
219 }
220 } else
221 iwl_rx_queue_reset(priv, rxq);
222
223 iwl_rx_replenish(priv);
224
225 iwl_rx_init(priv, rxq);
226
227 spin_lock_irqsave(&priv->lock, flags);
228
229 rxq->need_update = 1;
230 iwl_rx_queue_update_write_ptr(priv, rxq);
231
232 spin_unlock_irqrestore(&priv->lock, flags);
233
234 /* Allocate and init all Tx and Command queues */
235 ret = iwl_txq_ctx_reset(priv);
236 if (ret)
237 return ret;
238
239 set_bit(STATUS_INIT, &priv->status);
240
241 return 0;
242}
243EXPORT_SYMBOL(iwl_hw_nic_init);
244
14d2aac5
AK		 245/*
246 * QoS support
247*/
248void iwl_activate_qos(struct iwl_priv *priv, u8 force)
249{
250 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
251 return;
252
253 priv->qos_data.def_qos_parm.qos_flags = 0;
254
255 if (priv->qos_data.qos_cap.q_AP.queue_request &&
256 !priv->qos_data.qos_cap.q_AP.txop_request)
257 priv->qos_data.def_qos_parm.qos_flags |=
258 QOS_PARAM_FLG_TXOP_TYPE_MSK;
259 if (priv->qos_data.qos_active)
260 priv->qos_data.def_qos_parm.qos_flags |=
261 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
262
263 if (priv->current_ht_config.is_ht)
264 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
265
266 if (force || iwl_is_associated(priv)) {
267 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
268 priv->qos_data.qos_active,
269 priv->qos_data.def_qos_parm.qos_flags);
270
271 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
272 sizeof(struct iwl_qosparam_cmd),
273 &priv->qos_data.def_qos_parm, NULL);
274 }
275}
276EXPORT_SYMBOL(iwl_activate_qos);
277
f2c95b04
WYG		 278/*
279 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
280 * (802.11b) (802.11a/g)
281 * AC_BK 15 1023 7 0 0
282 * AC_BE 15 1023 3 0 0
283 * AC_VI 7 15 2 6.016ms 3.008ms
284 * AC_VO 3 7 2 3.264ms 1.504ms
285 */
c7de35cd 286void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 287{
288 u16 cw_min = 15;
289 u16 cw_max = 1023;
290 u8 aifs = 2;
30dab79e 291 bool is_legacy = false;
bf85ea4f
AK		 292 unsigned long flags;
293 int i;
294
295 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 296 /* QoS always active in AP and ADHOC mode
297 * In STA mode wait for association
298 */
299 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
300 priv->iw_mode == NL80211_IFTYPE_AP)
301 priv->qos_data.qos_active = 1;
302 else
303 priv->qos_data.qos_active = 0;
bf85ea4f 304
30dab79e
WT		 305 /* check for legacy mode */
306 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
307 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
308 (priv->iw_mode == NL80211_IFTYPE_STATION &&
309 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 310 cw_min = 31;
311 is_legacy = 1;
312 }
313
314 if (priv->qos_data.qos_active)
315 aifs = 3;
316
f2c95b04 317 /* AC_BE */
bf85ea4f
AK		 318 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
319 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
320 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
321 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
322 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
323
324 if (priv->qos_data.qos_active) {
f2c95b04 325 /* AC_BK */
bf85ea4f
AK		 326 i = 1;
327 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
328 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
329 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
330 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
331 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
332
f2c95b04 333 /* AC_VI */
bf85ea4f
AK		 334 i = 2;
335 priv->qos_data.def_qos_parm.ac[i].cw_min =
336 cpu_to_le16((cw_min + 1) / 2 - 1);
337 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 338 cpu_to_le16(cw_min);
bf85ea4f
AK		 339 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
340 if (is_legacy)
341 priv->qos_data.def_qos_parm.ac[i].edca_txop =
342 cpu_to_le16(6016);
343 else
344 priv->qos_data.def_qos_parm.ac[i].edca_txop =
345 cpu_to_le16(3008);
346 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
347
f2c95b04 348 /* AC_VO */
bf85ea4f
AK		 349 i = 3;
350 priv->qos_data.def_qos_parm.ac[i].cw_min =
351 cpu_to_le16((cw_min + 1) / 4 - 1);
352 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 353 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 354 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
355 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
356 if (is_legacy)
357 priv->qos_data.def_qos_parm.ac[i].edca_txop =
358 cpu_to_le16(3264);
359 else
360 priv->qos_data.def_qos_parm.ac[i].edca_txop =
361 cpu_to_le16(1504);
362 } else {
363 for (i = 1; i < 4; i++) {
364 priv->qos_data.def_qos_parm.ac[i].cw_min =
365 cpu_to_le16(cw_min);
366 priv->qos_data.def_qos_parm.ac[i].cw_max =
367 cpu_to_le16(cw_max);
368 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
369 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
370 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
371 }
372 }
e1623446 373 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 374
375 spin_unlock_irqrestore(&priv->lock, flags);
376}
c7de35cd
RR		 377EXPORT_SYMBOL(iwl_reset_qos);
378
d9fe60de
JB		 379#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
380#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 381static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 382 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 383 enum ieee80211_band band)
384{
39130df3
RR		 385 u16 max_bit_rate = 0;
386 u8 rx_chains_num = priv->hw_params.rx_chains_num;
387 u8 tx_chains_num = priv->hw_params.tx_chains_num;
388
c7de35cd 389 ht_info->cap = 0;
d9fe60de 390 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 391
d9fe60de 392 ht_info->ht_supported = true;
c7de35cd 393
d9fe60de
JB		 394 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
395 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
396 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 397 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 398
399 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 400 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 401 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
402 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
403 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 404 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 405 }
c7de35cd
RR		 406
407 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 408 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 409
410 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
411 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
412
d9fe60de 413 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 414 if (rx_chains_num >= 2)
d9fe60de 415 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 416 if (rx_chains_num >= 3)
d9fe60de 417 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 418
419 /* Highest supported Rx data rate */
420 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 421 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
422 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 423
424 /* Tx MCS capabilities */
d9fe60de 425 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 426 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 427 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
428 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
429 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 430 }
c7de35cd 431}
c7de35cd
RR		 432
433static void iwlcore_init_hw_rates(struct iwl_priv *priv,
434 struct ieee80211_rate *rates)
435{
436 int i;
437
438 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 439 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 440 rates[i].hw_value = i; /* Rate scaling will work on indexes */
441 rates[i].hw_value_short = i;
442 rates[i].flags = 0;
443 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
444 /*
445 * If CCK != 1M then set short preamble rate flag.
446 */
447 rates[i].flags |=
1826dcc0 448 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 449 0 : IEEE80211_RATE_SHORT_PREAMBLE;
450 }
451 }
452}
453
8ccde88a 454
c7de35cd
RR		 455/**
456 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
457 */
534166de 458int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 459{
460 struct iwl_channel_info *ch;
461 struct ieee80211_supported_band *sband;
462 struct ieee80211_channel *channels;
463 struct ieee80211_channel *geo_ch;
464 struct ieee80211_rate *rates;
465 int i = 0;
466
467 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
468 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 469 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 470 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
471 return 0;
472 }
473
474 channels = kzalloc(sizeof(struct ieee80211_channel) *
475 priv->channel_count, GFP_KERNEL);
476 if (!channels)
477 return -ENOMEM;
478
479 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
480 GFP_KERNEL);
481 if (!rates) {
482 kfree(channels);
483 return -ENOMEM;
484 }
485
486 /* 5.2GHz channels start after the 2.4GHz channels */
487 sband = &priv->bands[IEEE80211_BAND_5GHZ];
488 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
489 /* just OFDM */
490 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
491 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
492
49779293 493 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 494 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 495 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 496
497 sband = &priv->bands[IEEE80211_BAND_2GHZ];
498 sband->channels = channels;
499 /* OFDM & CCK */
500 sband->bitrates = rates;
501 sband->n_bitrates = IWL_RATE_COUNT;
502
49779293 503 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 504 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 505 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 506
507 priv->ieee_channels = channels;
508 priv->ieee_rates = rates;
509
c7de35cd
RR		 510 for (i = 0; i < priv->channel_count; i++) {
511 ch = &priv->channel_info[i];
512
513 /* FIXME: might be removed if scan is OK */
514 if (!is_channel_valid(ch))
515 continue;
516
517 if (is_channel_a_band(ch))
518 sband = &priv->bands[IEEE80211_BAND_5GHZ];
519 else
520 sband = &priv->bands[IEEE80211_BAND_2GHZ];
521
522 geo_ch = &sband->channels[sband->n_channels++];
523
524 geo_ch->center_freq =
525 ieee80211_channel_to_frequency(ch->channel);
526 geo_ch->max_power = ch->max_power_avg;
527 geo_ch->max_antenna_gain = 0xff;
528 geo_ch->hw_value = ch->channel;
529
530 if (is_channel_valid(ch)) {
531 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
532 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
533
534 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
535 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
536
537 if (ch->flags & EEPROM_CHANNEL_RADAR)
538 geo_ch->flags |= IEEE80211_CHAN_RADAR;
539
963f5517 540 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 541
630fe9b6
TW		 542 if (ch->max_power_avg > priv->tx_power_channel_lmt)
543 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 544 } else {
545 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
546 }
547
548 /* Save flags for reg domain usage */
549 geo_ch->orig_flags = geo_ch->flags;
550
e1623446 551 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 552 ch->channel, geo_ch->center_freq,
553 is_channel_a_band(ch) ? "5.2" : "2.4",
554 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
555 "restricted" : "valid",
556 geo_ch->flags);
557 }
558
559 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
560 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 561 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
562 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 563 priv->pci_dev->device,
564 priv->pci_dev->subsystem_device);
c7de35cd
RR		 565 priv->cfg->sku &= ~IWL_SKU_A;
566 }
567
978785a3 568 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 569 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
570 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 571
572 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
573
574 return 0;
575}
534166de 576EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 577
578/*
579 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
580 */
534166de 581void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 582{
583 kfree(priv->ieee_channels);
584 kfree(priv->ieee_rates);
585 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
586}
534166de 587EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 588
28a6b07a 589static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 590{
591 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 592 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
593 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 594}
963f5517 595
47c5196e
TW		 596static u8 iwl_is_channel_extension(struct iwl_priv *priv,
597 enum ieee80211_band band,
598 u16 channel, u8 extension_chan_offset)
599{
600 const struct iwl_channel_info *ch_info;
601
602 ch_info = iwl_get_channel_info(priv, band, channel);
603 if (!is_channel_valid(ch_info))
604 return 0;
605
d9fe60de 606 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517 607 return !(ch_info->fat_extension_channel &
689da1b3 608 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 609 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517 610 return !(ch_info->fat_extension_channel &
689da1b3 611 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 612
613 return 0;
614}
615
616u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 617 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 618{
619 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
620
621 if ((!iwl_ht_conf->is_ht) ||
a2b0f02e 622 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ))
47c5196e
TW		 623 return 0;
624
a2b0f02e
WYG		 625 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
626 * the bit will not set if it is pure 40MHz case
627 */
47c5196e 628 if (sta_ht_inf) {
a2b0f02e 629 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 630 return 0;
631 }
632
a2b0f02e
WYG		 633 if (iwl_ht_conf->ht_protection & IEEE80211_HT_OP_MODE_PROTECTION_20MHZ)
634 return 1;
635 else
636 return iwl_is_channel_extension(priv, priv->band,
637 le16_to_cpu(priv->staging_rxon.channel),
638 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 639}
640EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
641
8ccde88a
SO		 642void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
643{
644 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
645
646 if (hw_decrypt)
647 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
648 else
649 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
650
651}
652EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
653
654/**
655 * iwl_check_rxon_cmd - validate RXON structure is valid
656 *
657 * NOTE: This is really only useful during development and can eventually
658 * be #ifdef'd out once the driver is stable and folks aren't actively
659 * making changes
660 */
661int iwl_check_rxon_cmd(struct iwl_priv *priv)
662{
663 int error = 0;
664 int counter = 1;
665 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
666
667 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
668 error |= le32_to_cpu(rxon->flags &
669 (RXON_FLG_TGJ_NARROW_BAND_MSK |
670 RXON_FLG_RADAR_DETECT_MSK));
671 if (error)
672 IWL_WARN(priv, "check 24G fields %d | %d\n",
673 counter++, error);
674 } else {
675 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
676 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
677 if (error)
678 IWL_WARN(priv, "check 52 fields %d | %d\n",
679 counter++, error);
680 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
681 if (error)
682 IWL_WARN(priv, "check 52 CCK %d | %d\n",
683 counter++, error);
684 }
685 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
686 if (error)
687 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
688
689 /* make sure basic rates 6Mbps and 1Mbps are supported */
690 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
691 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
692 if (error)
693 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
694
695 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
696 if (error)
697 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
698
699 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
700 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
701 if (error)
702 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
703 counter++, error);
704
705 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
706 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
707 if (error)
708 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
709 counter++, error);
710
711 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
712 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
713 if (error)
714 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
715 counter++, error);
716
717 if (error)
718 IWL_WARN(priv, "Tuning to channel %d\n",
719 le16_to_cpu(rxon->channel));
720
721 if (error) {
722 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
723 return -1;
724 }
725 return 0;
726}
727EXPORT_SYMBOL(iwl_check_rxon_cmd);
728
729/**
730 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
731 * @priv: staging_rxon is compared to active_rxon
732 *
733 * If the RXON structure is changing enough to require a new tune,
734 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
735 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
736 */
737int iwl_full_rxon_required(struct iwl_priv *priv)
738{
739
740 /* These items are only settable from the full RXON command */
741 if (!(iwl_is_associated(priv)) ||
742 compare_ether_addr(priv->staging_rxon.bssid_addr,
743 priv->active_rxon.bssid_addr) ||
744 compare_ether_addr(priv->staging_rxon.node_addr,
745 priv->active_rxon.node_addr) ||
746 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
747 priv->active_rxon.wlap_bssid_addr) ||
748 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
749 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
750 (priv->staging_rxon.air_propagation !=
751 priv->active_rxon.air_propagation) ||
752 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
753 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
754 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
755 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 756 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
757 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 758 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
759 return 1;
760
761 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
762 * be updated with the RXON_ASSOC command -- however only some
763 * flag transitions are allowed using RXON_ASSOC */
764
765 /* Check if we are not switching bands */
766 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
767 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
768 return 1;
769
770 /* Check if we are switching association toggle */
771 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
772 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
773 return 1;
774
775 return 0;
776}
777EXPORT_SYMBOL(iwl_full_rxon_required);
778
779u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
780{
781 int i;
782 int rate_mask;
783
784 /* Set rate mask*/
785 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
786 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
787 else
788 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
789
790 /* Find lowest valid rate */
791 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
792 i = iwl_rates[i].next_ieee) {
793 if (rate_mask & (1 << i))
794 return iwl_rates[i].plcp;
795 }
796
797 /* No valid rate was found. Assign the lowest one */
798 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
799 return IWL_RATE_1M_PLCP;
800 else
801 return IWL_RATE_6M_PLCP;
802}
803EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
804
47c5196e
TW		 805void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
806{
c1adf9fb 807 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 808
42eb7c64 809 if (!ht_info->is_ht) {
a2b0f02e 810 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64
EG		 811 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
812 RXON_FLG_FAT_PROT_MSK |
813 RXON_FLG_HT_PROT_MSK);
47c5196e 814 return;
42eb7c64 815 }
47c5196e 816
a2b0f02e
WYG		 817 /* FIXME: if the definition of ht_protection changed, the "translation"
818 * will be needed for rxon->flags
819 */
820 rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
821
822 /* Set up channel bandwidth:
823 * 20 MHz only, 20/40 mixed or pure 40 if fat ok */
824 /* clear the HT channel mode before set the mode */
825 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
826 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
827 if (iwl_is_fat_tx_allowed(priv, NULL)) {
828 /* pure 40 fat */
829 if (rxon->flags & RXON_FLG_FAT_PROT_MSK)
830 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
831 else {
832 /* Note: control channel is opposite of extension channel */
833 switch (ht_info->extension_chan_offset) {
834 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
835 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
836 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
837 break;
838 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
839 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
840 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
841 break;
842 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
843 default:
844 /* channel location only valid if in Mixed mode */
845 IWL_ERR(priv, "invalid extension channel offset\n");
846 break;
847 }
848 }
849 } else {
850 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 851 }
852
45823531
AK		 853 if (priv->cfg->ops->hcmd->set_rxon_chain)
854 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 855
e1623446 856 IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
47c5196e 857 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 858 "extension channel offset 0x%x\n",
d9fe60de
JB		 859 ht_info->mcs.rx_mask[0],
860 ht_info->mcs.rx_mask[1],
861 ht_info->mcs.rx_mask[2],
47c5196e 862 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 863 ht_info->extension_chan_offset);
47c5196e
TW		 864 return;
865}
866EXPORT_SYMBOL(iwl_set_rxon_ht);
867
9e5e6c32
TW		 868#define IWL_NUM_RX_CHAINS_MULTIPLE 3
869#define IWL_NUM_RX_CHAINS_SINGLE 2
870#define IWL_NUM_IDLE_CHAINS_DUAL 2
871#define IWL_NUM_IDLE_CHAINS_SINGLE 1
872
873/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 874 * More provides better reception via diversity. Fewer saves power.
875 * MIMO (dual stream) requires at least 2, but works better with 3.
876 * This does not determine *which* chains to use, just how many.
877 */
28a6b07a 878static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 879{
28a6b07a
TW		 880 bool is_single = is_single_rx_stream(priv);
881 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 882
883 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 884 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
885 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 886 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 887 else
9e5e6c32 888 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 889}
c7de35cd 890
28a6b07a
TW		 891static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
892{
893 int idle_cnt;
894 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 895 /* # Rx chains when idling and maybe trying to save power */
12837be1 896 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 897 case WLAN_HT_CAP_SM_PS_STATIC:
898 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 899 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
900 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 901 break;
00c5ae2f 902 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 903 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 904 break;
00c5ae2f 905 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 906 default:
15b1687c 907 IWL_ERR(priv, "invalid mimo ps mode %d\n",
12837be1 908 priv->current_ht_config.sm_ps);
28a6b07a
TW		 909 WARN_ON(1);
910 idle_cnt = -1;
c7de35cd
RR		 911 break;
912 }
28a6b07a 913 return idle_cnt;
c7de35cd
RR		 914}
915
04816448
GE		 916/* up to 4 chains */
917static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
918{
919 u8 res;
920 res = (chain_bitmap & BIT(0)) >> 0;
921 res += (chain_bitmap & BIT(1)) >> 1;
922 res += (chain_bitmap & BIT(2)) >> 2;
923 res += (chain_bitmap & BIT(4)) >> 4;
924 return res;
925}
926
4c4df78f
CR		 927/**
928 * iwl_is_monitor_mode - Determine if interface in monitor mode
929 *
930 * priv->iw_mode is set in add_interface, but add_interface is
931 * never called for monitor mode. The only way mac80211 informs us about
932 * monitor mode is through configuring filters (call to configure_filter).
933 */
279b05d4 934bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 935{
936 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
937}
279b05d4 938EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 939
c7de35cd
RR		 940/**
941 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
942 *
943 * Selects how many and which Rx receivers/antennas/chains to use.
944 * This should not be used for scan command ... it puts data in wrong place.
945 */
946void iwl_set_rxon_chain(struct iwl_priv *priv)
947{
28a6b07a
TW		 948 bool is_single = is_single_rx_stream(priv);
949 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 950 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
951 u32 active_chains;
28a6b07a 952 u16 rx_chain;
c7de35cd
RR		 953
954 /* Tell uCode which antennas are actually connected.
955 * Before first association, we assume all antennas are connected.
956 * Just after first association, iwl_chain_noise_calibration()
957 * checks which antennas actually *are* connected. */
04816448
GE		 958 if (priv->chain_noise_data.active_chains)
959 active_chains = priv->chain_noise_data.active_chains;
960 else
961 active_chains = priv->hw_params.valid_rx_ant;
962
963 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 964
965 /* How many receivers should we use? */
28a6b07a
TW		 966 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
967 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
968
28a6b07a 969
04816448
GE		 970 /* correct rx chain count according hw settings
971 * and chain noise calibration
972 */
973 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
974 if (valid_rx_cnt < active_rx_cnt)
975 active_rx_cnt = valid_rx_cnt;
976
977 if (valid_rx_cnt < idle_rx_cnt)
978 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 979
980 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
981 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
982
7b841727
RF		 983 /* copied from 'iwl_bg_request_scan()' */
984 /* Force use of chains B and C (0x6) for Rx for 4965
985 * Avoid A (0x1) because of its off-channel reception on A-band.
986 * MIMO is not used here, but value is required */
987 if (iwl_is_monitor_mode(priv) &&
988 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
989 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 990 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
991 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
992 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
993 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 994 }
995
28a6b07a
TW		 996 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
997
9e5e6c32 998 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 999 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1000 else
1001 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1002
e1623446 1003 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1004 priv->staging_rxon.rx_chain,
1005 active_rx_cnt, idle_rx_cnt);
1006
1007 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1008 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1009}
1010EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1011
1012/**
17e72782 1013 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1014 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1015 * @channel: Any channel valid for the requested phymode
1016
1017 * In addition to setting the staging RXON, priv->phymode is also set.
1018 *
1019 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1020 * in the staging RXON flag structure based on the phymode
1021 */
17e72782 1022int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1023{
17e72782
TW		 1024 enum ieee80211_band band = ch->band;
1025 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1026
8622e705 1027 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1028 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1029 channel, band);
1030 return -EINVAL;
1031 }
1032
1033 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1034 (priv->band == band))
1035 return 0;
1036
1037 priv->staging_rxon.channel = cpu_to_le16(channel);
1038 if (band == IEEE80211_BAND_5GHZ)
1039 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1040 else
1041 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1042
1043 priv->band = band;
1044
e1623446 1045 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1046
1047 return 0;
1048}
c7de35cd 1049EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1050
8ccde88a
SO		 1051void iwl_set_flags_for_band(struct iwl_priv *priv,
1052 enum ieee80211_band band)
1053{
1054 if (band == IEEE80211_BAND_5GHZ) {
1055 priv->staging_rxon.flags &=
1056 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1057 | RXON_FLG_CCK_MSK);
1058 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1059 } else {
1060 /* Copied from iwl_post_associate() */
1061 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1062 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1063 else
1064 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1065
1066 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1067 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1068
1069 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1070 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1071 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1072 }
1073}
1074EXPORT_SYMBOL(iwl_set_flags_for_band);
1075
1076/*
1077 * initialize rxon structure with default values from eeprom
1078 */
1079void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1080{
1081 const struct iwl_channel_info *ch_info;
1082
1083 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1084
1085 switch (mode) {
1086 case NL80211_IFTYPE_AP:
1087 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1088 break;
1089
1090 case NL80211_IFTYPE_STATION:
1091 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1092 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1093 break;
1094
1095 case NL80211_IFTYPE_ADHOC:
1096 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1097 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1098 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1099 RXON_FILTER_ACCEPT_GRP_MSK;
1100 break;
1101
8ccde88a
SO		 1102 default:
1103 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1104 break;
1105 }
1106
1107#if 0
1108 /* TODO: Figure out when short_preamble would be set and cache from
1109 * that */
1110 if (!hw_to_local(priv->hw)->short_preamble)
1111 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1112 else
1113 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1114#endif
1115
1116 ch_info = iwl_get_channel_info(priv, priv->band,
1117 le16_to_cpu(priv->active_rxon.channel));
1118
1119 if (!ch_info)
1120 ch_info = &priv->channel_info[0];
1121
1122 /*
1123 * in some case A channels are all non IBSS
1124 * in this case force B/G channel
1125 */
1126 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1127 !(is_channel_ibss(ch_info)))
1128 ch_info = &priv->channel_info[0];
1129
1130 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1131 priv->band = ch_info->band;
1132
1133 iwl_set_flags_for_band(priv, priv->band);
1134
1135 priv->staging_rxon.ofdm_basic_rates =
1136 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1137 priv->staging_rxon.cck_basic_rates =
1138 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1139
a2b0f02e
WYG		 1140 /* clear both MIX and PURE40 mode flag */
1141 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1142 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1143 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1144 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1145 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1146 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1147 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1148}
1149EXPORT_SYMBOL(iwl_connection_init_rx_config);
1150
782571f4 1151static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1152{
1153 const struct ieee80211_supported_band *hw = NULL;
1154 struct ieee80211_rate *rate;
1155 int i;
1156
1157 hw = iwl_get_hw_mode(priv, priv->band);
1158 if (!hw) {
1159 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1160 return;
1161 }
1162
1163 priv->active_rate = 0;
1164 priv->active_rate_basic = 0;
1165
1166 for (i = 0; i < hw->n_bitrates; i++) {
1167 rate = &(hw->bitrates[i]);
1168 if (rate->hw_value < IWL_RATE_COUNT)
1169 priv->active_rate |= (1 << rate->hw_value);
1170 }
1171
e1623446 1172 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1173 priv->active_rate, priv->active_rate_basic);
1174
1175 /*
1176 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1177 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1178 * OFDM
1179 */
1180 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1181 priv->staging_rxon.cck_basic_rates =
1182 ((priv->active_rate_basic &
1183 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1184 else
1185 priv->staging_rxon.cck_basic_rates =
1186 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1187
1188 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1189 priv->staging_rxon.ofdm_basic_rates =
1190 ((priv->active_rate_basic &
1191 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1192 IWL_FIRST_OFDM_RATE) & 0xFF;
1193 else
1194 priv->staging_rxon.ofdm_basic_rates =
1195 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1196}
8ccde88a
SO		 1197
1198void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1199{
1200 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1201 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1202 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
e1623446 1203 IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
8ccde88a
SO		 1204 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
1205 rxon->channel = csa->channel;
1206 priv->staging_rxon.channel = csa->channel;
1207}
1208EXPORT_SYMBOL(iwl_rx_csa);
1209
1210#ifdef CONFIG_IWLWIFI_DEBUG
1211static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1212{
1213 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1214
e1623446 1215 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
8ccde88a 1216 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1217 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1218 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1219 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1220 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1221 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1222 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1223 rxon->ofdm_basic_rates);
e1623446
TW		 1224 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1225 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1226 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1227 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a
SO		 1228}
1229#endif
1230
1231/**
1232 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1233 */
1234void iwl_irq_handle_error(struct iwl_priv *priv)
1235{
1236 /* Set the FW error flag -- cleared on iwl_down */
1237 set_bit(STATUS_FW_ERROR, &priv->status);
1238
1239 /* Cancel currently queued command. */
1240 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1241
1242#ifdef CONFIG_IWLWIFI_DEBUG
1243 if (priv->debug_level & IWL_DL_FW_ERRORS) {
1244 iwl_dump_nic_error_log(priv);
1245 iwl_dump_nic_event_log(priv);
1246 iwl_print_rx_config_cmd(priv);
1247 }
1248#endif
1249
1250 wake_up_interruptible(&priv->wait_command_queue);
1251
1252 /* Keep the restart process from trying to send host
1253 * commands by clearing the INIT status bit */
1254 clear_bit(STATUS_READY, &priv->status);
1255
1256 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1257 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1258 "Restarting adapter due to uCode error.\n");
1259
8ccde88a
SO		 1260 if (priv->cfg->mod_params->restart_fw)
1261 queue_work(priv->workqueue, &priv->restart);
1262 }
1263}
1264EXPORT_SYMBOL(iwl_irq_handle_error);
1265
1266void iwl_configure_filter(struct ieee80211_hw *hw,
1267 unsigned int changed_flags,
1268 unsigned int *total_flags,
1269 int mc_count, struct dev_addr_list *mc_list)
1270{
1271 struct iwl_priv *priv = hw->priv;
1272 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1273
e1623446 1274 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1275 changed_flags, *total_flags);
1276
1277 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1278 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1279 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1280 else
1281 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1282 }
1283 if (changed_flags & FIF_ALLMULTI) {
1284 if (*total_flags & FIF_ALLMULTI)
1285 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1286 else
1287 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1288 }
1289 if (changed_flags & FIF_CONTROL) {
1290 if (*total_flags & FIF_CONTROL)
1291 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1292 else
1293 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1294 }
1295 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1296 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1297 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1298 else
1299 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1300 }
1301
1302 /* We avoid iwl_commit_rxon here to commit the new filter flags
1303 * since mac80211 will call ieee80211_hw_config immediately.
1304 * (mc_list is not supported at this time). Otherwise, we need to
1305 * queue a background iwl_commit_rxon work.
1306 */
1307
1308 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1309 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1310}
1311EXPORT_SYMBOL(iwl_configure_filter);
1312
6ba87956 1313int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 1314{
6ba87956 1315 int ret;
bf85ea4f 1316 struct ieee80211_hw *hw = priv->hw;
e227ceac 1317 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 1318
566bfe5a 1319 /* Tell mac80211 our characteristics */
605a0bd6 1320 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe 1321 IEEE80211_HW_NOISE_DBM |
4be8c387 1322 IEEE80211_HW_AMPDU_AGGREGATION |
286d9490 1323 IEEE80211_HW_SPECTRUM_MGMT;
f59ac048 1324 hw->wiphy->interface_modes =
f59ac048
LR		 1325 BIT(NL80211_IFTYPE_STATION) |
1326 BIT(NL80211_IFTYPE_ADHOC);
ea4a82dc 1327
2a44f911 1328 hw->wiphy->custom_regulatory = true;
1ecf9fc1
JB		 1329
1330 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
1331 /* we create the 802.11 header and a zero-length SSID element */
1332 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
ea4a82dc 1333
bf85ea4f
AK		 1334 /* Default value; 4 EDCA QOS priorities */
1335 hw->queues = 4;
6ba87956 1336
b5d7be5e 1337 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 1338
1339 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
1340 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1341 &priv->bands[IEEE80211_BAND_2GHZ];
1342 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
1343 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1344 &priv->bands[IEEE80211_BAND_5GHZ];
1345
1346 ret = ieee80211_register_hw(priv->hw);
1347 if (ret) {
15b1687c 1348 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
6ba87956
TW		 1349 return ret;
1350 }
1351 priv->mac80211_registered = 1;
1352
1353 return 0;
bf85ea4f 1354}
6ba87956 1355EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 1356
da154e30
RR		 1357int iwl_set_hw_params(struct iwl_priv *priv)
1358{
1359 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
1360 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1361 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1362 if (priv->cfg->mod_params->amsdu_size_8K)
1363 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1364 else
1365 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1366 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1367
49779293
RR		 1368 if (priv->cfg->mod_params->disable_11n)
1369 priv->cfg->sku &= ~IWL_SKU_N;
1370
da154e30
RR		 1371 /* Device-specific setup */
1372 return priv->cfg->ops->lib->set_hw_params(priv);
1373}
1374EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 1375
1376int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 1377{
1378 int ret;
c7de35cd 1379
c7de35cd
RR		 1380 priv->ibss_beacon = NULL;
1381
1382 spin_lock_init(&priv->lock);
c7de35cd
RR		 1383 spin_lock_init(&priv->sta_lock);
1384 spin_lock_init(&priv->hcmd_lock);
c7de35cd 1385
c7de35cd
RR		 1386 INIT_LIST_HEAD(&priv->free_frames);
1387
1388 mutex_init(&priv->mutex);
1389
1390 /* Clear the driver's (not device's) station table */
c587de0b 1391 iwl_clear_stations_table(priv);
c7de35cd
RR		 1392
1393 priv->data_retry_limit = -1;
1394 priv->ieee_channels = NULL;
1395 priv->ieee_rates = NULL;
1396 priv->band = IEEE80211_BAND_2GHZ;
1397
05c914fe 1398 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 1399
12837be1 1400 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 1401
1402 /* Choose which receivers/antennas to use */
45823531
AK		 1403 if (priv->cfg->ops->hcmd->set_rxon_chain)
1404 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1405
f53696de 1406 iwl_init_scan_params(priv);
c7de35cd
RR		 1407
1408 iwl_reset_qos(priv);
1409
1410 priv->qos_data.qos_active = 0;
1411 priv->qos_data.qos_cap.val = 0;
1412
c7de35cd 1413 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT		 1414 /* If power management is turned on, default to CAM mode */
1415 priv->power_mode = IWL_POWER_MODE_CAM;
630fe9b6 1416 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 1417
1418 ret = iwl_init_channel_map(priv);
1419 if (ret) {
15b1687c 1420 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
c7de35cd
RR		 1421 goto err;
1422 }
1423
1424 ret = iwlcore_init_geos(priv);
1425 if (ret) {
15b1687c 1426 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
c7de35cd
RR		 1427 goto err_free_channel_map;
1428 }
534166de 1429 iwlcore_init_hw_rates(priv, priv->ieee_rates);
c7de35cd 1430
c7de35cd
RR		 1431 return 0;
1432
c7de35cd
RR		 1433err_free_channel_map:
1434 iwl_free_channel_map(priv);
1435err:
1436 return ret;
1437}
6ba87956 1438EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 1439
630fe9b6
TW		 1440int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1441{
1442 int ret = 0;
1443 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1444 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1445 tx_power,
1446 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1447 return -EINVAL;
1448 }
1449
1450 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
daf518de
WF		 1451 IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
1452 tx_power,
1453 IWL_TX_POWER_TARGET_POWER_MAX);
630fe9b6
TW		 1454 return -EINVAL;
1455 }
1456
1457 if (priv->tx_power_user_lmt != tx_power)
1458 force = true;
1459
1460 priv->tx_power_user_lmt = tx_power;
1461
019fb97d
MA		 1462 /* if nic is not up don't send command */
1463 if (!iwl_is_ready_rf(priv))
1464 return ret;
1465
630fe9b6
TW		 1466 if (force && priv->cfg->ops->lib->send_tx_power)
1467 ret = priv->cfg->ops->lib->send_tx_power(priv);
1468
1469 return ret;
1470}
1471EXPORT_SYMBOL(iwl_set_tx_power);
1472
6ba87956 1473void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1474{
6e21f2c1 1475 iwl_calib_free_results(priv);
6ba87956
TW		 1476 iwlcore_free_geos(priv);
1477 iwl_free_channel_map(priv);
261415f7 1478 kfree(priv->scan);
bf85ea4f 1479}
6ba87956 1480EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1481
0ad91a35
WT		 1482
1483void iwl_disable_interrupts(struct iwl_priv *priv)
1484{
1485 clear_bit(STATUS_INT_ENABLED, &priv->status);
1486
1487 /* disable interrupts from uCode/NIC to host */
1488 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1489
1490 /* acknowledge/clear/reset any interrupts still pending
1491 * from uCode or flow handler (Rx/Tx DMA) */
1492 iwl_write32(priv, CSR_INT, 0xffffffff);
1493 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
e1623446 1494 IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
0ad91a35
WT		 1495}
1496EXPORT_SYMBOL(iwl_disable_interrupts);
1497
1498void iwl_enable_interrupts(struct iwl_priv *priv)
1499{
e1623446 1500 IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
0ad91a35 1501 set_bit(STATUS_INT_ENABLED, &priv->status);
40cefda9 1502 iwl_write32(priv, CSR_INT_MASK, priv->inta_mask);
0ad91a35
WT		 1503}
1504EXPORT_SYMBOL(iwl_enable_interrupts);
1505
ef850d7c
MA		 1506
1507#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1508
1509/* Free dram table */
1510void iwl_free_isr_ict(struct iwl_priv *priv)
1511{
1512 if (priv->ict_tbl_vir) {
1513 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1514 PAGE_SIZE, priv->ict_tbl_vir,
1515 priv->ict_tbl_dma);
1516 priv->ict_tbl_vir = NULL;
1517 }
1518}
1519EXPORT_SYMBOL(iwl_free_isr_ict);
1520
1521
1522/* allocate dram shared table it is a PAGE_SIZE aligned
1523 * also reset all data related to ICT table interrupt.
1524 */
1525int iwl_alloc_isr_ict(struct iwl_priv *priv)
1526{
1527
1528 if (priv->cfg->use_isr_legacy)
1529 return 0;
1530 /* allocate shrared data table */
1531 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1532 ICT_COUNT) + PAGE_SIZE,
1533 &priv->ict_tbl_dma);
1534 if (!priv->ict_tbl_vir)
1535 return -ENOMEM;
1536
1537 /* align table to PAGE_SIZE boundry */
1538 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1539
1540 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1541 (unsigned long long)priv->ict_tbl_dma,
1542 (unsigned long long)priv->aligned_ict_tbl_dma,
1543 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1544
1545 priv->ict_tbl = priv->ict_tbl_vir +
1546 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1547
1548 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1549 priv->ict_tbl, priv->ict_tbl_vir,
1550 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1551
1552 /* reset table and index to all 0 */
1553 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1554 priv->ict_index = 0;
1555
40cefda9
MA		 1556 /* add periodic RX interrupt */
1557 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1558 return 0;
1559}
1560EXPORT_SYMBOL(iwl_alloc_isr_ict);
1561
1562/* Device is going up inform it about using ICT interrupt table,
1563 * also we need to tell the driver to start using ICT interrupt.
1564 */
1565int iwl_reset_ict(struct iwl_priv *priv)
1566{
1567 u32 val;
1568 unsigned long flags;
1569
1570 if (!priv->ict_tbl_vir)
1571 return 0;
1572
1573 spin_lock_irqsave(&priv->lock, flags);
1574 iwl_disable_interrupts(priv);
1575
1576 memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT);
1577
1578 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1579
1580 val |= CSR_DRAM_INT_TBL_ENABLE;
1581 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1582
1583 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1584 "aligned dma address %Lx\n",
1585 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1586
1587 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1588 priv->use_ict = true;
1589 priv->ict_index = 0;
40cefda9 1590 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1591 iwl_enable_interrupts(priv);
1592 spin_unlock_irqrestore(&priv->lock, flags);
1593
1594 return 0;
1595}
1596EXPORT_SYMBOL(iwl_reset_ict);
1597
1598/* Device is going down disable ict interrupt usage */
1599void iwl_disable_ict(struct iwl_priv *priv)
1600{
1601 unsigned long flags;
1602
1603 spin_lock_irqsave(&priv->lock, flags);
1604 priv->use_ict = false;
1605 spin_unlock_irqrestore(&priv->lock, flags);
1606}
1607EXPORT_SYMBOL(iwl_disable_ict);
1608
1609/* interrupt handler using ict table, with this interrupt driver will
1610 * stop using INTA register to get device's interrupt, reading this register
1611 * is expensive, device will write interrupts in ICT dram table, increment
1612 * index then will fire interrupt to driver, driver will OR all ICT table
1613 * entries from current index up to table entry with 0 value. the result is
1614 * the interrupt we need to service, driver will set the entries back to 0 and
1615 * set index.
1616 */
1617irqreturn_t iwl_isr_ict(int irq, void *data)
1618{
1619 struct iwl_priv *priv = data;
1620 u32 inta, inta_mask;
1621 u32 val = 0;
1622
1623 if (!priv)
1624 return IRQ_NONE;
1625
1626 /* dram interrupt table not set yet,
1627 * use legacy interrupt.
1628 */
1629 if (!priv->use_ict)
1630 return iwl_isr(irq, data);
1631
1632 spin_lock(&priv->lock);
1633
1634 /* Disable (but don't clear!) interrupts here to avoid
1635 * back-to-back ISRs and sporadic interrupts from our NIC.
1636 * If we have something to service, the tasklet will re-enable ints.
1637 * If we *don't* have something, we'll re-enable before leaving here.
1638 */
1639 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1640 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1641
1642
1643 /* Ignore interrupt if there's nothing in NIC to service.
1644 * This may be due to IRQ shared with another device,
1645 * or due to sporadic interrupts thrown from our NIC. */
1646 if (!priv->ict_tbl[priv->ict_index]) {
1647 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1648 goto none;
1649 }
1650
1651 /* read all entries that not 0 start with ict_index */
1652 while (priv->ict_tbl[priv->ict_index]) {
1653
1654 val |= priv->ict_tbl[priv->ict_index];
1655 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1656 priv->ict_index,
1657 priv->ict_tbl[priv->ict_index]);
1658 priv->ict_tbl[priv->ict_index] = 0;
1659 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1660 ICT_COUNT);
1661
1662 }
1663
1664 /* We should not get this value, just ignore it. */
1665 if (val == 0xffffffff)
1666 val = 0;
1667
1668 inta = (0xff & val) | ((0xff00 & val) << 16);
1669 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1670 inta, inta_mask, val);
1671
40cefda9 1672 inta &= priv->inta_mask;
ef850d7c
MA		 1673 priv->inta |= inta;
1674
1675 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1676 if (likely(inta))
1677 tasklet_schedule(&priv->irq_tasklet);
1678 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1679 /* Allow interrupt if was disabled by this handler and
1680 * no tasklet was schedules, We should not enable interrupt,
1681 * tasklet will enable it.
1682 */
1683 iwl_enable_interrupts(priv);
1684 }
1685
1686 spin_unlock(&priv->lock);
1687 return IRQ_HANDLED;
1688
1689 none:
1690 /* re-enable interrupts here since we don't have anything to service.
1691 * only Re-enable if disabled by irq.
1692 */
1693 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1694 iwl_enable_interrupts(priv);
1695
1696 spin_unlock(&priv->lock);
1697 return IRQ_NONE;
1698}
1699EXPORT_SYMBOL(iwl_isr_ict);
1700
1701
1702static irqreturn_t iwl_isr(int irq, void *data)
1703{
1704 struct iwl_priv *priv = data;
1705 u32 inta, inta_mask;
d651ae32 1706#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1707 u32 inta_fh;
d651ae32 1708#endif
ef850d7c
MA		 1709 if (!priv)
1710 return IRQ_NONE;
1711
1712 spin_lock(&priv->lock);
1713
1714 /* Disable (but don't clear!) interrupts here to avoid
1715 * back-to-back ISRs and sporadic interrupts from our NIC.
1716 * If we have something to service, the tasklet will re-enable ints.
1717 * If we *don't* have something, we'll re-enable before leaving here. */
1718 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1719 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1720
1721 /* Discover which interrupts are active/pending */
1722 inta = iwl_read32(priv, CSR_INT);
1723
1724 /* Ignore interrupt if there's nothing in NIC to service.
1725 * This may be due to IRQ shared with another device,
1726 * or due to sporadic interrupts thrown from our NIC. */
1727 if (!inta) {
1728 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1729 goto none;
1730 }
1731
1732 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1733 /* Hardware disappeared. It might have already raised
1734 * an interrupt */
1735 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1736 goto unplugged;
1737 }
1738
1739#ifdef CONFIG_IWLWIFI_DEBUG
1740 if (priv->debug_level & (IWL_DL_ISR)) {
1741 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1742 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1743 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1744 }
1745#endif
1746
1747 priv->inta |= inta;
1748 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1749 if (likely(inta))
1750 tasklet_schedule(&priv->irq_tasklet);
1751 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1752 iwl_enable_interrupts(priv);
1753
1754 unplugged:
1755 spin_unlock(&priv->lock);
1756 return IRQ_HANDLED;
1757
1758 none:
1759 /* re-enable interrupts here since we don't have anything to service. */
1760 /* only Re-enable if diabled by irq and no schedules tasklet. */
1761 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1762 iwl_enable_interrupts(priv);
1763
1764 spin_unlock(&priv->lock);
1765 return IRQ_NONE;
1766}
1767
1768irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1769{
1770 struct iwl_priv *priv = data;
1771 u32 inta, inta_mask;
1772 u32 inta_fh;
1773 if (!priv)
1774 return IRQ_NONE;
1775
1776 spin_lock(&priv->lock);
1777
1778 /* Disable (but don't clear!) interrupts here to avoid
1779 * back-to-back ISRs and sporadic interrupts from our NIC.
1780 * If we have something to service, the tasklet will re-enable ints.
1781 * If we *don't* have something, we'll re-enable before leaving here. */
1782 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1783 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1784
1785 /* Discover which interrupts are active/pending */
1786 inta = iwl_read32(priv, CSR_INT);
1787 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1788
1789 /* Ignore interrupt if there's nothing in NIC to service.
1790 * This may be due to IRQ shared with another device,
1791 * or due to sporadic interrupts thrown from our NIC. */
1792 if (!inta && !inta_fh) {
1793 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1794 goto none;
1795 }
1796
1797 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1798 /* Hardware disappeared. It might have already raised
1799 * an interrupt */
1800 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1801 goto unplugged;
1802 }
1803
1804 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1805 inta, inta_mask, inta_fh);
1806
1807 inta &= ~CSR_INT_BIT_SCD;
1808
1809 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1810 if (likely(inta || inta_fh))
1811 tasklet_schedule(&priv->irq_tasklet);
1812
1813 unplugged:
1814 spin_unlock(&priv->lock);
1815 return IRQ_HANDLED;
1816
1817 none:
1818 /* re-enable interrupts here since we don't have anything to service. */
1819 /* only Re-enable if diabled by irq */
1820 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1821 iwl_enable_interrupts(priv);
1822 spin_unlock(&priv->lock);
1823 return IRQ_NONE;
1824}
ef850d7c 1825EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1826
17f841cd
SO		 1827int iwl_send_bt_config(struct iwl_priv *priv)
1828{
1829 struct iwl_bt_cmd bt_cmd = {
1830 .flags = 3,
1831 .lead_time = 0xAA,
1832 .max_kill = 1,
1833 .kill_ack_mask = 0,
1834 .kill_cts_mask = 0,
1835 };
1836
1837 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1838 sizeof(struct iwl_bt_cmd), &bt_cmd);
1839}
1840EXPORT_SYMBOL(iwl_send_bt_config);
1841
49ea8596
EG		 1842int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1843{
1844 u32 stat_flags = 0;
1845 struct iwl_host_cmd cmd = {
1846 .id = REPLY_STATISTICS_CMD,
1847 .meta.flags = flags,
1848 .len = sizeof(stat_flags),
1849 .data = (u8 *) &stat_flags,
1850 };
1851 return iwl_send_cmd(priv, &cmd);
1852}
1853EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1854
b0692f2f
EG		 1855/**
1856 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1857 * using sample data 100 bytes apart. If these sample points are good,
1858 * it's a pretty good bet that everything between them is good, too.
1859 */
1860static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1861{
1862 u32 val;
1863 int ret = 0;
1864 u32 errcnt = 0;
1865 u32 i;
1866
e1623446 1867 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 1868
b0692f2f
EG		 1869 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1870 /* read data comes through single port, auto-incr addr */
1871 /* NOTE: Use the debugless read so we don't flood kernel log
1872 * if IWL_DL_IO is set */
1873 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1874 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1875 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1876 if (val != le32_to_cpu(*image)) {
1877 ret = -EIO;
1878 errcnt++;
1879 if (errcnt >= 3)
1880 break;
1881 }
1882 }
1883
b0692f2f
EG		 1884 return ret;
1885}
1886
1887/**
1888 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1889 * looking at all data.
1890 */
1891static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1892 u32 len)
1893{
1894 u32 val;
1895 u32 save_len = len;
1896 int ret = 0;
1897 u32 errcnt;
1898
e1623446 1899 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 1900
250bdd21
SO		 1901 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1902 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1903
1904 errcnt = 0;
1905 for (; len > 0; len -= sizeof(u32), image++) {
1906 /* read data comes through single port, auto-incr addr */
1907 /* NOTE: Use the debugless read so we don't flood kernel log
1908 * if IWL_DL_IO is set */
1909 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1910 if (val != le32_to_cpu(*image)) {
15b1687c 1911 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 1912 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1913 save_len - len, val, le32_to_cpu(*image));
1914 ret = -EIO;
1915 errcnt++;
1916 if (errcnt >= 20)
1917 break;
1918 }
1919 }
1920
b0692f2f 1921 if (!errcnt)
e1623446
TW		 1922 IWL_DEBUG_INFO(priv,
1923 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 1924
1925 return ret;
1926}
1927
1928/**
1929 * iwl_verify_ucode - determine which instruction image is in SRAM,
1930 * and verify its contents
1931 */
1932int iwl_verify_ucode(struct iwl_priv *priv)
1933{
1934 __le32 *image;
1935 u32 len;
1936 int ret;
1937
1938 /* Try bootstrap */
1939 image = (__le32 *)priv->ucode_boot.v_addr;
1940 len = priv->ucode_boot.len;
1941 ret = iwlcore_verify_inst_sparse(priv, image, len);
1942 if (!ret) {
e1623446 1943 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 1944 return 0;
1945 }
1946
1947 /* Try initialize */
1948 image = (__le32 *)priv->ucode_init.v_addr;
1949 len = priv->ucode_init.len;
1950 ret = iwlcore_verify_inst_sparse(priv, image, len);
1951 if (!ret) {
e1623446 1952 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 1953 return 0;
1954 }
1955
1956 /* Try runtime/protocol */
1957 image = (__le32 *)priv->ucode_code.v_addr;
1958 len = priv->ucode_code.len;
1959 ret = iwlcore_verify_inst_sparse(priv, image, len);
1960 if (!ret) {
e1623446 1961 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 1962 return 0;
1963 }
1964
15b1687c 1965 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 1966
1967 /* Since nothing seems to match, show first several data entries in
1968 * instruction SRAM, so maybe visual inspection will give a clue.
1969 * Selection of bootstrap image (vs. other images) is arbitrary. */
1970 image = (__le32 *)priv->ucode_boot.v_addr;
1971 len = priv->ucode_boot.len;
1972 ret = iwl_verify_inst_full(priv, image, len);
1973
1974 return ret;
1975}
1976EXPORT_SYMBOL(iwl_verify_ucode);
1977
56e12615
JS		 1978
1979static const char *desc_lookup_text[] = {
1980 "OK",
1981 "FAIL",
1982 "BAD_PARAM",
1983 "BAD_CHECKSUM",
1984 "NMI_INTERRUPT_WDG",
1985 "SYSASSERT",
1986 "FATAL_ERROR",
1987 "BAD_COMMAND",
1988 "HW_ERROR_TUNE_LOCK",
1989 "HW_ERROR_TEMPERATURE",
1990 "ILLEGAL_CHAN_FREQ",
1991 "VCC_NOT_STABLE",
1992 "FH_ERROR",
1993 "NMI_INTERRUPT_HOST",
1994 "NMI_INTERRUPT_ACTION_PT",
1995 "NMI_INTERRUPT_UNKNOWN",
1996 "UCODE_VERSION_MISMATCH",
1997 "HW_ERROR_ABS_LOCK",
1998 "HW_ERROR_CAL_LOCK_FAIL",
1999 "NMI_INTERRUPT_INST_ACTION_PT",
2000 "NMI_INTERRUPT_DATA_ACTION_PT",
2001 "NMI_TRM_HW_ER",
2002 "NMI_INTERRUPT_TRM",
2003 "NMI_INTERRUPT_BREAK_POINT"
2004 "DEBUG_0",
2005 "DEBUG_1",
2006 "DEBUG_2",
2007 "DEBUG_3",
2008 "UNKNOWN"
2009};
2010
ede0cba4
EK		 2011static const char *desc_lookup(int i)
2012{
56e12615
JS		 2013 int max = ARRAY_SIZE(desc_lookup_text) - 1;
2014
2015 if (i < 0 || i > max)
2016 i = max;
ede0cba4 2017
56e12615 2018 return desc_lookup_text[i];
ede0cba4
EK		 2019}
2020
2021#define ERROR_START_OFFSET (1 * sizeof(u32))
2022#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2023
2024void iwl_dump_nic_error_log(struct iwl_priv *priv)
2025{
2026 u32 data2, line;
2027 u32 desc, time, count, base, data1;
2028 u32 blink1, blink2, ilink1, ilink2;
ede0cba4 2029
e1dfc085
GG		 2030 if (priv->ucode_type == UCODE_INIT)
2031 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2032 else
2033 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 2034
2035 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 2036 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
ede0cba4
EK		 2037 return;
2038 }
2039
ede0cba4
EK		 2040 count = iwl_read_targ_mem(priv, base);
2041
2042 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT		 2043 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2044 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2045 priv->status, count);
ede0cba4
EK		 2046 }
2047
2048 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2049 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2050 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2051 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2052 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2053 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2054 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2055 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2056 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2057
15b1687c 2058 IWL_ERR(priv, "Desc Time "
ede0cba4 2059 "data1 data2 line\n");
15b1687c 2060 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
ede0cba4 2061 desc_lookup(desc), desc, time, data1, data2, line);
15b1687c
WT		 2062 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
2063 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
ede0cba4
EK		 2064 ilink1, ilink2);
2065
ede0cba4
EK		 2066}
2067EXPORT_SYMBOL(iwl_dump_nic_error_log);
2068
189a2b59
EK		 2069#define EVENT_START_OFFSET (4 * sizeof(u32))
2070
2071/**
2072 * iwl_print_event_log - Dump error event log to syslog
2073 *
189a2b59 2074 */
a33c2f47 2075static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 2076 u32 num_events, u32 mode)
2077{
2078 u32 i;
2079 u32 base; /* SRAM byte address of event log header */
2080 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2081 u32 ptr; /* SRAM byte address of log data */
2082 u32 ev, time, data; /* event log data */
2083
2084 if (num_events == 0)
2085 return;
e1dfc085
GG		 2086 if (priv->ucode_type == UCODE_INIT)
2087 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2088 else
2089 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 2090
2091 if (mode == 0)
2092 event_size = 2 * sizeof(u32);
2093 else
2094 event_size = 3 * sizeof(u32);
2095
2096 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2097
2098 /* "time" is actually "data" for mode 0 (no timestamp).
2099 * place event id # at far right for easier visual parsing. */
2100 for (i = 0; i < num_events; i++) {
2101 ev = iwl_read_targ_mem(priv, ptr);
2102 ptr += sizeof(u32);
2103 time = iwl_read_targ_mem(priv, ptr);
2104 ptr += sizeof(u32);
77c5d08e
TW		 2105 if (mode == 0) {
2106 /* data, ev */
15b1687c 2107 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
77c5d08e 2108 } else {
189a2b59
EK		 2109 data = iwl_read_targ_mem(priv, ptr);
2110 ptr += sizeof(u32);
15b1687c 2111 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
77c5d08e 2112 time, data, ev);
189a2b59
EK		 2113 }
2114 }
2115}
189a2b59
EK		 2116
2117void iwl_dump_nic_event_log(struct iwl_priv *priv)
2118{
189a2b59
EK		 2119 u32 base; /* SRAM byte address of event log header */
2120 u32 capacity; /* event log capacity in # entries */
2121 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2122 u32 num_wraps; /* # times uCode wrapped to top of log */
2123 u32 next_entry; /* index of next entry to be written by uCode */
2124 u32 size; /* # entries that we'll print */
2125
e1dfc085
GG		 2126 if (priv->ucode_type == UCODE_INIT)
2127 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2128 else
2129 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2130
189a2b59 2131 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 2132 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
189a2b59
EK		 2133 return;
2134 }
2135
189a2b59
EK		 2136 /* event log header */
2137 capacity = iwl_read_targ_mem(priv, base);
2138 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2139 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2140 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2141
2142 size = num_wraps ? capacity : next_entry;
2143
2144 /* bail out if nothing in log */
2145 if (size == 0) {
15b1687c 2146 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
189a2b59
EK		 2147 return;
2148 }
2149
15b1687c 2150 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
189a2b59
EK		 2151 size, num_wraps);
2152
2153 /* if uCode has wrapped back to top of log, start at the oldest entry,
2154 * i.e the next one that uCode would fill. */
2155 if (num_wraps)
2156 iwl_print_event_log(priv, next_entry,
2157 capacity - next_entry, mode);
2158 /* (then/else) start at top of log */
2159 iwl_print_event_log(priv, 0, next_entry, mode);
2160
189a2b59
EK		 2161}
2162EXPORT_SYMBOL(iwl_dump_nic_event_log);
2163
47f4a587
EG		 2164void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2165{
2166 struct iwl_ct_kill_config cmd;
2167 unsigned long flags;
2168 int ret = 0;
2169
2170 spin_lock_irqsave(&priv->lock, flags);
2171 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2172 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2173 spin_unlock_irqrestore(&priv->lock, flags);
2174
2175 cmd.critical_temperature_R =
2176 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2177
47f4a587
EG		 2178 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2179 sizeof(cmd), &cmd);
2180 if (ret)
15b1687c 2181 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
47f4a587 2182 else
e1623446 2183 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
47f4a587
EG		 2184 "critical temperature is %d\n",
2185 cmd.critical_temperature_R);
2186}
2187EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2188
0ad91a35 2189
14a08a7f
EG		 2190/*
2191 * CARD_STATE_CMD
2192 *
2193 * Use: Sets the device's internal card state to enable, disable, or halt
2194 *
2195 * When in the 'enable' state the card operates as normal.
2196 * When in the 'disable' state, the card enters into a low power mode.
2197 * When in the 'halt' state, the card is shut down and must be fully
2198 * restarted to come back on.
2199 */
c496294e 2200int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2201{
2202 struct iwl_host_cmd cmd = {
2203 .id = REPLY_CARD_STATE_CMD,
2204 .len = sizeof(u32),
2205 .data = &flags,
2206 .meta.flags = meta_flag,
2207 };
2208
2209 return iwl_send_cmd(priv, &cmd);
2210}
c496294e 2211EXPORT_SYMBOL(iwl_send_card_state);
14a08a7f 2212
030f05ed
AK		 2213void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2214 struct iwl_rx_mem_buffer *rxb)
2215{
2216#ifdef CONFIG_IWLWIFI_DEBUG
2217 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2218 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2219 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2220 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2221#endif
2222}
2223EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2224
2225void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2226 struct iwl_rx_mem_buffer *rxb)
2227{
2228 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2229 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
2230 "notification for %s:\n",
2231 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
2232 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
2233}
2234EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2235
2236void iwl_rx_reply_error(struct iwl_priv *priv,
2237 struct iwl_rx_mem_buffer *rxb)
2238{
2239 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2240
2241 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2242 "seq 0x%04X ser 0x%08X\n",
2243 le32_to_cpu(pkt->u.err_resp.error_type),
2244 get_cmd_string(pkt->u.err_resp.cmd_id),
2245 pkt->u.err_resp.cmd_id,
2246 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2247 le32_to_cpu(pkt->u.err_resp.error_info));
2248}
2249EXPORT_SYMBOL(iwl_rx_reply_error);
2250
a83b9141
WYG		 2251void iwl_clear_isr_stats(struct iwl_priv *priv)
2252{
2253 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2254}
2255EXPORT_SYMBOL(iwl_clear_isr_stats);
2256
488829f1
AK		 2257int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2258 const struct ieee80211_tx_queue_params *params)
2259{
2260 struct iwl_priv *priv = hw->priv;
2261 unsigned long flags;
2262 int q;
2263
2264 IWL_DEBUG_MAC80211(priv, "enter\n");
2265
2266 if (!iwl_is_ready_rf(priv)) {
2267 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2268 return -EIO;
2269 }
2270
2271 if (queue >= AC_NUM) {
2272 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2273 return 0;
2274 }
2275
2276 q = AC_NUM - 1 - queue;
2277
2278 spin_lock_irqsave(&priv->lock, flags);
2279
2280 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2281 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2282 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2283 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2284 cpu_to_le16((params->txop * 32));
2285
2286 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2287 priv->qos_data.qos_active = 1;
2288
2289 if (priv->iw_mode == NL80211_IFTYPE_AP)
2290 iwl_activate_qos(priv, 1);
2291 else if (priv->assoc_id && iwl_is_associated(priv))
2292 iwl_activate_qos(priv, 0);
2293
2294 spin_unlock_irqrestore(&priv->lock, flags);
2295
2296 IWL_DEBUG_MAC80211(priv, "leave\n");
2297 return 0;
2298}
2299EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2300
2301static void iwl_ht_conf(struct iwl_priv *priv,
2302 struct ieee80211_bss_conf *bss_conf)
2303{
2304 struct ieee80211_sta_ht_cap *ht_conf;
2305 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
2306 struct ieee80211_sta *sta;
2307
2308 IWL_DEBUG_MAC80211(priv, "enter: \n");
2309
2310 if (!iwl_conf->is_ht)
2311 return;
2312
2313
2314 /*
2315 * It is totally wrong to base global information on something
2316 * that is valid only when associated, alas, this driver works
2317 * that way and I don't know how to fix it.
2318 */
2319
2320 rcu_read_lock();
2321 sta = ieee80211_find_sta(priv->hw, priv->bssid);
2322 if (!sta) {
2323 rcu_read_unlock();
2324 return;
2325 }
2326 ht_conf = &sta->ht_cap;
2327
2328 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
2329 iwl_conf->sgf |= HT_SHORT_GI_20MHZ;
2330 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
2331 iwl_conf->sgf |= HT_SHORT_GI_40MHZ;
2332
2333 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
2334 iwl_conf->max_amsdu_size =
2335 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
2336
2337 iwl_conf->supported_chan_width =
2338 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
2339
2340 /*
2341 * XXX: The HT configuration needs to be moved into iwl_mac_config()
2342 * to be done there correctly.
2343 */
2344
2345 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
2346 if (conf_is_ht40_minus(&priv->hw->conf))
2347 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2348 else if (conf_is_ht40_plus(&priv->hw->conf))
2349 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2350
2351 /* If no above or below channel supplied disable FAT channel */
2352 if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE &&
2353 iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW)
2354 iwl_conf->supported_chan_width = 0;
2355
2356 iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
2357
2358 memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
2359
2360 iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0;
2361 iwl_conf->ht_protection =
9ed6bcce 2362 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
5bbe233b 2363 iwl_conf->non_GF_STA_present =
9ed6bcce 2364 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b
AK		 2365
2366 rcu_read_unlock();
2367
2368 IWL_DEBUG_MAC80211(priv, "leave\n");
2369}
2370
2371#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2372void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2373 struct ieee80211_vif *vif,
2374 struct ieee80211_bss_conf *bss_conf,
2375 u32 changes)
5bbe233b
AK		 2376{
2377 struct iwl_priv *priv = hw->priv;
3a650292 2378 int ret;
5bbe233b
AK		 2379
2380 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2381
2d0ddec5
JB		 2382 if (!iwl_is_alive(priv))
2383 return;
2384
2385 mutex_lock(&priv->mutex);
2386
2387 if (changes & BSS_CHANGED_BEACON &&
2388 priv->iw_mode == NL80211_IFTYPE_AP) {
2389 dev_kfree_skb(priv->ibss_beacon);
2390 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2391 }
2392
2393 if ((changes & BSS_CHANGED_BSSID) && !iwl_is_rfkill(priv)) {
2394 /* If there is currently a HW scan going on in the background
2395 * then we need to cancel it else the RXON below will fail. */
2396 if (iwl_scan_cancel_timeout(priv, 100)) {
2397 IWL_WARN(priv, "Aborted scan still in progress "
2398 "after 100ms\n");
2399 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2400 mutex_unlock(&priv->mutex);
2401 return;
2402 }
2403 memcpy(priv->staging_rxon.bssid_addr,
2404 bss_conf->bssid, ETH_ALEN);
2405
2406 /* TODO: Audit driver for usage of these members and see
2407 * if mac80211 deprecates them (priv->bssid looks like it
2408 * shouldn't be there, but I haven't scanned the IBSS code
2409 * to verify) - jpk */
2410 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2411
2412 if (priv->iw_mode == NL80211_IFTYPE_AP)
2413 iwlcore_config_ap(priv);
2414 else {
2415 int rc = iwlcore_commit_rxon(priv);
2416 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
2417 iwl_rxon_add_station(
2418 priv, priv->active_rxon.bssid_addr, 1);
2419 }
2420 } else if (!iwl_is_rfkill(priv)) {
2421 iwl_scan_cancel_timeout(priv, 100);
2422 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2423 iwlcore_commit_rxon(priv);
2424 }
2425
2426 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2427 changes & BSS_CHANGED_BEACON) {
2428 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2429
2430 if (beacon)
2431 iwl_mac_beacon_update(hw, beacon);
2432 }
2433
2434 mutex_unlock(&priv->mutex);
2435
5bbe233b
AK		 2436 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2437 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2438 bss_conf->use_short_preamble);
2439 if (bss_conf->use_short_preamble)
2440 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2441 else
2442 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2443 }
2444
2445 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2446 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2447 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2448 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2449 else
2450 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2451 }
2452
2453 if (changes & BSS_CHANGED_HT) {
2454 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2455
2456 if (priv->cfg->ops->hcmd->set_rxon_chain)
2457 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2458 }
2459
2460 if (changes & BSS_CHANGED_ASSOC) {
2461 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
2462 /* This should never happen as this function should
2463 * never be called from interrupt context. */
2464 if (WARN_ON_ONCE(in_interrupt()))
2465 return;
2466 if (bss_conf->assoc) {
2467 priv->assoc_id = bss_conf->aid;
2468 priv->beacon_int = bss_conf->beacon_int;
2469 priv->power_data.dtim_period = bss_conf->dtim_period;
2470 priv->timestamp = bss_conf->timestamp;
2471 priv->assoc_capability = bss_conf->assoc_capability;
2472
2473 /* we have just associated, don't start scan too early
2474 * leave time for EAPOL exchange to complete
2475 */
2476 priv->next_scan_jiffies = jiffies +
2477 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
2478 mutex_lock(&priv->mutex);
2479 priv->cfg->ops->lib->post_associate(priv);
2480 mutex_unlock(&priv->mutex);
2481 } else {
2482 priv->assoc_id = 0;
2483 IWL_DEBUG_MAC80211(priv, "DISASSOC %d\n", bss_conf->assoc);
2484 }
2485 } else if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2486 IWL_DEBUG_MAC80211(priv, "Associated Changes %d\n", changes);
3a650292
MA		 2487 ret = iwl_send_rxon_assoc(priv);
2488 if (!ret)
2489 /* Sync active_rxon with latest change. */
2490 memcpy((void *)&priv->active_rxon,
2491 &priv->staging_rxon,
2492 sizeof(struct iwl_rxon_cmd));
5bbe233b 2493 }
2d0ddec5 2494 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2495}
2496EXPORT_SYMBOL(iwl_bss_info_changed);
2497
9944b938
AK		 2498int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2499{
2500 struct iwl_priv *priv = hw->priv;
2501 unsigned long flags;
2502 __le64 timestamp;
2503
2504 IWL_DEBUG_MAC80211(priv, "enter\n");
2505
2506 if (!iwl_is_ready_rf(priv)) {
2507 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2508 return -EIO;
2509 }
2510
2511 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2512 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2513 return -EIO;
2514 }
2515
2516 spin_lock_irqsave(&priv->lock, flags);
2517
2518 if (priv->ibss_beacon)
2519 dev_kfree_skb(priv->ibss_beacon);
2520
2521 priv->ibss_beacon = skb;
2522
2523 priv->assoc_id = 0;
2524 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2525 priv->timestamp = le64_to_cpu(timestamp);
2526
2527 IWL_DEBUG_MAC80211(priv, "leave\n");
2528 spin_unlock_irqrestore(&priv->lock, flags);
2529
2530 iwl_reset_qos(priv);
2531
2532 priv->cfg->ops->lib->post_associate(priv);
2533
2534
2535 return 0;
2536}
2537EXPORT_SYMBOL(iwl_mac_beacon_update);
2538
727882d6
AK		 2539int iwl_set_mode(struct iwl_priv *priv, int mode)
2540{
2541 if (mode == NL80211_IFTYPE_ADHOC) {
2542 const struct iwl_channel_info *ch_info;
2543
2544 ch_info = iwl_get_channel_info(priv,
2545 priv->band,
2546 le16_to_cpu(priv->staging_rxon.channel));
2547
2548 if (!ch_info || !is_channel_ibss(ch_info)) {
2549 IWL_ERR(priv, "channel %d not IBSS channel\n",
2550 le16_to_cpu(priv->staging_rxon.channel));
2551 return -EINVAL;
2552 }
2553 }
2554
2555 iwl_connection_init_rx_config(priv, mode);
2556
2557 if (priv->cfg->ops->hcmd->set_rxon_chain)
2558 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2559
2560 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2561
c587de0b 2562 iwl_clear_stations_table(priv);
727882d6
AK		 2563
2564 /* dont commit rxon if rf-kill is on*/
2565 if (!iwl_is_ready_rf(priv))
2566 return -EAGAIN;
2567
727882d6
AK		 2568 iwlcore_commit_rxon(priv);
2569
2570 return 0;
2571}
2572EXPORT_SYMBOL(iwl_set_mode);
2573
cbb6ab94
AK		 2574int iwl_mac_add_interface(struct ieee80211_hw *hw,
2575 struct ieee80211_if_init_conf *conf)
2576{
2577 struct iwl_priv *priv = hw->priv;
2578 unsigned long flags;
2579
2580 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2581
2582 if (priv->vif) {
2583 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2584 return -EOPNOTSUPP;
2585 }
2586
2587 spin_lock_irqsave(&priv->lock, flags);
2588 priv->vif = conf->vif;
2589 priv->iw_mode = conf->type;
2590
2591 spin_unlock_irqrestore(&priv->lock, flags);
2592
2593 mutex_lock(&priv->mutex);
2594
2595 if (conf->mac_addr) {
2596 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2597 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2598 }
2599
2600 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2601 /* we are not ready, will run again when ready */
2602 set_bit(STATUS_MODE_PENDING, &priv->status);
2603
2604 mutex_unlock(&priv->mutex);
2605
2606 IWL_DEBUG_MAC80211(priv, "leave\n");
2607 return 0;
2608}
2609EXPORT_SYMBOL(iwl_mac_add_interface);
2610
d8052319
AK		 2611void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2612 struct ieee80211_if_init_conf *conf)
2613{
2614 struct iwl_priv *priv = hw->priv;
2615
2616 IWL_DEBUG_MAC80211(priv, "enter\n");
2617
2618 mutex_lock(&priv->mutex);
2619
2620 if (iwl_is_ready_rf(priv)) {
2621 iwl_scan_cancel_timeout(priv, 100);
2622 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2623 iwlcore_commit_rxon(priv);
2624 }
2625 if (priv->vif == conf->vif) {
2626 priv->vif = NULL;
2627 memset(priv->bssid, 0, ETH_ALEN);
2628 }
2629 mutex_unlock(&priv->mutex);
2630
2631 IWL_DEBUG_MAC80211(priv, "leave\n");
2632
2633}
2634EXPORT_SYMBOL(iwl_mac_remove_interface);
2635
4808368d
AK		 2636/**
2637 * iwl_mac_config - mac80211 config callback
2638 *
2639 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2640 * be set inappropriately and the driver currently sets the hardware up to
2641 * use it whenever needed.
2642 */
2643int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2644{
2645 struct iwl_priv *priv = hw->priv;
2646 const struct iwl_channel_info *ch_info;
2647 struct ieee80211_conf *conf = &hw->conf;
2648 unsigned long flags = 0;
2649 int ret = 0;
2650 u16 ch;
2651 int scan_active = 0;
2652
2653 mutex_lock(&priv->mutex);
2654
4808368d
AK		 2655 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2656 conf->channel->hw_value, changed);
2657
2658 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2659 test_bit(STATUS_SCANNING, &priv->status))) {
2660 scan_active = 1;
2661 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2662 }
2663
2664
2665 /* during scanning mac80211 will delay channel setting until
2666 * scan finish with changed = 0
2667 */
2668 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2669 if (scan_active)
2670 goto set_ch_out;
2671
2672 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2673 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2674 if (!is_channel_valid(ch_info)) {
2675 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2676 ret = -EINVAL;
2677 goto set_ch_out;
2678 }
2679
2680 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2681 !is_channel_ibss(ch_info)) {
2682 IWL_ERR(priv, "channel %d in band %d not "
2683 "IBSS channel\n",
2684 conf->channel->hw_value, conf->channel->band);
2685 ret = -EINVAL;
2686 goto set_ch_out;
2687 }
2688
2689 priv->current_ht_config.is_ht = conf_is_ht(conf);
2690
2691 spin_lock_irqsave(&priv->lock, flags);
2692
2693
2694 /* if we are switching from ht to 2.4 clear flags
2695 * from any ht related info since 2.4 does not
2696 * support ht */
2697 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2698 priv->staging_rxon.flags = 0;
2699
2700 iwl_set_rxon_channel(priv, conf->channel);
2701
2702 iwl_set_flags_for_band(priv, conf->channel->band);
2703 spin_unlock_irqrestore(&priv->lock, flags);
2704 set_ch_out:
2705 /* The list of supported rates and rate mask can be different
2706 * for each band; since the band may have changed, reset
2707 * the rate mask to what mac80211 lists */
2708 iwl_set_rate(priv);
2709 }
2710
7af2c460
JB		 2711 if (changed & IEEE80211_CONF_CHANGE_PS &&
2712 priv->iw_mode == NL80211_IFTYPE_STATION) {
2713 priv->power_data.power_disabled =
2714 !(conf->flags & IEEE80211_CONF_PS);
2715 ret = iwl_power_update_mode(priv, 0);
4808368d
AK		 2716 if (ret)
2717 IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
4808368d
AK		 2718 }
2719
2720 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2721 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2722 priv->tx_power_user_lmt, conf->power_level);
2723
2724 iwl_set_tx_power(priv, conf->power_level, false);
2725 }
2726
2727 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2728 if (priv->cfg->ops->hcmd->set_rxon_chain)
2729 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2730
0cf4c01e
MA		 2731 if (!iwl_is_ready(priv)) {
2732 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2733 goto out;
2734 }
2735
4808368d
AK		 2736 if (scan_active)
2737 goto out;
2738
2739 if (memcmp(&priv->active_rxon,
2740 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2741 iwlcore_commit_rxon(priv);
2742 else
2743 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2744
2745
2746out:
2747 IWL_DEBUG_MAC80211(priv, "leave\n");
2748 mutex_unlock(&priv->mutex);
2749 return ret;
2750}
2751EXPORT_SYMBOL(iwl_mac_config);
2752
aa89f31e
AK		 2753int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2754 struct ieee80211_tx_queue_stats *stats)
2755{
2756 struct iwl_priv *priv = hw->priv;
2757 int i, avail;
2758 struct iwl_tx_queue *txq;
2759 struct iwl_queue *q;
2760 unsigned long flags;
2761
2762 IWL_DEBUG_MAC80211(priv, "enter\n");
2763
2764 if (!iwl_is_ready_rf(priv)) {
2765 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2766 return -EIO;
2767 }
2768
2769 spin_lock_irqsave(&priv->lock, flags);
2770
2771 for (i = 0; i < AC_NUM; i++) {
2772 txq = &priv->txq[i];
2773 q = &txq->q;
2774 avail = iwl_queue_space(q);
2775
2776 stats[i].len = q->n_window - avail;
2777 stats[i].limit = q->n_window - q->high_mark;
2778 stats[i].count = q->n_window;
2779
2780 }
2781 spin_unlock_irqrestore(&priv->lock, flags);
2782
2783 IWL_DEBUG_MAC80211(priv, "leave\n");
2784
2785 return 0;
2786}
2787EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2788
bd564261
AK		 2789void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2790{
2791 struct iwl_priv *priv = hw->priv;
2792 unsigned long flags;
2793
2794 mutex_lock(&priv->mutex);
2795 IWL_DEBUG_MAC80211(priv, "enter\n");
2796
2797 spin_lock_irqsave(&priv->lock, flags);
2798 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
2799 spin_unlock_irqrestore(&priv->lock, flags);
2800
2801 iwl_reset_qos(priv);
2802
2803 spin_lock_irqsave(&priv->lock, flags);
2804 priv->assoc_id = 0;
2805 priv->assoc_capability = 0;
2806 priv->assoc_station_added = 0;
2807
2808 /* new association get rid of ibss beacon skb */
2809 if (priv->ibss_beacon)
2810 dev_kfree_skb(priv->ibss_beacon);
2811
2812 priv->ibss_beacon = NULL;
2813
57c4d7b4 2814 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2815 priv->timestamp = 0;
2816 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2817 priv->beacon_int = 0;
2818
2819 spin_unlock_irqrestore(&priv->lock, flags);
2820
2821 if (!iwl_is_ready_rf(priv)) {
2822 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2823 mutex_unlock(&priv->mutex);
2824 return;
2825 }
2826
2827 /* we are restarting association process
2828 * clear RXON_FILTER_ASSOC_MSK bit
2829 */
2830 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2831 iwl_scan_cancel_timeout(priv, 100);
2832 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2833 iwlcore_commit_rxon(priv);
2834 }
2835
bd564261 2836 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2837 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2838 mutex_unlock(&priv->mutex);
2839 return;
2840 }
2841
2842 iwl_set_rate(priv);
2843
2844 mutex_unlock(&priv->mutex);
2845
2846 IWL_DEBUG_MAC80211(priv, "leave\n");
2847}
2848EXPORT_SYMBOL(iwl_mac_reset_tsf);
2849
6da3a13e
WYG		 2850#ifdef CONFIG_PM
2851
2852int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2853{
2854 struct iwl_priv *priv = pci_get_drvdata(pdev);
2855
2856 /*
2857 * This function is called when system goes into suspend state
2858 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
2859 * first but since iwl_mac_stop() has no knowledge of who the caller is,
2860 * it will not call apm_ops.stop() to stop the DMA operation.
2861 * Calling apm_ops.stop here to make sure we stop the DMA.
2862 */
2863 priv->cfg->ops->lib->apm_ops.stop(priv);
2864
2865 pci_save_state(pdev);
2866 pci_disable_device(pdev);
2867 pci_set_power_state(pdev, PCI_D3hot);
2868
2869 return 0;
2870}
2871EXPORT_SYMBOL(iwl_pci_suspend);
2872
2873int iwl_pci_resume(struct pci_dev *pdev)
2874{
2875 struct iwl_priv *priv = pci_get_drvdata(pdev);
2876 int ret;
2877
2878 pci_set_power_state(pdev, PCI_D0);
2879 ret = pci_enable_device(pdev);
2880 if (ret)
2881 return ret;
2882 pci_restore_state(pdev);
2883 iwl_enable_interrupts(priv);
2884
2885 return 0;
2886}
2887EXPORT_SYMBOL(iwl_pci_resume);
2888
2889#endif /* CONFIG_PM */
Linux kernel - Deliverables
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