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iwlwifi: add iwl_cmd_queue_free for readability
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
1d0a082d 31#include <net/mac80211.h>
df48c323 32
712b6cf5 33struct iwl_priv; /* FIXME: remove */
0a6857e7 34#include "iwl-debug.h"
6bc913bd 35#include "iwl-eeprom.h"
3e0d4cb1 36#include "iwl-dev.h" /* FIXME: remove */
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
ad97edd2 39#include "iwl-rfkill.h"
5da4b55f 40#include "iwl-power.h"
df48c323 41
1d0a082d 42
df48c323
TW		 43MODULE_DESCRIPTION("iwl core");
44MODULE_VERSION(IWLWIFI_VERSION);
45MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 46MODULE_LICENSE("GPL");
df48c323 47
c7de35cd
RR		 48#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
60
61/*
62 * Parameter order:
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
1826dcc0 69const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 70 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
84};
1826dcc0 85EXPORT_SYMBOL(iwl_rates);
c7de35cd 86
e7d326ac
TW		 87/**
88 * translate ucode response to mac80211 tx status control values
89 */
90void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 91 struct ieee80211_tx_info *info)
e7d326ac
TW		 92{
93 int rate_index;
e6a9854b 94 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 95
e6a9854b 96 info->antenna_sel_tx =
e7d326ac
TW		 97 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
98 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 99 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 100 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 101 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
e7d326ac 102 if (rate_n_flags & RATE_MCS_FAT_MSK)
e6a9854b 103 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 104 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 105 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 106 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 107 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 108 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 109 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 110 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 111 r->idx = rate_index;
e7d326ac
TW		 112}
113EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
114
115int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
116{
117 int idx = 0;
118
119 /* HT rate format */
120 if (rate_n_flags & RATE_MCS_HT_MSK) {
121 idx = (rate_n_flags & 0xff);
122
123 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
124 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
125
126 idx += IWL_FIRST_OFDM_RATE;
127 /* skip 9M not supported in ht*/
128 if (idx >= IWL_RATE_9M_INDEX)
129 idx += 1;
130 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
131 return idx;
132
133 /* legacy rate format, search for match in table */
134 } else {
135 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
136 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
137 return idx;
138 }
139
140 return -1;
141}
142EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
143
144
57bd1bea
TW		 145
146const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
147EXPORT_SYMBOL(iwl_bcast_addr);
148
149
1d0a082d
AK		 150/* This function both allocates and initializes hw and priv. */
151struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
152 struct ieee80211_ops *hw_ops)
153{
154 struct iwl_priv *priv;
155
156 /* mac80211 allocates memory for this device instance, including
157 * space for this driver's private structure */
158 struct ieee80211_hw *hw =
159 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
160 if (hw == NULL) {
161 IWL_ERROR("Can not allocate network device\n");
162 goto out;
163 }
164
165 priv = hw->priv;
166 priv->hw = hw;
167
168out:
169 return hw;
170}
171EXPORT_SYMBOL(iwl_alloc_all);
172
b661c819
TW		 173void iwl_hw_detect(struct iwl_priv *priv)
174{
175 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
176 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
177 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
178}
179EXPORT_SYMBOL(iwl_hw_detect);
180
1053d35f
RR		 181/* Tell nic where to find the "keep warm" buffer */
182int iwl_kw_init(struct iwl_priv *priv)
183{
184 unsigned long flags;
185 int ret;
186
187 spin_lock_irqsave(&priv->lock, flags);
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
193 priv->kw.dma_addr >> 4);
194 iwl_release_nic_access(priv);
195out:
196 spin_unlock_irqrestore(&priv->lock, flags);
197 return ret;
198}
199
200int iwl_kw_alloc(struct iwl_priv *priv)
201{
202 struct pci_dev *dev = priv->pci_dev;
16466903 203 struct iwl_kw *kw = &priv->kw;
1053d35f 204
16466903 205 kw->size = IWL_KW_SIZE;
1053d35f
RR		 206 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
207 if (!kw->v_addr)
208 return -ENOMEM;
209
210 return 0;
211}
212
213/**
214 * iwl_kw_free - Free the "keep warm" buffer
215 */
216void iwl_kw_free(struct iwl_priv *priv)
217{
218 struct pci_dev *dev = priv->pci_dev;
16466903 219 struct iwl_kw *kw = &priv->kw;
1053d35f
RR		 220
221 if (kw->v_addr) {
222 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
223 memset(kw, 0, sizeof(*kw));
224 }
225}
226
227int iwl_hw_nic_init(struct iwl_priv *priv)
228{
229 unsigned long flags;
230 struct iwl_rx_queue *rxq = &priv->rxq;
231 int ret;
232
233 /* nic_init */
1053d35f 234 spin_lock_irqsave(&priv->lock, flags);
1b73af82 235 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 236 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
237 spin_unlock_irqrestore(&priv->lock, flags);
238
239 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
240
241 priv->cfg->ops->lib->apm_ops.config(priv);
242
243 /* Allocate the RX queue, or reset if it is already allocated */
244 if (!rxq->bd) {
245 ret = iwl_rx_queue_alloc(priv);
246 if (ret) {
247 IWL_ERROR("Unable to initialize Rx queue\n");
248 return -ENOMEM;
249 }
250 } else
251 iwl_rx_queue_reset(priv, rxq);
252
253 iwl_rx_replenish(priv);
254
255 iwl_rx_init(priv, rxq);
256
257 spin_lock_irqsave(&priv->lock, flags);
258
259 rxq->need_update = 1;
260 iwl_rx_queue_update_write_ptr(priv, rxq);
261
262 spin_unlock_irqrestore(&priv->lock, flags);
263
264 /* Allocate and init all Tx and Command queues */
265 ret = iwl_txq_ctx_reset(priv);
266 if (ret)
267 return ret;
268
269 set_bit(STATUS_INIT, &priv->status);
270
271 return 0;
272}
273EXPORT_SYMBOL(iwl_hw_nic_init);
274
bf85ea4f 275/**
37deb2a0 276 * iwl_clear_stations_table - Clear the driver's station table
bf85ea4f
AK		 277 *
278 * NOTE: This does not clear or otherwise alter the device's station table.
279 */
37deb2a0 280void iwl_clear_stations_table(struct iwl_priv *priv)
bf85ea4f
AK		 281{
282 unsigned long flags;
283
284 spin_lock_irqsave(&priv->sta_lock, flags);
285
24e5c401 286 if (iwl_is_alive(priv) &&
37deb2a0
EG		 287 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
288 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
24e5c401
EG		 289 IWL_ERROR("Couldn't clear the station table\n");
290
37deb2a0 291 priv->num_stations = 0;
bf85ea4f
AK		 292 memset(priv->stations, 0, sizeof(priv->stations));
293
294 spin_unlock_irqrestore(&priv->sta_lock, flags);
295}
37deb2a0 296EXPORT_SYMBOL(iwl_clear_stations_table);
bf85ea4f 297
c7de35cd 298void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 299{
300 u16 cw_min = 15;
301 u16 cw_max = 1023;
302 u8 aifs = 2;
303 u8 is_legacy = 0;
304 unsigned long flags;
305 int i;
306
307 spin_lock_irqsave(&priv->lock, flags);
308 priv->qos_data.qos_active = 0;
309
05c914fe 310 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
bf85ea4f
AK		 311 if (priv->qos_data.qos_enable)
312 priv->qos_data.qos_active = 1;
313 if (!(priv->active_rate & 0xfff0)) {
314 cw_min = 31;
315 is_legacy = 1;
316 }
05c914fe 317 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
bf85ea4f
AK		 318 if (priv->qos_data.qos_enable)
319 priv->qos_data.qos_active = 1;
320 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
321 cw_min = 31;
322 is_legacy = 1;
323 }
324
325 if (priv->qos_data.qos_active)
326 aifs = 3;
327
328 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
329 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
330 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
331 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
332 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
333
334 if (priv->qos_data.qos_active) {
335 i = 1;
336 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
337 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
338 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
339 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
340 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
341
342 i = 2;
343 priv->qos_data.def_qos_parm.ac[i].cw_min =
344 cpu_to_le16((cw_min + 1) / 2 - 1);
345 priv->qos_data.def_qos_parm.ac[i].cw_max =
346 cpu_to_le16(cw_max);
347 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
348 if (is_legacy)
349 priv->qos_data.def_qos_parm.ac[i].edca_txop =
350 cpu_to_le16(6016);
351 else
352 priv->qos_data.def_qos_parm.ac[i].edca_txop =
353 cpu_to_le16(3008);
354 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
355
356 i = 3;
357 priv->qos_data.def_qos_parm.ac[i].cw_min =
358 cpu_to_le16((cw_min + 1) / 4 - 1);
359 priv->qos_data.def_qos_parm.ac[i].cw_max =
360 cpu_to_le16((cw_max + 1) / 2 - 1);
361 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
362 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
363 if (is_legacy)
364 priv->qos_data.def_qos_parm.ac[i].edca_txop =
365 cpu_to_le16(3264);
366 else
367 priv->qos_data.def_qos_parm.ac[i].edca_txop =
368 cpu_to_le16(1504);
369 } else {
370 for (i = 1; i < 4; i++) {
371 priv->qos_data.def_qos_parm.ac[i].cw_min =
372 cpu_to_le16(cw_min);
373 priv->qos_data.def_qos_parm.ac[i].cw_max =
374 cpu_to_le16(cw_max);
375 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
376 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
377 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
378 }
379 }
380 IWL_DEBUG_QOS("set QoS to default \n");
381
382 spin_unlock_irqrestore(&priv->lock, flags);
383}
c7de35cd
RR		 384EXPORT_SYMBOL(iwl_reset_qos);
385
d9fe60de
JB		 386#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
387#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 388static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 389 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 390 enum ieee80211_band band)
391{
39130df3
RR		 392 u16 max_bit_rate = 0;
393 u8 rx_chains_num = priv->hw_params.rx_chains_num;
394 u8 tx_chains_num = priv->hw_params.tx_chains_num;
395
c7de35cd 396 ht_info->cap = 0;
d9fe60de 397 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 398
d9fe60de 399 ht_info->ht_supported = true;
c7de35cd 400
d9fe60de
JB		 401 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
402 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
403 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 404 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 405
406 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 407 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 408 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
409 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
410 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 411 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 412 }
c7de35cd
RR		 413
414 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 415 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 416
417 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
418 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
419
d9fe60de 420 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 421 if (rx_chains_num >= 2)
d9fe60de 422 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 423 if (rx_chains_num >= 3)
d9fe60de 424 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 425
426 /* Highest supported Rx data rate */
427 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 428 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
429 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 430
431 /* Tx MCS capabilities */
d9fe60de 432 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 433 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 434 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
435 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
436 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 437 }
c7de35cd 438}
c7de35cd
RR		 439
440static void iwlcore_init_hw_rates(struct iwl_priv *priv,
441 struct ieee80211_rate *rates)
442{
443 int i;
444
445 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 446 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 447 rates[i].hw_value = i; /* Rate scaling will work on indexes */
448 rates[i].hw_value_short = i;
449 rates[i].flags = 0;
450 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
451 /*
452 * If CCK != 1M then set short preamble rate flag.
453 */
454 rates[i].flags |=
1826dcc0 455 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 456 0 : IEEE80211_RATE_SHORT_PREAMBLE;
457 }
458 }
459}
460
461/**
462 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
463 */
464static int iwlcore_init_geos(struct iwl_priv *priv)
465{
466 struct iwl_channel_info *ch;
467 struct ieee80211_supported_band *sband;
468 struct ieee80211_channel *channels;
469 struct ieee80211_channel *geo_ch;
470 struct ieee80211_rate *rates;
471 int i = 0;
472
473 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
474 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
475 IWL_DEBUG_INFO("Geography modes already initialized.\n");
476 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
477 return 0;
478 }
479
480 channels = kzalloc(sizeof(struct ieee80211_channel) *
481 priv->channel_count, GFP_KERNEL);
482 if (!channels)
483 return -ENOMEM;
484
485 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
486 GFP_KERNEL);
487 if (!rates) {
488 kfree(channels);
489 return -ENOMEM;
490 }
491
492 /* 5.2GHz channels start after the 2.4GHz channels */
493 sband = &priv->bands[IEEE80211_BAND_5GHZ];
494 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
495 /* just OFDM */
496 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
497 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
498
49779293 499 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 500 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 501 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 502
503 sband = &priv->bands[IEEE80211_BAND_2GHZ];
504 sband->channels = channels;
505 /* OFDM & CCK */
506 sband->bitrates = rates;
507 sband->n_bitrates = IWL_RATE_COUNT;
508
49779293 509 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 510 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 511 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 512
513 priv->ieee_channels = channels;
514 priv->ieee_rates = rates;
515
516 iwlcore_init_hw_rates(priv, rates);
517
518 for (i = 0; i < priv->channel_count; i++) {
519 ch = &priv->channel_info[i];
520
521 /* FIXME: might be removed if scan is OK */
522 if (!is_channel_valid(ch))
523 continue;
524
525 if (is_channel_a_band(ch))
526 sband = &priv->bands[IEEE80211_BAND_5GHZ];
527 else
528 sband = &priv->bands[IEEE80211_BAND_2GHZ];
529
530 geo_ch = &sband->channels[sband->n_channels++];
531
532 geo_ch->center_freq =
533 ieee80211_channel_to_frequency(ch->channel);
534 geo_ch->max_power = ch->max_power_avg;
535 geo_ch->max_antenna_gain = 0xff;
536 geo_ch->hw_value = ch->channel;
537
538 if (is_channel_valid(ch)) {
539 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
540 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
541
542 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
543 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
544
545 if (ch->flags & EEPROM_CHANNEL_RADAR)
546 geo_ch->flags |= IEEE80211_CHAN_RADAR;
547
963f5517 548 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 549
630fe9b6
TW		 550 if (ch->max_power_avg > priv->tx_power_channel_lmt)
551 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 552 } else {
553 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
554 }
555
556 /* Save flags for reg domain usage */
557 geo_ch->orig_flags = geo_ch->flags;
558
963f5517 559 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 560 ch->channel, geo_ch->center_freq,
561 is_channel_a_band(ch) ? "5.2" : "2.4",
562 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
563 "restricted" : "valid",
564 geo_ch->flags);
565 }
566
567 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
568 priv->cfg->sku & IWL_SKU_A) {
569 printk(KERN_INFO DRV_NAME
570 ": Incorrectly detected BG card as ABG. Please send "
571 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
572 priv->pci_dev->device, priv->pci_dev->subsystem_device);
573 priv->cfg->sku &= ~IWL_SKU_A;
574 }
575
576 printk(KERN_INFO DRV_NAME
577 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
578 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
579 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
580
c7de35cd
RR		 581
582 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
583
584 return 0;
585}
586
587/*
588 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
589 */
6ba87956 590static void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 591{
592 kfree(priv->ieee_channels);
593 kfree(priv->ieee_rates);
594 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
595}
c7de35cd 596
28a6b07a 597static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 598{
599 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 600 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
601 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 602}
963f5517 603
47c5196e
TW		 604static u8 iwl_is_channel_extension(struct iwl_priv *priv,
605 enum ieee80211_band band,
606 u16 channel, u8 extension_chan_offset)
607{
608 const struct iwl_channel_info *ch_info;
609
610 ch_info = iwl_get_channel_info(priv, band, channel);
611 if (!is_channel_valid(ch_info))
612 return 0;
613
d9fe60de 614 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517
EG		 615 return !(ch_info->fat_extension_channel &
616 IEEE80211_CHAN_NO_FAT_ABOVE);
d9fe60de 617 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517
EG		 618 return !(ch_info->fat_extension_channel &
619 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 620
621 return 0;
622}
623
624u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 625 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 626{
627 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
628
629 if ((!iwl_ht_conf->is_ht) ||
630 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
d9fe60de 631 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
47c5196e
TW		 632 return 0;
633
634 if (sta_ht_inf) {
635 if ((!sta_ht_inf->ht_supported) ||
d9fe60de 636 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
47c5196e
TW		 637 return 0;
638 }
639
640 return iwl_is_channel_extension(priv, priv->band,
ae5eb026
JB		 641 le16_to_cpu(priv->staging_rxon.channel),
642 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 643}
644EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
645
646void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
647{
c1adf9fb 648 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 649 u32 val;
650
42eb7c64
EG		 651 if (!ht_info->is_ht) {
652 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
653 RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
654 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
655 RXON_FLG_FAT_PROT_MSK |
656 RXON_FLG_HT_PROT_MSK);
47c5196e 657 return;
42eb7c64 658 }
47c5196e
TW		 659
660 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
661 if (iwl_is_fat_tx_allowed(priv, NULL))
662 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
663 else
664 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
665 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
666
47c5196e
TW		 667 /* Note: control channel is opposite of extension channel */
668 switch (ht_info->extension_chan_offset) {
d9fe60de 669 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
47c5196e
TW		 670 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
671 break;
d9fe60de 672 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
47c5196e
TW		 673 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
674 break;
d9fe60de 675 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
47c5196e
TW		 676 default:
677 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
678 break;
679 }
680
681 val = ht_info->ht_protection;
682
683 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
684
685 iwl_set_rxon_chain(priv);
686
687 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
688 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 689 "extension channel offset 0x%x\n",
d9fe60de
JB		 690 ht_info->mcs.rx_mask[0],
691 ht_info->mcs.rx_mask[1],
692 ht_info->mcs.rx_mask[2],
47c5196e 693 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 694 ht_info->extension_chan_offset);
47c5196e
TW		 695 return;
696}
697EXPORT_SYMBOL(iwl_set_rxon_ht);
698
9e5e6c32
TW		 699#define IWL_NUM_RX_CHAINS_MULTIPLE 3
700#define IWL_NUM_RX_CHAINS_SINGLE 2
701#define IWL_NUM_IDLE_CHAINS_DUAL 2
702#define IWL_NUM_IDLE_CHAINS_SINGLE 1
703
704/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 705 * More provides better reception via diversity. Fewer saves power.
706 * MIMO (dual stream) requires at least 2, but works better with 3.
707 * This does not determine *which* chains to use, just how many.
708 */
28a6b07a 709static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 710{
28a6b07a
TW		 711 bool is_single = is_single_rx_stream(priv);
712 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 713
714 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 715 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
716 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 717 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 718 else
9e5e6c32 719 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 720}
c7de35cd 721
28a6b07a
TW		 722static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
723{
724 int idle_cnt;
725 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 726 /* # Rx chains when idling and maybe trying to save power */
12837be1 727 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 728 case WLAN_HT_CAP_SM_PS_STATIC:
729 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 730 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
731 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 732 break;
00c5ae2f 733 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 734 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 735 break;
00c5ae2f 736 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 737 default:
12837be1
RR		 738 IWL_ERROR("invalide mimo ps mode %d\n",
739 priv->current_ht_config.sm_ps);
28a6b07a
TW		 740 WARN_ON(1);
741 idle_cnt = -1;
c7de35cd
RR		 742 break;
743 }
28a6b07a 744 return idle_cnt;
c7de35cd
RR		 745}
746
04816448
GE		 747/* up to 4 chains */
748static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
749{
750 u8 res;
751 res = (chain_bitmap & BIT(0)) >> 0;
752 res += (chain_bitmap & BIT(1)) >> 1;
753 res += (chain_bitmap & BIT(2)) >> 2;
754 res += (chain_bitmap & BIT(4)) >> 4;
755 return res;
756}
757
c7de35cd
RR		 758/**
759 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
760 *
761 * Selects how many and which Rx receivers/antennas/chains to use.
762 * This should not be used for scan command ... it puts data in wrong place.
763 */
764void iwl_set_rxon_chain(struct iwl_priv *priv)
765{
28a6b07a
TW		 766 bool is_single = is_single_rx_stream(priv);
767 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 768 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
769 u32 active_chains;
28a6b07a 770 u16 rx_chain;
c7de35cd
RR		 771
772 /* Tell uCode which antennas are actually connected.
773 * Before first association, we assume all antennas are connected.
774 * Just after first association, iwl_chain_noise_calibration()
775 * checks which antennas actually *are* connected. */
04816448
GE		 776 if (priv->chain_noise_data.active_chains)
777 active_chains = priv->chain_noise_data.active_chains;
778 else
779 active_chains = priv->hw_params.valid_rx_ant;
780
781 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 782
783 /* How many receivers should we use? */
28a6b07a
TW		 784 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
785 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
786
28a6b07a 787
04816448
GE		 788 /* correct rx chain count according hw settings
789 * and chain noise calibration
790 */
791 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
792 if (valid_rx_cnt < active_rx_cnt)
793 active_rx_cnt = valid_rx_cnt;
794
795 if (valid_rx_cnt < idle_rx_cnt)
796 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 797
798 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
799 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
800
801 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
802
9e5e6c32 803 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 804 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
805 else
806 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
807
a33c2f47 808 IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 809 priv->staging_rxon.rx_chain,
810 active_rx_cnt, idle_rx_cnt);
811
812 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
813 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 814}
815EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 816
817/**
17e72782 818 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 819 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
820 * @channel: Any channel valid for the requested phymode
821
822 * In addition to setting the staging RXON, priv->phymode is also set.
823 *
824 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
825 * in the staging RXON flag structure based on the phymode
826 */
17e72782 827int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 828{
17e72782
TW		 829 enum ieee80211_band band = ch->band;
830 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
831
8622e705 832 if (!iwl_get_channel_info(priv, band, channel)) {
bf85ea4f
AK		 833 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
834 channel, band);
835 return -EINVAL;
836 }
837
838 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
839 (priv->band == band))
840 return 0;
841
842 priv->staging_rxon.channel = cpu_to_le16(channel);
843 if (band == IEEE80211_BAND_5GHZ)
844 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
845 else
846 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
847
848 priv->band = band;
849
850 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
851
852 return 0;
853}
c7de35cd 854EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 855
6ba87956 856int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 857{
6ba87956 858 int ret;
bf85ea4f 859 struct ieee80211_hw *hw = priv->hw;
e227ceac 860 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 861
566bfe5a 862 /* Tell mac80211 our characteristics */
605a0bd6 863 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 864 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 865 hw->wiphy->interface_modes =
866 BIT(NL80211_IFTYPE_AP) |
867 BIT(NL80211_IFTYPE_STATION) |
868 BIT(NL80211_IFTYPE_ADHOC);
bf85ea4f
AK		 869 /* Default value; 4 EDCA QOS priorities */
870 hw->queues = 4;
49779293
RR		 871 /* queues to support 11n aggregation */
872 if (priv->cfg->sku & IWL_SKU_N)
9f17b318 873 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
6ba87956
TW		 874
875 hw->conf.beacon_int = 100;
b5d7be5e 876 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 877
878 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
879 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
880 &priv->bands[IEEE80211_BAND_2GHZ];
881 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
882 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
883 &priv->bands[IEEE80211_BAND_5GHZ];
884
885 ret = ieee80211_register_hw(priv->hw);
886 if (ret) {
887 IWL_ERROR("Failed to register hw (error %d)\n", ret);
888 return ret;
889 }
890 priv->mac80211_registered = 1;
891
892 return 0;
bf85ea4f 893}
6ba87956 894EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 895
da154e30
RR		 896int iwl_set_hw_params(struct iwl_priv *priv)
897{
898 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
899 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
900 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
901 if (priv->cfg->mod_params->amsdu_size_8K)
902 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
903 else
904 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
905 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
906
49779293
RR		 907 if (priv->cfg->mod_params->disable_11n)
908 priv->cfg->sku &= ~IWL_SKU_N;
909
da154e30
RR		 910 /* Device-specific setup */
911 return priv->cfg->ops->lib->set_hw_params(priv);
912}
913EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 914
915int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 916{
917 int ret;
c7de35cd
RR		 918
919 priv->retry_rate = 1;
920 priv->ibss_beacon = NULL;
921
922 spin_lock_init(&priv->lock);
923 spin_lock_init(&priv->power_data.lock);
924 spin_lock_init(&priv->sta_lock);
925 spin_lock_init(&priv->hcmd_lock);
c7de35cd 926
c7de35cd
RR		 927 INIT_LIST_HEAD(&priv->free_frames);
928
929 mutex_init(&priv->mutex);
930
931 /* Clear the driver's (not device's) station table */
37deb2a0 932 iwl_clear_stations_table(priv);
c7de35cd
RR		 933
934 priv->data_retry_limit = -1;
935 priv->ieee_channels = NULL;
936 priv->ieee_rates = NULL;
937 priv->band = IEEE80211_BAND_2GHZ;
938
05c914fe 939 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd
RR		 940
941 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
12837be1 942 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 943
944 /* Choose which receivers/antennas to use */
945 iwl_set_rxon_chain(priv);
f53696de 946 iwl_init_scan_params(priv);
c7de35cd 947
6ba87956
TW		 948 if (priv->cfg->mod_params->enable_qos)
949 priv->qos_data.qos_enable = 1;
950
c7de35cd
RR		 951 iwl_reset_qos(priv);
952
953 priv->qos_data.qos_active = 0;
954 priv->qos_data.qos_cap.val = 0;
955
c7de35cd
RR		 956 priv->rates_mask = IWL_RATES_MASK;
957 /* If power management is turned on, default to AC mode */
958 priv->power_mode = IWL_POWER_AC;
630fe9b6 959 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 960
961 ret = iwl_init_channel_map(priv);
962 if (ret) {
963 IWL_ERROR("initializing regulatory failed: %d\n", ret);
964 goto err;
965 }
966
967 ret = iwlcore_init_geos(priv);
968 if (ret) {
969 IWL_ERROR("initializing geos failed: %d\n", ret);
970 goto err_free_channel_map;
971 }
972
c7de35cd
RR		 973 return 0;
974
c7de35cd
RR		 975err_free_channel_map:
976 iwl_free_channel_map(priv);
977err:
978 return ret;
979}
6ba87956 980EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 981
630fe9b6
TW		 982int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
983{
984 int ret = 0;
985 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
986 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
987 priv->tx_power_user_lmt);
988 return -EINVAL;
989 }
990
991 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
992 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
993 priv->tx_power_user_lmt);
994 return -EINVAL;
995 }
996
997 if (priv->tx_power_user_lmt != tx_power)
998 force = true;
999
1000 priv->tx_power_user_lmt = tx_power;
1001
1002 if (force && priv->cfg->ops->lib->send_tx_power)
1003 ret = priv->cfg->ops->lib->send_tx_power(priv);
1004
1005 return ret;
1006}
1007EXPORT_SYMBOL(iwl_set_tx_power);
1008
6ba87956 1009void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1010{
6e21f2c1 1011 iwl_calib_free_results(priv);
6ba87956
TW		 1012 iwlcore_free_geos(priv);
1013 iwl_free_channel_map(priv);
261415f7 1014 kfree(priv->scan);
bf85ea4f 1015}
6ba87956 1016EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1017
49ea8596
EG		 1018int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1019{
1020 u32 stat_flags = 0;
1021 struct iwl_host_cmd cmd = {
1022 .id = REPLY_STATISTICS_CMD,
1023 .meta.flags = flags,
1024 .len = sizeof(stat_flags),
1025 .data = (u8 *) &stat_flags,
1026 };
1027 return iwl_send_cmd(priv, &cmd);
1028}
1029EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1030
b0692f2f
EG		 1031/**
1032 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1033 * using sample data 100 bytes apart. If these sample points are good,
1034 * it's a pretty good bet that everything between them is good, too.
1035 */
1036static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1037{
1038 u32 val;
1039 int ret = 0;
1040 u32 errcnt = 0;
1041 u32 i;
1042
1043 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1044
1045 ret = iwl_grab_nic_access(priv);
1046 if (ret)
1047 return ret;
1048
1049 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1050 /* read data comes through single port, auto-incr addr */
1051 /* NOTE: Use the debugless read so we don't flood kernel log
1052 * if IWL_DL_IO is set */
1053 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1054 i + RTC_INST_LOWER_BOUND);
1055 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1056 if (val != le32_to_cpu(*image)) {
1057 ret = -EIO;
1058 errcnt++;
1059 if (errcnt >= 3)
1060 break;
1061 }
1062 }
1063
1064 iwl_release_nic_access(priv);
1065
1066 return ret;
1067}
1068
1069/**
1070 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1071 * looking at all data.
1072 */
1073static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1074 u32 len)
1075{
1076 u32 val;
1077 u32 save_len = len;
1078 int ret = 0;
1079 u32 errcnt;
1080
1081 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1082
1083 ret = iwl_grab_nic_access(priv);
1084 if (ret)
1085 return ret;
1086
1087 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1088
1089 errcnt = 0;
1090 for (; len > 0; len -= sizeof(u32), image++) {
1091 /* read data comes through single port, auto-incr addr */
1092 /* NOTE: Use the debugless read so we don't flood kernel log
1093 * if IWL_DL_IO is set */
1094 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1095 if (val != le32_to_cpu(*image)) {
1096 IWL_ERROR("uCode INST section is invalid at "
1097 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1098 save_len - len, val, le32_to_cpu(*image));
1099 ret = -EIO;
1100 errcnt++;
1101 if (errcnt >= 20)
1102 break;
1103 }
1104 }
1105
1106 iwl_release_nic_access(priv);
1107
1108 if (!errcnt)
1109 IWL_DEBUG_INFO
1110 ("ucode image in INSTRUCTION memory is good\n");
1111
1112 return ret;
1113}
1114
1115/**
1116 * iwl_verify_ucode - determine which instruction image is in SRAM,
1117 * and verify its contents
1118 */
1119int iwl_verify_ucode(struct iwl_priv *priv)
1120{
1121 __le32 *image;
1122 u32 len;
1123 int ret;
1124
1125 /* Try bootstrap */
1126 image = (__le32 *)priv->ucode_boot.v_addr;
1127 len = priv->ucode_boot.len;
1128 ret = iwlcore_verify_inst_sparse(priv, image, len);
1129 if (!ret) {
1130 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1131 return 0;
1132 }
1133
1134 /* Try initialize */
1135 image = (__le32 *)priv->ucode_init.v_addr;
1136 len = priv->ucode_init.len;
1137 ret = iwlcore_verify_inst_sparse(priv, image, len);
1138 if (!ret) {
1139 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1140 return 0;
1141 }
1142
1143 /* Try runtime/protocol */
1144 image = (__le32 *)priv->ucode_code.v_addr;
1145 len = priv->ucode_code.len;
1146 ret = iwlcore_verify_inst_sparse(priv, image, len);
1147 if (!ret) {
1148 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1149 return 0;
1150 }
1151
1152 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1153
1154 /* Since nothing seems to match, show first several data entries in
1155 * instruction SRAM, so maybe visual inspection will give a clue.
1156 * Selection of bootstrap image (vs. other images) is arbitrary. */
1157 image = (__le32 *)priv->ucode_boot.v_addr;
1158 len = priv->ucode_boot.len;
1159 ret = iwl_verify_inst_full(priv, image, len);
1160
1161 return ret;
1162}
1163EXPORT_SYMBOL(iwl_verify_ucode);
1164
56e12615
JS		 1165
1166static const char *desc_lookup_text[] = {
1167 "OK",
1168 "FAIL",
1169 "BAD_PARAM",
1170 "BAD_CHECKSUM",
1171 "NMI_INTERRUPT_WDG",
1172 "SYSASSERT",
1173 "FATAL_ERROR",
1174 "BAD_COMMAND",
1175 "HW_ERROR_TUNE_LOCK",
1176 "HW_ERROR_TEMPERATURE",
1177 "ILLEGAL_CHAN_FREQ",
1178 "VCC_NOT_STABLE",
1179 "FH_ERROR",
1180 "NMI_INTERRUPT_HOST",
1181 "NMI_INTERRUPT_ACTION_PT",
1182 "NMI_INTERRUPT_UNKNOWN",
1183 "UCODE_VERSION_MISMATCH",
1184 "HW_ERROR_ABS_LOCK",
1185 "HW_ERROR_CAL_LOCK_FAIL",
1186 "NMI_INTERRUPT_INST_ACTION_PT",
1187 "NMI_INTERRUPT_DATA_ACTION_PT",
1188 "NMI_TRM_HW_ER",
1189 "NMI_INTERRUPT_TRM",
1190 "NMI_INTERRUPT_BREAK_POINT"
1191 "DEBUG_0",
1192 "DEBUG_1",
1193 "DEBUG_2",
1194 "DEBUG_3",
1195 "UNKNOWN"
1196};
1197
ede0cba4
EK		 1198static const char *desc_lookup(int i)
1199{
56e12615
JS		 1200 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1201
1202 if (i < 0 || i > max)
1203 i = max;
ede0cba4 1204
56e12615 1205 return desc_lookup_text[i];
ede0cba4
EK		 1206}
1207
1208#define ERROR_START_OFFSET (1 * sizeof(u32))
1209#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1210
1211void iwl_dump_nic_error_log(struct iwl_priv *priv)
1212{
1213 u32 data2, line;
1214 u32 desc, time, count, base, data1;
1215 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1216 int ret;
ede0cba4 1217
e1dfc085
GG		 1218 if (priv->ucode_type == UCODE_INIT)
1219 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1220 else
1221 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1222
1223 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1224 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1225 return;
1226 }
1227
e1dfc085
GG		 1228 ret = iwl_grab_nic_access(priv);
1229 if (ret) {
ede0cba4
EK		 1230 IWL_WARNING("Can not read from adapter at this time.\n");
1231 return;
1232 }
1233
1234 count = iwl_read_targ_mem(priv, base);
1235
1236 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1237 IWL_ERROR("Start IWL Error Log Dump:\n");
1238 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1239 }
1240
1241 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1242 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1243 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1244 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1245 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1246 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1247 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1248 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1249 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1250
56e12615 1251 IWL_ERROR("Desc Time "
ede0cba4 1252 "data1 data2 line\n");
56e12615 1253 IWL_ERROR("%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
ede0cba4
EK		 1254 desc_lookup(desc), desc, time, data1, data2, line);
1255 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1256 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1257 ilink1, ilink2);
1258
1259 iwl_release_nic_access(priv);
1260}
1261EXPORT_SYMBOL(iwl_dump_nic_error_log);
1262
189a2b59
EK		 1263#define EVENT_START_OFFSET (4 * sizeof(u32))
1264
1265/**
1266 * iwl_print_event_log - Dump error event log to syslog
1267 *
a33c2f47 1268 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
189a2b59 1269 */
a33c2f47 1270static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 1271 u32 num_events, u32 mode)
1272{
1273 u32 i;
1274 u32 base; /* SRAM byte address of event log header */
1275 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1276 u32 ptr; /* SRAM byte address of log data */
1277 u32 ev, time, data; /* event log data */
1278
1279 if (num_events == 0)
1280 return;
e1dfc085
GG		 1281 if (priv->ucode_type == UCODE_INIT)
1282 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1283 else
1284 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1285
1286 if (mode == 0)
1287 event_size = 2 * sizeof(u32);
1288 else
1289 event_size = 3 * sizeof(u32);
1290
1291 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1292
1293 /* "time" is actually "data" for mode 0 (no timestamp).
1294 * place event id # at far right for easier visual parsing. */
1295 for (i = 0; i < num_events; i++) {
1296 ev = iwl_read_targ_mem(priv, ptr);
1297 ptr += sizeof(u32);
1298 time = iwl_read_targ_mem(priv, ptr);
1299 ptr += sizeof(u32);
77c5d08e
TW		 1300 if (mode == 0) {
1301 /* data, ev */
1302 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1303 } else {
189a2b59
EK		 1304 data = iwl_read_targ_mem(priv, ptr);
1305 ptr += sizeof(u32);
77c5d08e
TW		 1306 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1307 time, data, ev);
189a2b59
EK		 1308 }
1309 }
1310}
189a2b59
EK		 1311
1312void iwl_dump_nic_event_log(struct iwl_priv *priv)
1313{
e1dfc085 1314 int ret;
189a2b59
EK		 1315 u32 base; /* SRAM byte address of event log header */
1316 u32 capacity; /* event log capacity in # entries */
1317 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1318 u32 num_wraps; /* # times uCode wrapped to top of log */
1319 u32 next_entry; /* index of next entry to be written by uCode */
1320 u32 size; /* # entries that we'll print */
1321
e1dfc085
GG		 1322 if (priv->ucode_type == UCODE_INIT)
1323 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1324 else
1325 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1326
189a2b59
EK		 1327 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1328 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1329 return;
1330 }
1331
e1dfc085
GG		 1332 ret = iwl_grab_nic_access(priv);
1333 if (ret) {
189a2b59
EK		 1334 IWL_WARNING("Can not read from adapter at this time.\n");
1335 return;
1336 }
1337
1338 /* event log header */
1339 capacity = iwl_read_targ_mem(priv, base);
1340 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1341 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1342 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1343
1344 size = num_wraps ? capacity : next_entry;
1345
1346 /* bail out if nothing in log */
1347 if (size == 0) {
1348 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1349 iwl_release_nic_access(priv);
1350 return;
1351 }
1352
1353 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1354 size, num_wraps);
1355
1356 /* if uCode has wrapped back to top of log, start at the oldest entry,
1357 * i.e the next one that uCode would fill. */
1358 if (num_wraps)
1359 iwl_print_event_log(priv, next_entry,
1360 capacity - next_entry, mode);
1361 /* (then/else) start at top of log */
1362 iwl_print_event_log(priv, 0, next_entry, mode);
1363
1364 iwl_release_nic_access(priv);
1365}
1366EXPORT_SYMBOL(iwl_dump_nic_event_log);
1367
47f4a587
EG		 1368void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1369{
1370 struct iwl_ct_kill_config cmd;
1371 unsigned long flags;
1372 int ret = 0;
1373
1374 spin_lock_irqsave(&priv->lock, flags);
1375 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1376 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1377 spin_unlock_irqrestore(&priv->lock, flags);
1378
1379 cmd.critical_temperature_R =
1380 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1381
47f4a587
EG		 1382 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1383 sizeof(cmd), &cmd);
1384 if (ret)
1385 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1386 else
1387 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1388 "critical temperature is %d\n",
1389 cmd.critical_temperature_R);
1390}
1391EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f
EG		 1392
1393/*
1394 * CARD_STATE_CMD
1395 *
1396 * Use: Sets the device's internal card state to enable, disable, or halt
1397 *
1398 * When in the 'enable' state the card operates as normal.
1399 * When in the 'disable' state, the card enters into a low power mode.
1400 * When in the 'halt' state, the card is shut down and must be fully
1401 * restarted to come back on.
1402 */
1403static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1404{
1405 struct iwl_host_cmd cmd = {
1406 .id = REPLY_CARD_STATE_CMD,
1407 .len = sizeof(u32),
1408 .data = &flags,
1409 .meta.flags = meta_flag,
1410 };
1411
1412 return iwl_send_cmd(priv, &cmd);
1413}
1414
1415void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1416{
1417 unsigned long flags;
1418
1419 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1420 return;
1421
1422 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1423
1424 iwl_scan_cancel(priv);
1425 /* FIXME: This is a workaround for AP */
05c914fe 1426 if (priv->iw_mode != NL80211_IFTYPE_AP) {
14a08a7f
EG		 1427 spin_lock_irqsave(&priv->lock, flags);
1428 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1429 CSR_UCODE_SW_BIT_RFKILL);
1430 spin_unlock_irqrestore(&priv->lock, flags);
1431 /* call the host command only if no hw rf-kill set */
1432 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1433 iwl_is_ready(priv))
1434 iwl_send_card_state(priv,
1435 CARD_STATE_CMD_DISABLE, 0);
1436 set_bit(STATUS_RF_KILL_SW, &priv->status);
1437 /* make sure mac80211 stop sending Tx frame */
1438 if (priv->mac80211_registered)
1439 ieee80211_stop_queues(priv->hw);
1440 }
1441}
1442EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1443
1444int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1445{
1446 unsigned long flags;
1447
1448 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1449 return 0;
1450
1451 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1452
1453 spin_lock_irqsave(&priv->lock, flags);
1454 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1455
a9efa652
EG		 1456 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1457 * notification where it will clear SW rfkill status.
1458 * Setting it here would break the handler. Only if the
1459 * interface is down we can set here since we don't
1460 * receive any further notification.
1461 */
1462 if (!priv->is_open)
1463 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 1464 spin_unlock_irqrestore(&priv->lock, flags);
1465
1466 /* wake up ucode */
1467 msleep(10);
1468
1469 spin_lock_irqsave(&priv->lock, flags);
1470 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1471 if (!iwl_grab_nic_access(priv))
1472 iwl_release_nic_access(priv);
1473 spin_unlock_irqrestore(&priv->lock, flags);
1474
1475 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1476 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1477 "disabled by HW switch\n");
1478 return 0;
1479 }
1480
a9efa652
EG		 1481 /* If the driver is already loaded, it will receive
1482 * CARD_STATE_NOTIFICATION notifications and the handler will
1483 * call restart to reload the driver.
1484 */
14a08a7f
EG		 1485 return 1;
1486}
1487EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
Linux kernel - Deliverables
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