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iwlwifi: use station HT capabilities and BSS operating mode for Green-field
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
a562a9dd
RC		 62u32 iwl_debug_level;
63EXPORT_SYMBOL(iwl_debug_level);
64
ef850d7c
MA		 65static irqreturn_t iwl_isr(int irq, void *data);
66
c7de35cd
RR		 67/*
68 * Parameter order:
69 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
1826dcc0 75const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 76 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
88 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
89 /* FIXME:RS: ^^ should be INV (legacy) */
90};
1826dcc0 91EXPORT_SYMBOL(iwl_rates);
c7de35cd 92
e7d326ac
TW		 93/**
94 * translate ucode response to mac80211 tx status control values
95 */
96void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 97 struct ieee80211_tx_info *info)
e7d326ac
TW		 98{
99 int rate_index;
e6a9854b 100 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 101
e6a9854b 102 info->antenna_sel_tx =
e7d326ac
TW		 103 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
104 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 105 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 106 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 107 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 108 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 109 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 110 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 111 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 112 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 113 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 114 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 115 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 116 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 117 r->idx = rate_index;
e7d326ac
TW		 118}
119EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
120
121int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
122{
123 int idx = 0;
124
125 /* HT rate format */
126 if (rate_n_flags & RATE_MCS_HT_MSK) {
127 idx = (rate_n_flags & 0xff);
128
60d32215
DH		 129 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
130 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
131 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 132 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
133
134 idx += IWL_FIRST_OFDM_RATE;
135 /* skip 9M not supported in ht*/
136 if (idx >= IWL_RATE_9M_INDEX)
137 idx += 1;
138 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
139 return idx;
140
141 /* legacy rate format, search for match in table */
142 } else {
143 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
144 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
145 return idx;
146 }
147
148 return -1;
149}
150EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
151
76eff18b
TW		 152u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
153{
154 int i;
155 u8 ind = ant;
156 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
157 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
158 if (priv->hw_params.valid_tx_ant & BIT(ind))
159 return ind;
160 }
161 return ant;
162}
57bd1bea
TW		 163
164const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
165EXPORT_SYMBOL(iwl_bcast_addr);
166
167
1d0a082d
AK		 168/* This function both allocates and initializes hw and priv. */
169struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
170 struct ieee80211_ops *hw_ops)
171{
172 struct iwl_priv *priv;
173
174 /* mac80211 allocates memory for this device instance, including
175 * space for this driver's private structure */
176 struct ieee80211_hw *hw =
177 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
178 if (hw == NULL) {
a3139c59
SO		 179 printk(KERN_ERR "%s: Can not allocate network device\n",
180 cfg->name);
1d0a082d
AK		 181 goto out;
182 }
183
184 priv = hw->priv;
185 priv->hw = hw;
186
187out:
188 return hw;
189}
190EXPORT_SYMBOL(iwl_alloc_all);
191
b661c819
TW		 192void iwl_hw_detect(struct iwl_priv *priv)
193{
194 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
195 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
196 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
197}
198EXPORT_SYMBOL(iwl_hw_detect);
199
1053d35f
RR		 200int iwl_hw_nic_init(struct iwl_priv *priv)
201{
202 unsigned long flags;
203 struct iwl_rx_queue *rxq = &priv->rxq;
204 int ret;
205
206 /* nic_init */
1053d35f 207 spin_lock_irqsave(&priv->lock, flags);
1b73af82 208 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 209 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
210 spin_unlock_irqrestore(&priv->lock, flags);
211
212 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
213
214 priv->cfg->ops->lib->apm_ops.config(priv);
215
216 /* Allocate the RX queue, or reset if it is already allocated */
217 if (!rxq->bd) {
218 ret = iwl_rx_queue_alloc(priv);
219 if (ret) {
15b1687c 220 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 221 return -ENOMEM;
222 }
223 } else
224 iwl_rx_queue_reset(priv, rxq);
225
226 iwl_rx_replenish(priv);
227
228 iwl_rx_init(priv, rxq);
229
230 spin_lock_irqsave(&priv->lock, flags);
231
232 rxq->need_update = 1;
233 iwl_rx_queue_update_write_ptr(priv, rxq);
234
235 spin_unlock_irqrestore(&priv->lock, flags);
236
237 /* Allocate and init all Tx and Command queues */
238 ret = iwl_txq_ctx_reset(priv);
239 if (ret)
240 return ret;
241
242 set_bit(STATUS_INIT, &priv->status);
243
244 return 0;
245}
246EXPORT_SYMBOL(iwl_hw_nic_init);
247
14d2aac5
AK		 248/*
249 * QoS support
250*/
251void iwl_activate_qos(struct iwl_priv *priv, u8 force)
252{
253 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
254 return;
255
256 priv->qos_data.def_qos_parm.qos_flags = 0;
257
258 if (priv->qos_data.qos_cap.q_AP.queue_request &&
259 !priv->qos_data.qos_cap.q_AP.txop_request)
260 priv->qos_data.def_qos_parm.qos_flags |=
261 QOS_PARAM_FLG_TXOP_TYPE_MSK;
262 if (priv->qos_data.qos_active)
263 priv->qos_data.def_qos_parm.qos_flags |=
264 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
265
266 if (priv->current_ht_config.is_ht)
267 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
268
269 if (force || iwl_is_associated(priv)) {
270 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
271 priv->qos_data.qos_active,
272 priv->qos_data.def_qos_parm.qos_flags);
273
274 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
275 sizeof(struct iwl_qosparam_cmd),
276 &priv->qos_data.def_qos_parm, NULL);
277 }
278}
279EXPORT_SYMBOL(iwl_activate_qos);
280
f2c95b04
WYG		 281/*
282 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
283 * (802.11b) (802.11a/g)
284 * AC_BK 15 1023 7 0 0
285 * AC_BE 15 1023 3 0 0
286 * AC_VI 7 15 2 6.016ms 3.008ms
287 * AC_VO 3 7 2 3.264ms 1.504ms
288 */
c7de35cd 289void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 290{
291 u16 cw_min = 15;
292 u16 cw_max = 1023;
293 u8 aifs = 2;
30dab79e 294 bool is_legacy = false;
bf85ea4f
AK		 295 unsigned long flags;
296 int i;
297
298 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 299 /* QoS always active in AP and ADHOC mode
300 * In STA mode wait for association
301 */
302 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
303 priv->iw_mode == NL80211_IFTYPE_AP)
304 priv->qos_data.qos_active = 1;
305 else
306 priv->qos_data.qos_active = 0;
bf85ea4f 307
30dab79e
WT		 308 /* check for legacy mode */
309 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
310 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
311 (priv->iw_mode == NL80211_IFTYPE_STATION &&
312 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 313 cw_min = 31;
314 is_legacy = 1;
315 }
316
317 if (priv->qos_data.qos_active)
318 aifs = 3;
319
f2c95b04 320 /* AC_BE */
bf85ea4f
AK		 321 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
322 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
323 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
324 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
325 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
326
327 if (priv->qos_data.qos_active) {
f2c95b04 328 /* AC_BK */
bf85ea4f
AK		 329 i = 1;
330 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
331 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
332 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
333 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
334 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
335
f2c95b04 336 /* AC_VI */
bf85ea4f
AK		 337 i = 2;
338 priv->qos_data.def_qos_parm.ac[i].cw_min =
339 cpu_to_le16((cw_min + 1) / 2 - 1);
340 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 341 cpu_to_le16(cw_min);
bf85ea4f
AK		 342 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
343 if (is_legacy)
344 priv->qos_data.def_qos_parm.ac[i].edca_txop =
345 cpu_to_le16(6016);
346 else
347 priv->qos_data.def_qos_parm.ac[i].edca_txop =
348 cpu_to_le16(3008);
349 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
350
f2c95b04 351 /* AC_VO */
bf85ea4f
AK		 352 i = 3;
353 priv->qos_data.def_qos_parm.ac[i].cw_min =
354 cpu_to_le16((cw_min + 1) / 4 - 1);
355 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 356 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 357 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
358 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
359 if (is_legacy)
360 priv->qos_data.def_qos_parm.ac[i].edca_txop =
361 cpu_to_le16(3264);
362 else
363 priv->qos_data.def_qos_parm.ac[i].edca_txop =
364 cpu_to_le16(1504);
365 } else {
366 for (i = 1; i < 4; i++) {
367 priv->qos_data.def_qos_parm.ac[i].cw_min =
368 cpu_to_le16(cw_min);
369 priv->qos_data.def_qos_parm.ac[i].cw_max =
370 cpu_to_le16(cw_max);
371 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
372 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
373 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
374 }
375 }
e1623446 376 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 377
378 spin_unlock_irqrestore(&priv->lock, flags);
379}
c7de35cd
RR		 380EXPORT_SYMBOL(iwl_reset_qos);
381
d9fe60de
JB		 382#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
383#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 384static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 385 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 386 enum ieee80211_band band)
387{
39130df3
RR		 388 u16 max_bit_rate = 0;
389 u8 rx_chains_num = priv->hw_params.rx_chains_num;
390 u8 tx_chains_num = priv->hw_params.tx_chains_num;
391
c7de35cd 392 ht_info->cap = 0;
d9fe60de 393 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 394
d9fe60de 395 ht_info->ht_supported = true;
c7de35cd 396
b261793d
DH		 397 if (priv->cfg->ht_greenfield_support)
398 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de
JB		 399 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
400 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 401 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 402
403 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 404 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 405 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
406 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
407 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 408 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 409 }
c7de35cd
RR		 410
411 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 412 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 413
414 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
415 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
416
d9fe60de 417 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 418 if (rx_chains_num >= 2)
d9fe60de 419 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 420 if (rx_chains_num >= 3)
d9fe60de 421 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 422
423 /* Highest supported Rx data rate */
424 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 425 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
426 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 427
428 /* Tx MCS capabilities */
d9fe60de 429 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 430 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 431 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
432 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
433 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 434 }
c7de35cd 435}
c7de35cd
RR		 436
437static void iwlcore_init_hw_rates(struct iwl_priv *priv,
438 struct ieee80211_rate *rates)
439{
440 int i;
441
442 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 443 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 444 rates[i].hw_value = i; /* Rate scaling will work on indexes */
445 rates[i].hw_value_short = i;
446 rates[i].flags = 0;
447 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
448 /*
449 * If CCK != 1M then set short preamble rate flag.
450 */
451 rates[i].flags |=
1826dcc0 452 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 453 0 : IEEE80211_RATE_SHORT_PREAMBLE;
454 }
455 }
456}
457
8ccde88a 458
c7de35cd
RR		 459/**
460 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
461 */
534166de 462int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 463{
464 struct iwl_channel_info *ch;
465 struct ieee80211_supported_band *sband;
466 struct ieee80211_channel *channels;
467 struct ieee80211_channel *geo_ch;
468 struct ieee80211_rate *rates;
469 int i = 0;
470
471 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
472 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 473 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 474 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
475 return 0;
476 }
477
478 channels = kzalloc(sizeof(struct ieee80211_channel) *
479 priv->channel_count, GFP_KERNEL);
480 if (!channels)
481 return -ENOMEM;
482
483 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
484 GFP_KERNEL);
485 if (!rates) {
486 kfree(channels);
487 return -ENOMEM;
488 }
489
490 /* 5.2GHz channels start after the 2.4GHz channels */
491 sband = &priv->bands[IEEE80211_BAND_5GHZ];
492 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
493 /* just OFDM */
494 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
495 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
496
49779293 497 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 498 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 499 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 500
501 sband = &priv->bands[IEEE80211_BAND_2GHZ];
502 sband->channels = channels;
503 /* OFDM & CCK */
504 sband->bitrates = rates;
505 sband->n_bitrates = IWL_RATE_COUNT;
506
49779293 507 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 508 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 509 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 510
511 priv->ieee_channels = channels;
512 priv->ieee_rates = rates;
513
c7de35cd
RR		 514 for (i = 0; i < priv->channel_count; i++) {
515 ch = &priv->channel_info[i];
516
517 /* FIXME: might be removed if scan is OK */
518 if (!is_channel_valid(ch))
519 continue;
520
521 if (is_channel_a_band(ch))
522 sband = &priv->bands[IEEE80211_BAND_5GHZ];
523 else
524 sband = &priv->bands[IEEE80211_BAND_2GHZ];
525
526 geo_ch = &sband->channels[sband->n_channels++];
527
528 geo_ch->center_freq =
529 ieee80211_channel_to_frequency(ch->channel);
530 geo_ch->max_power = ch->max_power_avg;
531 geo_ch->max_antenna_gain = 0xff;
532 geo_ch->hw_value = ch->channel;
533
534 if (is_channel_valid(ch)) {
535 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
536 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
537
538 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
539 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
540
541 if (ch->flags & EEPROM_CHANNEL_RADAR)
542 geo_ch->flags |= IEEE80211_CHAN_RADAR;
543
7aafef1c 544 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 545
630fe9b6
TW		 546 if (ch->max_power_avg > priv->tx_power_channel_lmt)
547 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 548 } else {
549 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
550 }
551
e1623446 552 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 553 ch->channel, geo_ch->center_freq,
554 is_channel_a_band(ch) ? "5.2" : "2.4",
555 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
556 "restricted" : "valid",
557 geo_ch->flags);
558 }
559
560 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
561 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 562 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
563 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 564 priv->pci_dev->device,
565 priv->pci_dev->subsystem_device);
c7de35cd
RR		 566 priv->cfg->sku &= ~IWL_SKU_A;
567 }
568
978785a3 569 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 570 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
571 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 572
573 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
574
575 return 0;
576}
534166de 577EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 578
579/*
580 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
581 */
534166de 582void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 583{
584 kfree(priv->ieee_channels);
585 kfree(priv->ieee_rates);
586 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
587}
534166de 588EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 589
28a6b07a 590static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 591{
592 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 593 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
594 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 595}
963f5517 596
47c5196e
TW		 597static u8 iwl_is_channel_extension(struct iwl_priv *priv,
598 enum ieee80211_band band,
599 u16 channel, u8 extension_chan_offset)
600{
601 const struct iwl_channel_info *ch_info;
602
603 ch_info = iwl_get_channel_info(priv, band, channel);
604 if (!is_channel_valid(ch_info))
605 return 0;
606
d9fe60de 607 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 608 return !(ch_info->ht40_extension_channel &
689da1b3 609 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 610 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 611 return !(ch_info->ht40_extension_channel &
689da1b3 612 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 613
614 return 0;
615}
616
7aafef1c 617u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 618 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 619{
620 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
621
622 if ((!iwl_ht_conf->is_ht) ||
a2b0f02e 623 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ))
47c5196e
TW		 624 return 0;
625
a2b0f02e
WYG		 626 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
627 * the bit will not set if it is pure 40MHz case
628 */
47c5196e 629 if (sta_ht_inf) {
a2b0f02e 630 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 631 return 0;
632 }
1e4247d4
WYG		 633#ifdef CONFIG_IWLWIFI_DEBUG
634 if (priv->disable_ht40)
635 return 0;
636#endif
611d3eb7
WYG		 637 return iwl_is_channel_extension(priv, priv->band,
638 le16_to_cpu(priv->staging_rxon.channel),
639 iwl_ht_conf->extension_chan_offset);
47c5196e 640}
7aafef1c 641EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 642
2c2f3b33
TW		 643static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
644{
645 u16 new_val = 0;
646 u16 beacon_factor = 0;
647
648 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
649 new_val = beacon_val / beacon_factor;
650
651 if (!new_val)
652 new_val = max_beacon_val;
653
654 return new_val;
655}
656
657void iwl_setup_rxon_timing(struct iwl_priv *priv)
658{
659 u64 tsf;
660 s32 interval_tm, rem;
661 unsigned long flags;
662 struct ieee80211_conf *conf = NULL;
663 u16 beacon_int;
664
665 conf = ieee80211_get_hw_conf(priv->hw);
666
667 spin_lock_irqsave(&priv->lock, flags);
668 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
669 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
670
671 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
672 beacon_int = priv->beacon_int;
673 priv->rxon_timing.atim_window = 0;
674 } else {
675 beacon_int = priv->vif->bss_conf.beacon_int;
676
677 /* TODO: we need to get atim_window from upper stack
678 * for now we set to 0 */
679 priv->rxon_timing.atim_window = 0;
680 }
681
682 beacon_int = iwl_adjust_beacon_interval(beacon_int,
683 priv->hw_params.max_beacon_itrvl * 1024);
684 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
685
686 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
687 interval_tm = beacon_int * 1024;
688 rem = do_div(tsf, interval_tm);
689 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
690
691 spin_unlock_irqrestore(&priv->lock, flags);
692 IWL_DEBUG_ASSOC(priv,
693 "beacon interval %d beacon timer %d beacon tim %d\n",
694 le16_to_cpu(priv->rxon_timing.beacon_interval),
695 le32_to_cpu(priv->rxon_timing.beacon_init_val),
696 le16_to_cpu(priv->rxon_timing.atim_window));
697}
698EXPORT_SYMBOL(iwl_setup_rxon_timing);
699
8ccde88a
SO		 700void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
701{
702 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
703
704 if (hw_decrypt)
705 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
706 else
707 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
708
709}
710EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
711
712/**
713 * iwl_check_rxon_cmd - validate RXON structure is valid
714 *
715 * NOTE: This is really only useful during development and can eventually
716 * be #ifdef'd out once the driver is stable and folks aren't actively
717 * making changes
718 */
719int iwl_check_rxon_cmd(struct iwl_priv *priv)
720{
721 int error = 0;
722 int counter = 1;
723 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
724
725 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
726 error |= le32_to_cpu(rxon->flags &
727 (RXON_FLG_TGJ_NARROW_BAND_MSK |
728 RXON_FLG_RADAR_DETECT_MSK));
729 if (error)
730 IWL_WARN(priv, "check 24G fields %d | %d\n",
731 counter++, error);
732 } else {
733 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
734 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
735 if (error)
736 IWL_WARN(priv, "check 52 fields %d | %d\n",
737 counter++, error);
738 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
739 if (error)
740 IWL_WARN(priv, "check 52 CCK %d | %d\n",
741 counter++, error);
742 }
743 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
744 if (error)
745 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
746
747 /* make sure basic rates 6Mbps and 1Mbps are supported */
748 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
749 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
750 if (error)
751 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
752
753 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
754 if (error)
755 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
756
757 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
758 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
759 if (error)
760 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
761 counter++, error);
762
763 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
764 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
765 if (error)
766 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
767 counter++, error);
768
769 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
770 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
771 if (error)
772 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
773 counter++, error);
774
775 if (error)
776 IWL_WARN(priv, "Tuning to channel %d\n",
777 le16_to_cpu(rxon->channel));
778
779 if (error) {
780 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
781 return -1;
782 }
783 return 0;
784}
785EXPORT_SYMBOL(iwl_check_rxon_cmd);
786
787/**
788 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
789 * @priv: staging_rxon is compared to active_rxon
790 *
791 * If the RXON structure is changing enough to require a new tune,
792 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
793 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
794 */
795int iwl_full_rxon_required(struct iwl_priv *priv)
796{
797
798 /* These items are only settable from the full RXON command */
799 if (!(iwl_is_associated(priv)) ||
800 compare_ether_addr(priv->staging_rxon.bssid_addr,
801 priv->active_rxon.bssid_addr) ||
802 compare_ether_addr(priv->staging_rxon.node_addr,
803 priv->active_rxon.node_addr) ||
804 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
805 priv->active_rxon.wlap_bssid_addr) ||
806 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
807 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
808 (priv->staging_rxon.air_propagation !=
809 priv->active_rxon.air_propagation) ||
810 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
811 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
812 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
813 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 814 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
815 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 816 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
817 return 1;
818
819 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
820 * be updated with the RXON_ASSOC command -- however only some
821 * flag transitions are allowed using RXON_ASSOC */
822
823 /* Check if we are not switching bands */
824 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
825 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
826 return 1;
827
828 /* Check if we are switching association toggle */
829 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
830 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
831 return 1;
832
833 return 0;
834}
835EXPORT_SYMBOL(iwl_full_rxon_required);
836
837u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
838{
839 int i;
840 int rate_mask;
841
842 /* Set rate mask*/
843 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
844 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
845 else
846 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
847
848 /* Find lowest valid rate */
849 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
850 i = iwl_rates[i].next_ieee) {
851 if (rate_mask & (1 << i))
852 return iwl_rates[i].plcp;
853 }
854
855 /* No valid rate was found. Assign the lowest one */
856 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
857 return IWL_RATE_1M_PLCP;
858 else
859 return IWL_RATE_6M_PLCP;
860}
861EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
862
47c5196e
TW		 863void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
864{
c1adf9fb 865 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 866
42eb7c64 867 if (!ht_info->is_ht) {
a2b0f02e 868 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 869 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 870 RXON_FLG_HT40_PROT_MSK |
42eb7c64 871 RXON_FLG_HT_PROT_MSK);
47c5196e 872 return;
42eb7c64 873 }
47c5196e 874
a2b0f02e
WYG		 875 /* FIXME: if the definition of ht_protection changed, the "translation"
876 * will be needed for rxon->flags
877 */
878 rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
879
880 /* Set up channel bandwidth:
7aafef1c 881 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 882 /* clear the HT channel mode before set the mode */
883 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
884 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 885 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
886 /* pure ht40 */
508b08e7 887 if (ht_info->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 888 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7
WYG		 889 /* Note: control channel is opposite of extension channel */
890 switch (ht_info->extension_chan_offset) {
891 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
892 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
893 break;
894 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
895 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
896 break;
897 }
898 } else {
a2b0f02e
WYG		 899 /* Note: control channel is opposite of extension channel */
900 switch (ht_info->extension_chan_offset) {
901 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
902 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
903 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
904 break;
905 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
906 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
907 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
908 break;
909 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
910 default:
911 /* channel location only valid if in Mixed mode */
912 IWL_ERR(priv, "invalid extension channel offset\n");
913 break;
914 }
915 }
916 } else {
917 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 918 }
919
45823531
AK		 920 if (priv->cfg->ops->hcmd->set_rxon_chain)
921 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 922
e1623446 923 IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
47c5196e 924 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 925 "extension channel offset 0x%x\n",
d9fe60de
JB		 926 ht_info->mcs.rx_mask[0],
927 ht_info->mcs.rx_mask[1],
928 ht_info->mcs.rx_mask[2],
47c5196e 929 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 930 ht_info->extension_chan_offset);
47c5196e
TW		 931 return;
932}
933EXPORT_SYMBOL(iwl_set_rxon_ht);
934
9e5e6c32
TW		 935#define IWL_NUM_RX_CHAINS_MULTIPLE 3
936#define IWL_NUM_RX_CHAINS_SINGLE 2
937#define IWL_NUM_IDLE_CHAINS_DUAL 2
938#define IWL_NUM_IDLE_CHAINS_SINGLE 1
939
940/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 941 * More provides better reception via diversity. Fewer saves power.
942 * MIMO (dual stream) requires at least 2, but works better with 3.
943 * This does not determine *which* chains to use, just how many.
944 */
28a6b07a 945static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 946{
28a6b07a
TW		 947 bool is_single = is_single_rx_stream(priv);
948 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 949
950 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 951 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
952 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 953 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 954 else
9e5e6c32 955 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 956}
c7de35cd 957
28a6b07a
TW		 958static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
959{
960 int idle_cnt;
961 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 962 /* # Rx chains when idling and maybe trying to save power */
12837be1 963 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 964 case WLAN_HT_CAP_SM_PS_STATIC:
965 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 966 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
967 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 968 break;
00c5ae2f 969 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 970 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 971 break;
00c5ae2f 972 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 973 default:
15b1687c 974 IWL_ERR(priv, "invalid mimo ps mode %d\n",
12837be1 975 priv->current_ht_config.sm_ps);
28a6b07a
TW		 976 WARN_ON(1);
977 idle_cnt = -1;
c7de35cd
RR		 978 break;
979 }
28a6b07a 980 return idle_cnt;
c7de35cd
RR		 981}
982
04816448
GE		 983/* up to 4 chains */
984static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
985{
986 u8 res;
987 res = (chain_bitmap & BIT(0)) >> 0;
988 res += (chain_bitmap & BIT(1)) >> 1;
989 res += (chain_bitmap & BIT(2)) >> 2;
990 res += (chain_bitmap & BIT(4)) >> 4;
991 return res;
992}
993
4c4df78f
CR		 994/**
995 * iwl_is_monitor_mode - Determine if interface in monitor mode
996 *
997 * priv->iw_mode is set in add_interface, but add_interface is
998 * never called for monitor mode. The only way mac80211 informs us about
999 * monitor mode is through configuring filters (call to configure_filter).
1000 */
279b05d4 1001bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1002{
1003 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1004}
279b05d4 1005EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1006
c7de35cd
RR		 1007/**
1008 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1009 *
1010 * Selects how many and which Rx receivers/antennas/chains to use.
1011 * This should not be used for scan command ... it puts data in wrong place.
1012 */
1013void iwl_set_rxon_chain(struct iwl_priv *priv)
1014{
28a6b07a
TW		 1015 bool is_single = is_single_rx_stream(priv);
1016 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1017 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1018 u32 active_chains;
28a6b07a 1019 u16 rx_chain;
c7de35cd
RR		 1020
1021 /* Tell uCode which antennas are actually connected.
1022 * Before first association, we assume all antennas are connected.
1023 * Just after first association, iwl_chain_noise_calibration()
1024 * checks which antennas actually *are* connected. */
04816448
GE		 1025 if (priv->chain_noise_data.active_chains)
1026 active_chains = priv->chain_noise_data.active_chains;
1027 else
1028 active_chains = priv->hw_params.valid_rx_ant;
1029
1030 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1031
1032 /* How many receivers should we use? */
28a6b07a
TW		 1033 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1034 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1035
28a6b07a 1036
04816448
GE		 1037 /* correct rx chain count according hw settings
1038 * and chain noise calibration
1039 */
1040 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1041 if (valid_rx_cnt < active_rx_cnt)
1042 active_rx_cnt = valid_rx_cnt;
1043
1044 if (valid_rx_cnt < idle_rx_cnt)
1045 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1046
1047 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1048 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1049
7b841727
RF		 1050 /* copied from 'iwl_bg_request_scan()' */
1051 /* Force use of chains B and C (0x6) for Rx for 4965
1052 * Avoid A (0x1) because of its off-channel reception on A-band.
1053 * MIMO is not used here, but value is required */
1054 if (iwl_is_monitor_mode(priv) &&
1055 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1056 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1057 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1058 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1059 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1060 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1061 }
1062
28a6b07a
TW		 1063 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1064
9e5e6c32 1065 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1066 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1067 else
1068 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1069
e1623446 1070 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1071 priv->staging_rxon.rx_chain,
1072 active_rx_cnt, idle_rx_cnt);
1073
1074 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1075 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1076}
1077EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1078
1079/**
17e72782 1080 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1081 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1082 * @channel: Any channel valid for the requested phymode
1083
1084 * In addition to setting the staging RXON, priv->phymode is also set.
1085 *
1086 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1087 * in the staging RXON flag structure based on the phymode
1088 */
17e72782 1089int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1090{
17e72782
TW		 1091 enum ieee80211_band band = ch->band;
1092 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1093
8622e705 1094 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1095 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1096 channel, band);
1097 return -EINVAL;
1098 }
1099
1100 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1101 (priv->band == band))
1102 return 0;
1103
1104 priv->staging_rxon.channel = cpu_to_le16(channel);
1105 if (band == IEEE80211_BAND_5GHZ)
1106 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1107 else
1108 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1109
1110 priv->band = band;
1111
e1623446 1112 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1113
1114 return 0;
1115}
c7de35cd 1116EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1117
8ccde88a
SO		 1118void iwl_set_flags_for_band(struct iwl_priv *priv,
1119 enum ieee80211_band band)
1120{
1121 if (band == IEEE80211_BAND_5GHZ) {
1122 priv->staging_rxon.flags &=
1123 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1124 | RXON_FLG_CCK_MSK);
1125 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1126 } else {
1127 /* Copied from iwl_post_associate() */
1128 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1129 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1130 else
1131 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1132
1133 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1134 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1135
1136 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1137 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1138 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1139 }
1140}
8ccde88a
SO		 1141
1142/*
1143 * initialize rxon structure with default values from eeprom
1144 */
1145void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1146{
1147 const struct iwl_channel_info *ch_info;
1148
1149 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1150
1151 switch (mode) {
1152 case NL80211_IFTYPE_AP:
1153 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1154 break;
1155
1156 case NL80211_IFTYPE_STATION:
1157 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1158 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1159 break;
1160
1161 case NL80211_IFTYPE_ADHOC:
1162 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1163 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1164 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1165 RXON_FILTER_ACCEPT_GRP_MSK;
1166 break;
1167
8ccde88a
SO		 1168 default:
1169 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1170 break;
1171 }
1172
1173#if 0
1174 /* TODO: Figure out when short_preamble would be set and cache from
1175 * that */
1176 if (!hw_to_local(priv->hw)->short_preamble)
1177 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1178 else
1179 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1180#endif
1181
1182 ch_info = iwl_get_channel_info(priv, priv->band,
1183 le16_to_cpu(priv->active_rxon.channel));
1184
1185 if (!ch_info)
1186 ch_info = &priv->channel_info[0];
1187
1188 /*
1189 * in some case A channels are all non IBSS
1190 * in this case force B/G channel
1191 */
1192 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1193 !(is_channel_ibss(ch_info)))
1194 ch_info = &priv->channel_info[0];
1195
1196 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1197 priv->band = ch_info->band;
1198
1199 iwl_set_flags_for_band(priv, priv->band);
1200
1201 priv->staging_rxon.ofdm_basic_rates =
1202 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1203 priv->staging_rxon.cck_basic_rates =
1204 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1205
a2b0f02e
WYG		 1206 /* clear both MIX and PURE40 mode flag */
1207 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1208 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1209 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1210 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1211 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1212 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1213 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1214}
1215EXPORT_SYMBOL(iwl_connection_init_rx_config);
1216
782571f4 1217static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1218{
1219 const struct ieee80211_supported_band *hw = NULL;
1220 struct ieee80211_rate *rate;
1221 int i;
1222
1223 hw = iwl_get_hw_mode(priv, priv->band);
1224 if (!hw) {
1225 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1226 return;
1227 }
1228
1229 priv->active_rate = 0;
1230 priv->active_rate_basic = 0;
1231
1232 for (i = 0; i < hw->n_bitrates; i++) {
1233 rate = &(hw->bitrates[i]);
1234 if (rate->hw_value < IWL_RATE_COUNT)
1235 priv->active_rate |= (1 << rate->hw_value);
1236 }
1237
e1623446 1238 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1239 priv->active_rate, priv->active_rate_basic);
1240
1241 /*
1242 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1243 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1244 * OFDM
1245 */
1246 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1247 priv->staging_rxon.cck_basic_rates =
1248 ((priv->active_rate_basic &
1249 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1250 else
1251 priv->staging_rxon.cck_basic_rates =
1252 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1253
1254 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1255 priv->staging_rxon.ofdm_basic_rates =
1256 ((priv->active_rate_basic &
1257 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1258 IWL_FIRST_OFDM_RATE) & 0xFF;
1259 else
1260 priv->staging_rxon.ofdm_basic_rates =
1261 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1262}
8ccde88a
SO		 1263
1264void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1265{
1266 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1267 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1268 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
e1623446 1269 IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
8ccde88a
SO		 1270 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
1271 rxon->channel = csa->channel;
1272 priv->staging_rxon.channel = csa->channel;
1273}
1274EXPORT_SYMBOL(iwl_rx_csa);
1275
1276#ifdef CONFIG_IWLWIFI_DEBUG
1277static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1278{
1279 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1280
e1623446 1281 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1282 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1283 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1284 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1285 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1286 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1287 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1288 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1289 rxon->ofdm_basic_rates);
e1623446
TW		 1290 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1291 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1292 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1293 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1294}
8ccde88a 1295
a94ca4e7
JB		 1296static const char *desc_lookup_text[] = {
1297 "OK",
1298 "FAIL",
1299 "BAD_PARAM",
1300 "BAD_CHECKSUM",
1301 "NMI_INTERRUPT_WDG",
1302 "SYSASSERT",
1303 "FATAL_ERROR",
1304 "BAD_COMMAND",
1305 "HW_ERROR_TUNE_LOCK",
1306 "HW_ERROR_TEMPERATURE",
1307 "ILLEGAL_CHAN_FREQ",
1308 "VCC_NOT_STABLE",
1309 "FH_ERROR",
1310 "NMI_INTERRUPT_HOST",
1311 "NMI_INTERRUPT_ACTION_PT",
1312 "NMI_INTERRUPT_UNKNOWN",
1313 "UCODE_VERSION_MISMATCH",
1314 "HW_ERROR_ABS_LOCK",
1315 "HW_ERROR_CAL_LOCK_FAIL",
1316 "NMI_INTERRUPT_INST_ACTION_PT",
1317 "NMI_INTERRUPT_DATA_ACTION_PT",
1318 "NMI_TRM_HW_ER",
1319 "NMI_INTERRUPT_TRM",
1320 "NMI_INTERRUPT_BREAK_POINT"
1321 "DEBUG_0",
1322 "DEBUG_1",
1323 "DEBUG_2",
1324 "DEBUG_3",
1325 "UNKNOWN"
1326};
1327
1328static const char *desc_lookup(int i)
1329{
1330 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1331
1332 if (i < 0 || i > max)
1333 i = max;
1334
1335 return desc_lookup_text[i];
1336}
1337
1338#define ERROR_START_OFFSET (1 * sizeof(u32))
1339#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1340
1341static void iwl_dump_nic_error_log(struct iwl_priv *priv)
1342{
1343 u32 data2, line;
1344 u32 desc, time, count, base, data1;
1345 u32 blink1, blink2, ilink1, ilink2;
1346
c03ea162 1347 if (priv->ucode_type == UCODE_INIT)
34a66de6 1348 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
c03ea162
RC		 1349 else
1350 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
a94ca4e7
JB		 1351
1352 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1353 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1354 return;
1355 }
1356
1357 count = iwl_read_targ_mem(priv, base);
1358
1359 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1360 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1361 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1362 priv->status, count);
1363 }
1364
1365 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1366 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1367 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1368 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1369 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1370 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1371 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1372 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1373 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1374
1375 IWL_ERR(priv, "Desc Time "
1376 "data1 data2 line\n");
1377 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1378 desc_lookup(desc), desc, time, data1, data2, line);
1379 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1380 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1381 ilink1, ilink2);
1382
1383}
1384
1385#define EVENT_START_OFFSET (4 * sizeof(u32))
1386
1387/**
1388 * iwl_print_event_log - Dump error event log to syslog
1389 *
1390 */
1391static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1392 u32 num_events, u32 mode)
1393{
1394 u32 i;
1395 u32 base; /* SRAM byte address of event log header */
1396 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1397 u32 ptr; /* SRAM byte address of log data */
1398 u32 ev, time, data; /* event log data */
1399
1400 if (num_events == 0)
1401 return;
c03ea162 1402 if (priv->ucode_type == UCODE_INIT)
34a66de6 1403 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
c03ea162
RC		 1404 else
1405 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
a94ca4e7
JB		 1406
1407 if (mode == 0)
1408 event_size = 2 * sizeof(u32);
1409 else
1410 event_size = 3 * sizeof(u32);
1411
1412 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1413
1414 /* "time" is actually "data" for mode 0 (no timestamp).
1415 * place event id # at far right for easier visual parsing. */
1416 for (i = 0; i < num_events; i++) {
1417 ev = iwl_read_targ_mem(priv, ptr);
1418 ptr += sizeof(u32);
1419 time = iwl_read_targ_mem(priv, ptr);
1420 ptr += sizeof(u32);
1421 if (mode == 0) {
1422 /* data, ev */
1423 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1424 } else {
1425 data = iwl_read_targ_mem(priv, ptr);
1426 ptr += sizeof(u32);
1427 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1428 time, data, ev);
1429 }
1430 }
1431}
1432
1433void iwl_dump_nic_event_log(struct iwl_priv *priv)
1434{
1435 u32 base; /* SRAM byte address of event log header */
1436 u32 capacity; /* event log capacity in # entries */
1437 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1438 u32 num_wraps; /* # times uCode wrapped to top of log */
1439 u32 next_entry; /* index of next entry to be written by uCode */
1440 u32 size; /* # entries that we'll print */
1441
c03ea162 1442 if (priv->ucode_type == UCODE_INIT)
34a66de6 1443 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
c03ea162
RC		 1444 else
1445 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
a94ca4e7
JB		 1446
1447 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1448 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1449 return;
1450 }
1451
1452 /* event log header */
1453 capacity = iwl_read_targ_mem(priv, base);
1454 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1455 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1456 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1457
1458 size = num_wraps ? capacity : next_entry;
1459
1460 /* bail out if nothing in log */
1461 if (size == 0) {
1462 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1463 return;
1464 }
1465
1466 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1467 size, num_wraps);
1468
1469 /* if uCode has wrapped back to top of log, start at the oldest entry,
1470 * i.e the next one that uCode would fill. */
1471 if (num_wraps)
1472 iwl_print_event_log(priv, next_entry,
1473 capacity - next_entry, mode);
1474 /* (then/else) start at top of log */
1475 iwl_print_event_log(priv, 0, next_entry, mode);
1476
1477}
6686d17e 1478#endif
8ccde88a
SO		 1479/**
1480 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1481 */
1482void iwl_irq_handle_error(struct iwl_priv *priv)
1483{
1484 /* Set the FW error flag -- cleared on iwl_down */
1485 set_bit(STATUS_FW_ERROR, &priv->status);
1486
1487 /* Cancel currently queued command. */
1488 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1489
1490#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1491 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
8ccde88a
SO		 1492 iwl_dump_nic_error_log(priv);
1493 iwl_dump_nic_event_log(priv);
1494 iwl_print_rx_config_cmd(priv);
1495 }
1496#endif
1497
1498 wake_up_interruptible(&priv->wait_command_queue);
1499
1500 /* Keep the restart process from trying to send host
1501 * commands by clearing the INIT status bit */
1502 clear_bit(STATUS_READY, &priv->status);
1503
1504 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1505 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1506 "Restarting adapter due to uCode error.\n");
1507
8ccde88a
SO		 1508 if (priv->cfg->mod_params->restart_fw)
1509 queue_work(priv->workqueue, &priv->restart);
1510 }
1511}
1512EXPORT_SYMBOL(iwl_irq_handle_error);
1513
1514void iwl_configure_filter(struct ieee80211_hw *hw,
1515 unsigned int changed_flags,
1516 unsigned int *total_flags,
1517 int mc_count, struct dev_addr_list *mc_list)
1518{
1519 struct iwl_priv *priv = hw->priv;
1520 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1521
e1623446 1522 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1523 changed_flags, *total_flags);
1524
1525 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1526 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1527 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1528 else
1529 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1530 }
1531 if (changed_flags & FIF_ALLMULTI) {
1532 if (*total_flags & FIF_ALLMULTI)
1533 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1534 else
1535 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1536 }
1537 if (changed_flags & FIF_CONTROL) {
1538 if (*total_flags & FIF_CONTROL)
1539 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1540 else
1541 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1542 }
1543 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1544 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1545 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1546 else
1547 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1548 }
1549
1550 /* We avoid iwl_commit_rxon here to commit the new filter flags
1551 * since mac80211 will call ieee80211_hw_config immediately.
1552 * (mc_list is not supported at this time). Otherwise, we need to
1553 * queue a background iwl_commit_rxon work.
1554 */
1555
1556 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1557 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1558}
1559EXPORT_SYMBOL(iwl_configure_filter);
1560
6ba87956 1561int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 1562{
6ba87956 1563 int ret;
bf85ea4f 1564 struct ieee80211_hw *hw = priv->hw;
e227ceac 1565 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 1566
566bfe5a 1567 /* Tell mac80211 our characteristics */
605a0bd6 1568 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe 1569 IEEE80211_HW_NOISE_DBM |
4be8c387 1570 IEEE80211_HW_AMPDU_AGGREGATION |
f55e668f 1571 IEEE80211_HW_SPECTRUM_MGMT |
e312c24c
JB		 1572 IEEE80211_HW_SUPPORTS_PS |
1573 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
f59ac048 1574 hw->wiphy->interface_modes =
f59ac048
LR		 1575 BIT(NL80211_IFTYPE_STATION) |
1576 BIT(NL80211_IFTYPE_ADHOC);
ea4a82dc 1577
2a44f911 1578 hw->wiphy->custom_regulatory = true;
1ecf9fc1 1579
37184244
LR		 1580 /* Firmware does not support this */
1581 hw->wiphy->disable_beacon_hints = true;
1582
1ecf9fc1
JB		 1583 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
1584 /* we create the 802.11 header and a zero-length SSID element */
1585 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
ea4a82dc 1586
bf85ea4f
AK		 1587 /* Default value; 4 EDCA QOS priorities */
1588 hw->queues = 4;
6ba87956 1589
b5d7be5e 1590 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 1591
1592 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
1593 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1594 &priv->bands[IEEE80211_BAND_2GHZ];
1595 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
1596 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1597 &priv->bands[IEEE80211_BAND_5GHZ];
1598
1599 ret = ieee80211_register_hw(priv->hw);
1600 if (ret) {
15b1687c 1601 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
6ba87956
TW		 1602 return ret;
1603 }
1604 priv->mac80211_registered = 1;
1605
1606 return 0;
bf85ea4f 1607}
6ba87956 1608EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 1609
da154e30
RR		 1610int iwl_set_hw_params(struct iwl_priv *priv)
1611{
da154e30
RR		 1612 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1613 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1614 if (priv->cfg->mod_params->amsdu_size_8K)
1615 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1616 else
1617 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1618 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1619
2c2f3b33
TW		 1620 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1621
49779293
RR		 1622 if (priv->cfg->mod_params->disable_11n)
1623 priv->cfg->sku &= ~IWL_SKU_N;
1624
da154e30
RR		 1625 /* Device-specific setup */
1626 return priv->cfg->ops->lib->set_hw_params(priv);
1627}
1628EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 1629
1630int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 1631{
1632 int ret;
c7de35cd 1633
c7de35cd
RR		 1634 priv->ibss_beacon = NULL;
1635
1636 spin_lock_init(&priv->lock);
c7de35cd
RR		 1637 spin_lock_init(&priv->sta_lock);
1638 spin_lock_init(&priv->hcmd_lock);
c7de35cd 1639
c7de35cd
RR		 1640 INIT_LIST_HEAD(&priv->free_frames);
1641
1642 mutex_init(&priv->mutex);
1643
1644 /* Clear the driver's (not device's) station table */
c587de0b 1645 iwl_clear_stations_table(priv);
c7de35cd
RR		 1646
1647 priv->data_retry_limit = -1;
1648 priv->ieee_channels = NULL;
1649 priv->ieee_rates = NULL;
1650 priv->band = IEEE80211_BAND_2GHZ;
1651
05c914fe 1652 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 1653
12837be1 1654 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 1655
1656 /* Choose which receivers/antennas to use */
45823531
AK		 1657 if (priv->cfg->ops->hcmd->set_rxon_chain)
1658 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1659
f53696de 1660 iwl_init_scan_params(priv);
c7de35cd
RR		 1661
1662 iwl_reset_qos(priv);
1663
1664 priv->qos_data.qos_active = 0;
1665 priv->qos_data.qos_cap.val = 0;
1666
c7de35cd 1667 priv->rates_mask = IWL_RATES_MASK;
630fe9b6 1668 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 1669
1670 ret = iwl_init_channel_map(priv);
1671 if (ret) {
15b1687c 1672 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
c7de35cd
RR		 1673 goto err;
1674 }
1675
1676 ret = iwlcore_init_geos(priv);
1677 if (ret) {
15b1687c 1678 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
c7de35cd
RR		 1679 goto err_free_channel_map;
1680 }
534166de 1681 iwlcore_init_hw_rates(priv, priv->ieee_rates);
c7de35cd 1682
c7de35cd
RR		 1683 return 0;
1684
c7de35cd
RR		 1685err_free_channel_map:
1686 iwl_free_channel_map(priv);
1687err:
1688 return ret;
1689}
6ba87956 1690EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 1691
630fe9b6
TW		 1692int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1693{
1694 int ret = 0;
1695 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1696 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1697 tx_power,
1698 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1699 return -EINVAL;
1700 }
1701
1702 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
daf518de
WF		 1703 IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
1704 tx_power,
1705 IWL_TX_POWER_TARGET_POWER_MAX);
630fe9b6
TW		 1706 return -EINVAL;
1707 }
1708
1709 if (priv->tx_power_user_lmt != tx_power)
1710 force = true;
1711
1712 priv->tx_power_user_lmt = tx_power;
1713
019fb97d
MA		 1714 /* if nic is not up don't send command */
1715 if (!iwl_is_ready_rf(priv))
1716 return ret;
1717
630fe9b6
TW		 1718 if (force && priv->cfg->ops->lib->send_tx_power)
1719 ret = priv->cfg->ops->lib->send_tx_power(priv);
1720
1721 return ret;
1722}
1723EXPORT_SYMBOL(iwl_set_tx_power);
1724
6ba87956 1725void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1726{
6e21f2c1 1727 iwl_calib_free_results(priv);
6ba87956
TW		 1728 iwlcore_free_geos(priv);
1729 iwl_free_channel_map(priv);
261415f7 1730 kfree(priv->scan);
bf85ea4f 1731}
6ba87956 1732EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1733
ef850d7c
MA		 1734#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1735
1736/* Free dram table */
1737void iwl_free_isr_ict(struct iwl_priv *priv)
1738{
1739 if (priv->ict_tbl_vir) {
1740 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1741 PAGE_SIZE, priv->ict_tbl_vir,
1742 priv->ict_tbl_dma);
1743 priv->ict_tbl_vir = NULL;
1744 }
1745}
1746EXPORT_SYMBOL(iwl_free_isr_ict);
1747
1748
1749/* allocate dram shared table it is a PAGE_SIZE aligned
1750 * also reset all data related to ICT table interrupt.
1751 */
1752int iwl_alloc_isr_ict(struct iwl_priv *priv)
1753{
1754
1755 if (priv->cfg->use_isr_legacy)
1756 return 0;
1757 /* allocate shrared data table */
1758 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1759 ICT_COUNT) + PAGE_SIZE,
1760 &priv->ict_tbl_dma);
1761 if (!priv->ict_tbl_vir)
1762 return -ENOMEM;
1763
1764 /* align table to PAGE_SIZE boundry */
1765 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1766
1767 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1768 (unsigned long long)priv->ict_tbl_dma,
1769 (unsigned long long)priv->aligned_ict_tbl_dma,
1770 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1771
1772 priv->ict_tbl = priv->ict_tbl_vir +
1773 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1774
1775 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1776 priv->ict_tbl, priv->ict_tbl_vir,
1777 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1778
1779 /* reset table and index to all 0 */
1780 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1781 priv->ict_index = 0;
1782
40cefda9
MA		 1783 /* add periodic RX interrupt */
1784 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1785 return 0;
1786}
1787EXPORT_SYMBOL(iwl_alloc_isr_ict);
1788
1789/* Device is going up inform it about using ICT interrupt table,
1790 * also we need to tell the driver to start using ICT interrupt.
1791 */
1792int iwl_reset_ict(struct iwl_priv *priv)
1793{
1794 u32 val;
1795 unsigned long flags;
1796
1797 if (!priv->ict_tbl_vir)
1798 return 0;
1799
1800 spin_lock_irqsave(&priv->lock, flags);
1801 iwl_disable_interrupts(priv);
1802
1803 memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT);
1804
1805 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1806
1807 val |= CSR_DRAM_INT_TBL_ENABLE;
1808 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1809
1810 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1811 "aligned dma address %Lx\n",
1812 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1813
1814 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1815 priv->use_ict = true;
1816 priv->ict_index = 0;
40cefda9 1817 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1818 iwl_enable_interrupts(priv);
1819 spin_unlock_irqrestore(&priv->lock, flags);
1820
1821 return 0;
1822}
1823EXPORT_SYMBOL(iwl_reset_ict);
1824
1825/* Device is going down disable ict interrupt usage */
1826void iwl_disable_ict(struct iwl_priv *priv)
1827{
1828 unsigned long flags;
1829
1830 spin_lock_irqsave(&priv->lock, flags);
1831 priv->use_ict = false;
1832 spin_unlock_irqrestore(&priv->lock, flags);
1833}
1834EXPORT_SYMBOL(iwl_disable_ict);
1835
1836/* interrupt handler using ict table, with this interrupt driver will
1837 * stop using INTA register to get device's interrupt, reading this register
1838 * is expensive, device will write interrupts in ICT dram table, increment
1839 * index then will fire interrupt to driver, driver will OR all ICT table
1840 * entries from current index up to table entry with 0 value. the result is
1841 * the interrupt we need to service, driver will set the entries back to 0 and
1842 * set index.
1843 */
1844irqreturn_t iwl_isr_ict(int irq, void *data)
1845{
1846 struct iwl_priv *priv = data;
1847 u32 inta, inta_mask;
1848 u32 val = 0;
1849
1850 if (!priv)
1851 return IRQ_NONE;
1852
1853 /* dram interrupt table not set yet,
1854 * use legacy interrupt.
1855 */
1856 if (!priv->use_ict)
1857 return iwl_isr(irq, data);
1858
1859 spin_lock(&priv->lock);
1860
1861 /* Disable (but don't clear!) interrupts here to avoid
1862 * back-to-back ISRs and sporadic interrupts from our NIC.
1863 * If we have something to service, the tasklet will re-enable ints.
1864 * If we *don't* have something, we'll re-enable before leaving here.
1865 */
1866 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1867 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1868
1869
1870 /* Ignore interrupt if there's nothing in NIC to service.
1871 * This may be due to IRQ shared with another device,
1872 * or due to sporadic interrupts thrown from our NIC. */
1873 if (!priv->ict_tbl[priv->ict_index]) {
1874 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1875 goto none;
1876 }
1877
1878 /* read all entries that not 0 start with ict_index */
1879 while (priv->ict_tbl[priv->ict_index]) {
1880
1881 val |= priv->ict_tbl[priv->ict_index];
1882 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1883 priv->ict_index,
1884 priv->ict_tbl[priv->ict_index]);
1885 priv->ict_tbl[priv->ict_index] = 0;
1886 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1887 ICT_COUNT);
1888
1889 }
1890
1891 /* We should not get this value, just ignore it. */
1892 if (val == 0xffffffff)
1893 val = 0;
1894
1895 inta = (0xff & val) | ((0xff00 & val) << 16);
1896 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1897 inta, inta_mask, val);
1898
40cefda9 1899 inta &= priv->inta_mask;
ef850d7c
MA		 1900 priv->inta |= inta;
1901
1902 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1903 if (likely(inta))
1904 tasklet_schedule(&priv->irq_tasklet);
1905 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1906 /* Allow interrupt if was disabled by this handler and
1907 * no tasklet was schedules, We should not enable interrupt,
1908 * tasklet will enable it.
1909 */
1910 iwl_enable_interrupts(priv);
1911 }
1912
1913 spin_unlock(&priv->lock);
1914 return IRQ_HANDLED;
1915
1916 none:
1917 /* re-enable interrupts here since we don't have anything to service.
1918 * only Re-enable if disabled by irq.
1919 */
1920 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1921 iwl_enable_interrupts(priv);
1922
1923 spin_unlock(&priv->lock);
1924 return IRQ_NONE;
1925}
1926EXPORT_SYMBOL(iwl_isr_ict);
1927
1928
1929static irqreturn_t iwl_isr(int irq, void *data)
1930{
1931 struct iwl_priv *priv = data;
1932 u32 inta, inta_mask;
d651ae32 1933#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1934 u32 inta_fh;
d651ae32 1935#endif
ef850d7c
MA		 1936 if (!priv)
1937 return IRQ_NONE;
1938
1939 spin_lock(&priv->lock);
1940
1941 /* Disable (but don't clear!) interrupts here to avoid
1942 * back-to-back ISRs and sporadic interrupts from our NIC.
1943 * If we have something to service, the tasklet will re-enable ints.
1944 * If we *don't* have something, we'll re-enable before leaving here. */
1945 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1946 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1947
1948 /* Discover which interrupts are active/pending */
1949 inta = iwl_read32(priv, CSR_INT);
1950
1951 /* Ignore interrupt if there's nothing in NIC to service.
1952 * This may be due to IRQ shared with another device,
1953 * or due to sporadic interrupts thrown from our NIC. */
1954 if (!inta) {
1955 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1956 goto none;
1957 }
1958
1959 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1960 /* Hardware disappeared. It might have already raised
1961 * an interrupt */
1962 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1963 goto unplugged;
1964 }
1965
1966#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1967 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1968 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1969 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1970 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1971 }
1972#endif
1973
1974 priv->inta |= inta;
1975 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1976 if (likely(inta))
1977 tasklet_schedule(&priv->irq_tasklet);
1978 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1979 iwl_enable_interrupts(priv);
1980
1981 unplugged:
1982 spin_unlock(&priv->lock);
1983 return IRQ_HANDLED;
1984
1985 none:
1986 /* re-enable interrupts here since we don't have anything to service. */
1987 /* only Re-enable if diabled by irq and no schedules tasklet. */
1988 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1989 iwl_enable_interrupts(priv);
1990
1991 spin_unlock(&priv->lock);
1992 return IRQ_NONE;
1993}
1994
1995irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1996{
1997 struct iwl_priv *priv = data;
1998 u32 inta, inta_mask;
1999 u32 inta_fh;
2000 if (!priv)
2001 return IRQ_NONE;
2002
2003 spin_lock(&priv->lock);
2004
2005 /* Disable (but don't clear!) interrupts here to avoid
2006 * back-to-back ISRs and sporadic interrupts from our NIC.
2007 * If we have something to service, the tasklet will re-enable ints.
2008 * If we *don't* have something, we'll re-enable before leaving here. */
2009 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
2010 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
2011
2012 /* Discover which interrupts are active/pending */
2013 inta = iwl_read32(priv, CSR_INT);
2014 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
2015
2016 /* Ignore interrupt if there's nothing in NIC to service.
2017 * This may be due to IRQ shared with another device,
2018 * or due to sporadic interrupts thrown from our NIC. */
2019 if (!inta && !inta_fh) {
2020 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
2021 goto none;
2022 }
2023
2024 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
2025 /* Hardware disappeared. It might have already raised
2026 * an interrupt */
2027 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
2028 goto unplugged;
2029 }
2030
2031 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
2032 inta, inta_mask, inta_fh);
2033
2034 inta &= ~CSR_INT_BIT_SCD;
2035
2036 /* iwl_irq_tasklet() will service interrupts and re-enable them */
2037 if (likely(inta || inta_fh))
2038 tasklet_schedule(&priv->irq_tasklet);
2039
2040 unplugged:
2041 spin_unlock(&priv->lock);
2042 return IRQ_HANDLED;
2043
2044 none:
2045 /* re-enable interrupts here since we don't have anything to service. */
2046 /* only Re-enable if diabled by irq */
2047 if (test_bit(STATUS_INT_ENABLED, &priv->status))
2048 iwl_enable_interrupts(priv);
2049 spin_unlock(&priv->lock);
2050 return IRQ_NONE;
2051}
ef850d7c 2052EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 2053
17f841cd
SO		 2054int iwl_send_bt_config(struct iwl_priv *priv)
2055{
2056 struct iwl_bt_cmd bt_cmd = {
2057 .flags = 3,
2058 .lead_time = 0xAA,
2059 .max_kill = 1,
2060 .kill_ack_mask = 0,
2061 .kill_cts_mask = 0,
2062 };
2063
2064 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
2065 sizeof(struct iwl_bt_cmd), &bt_cmd);
2066}
2067EXPORT_SYMBOL(iwl_send_bt_config);
2068
49ea8596
EG		 2069int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
2070{
2071 u32 stat_flags = 0;
2072 struct iwl_host_cmd cmd = {
2073 .id = REPLY_STATISTICS_CMD,
c2acea8e 2074 .flags = flags,
49ea8596
EG		 2075 .len = sizeof(stat_flags),
2076 .data = (u8 *) &stat_flags,
2077 };
2078 return iwl_send_cmd(priv, &cmd);
2079}
2080EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2081
b0692f2f
EG		 2082/**
2083 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2084 * using sample data 100 bytes apart. If these sample points are good,
2085 * it's a pretty good bet that everything between them is good, too.
2086 */
2087static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2088{
2089 u32 val;
2090 int ret = 0;
2091 u32 errcnt = 0;
2092 u32 i;
2093
e1623446 2094 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2095
b0692f2f
EG		 2096 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2097 /* read data comes through single port, auto-incr addr */
2098 /* NOTE: Use the debugless read so we don't flood kernel log
2099 * if IWL_DL_IO is set */
2100 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2101 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2102 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2103 if (val != le32_to_cpu(*image)) {
2104 ret = -EIO;
2105 errcnt++;
2106 if (errcnt >= 3)
2107 break;
2108 }
2109 }
2110
b0692f2f
EG		 2111 return ret;
2112}
2113
2114/**
2115 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2116 * looking at all data.
2117 */
2118static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2119 u32 len)
2120{
2121 u32 val;
2122 u32 save_len = len;
2123 int ret = 0;
2124 u32 errcnt;
2125
e1623446 2126 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2127
250bdd21
SO		 2128 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2129 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2130
2131 errcnt = 0;
2132 for (; len > 0; len -= sizeof(u32), image++) {
2133 /* read data comes through single port, auto-incr addr */
2134 /* NOTE: Use the debugless read so we don't flood kernel log
2135 * if IWL_DL_IO is set */
2136 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2137 if (val != le32_to_cpu(*image)) {
15b1687c 2138 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2139 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2140 save_len - len, val, le32_to_cpu(*image));
2141 ret = -EIO;
2142 errcnt++;
2143 if (errcnt >= 20)
2144 break;
2145 }
2146 }
2147
b0692f2f 2148 if (!errcnt)
e1623446
TW		 2149 IWL_DEBUG_INFO(priv,
2150 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2151
2152 return ret;
2153}
2154
2155/**
2156 * iwl_verify_ucode - determine which instruction image is in SRAM,
2157 * and verify its contents
2158 */
2159int iwl_verify_ucode(struct iwl_priv *priv)
2160{
2161 __le32 *image;
2162 u32 len;
2163 int ret;
2164
2165 /* Try bootstrap */
2166 image = (__le32 *)priv->ucode_boot.v_addr;
2167 len = priv->ucode_boot.len;
2168 ret = iwlcore_verify_inst_sparse(priv, image, len);
2169 if (!ret) {
e1623446 2170 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2171 return 0;
2172 }
2173
2174 /* Try initialize */
2175 image = (__le32 *)priv->ucode_init.v_addr;
2176 len = priv->ucode_init.len;
2177 ret = iwlcore_verify_inst_sparse(priv, image, len);
2178 if (!ret) {
e1623446 2179 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2180 return 0;
2181 }
2182
2183 /* Try runtime/protocol */
2184 image = (__le32 *)priv->ucode_code.v_addr;
2185 len = priv->ucode_code.len;
2186 ret = iwlcore_verify_inst_sparse(priv, image, len);
2187 if (!ret) {
e1623446 2188 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2189 return 0;
2190 }
2191
15b1687c 2192 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2193
2194 /* Since nothing seems to match, show first several data entries in
2195 * instruction SRAM, so maybe visual inspection will give a clue.
2196 * Selection of bootstrap image (vs. other images) is arbitrary. */
2197 image = (__le32 *)priv->ucode_boot.v_addr;
2198 len = priv->ucode_boot.len;
2199 ret = iwl_verify_inst_full(priv, image, len);
2200
2201 return ret;
2202}
2203EXPORT_SYMBOL(iwl_verify_ucode);
2204
56e12615 2205
47f4a587
EG		 2206void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2207{
2208 struct iwl_ct_kill_config cmd;
672639de 2209 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2210 unsigned long flags;
2211 int ret = 0;
2212
2213 spin_lock_irqsave(&priv->lock, flags);
2214 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2215 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2216 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2217 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2218
672639de
WYG		 2219 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
2220 case CSR_HW_REV_TYPE_1000:
2221 case CSR_HW_REV_TYPE_6x00:
2222 case CSR_HW_REV_TYPE_6x50:
2223 adv_cmd.critical_temperature_enter =
2224 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2225 adv_cmd.critical_temperature_exit =
2226 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2227
2228 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2229 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2230 if (ret)
2231 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2232 else
2233 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2234 "succeeded, "
2235 "critical temperature enter is %d,"
2236 "exit is %d\n",
2237 priv->hw_params.ct_kill_threshold,
2238 priv->hw_params.ct_kill_exit_threshold);
672639de
WYG		 2239 break;
2240 default:
2241 cmd.critical_temperature_R =
2242 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2243
672639de
WYG		 2244 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2245 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2246 if (ret)
2247 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2248 else
2249 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2250 "succeeded, "
2251 "critical temperature is %d\n",
2252 priv->hw_params.ct_kill_threshold);
672639de
WYG		 2253 break;
2254 }
47f4a587
EG		 2255}
2256EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2257
0ad91a35 2258
14a08a7f
EG		 2259/*
2260 * CARD_STATE_CMD
2261 *
2262 * Use: Sets the device's internal card state to enable, disable, or halt
2263 *
2264 * When in the 'enable' state the card operates as normal.
2265 * When in the 'disable' state, the card enters into a low power mode.
2266 * When in the 'halt' state, the card is shut down and must be fully
2267 * restarted to come back on.
2268 */
c496294e 2269int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2270{
2271 struct iwl_host_cmd cmd = {
2272 .id = REPLY_CARD_STATE_CMD,
2273 .len = sizeof(u32),
2274 .data = &flags,
c2acea8e 2275 .flags = meta_flag,
14a08a7f
EG		 2276 };
2277
2278 return iwl_send_cmd(priv, &cmd);
2279}
2280
030f05ed
AK		 2281void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2282 struct iwl_rx_mem_buffer *rxb)
2283{
2284#ifdef CONFIG_IWLWIFI_DEBUG
2285 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2286 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2287 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2288 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2289#endif
2290}
2291EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2292
2293void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2294 struct iwl_rx_mem_buffer *rxb)
2295{
2296 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2297 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
2298 "notification for %s:\n",
2299 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
3d816c77 2300 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
030f05ed
AK		 2301}
2302EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2303
2304void iwl_rx_reply_error(struct iwl_priv *priv,
2305 struct iwl_rx_mem_buffer *rxb)
2306{
2307 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2308
2309 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2310 "seq 0x%04X ser 0x%08X\n",
2311 le32_to_cpu(pkt->u.err_resp.error_type),
2312 get_cmd_string(pkt->u.err_resp.cmd_id),
2313 pkt->u.err_resp.cmd_id,
2314 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2315 le32_to_cpu(pkt->u.err_resp.error_info));
2316}
2317EXPORT_SYMBOL(iwl_rx_reply_error);
2318
a83b9141
WYG		 2319void iwl_clear_isr_stats(struct iwl_priv *priv)
2320{
2321 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2322}
a83b9141 2323
488829f1
AK		 2324int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2325 const struct ieee80211_tx_queue_params *params)
2326{
2327 struct iwl_priv *priv = hw->priv;
2328 unsigned long flags;
2329 int q;
2330
2331 IWL_DEBUG_MAC80211(priv, "enter\n");
2332
2333 if (!iwl_is_ready_rf(priv)) {
2334 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2335 return -EIO;
2336 }
2337
2338 if (queue >= AC_NUM) {
2339 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2340 return 0;
2341 }
2342
2343 q = AC_NUM - 1 - queue;
2344
2345 spin_lock_irqsave(&priv->lock, flags);
2346
2347 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2348 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2349 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2350 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2351 cpu_to_le16((params->txop * 32));
2352
2353 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2354 priv->qos_data.qos_active = 1;
2355
2356 if (priv->iw_mode == NL80211_IFTYPE_AP)
2357 iwl_activate_qos(priv, 1);
2358 else if (priv->assoc_id && iwl_is_associated(priv))
2359 iwl_activate_qos(priv, 0);
2360
2361 spin_unlock_irqrestore(&priv->lock, flags);
2362
2363 IWL_DEBUG_MAC80211(priv, "leave\n");
2364 return 0;
2365}
2366EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2367
2368static void iwl_ht_conf(struct iwl_priv *priv,
2369 struct ieee80211_bss_conf *bss_conf)
2370{
2371 struct ieee80211_sta_ht_cap *ht_conf;
2372 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
2373 struct ieee80211_sta *sta;
2374
2375 IWL_DEBUG_MAC80211(priv, "enter: \n");
2376
2377 if (!iwl_conf->is_ht)
2378 return;
2379
2380
2381 /*
2382 * It is totally wrong to base global information on something
2383 * that is valid only when associated, alas, this driver works
2384 * that way and I don't know how to fix it.
2385 */
2386
2387 rcu_read_lock();
2388 sta = ieee80211_find_sta(priv->hw, priv->bssid);
2389 if (!sta) {
2390 rcu_read_unlock();
2391 return;
2392 }
2393 ht_conf = &sta->ht_cap;
2394
5bbe233b
AK		 2395 iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
2396
2397 memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
2398
5bbe233b 2399 iwl_conf->ht_protection =
9ed6bcce 2400 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
5bbe233b 2401 iwl_conf->non_GF_STA_present =
9ed6bcce 2402 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b
AK		 2403
2404 rcu_read_unlock();
2405
2406 IWL_DEBUG_MAC80211(priv, "leave\n");
2407}
2408
2409#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2410void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2411 struct ieee80211_vif *vif,
2412 struct ieee80211_bss_conf *bss_conf,
2413 u32 changes)
5bbe233b
AK		 2414{
2415 struct iwl_priv *priv = hw->priv;
3a650292 2416 int ret;
5bbe233b
AK		 2417
2418 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2419
2d0ddec5
JB		 2420 if (!iwl_is_alive(priv))
2421 return;
2422
2423 mutex_lock(&priv->mutex);
2424
2425 if (changes & BSS_CHANGED_BEACON &&
2426 priv->iw_mode == NL80211_IFTYPE_AP) {
2427 dev_kfree_skb(priv->ibss_beacon);
2428 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2429 }
2430
d7129e19
JB		 2431 if (changes & BSS_CHANGED_BEACON_INT) {
2432 priv->beacon_int = bss_conf->beacon_int;
2433 /* TODO: in AP mode, do something to make this take effect */
2434 }
2435
2436 if (changes & BSS_CHANGED_BSSID) {
2437 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2438
2439 /*
2440 * If there is currently a HW scan going on in the
2441 * background then we need to cancel it else the RXON
2442 * below/in post_associate will fail.
2443 */
2d0ddec5 2444 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2445 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2446 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2447 mutex_unlock(&priv->mutex);
2448 return;
2449 }
2d0ddec5 2450
d7129e19
JB		 2451 /* mac80211 only sets assoc when in STATION mode */
2452 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2453 bss_conf->assoc) {
2454 memcpy(priv->staging_rxon.bssid_addr,
2455 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2456
d7129e19
JB		 2457 /* currently needed in a few places */
2458 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2459 } else {
2460 priv->staging_rxon.filter_flags &=
2461 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2462 }
d7129e19 2463
2d0ddec5
JB		 2464 }
2465
d7129e19
JB		 2466 /*
2467 * This needs to be after setting the BSSID in case
2468 * mac80211 decides to do both changes at once because
2469 * it will invoke post_associate.
2470 */
2d0ddec5
JB		 2471 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2472 changes & BSS_CHANGED_BEACON) {
2473 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2474
2475 if (beacon)
2476 iwl_mac_beacon_update(hw, beacon);
2477 }
2478
5bbe233b
AK		 2479 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2480 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2481 bss_conf->use_short_preamble);
2482 if (bss_conf->use_short_preamble)
2483 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2484 else
2485 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2486 }
2487
2488 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2489 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2490 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2491 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2492 else
2493 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2494 }
2495
d7129e19
JB		 2496 if (changes & BSS_CHANGED_BASIC_RATES) {
2497 /* XXX use this information
2498 *
2499 * To do that, remove code from iwl_set_rate() and put something
2500 * like this here:
2501 *
2502 if (A-band)
2503 priv->staging_rxon.ofdm_basic_rates =
2504 bss_conf->basic_rates;
2505 else
2506 priv->staging_rxon.ofdm_basic_rates =
2507 bss_conf->basic_rates >> 4;
2508 priv->staging_rxon.cck_basic_rates =
2509 bss_conf->basic_rates & 0xF;
2510 */
2511 }
2512
5bbe233b
AK		 2513 if (changes & BSS_CHANGED_HT) {
2514 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2515
2516 if (priv->cfg->ops->hcmd->set_rxon_chain)
2517 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2518 }
2519
2520 if (changes & BSS_CHANGED_ASSOC) {
2521 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2522 if (bss_conf->assoc) {
2523 priv->assoc_id = bss_conf->aid;
2524 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2525 priv->timestamp = bss_conf->timestamp;
2526 priv->assoc_capability = bss_conf->assoc_capability;
2527
d7129e19
JB		 2528 /*
2529 * We have just associated, don't start scan too early
2530 * leave time for EAPOL exchange to complete.
2531 *
2532 * XXX: do this in mac80211
5bbe233b
AK		 2533 */
2534 priv->next_scan_jiffies = jiffies +
2535 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2536 if (!iwl_is_rfkill(priv))
2537 priv->cfg->ops->lib->post_associate(priv);
2538 } else
5bbe233b 2539 priv->assoc_id = 0;
d7129e19
JB		 2540
2541 }
2542
2543 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2544 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2545 changes);
2546 ret = iwl_send_rxon_assoc(priv);
2547 if (!ret) {
2548 /* Sync active_rxon with latest change. */
2549 memcpy((void *)&priv->active_rxon,
2550 &priv->staging_rxon,
2551 sizeof(struct iwl_rxon_cmd));
5bbe233b 2552 }
5bbe233b 2553 }
d7129e19
JB		 2554
2555 mutex_unlock(&priv->mutex);
2556
2d0ddec5 2557 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2558}
2559EXPORT_SYMBOL(iwl_bss_info_changed);
2560
9944b938
AK		 2561int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2562{
2563 struct iwl_priv *priv = hw->priv;
2564 unsigned long flags;
2565 __le64 timestamp;
2566
2567 IWL_DEBUG_MAC80211(priv, "enter\n");
2568
2569 if (!iwl_is_ready_rf(priv)) {
2570 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2571 return -EIO;
2572 }
2573
2574 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2575 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2576 return -EIO;
2577 }
2578
2579 spin_lock_irqsave(&priv->lock, flags);
2580
2581 if (priv->ibss_beacon)
2582 dev_kfree_skb(priv->ibss_beacon);
2583
2584 priv->ibss_beacon = skb;
2585
2586 priv->assoc_id = 0;
2587 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2588 priv->timestamp = le64_to_cpu(timestamp);
2589
2590 IWL_DEBUG_MAC80211(priv, "leave\n");
2591 spin_unlock_irqrestore(&priv->lock, flags);
2592
2593 iwl_reset_qos(priv);
2594
2595 priv->cfg->ops->lib->post_associate(priv);
2596
2597
2598 return 0;
2599}
2600EXPORT_SYMBOL(iwl_mac_beacon_update);
2601
727882d6
AK		 2602int iwl_set_mode(struct iwl_priv *priv, int mode)
2603{
2604 if (mode == NL80211_IFTYPE_ADHOC) {
2605 const struct iwl_channel_info *ch_info;
2606
2607 ch_info = iwl_get_channel_info(priv,
2608 priv->band,
2609 le16_to_cpu(priv->staging_rxon.channel));
2610
2611 if (!ch_info || !is_channel_ibss(ch_info)) {
2612 IWL_ERR(priv, "channel %d not IBSS channel\n",
2613 le16_to_cpu(priv->staging_rxon.channel));
2614 return -EINVAL;
2615 }
2616 }
2617
2618 iwl_connection_init_rx_config(priv, mode);
2619
2620 if (priv->cfg->ops->hcmd->set_rxon_chain)
2621 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2622
2623 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2624
c587de0b 2625 iwl_clear_stations_table(priv);
727882d6
AK		 2626
2627 /* dont commit rxon if rf-kill is on*/
2628 if (!iwl_is_ready_rf(priv))
2629 return -EAGAIN;
2630
727882d6
AK		 2631 iwlcore_commit_rxon(priv);
2632
2633 return 0;
2634}
2635EXPORT_SYMBOL(iwl_set_mode);
2636
cbb6ab94
AK		 2637int iwl_mac_add_interface(struct ieee80211_hw *hw,
2638 struct ieee80211_if_init_conf *conf)
2639{
2640 struct iwl_priv *priv = hw->priv;
2641 unsigned long flags;
2642
2643 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2644
2645 if (priv->vif) {
2646 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2647 return -EOPNOTSUPP;
2648 }
2649
2650 spin_lock_irqsave(&priv->lock, flags);
2651 priv->vif = conf->vif;
2652 priv->iw_mode = conf->type;
2653
2654 spin_unlock_irqrestore(&priv->lock, flags);
2655
2656 mutex_lock(&priv->mutex);
2657
2658 if (conf->mac_addr) {
2659 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2660 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2661 }
2662
2663 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2664 /* we are not ready, will run again when ready */
2665 set_bit(STATUS_MODE_PENDING, &priv->status);
2666
2667 mutex_unlock(&priv->mutex);
2668
2669 IWL_DEBUG_MAC80211(priv, "leave\n");
2670 return 0;
2671}
2672EXPORT_SYMBOL(iwl_mac_add_interface);
2673
d8052319
AK		 2674void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2675 struct ieee80211_if_init_conf *conf)
2676{
2677 struct iwl_priv *priv = hw->priv;
2678
2679 IWL_DEBUG_MAC80211(priv, "enter\n");
2680
2681 mutex_lock(&priv->mutex);
2682
2683 if (iwl_is_ready_rf(priv)) {
2684 iwl_scan_cancel_timeout(priv, 100);
2685 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2686 iwlcore_commit_rxon(priv);
2687 }
2688 if (priv->vif == conf->vif) {
2689 priv->vif = NULL;
2690 memset(priv->bssid, 0, ETH_ALEN);
2691 }
2692 mutex_unlock(&priv->mutex);
2693
2694 IWL_DEBUG_MAC80211(priv, "leave\n");
2695
2696}
2697EXPORT_SYMBOL(iwl_mac_remove_interface);
2698
4808368d
AK		 2699/**
2700 * iwl_mac_config - mac80211 config callback
2701 *
2702 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2703 * be set inappropriately and the driver currently sets the hardware up to
2704 * use it whenever needed.
2705 */
2706int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2707{
2708 struct iwl_priv *priv = hw->priv;
2709 const struct iwl_channel_info *ch_info;
2710 struct ieee80211_conf *conf = &hw->conf;
28bd723b 2711 struct iwl_ht_info *ht_conf = &priv->current_ht_config;
4808368d
AK		 2712 unsigned long flags = 0;
2713 int ret = 0;
2714 u16 ch;
2715 int scan_active = 0;
2716
2717 mutex_lock(&priv->mutex);
2718
4808368d
AK		 2719 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2720 conf->channel->hw_value, changed);
2721
2722 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2723 test_bit(STATUS_SCANNING, &priv->status))) {
2724 scan_active = 1;
2725 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2726 }
2727
2728
2729 /* during scanning mac80211 will delay channel setting until
2730 * scan finish with changed = 0
2731 */
2732 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2733 if (scan_active)
2734 goto set_ch_out;
2735
2736 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2737 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2738 if (!is_channel_valid(ch_info)) {
2739 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2740 ret = -EINVAL;
2741 goto set_ch_out;
2742 }
2743
2744 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2745 !is_channel_ibss(ch_info)) {
2746 IWL_ERR(priv, "channel %d in band %d not "
2747 "IBSS channel\n",
2748 conf->channel->hw_value, conf->channel->band);
2749 ret = -EINVAL;
2750 goto set_ch_out;
2751 }
2752
4808368d
AK		 2753 spin_lock_irqsave(&priv->lock, flags);
2754
28bd723b
DH		 2755 /* Configure HT40 channels */
2756 ht_conf->is_ht = conf_is_ht(conf);
2757 if (ht_conf->is_ht) {
2758 if (conf_is_ht40_minus(conf)) {
2759 ht_conf->extension_chan_offset =
2760 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2761 ht_conf->supported_chan_width =
2762 IWL_CHANNEL_WIDTH_40MHZ;
2763 } else if (conf_is_ht40_plus(conf)) {
2764 ht_conf->extension_chan_offset =
2765 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2766 ht_conf->supported_chan_width =
2767 IWL_CHANNEL_WIDTH_40MHZ;
2768 } else {
2769 ht_conf->extension_chan_offset =
2770 IEEE80211_HT_PARAM_CHA_SEC_NONE;
2771 ht_conf->supported_chan_width =
2772 IWL_CHANNEL_WIDTH_20MHZ;
2773 }
2774 } else
2775 ht_conf->supported_chan_width = IWL_CHANNEL_WIDTH_20MHZ;
2776 /* Default to no protection. Protection mode will later be set
2777 * from BSS config in iwl_ht_conf */
2778 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2779
2780 /* if we are switching from ht to 2.4 clear flags
2781 * from any ht related info since 2.4 does not
2782 * support ht */
2783 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2784 priv->staging_rxon.flags = 0;
2785
2786 iwl_set_rxon_channel(priv, conf->channel);
2787
2788 iwl_set_flags_for_band(priv, conf->channel->band);
2789 spin_unlock_irqrestore(&priv->lock, flags);
2790 set_ch_out:
2791 /* The list of supported rates and rate mask can be different
2792 * for each band; since the band may have changed, reset
2793 * the rate mask to what mac80211 lists */
2794 iwl_set_rate(priv);
2795 }
2796
e312c24c
JB		 2797 if (changed & IEEE80211_CONF_CHANGE_PS) {
2798 ret = iwl_power_update_mode(priv, false);
4808368d 2799 if (ret)
e312c24c 2800 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2801 }
2802
2803 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2804 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2805 priv->tx_power_user_lmt, conf->power_level);
2806
2807 iwl_set_tx_power(priv, conf->power_level, false);
2808 }
2809
2810 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2811 if (priv->cfg->ops->hcmd->set_rxon_chain)
2812 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2813
0cf4c01e
MA		 2814 if (!iwl_is_ready(priv)) {
2815 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2816 goto out;
2817 }
2818
4808368d
AK		 2819 if (scan_active)
2820 goto out;
2821
2822 if (memcmp(&priv->active_rxon,
2823 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2824 iwlcore_commit_rxon(priv);
2825 else
2826 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2827
2828
2829out:
2830 IWL_DEBUG_MAC80211(priv, "leave\n");
2831 mutex_unlock(&priv->mutex);
2832 return ret;
2833}
2834EXPORT_SYMBOL(iwl_mac_config);
2835
aa89f31e
AK		 2836int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2837 struct ieee80211_tx_queue_stats *stats)
2838{
2839 struct iwl_priv *priv = hw->priv;
2840 int i, avail;
2841 struct iwl_tx_queue *txq;
2842 struct iwl_queue *q;
2843 unsigned long flags;
2844
2845 IWL_DEBUG_MAC80211(priv, "enter\n");
2846
2847 if (!iwl_is_ready_rf(priv)) {
2848 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2849 return -EIO;
2850 }
2851
2852 spin_lock_irqsave(&priv->lock, flags);
2853
2854 for (i = 0; i < AC_NUM; i++) {
2855 txq = &priv->txq[i];
2856 q = &txq->q;
2857 avail = iwl_queue_space(q);
2858
2859 stats[i].len = q->n_window - avail;
2860 stats[i].limit = q->n_window - q->high_mark;
2861 stats[i].count = q->n_window;
2862
2863 }
2864 spin_unlock_irqrestore(&priv->lock, flags);
2865
2866 IWL_DEBUG_MAC80211(priv, "leave\n");
2867
2868 return 0;
2869}
2870EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2871
bd564261
AK		 2872void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2873{
2874 struct iwl_priv *priv = hw->priv;
2875 unsigned long flags;
2876
2877 mutex_lock(&priv->mutex);
2878 IWL_DEBUG_MAC80211(priv, "enter\n");
2879
2880 spin_lock_irqsave(&priv->lock, flags);
2881 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
2882 spin_unlock_irqrestore(&priv->lock, flags);
2883
2884 iwl_reset_qos(priv);
2885
2886 spin_lock_irqsave(&priv->lock, flags);
2887 priv->assoc_id = 0;
2888 priv->assoc_capability = 0;
2889 priv->assoc_station_added = 0;
2890
2891 /* new association get rid of ibss beacon skb */
2892 if (priv->ibss_beacon)
2893 dev_kfree_skb(priv->ibss_beacon);
2894
2895 priv->ibss_beacon = NULL;
2896
57c4d7b4 2897 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2898 priv->timestamp = 0;
2899 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2900 priv->beacon_int = 0;
2901
2902 spin_unlock_irqrestore(&priv->lock, flags);
2903
2904 if (!iwl_is_ready_rf(priv)) {
2905 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2906 mutex_unlock(&priv->mutex);
2907 return;
2908 }
2909
2910 /* we are restarting association process
2911 * clear RXON_FILTER_ASSOC_MSK bit
2912 */
2913 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2914 iwl_scan_cancel_timeout(priv, 100);
2915 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2916 iwlcore_commit_rxon(priv);
2917 }
2918
bd564261 2919 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2920 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2921 mutex_unlock(&priv->mutex);
2922 return;
2923 }
2924
2925 iwl_set_rate(priv);
2926
2927 mutex_unlock(&priv->mutex);
2928
2929 IWL_DEBUG_MAC80211(priv, "leave\n");
2930}
2931EXPORT_SYMBOL(iwl_mac_reset_tsf);
2932
20594eb0
WYG		 2933#ifdef CONFIG_IWLWIFI_DEBUGFS
2934
2935#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2936
2937void iwl_reset_traffic_log(struct iwl_priv *priv)
2938{
2939 priv->tx_traffic_idx = 0;
2940 priv->rx_traffic_idx = 0;
2941 if (priv->tx_traffic)
2942 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2943 if (priv->rx_traffic)
2944 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2945}
2946
2947int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2948{
2949 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2950
2951 if (iwl_debug_level & IWL_DL_TX) {
2952 if (!priv->tx_traffic) {
2953 priv->tx_traffic =
2954 kzalloc(traffic_size, GFP_KERNEL);
2955 if (!priv->tx_traffic)
2956 return -ENOMEM;
2957 }
2958 }
2959 if (iwl_debug_level & IWL_DL_RX) {
2960 if (!priv->rx_traffic) {
2961 priv->rx_traffic =
2962 kzalloc(traffic_size, GFP_KERNEL);
2963 if (!priv->rx_traffic)
2964 return -ENOMEM;
2965 }
2966 }
2967 iwl_reset_traffic_log(priv);
2968 return 0;
2969}
2970EXPORT_SYMBOL(iwl_alloc_traffic_mem);
2971
2972void iwl_free_traffic_mem(struct iwl_priv *priv)
2973{
2974 kfree(priv->tx_traffic);
2975 priv->tx_traffic = NULL;
2976
2977 kfree(priv->rx_traffic);
2978 priv->rx_traffic = NULL;
2979}
2980EXPORT_SYMBOL(iwl_free_traffic_mem);
2981
2982void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
2983 u16 length, struct ieee80211_hdr *header)
2984{
2985 __le16 fc;
2986 u16 len;
2987
2988 if (likely(!(iwl_debug_level & IWL_DL_TX)))
2989 return;
2990
2991 if (!priv->tx_traffic)
2992 return;
2993
2994 fc = header->frame_control;
2995 if (ieee80211_is_data(fc)) {
2996 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
2997 ? IWL_TRAFFIC_ENTRY_SIZE : length;
2998 memcpy((priv->tx_traffic +
2999 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3000 header, len);
3001 priv->tx_traffic_idx =
3002 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3003 }
3004}
3005EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
3006
3007void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
3008 u16 length, struct ieee80211_hdr *header)
3009{
3010 __le16 fc;
3011 u16 len;
3012
3013 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3014 return;
3015
3016 if (!priv->rx_traffic)
3017 return;
3018
3019 fc = header->frame_control;
3020 if (ieee80211_is_data(fc)) {
3021 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3022 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3023 memcpy((priv->rx_traffic +
3024 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3025 header, len);
3026 priv->rx_traffic_idx =
3027 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3028 }
3029}
3030EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 3031
3032const char *get_mgmt_string(int cmd)
3033{
3034 switch (cmd) {
3035 IWL_CMD(MANAGEMENT_ASSOC_REQ);
3036 IWL_CMD(MANAGEMENT_ASSOC_RESP);
3037 IWL_CMD(MANAGEMENT_REASSOC_REQ);
3038 IWL_CMD(MANAGEMENT_REASSOC_RESP);
3039 IWL_CMD(MANAGEMENT_PROBE_REQ);
3040 IWL_CMD(MANAGEMENT_PROBE_RESP);
3041 IWL_CMD(MANAGEMENT_BEACON);
3042 IWL_CMD(MANAGEMENT_ATIM);
3043 IWL_CMD(MANAGEMENT_DISASSOC);
3044 IWL_CMD(MANAGEMENT_AUTH);
3045 IWL_CMD(MANAGEMENT_DEAUTH);
3046 IWL_CMD(MANAGEMENT_ACTION);
3047 default:
3048 return "UNKNOWN";
3049
3050 }
3051}
3052
3053const char *get_ctrl_string(int cmd)
3054{
3055 switch (cmd) {
3056 IWL_CMD(CONTROL_BACK_REQ);
3057 IWL_CMD(CONTROL_BACK);
3058 IWL_CMD(CONTROL_PSPOLL);
3059 IWL_CMD(CONTROL_RTS);
3060 IWL_CMD(CONTROL_CTS);
3061 IWL_CMD(CONTROL_ACK);
3062 IWL_CMD(CONTROL_CFEND);
3063 IWL_CMD(CONTROL_CFENDACK);
3064 default:
3065 return "UNKNOWN";
3066
3067 }
3068}
3069
3070void iwl_clear_tx_stats(struct iwl_priv *priv)
3071{
3072 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
3073
3074}
3075
3076void iwl_clear_rx_stats(struct iwl_priv *priv)
3077{
3078 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
3079}
3080
3081/*
3082 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3083 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3084 * Use debugFs to display the rx/rx_statistics
3085 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3086 * information will be recorded, but DATA pkt still will be recorded
3087 * for the reason of iwl_led.c need to control the led blinking based on
3088 * number of tx and rx data.
3089 *
3090 */
3091void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3092{
3093 struct traffic_stats *stats;
3094
3095 if (is_tx)
3096 stats = &priv->tx_stats;
3097 else
3098 stats = &priv->rx_stats;
3099
3100 if (ieee80211_is_mgmt(fc)) {
3101 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3102 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3103 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3104 break;
3105 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3106 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3107 break;
3108 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3109 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3110 break;
3111 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3112 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3113 break;
3114 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3115 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3116 break;
3117 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3118 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3119 break;
3120 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3121 stats->mgmt[MANAGEMENT_BEACON]++;
3122 break;
3123 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3124 stats->mgmt[MANAGEMENT_ATIM]++;
3125 break;
3126 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3127 stats->mgmt[MANAGEMENT_DISASSOC]++;
3128 break;
3129 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3130 stats->mgmt[MANAGEMENT_AUTH]++;
3131 break;
3132 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3133 stats->mgmt[MANAGEMENT_DEAUTH]++;
3134 break;
3135 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3136 stats->mgmt[MANAGEMENT_ACTION]++;
3137 break;
3138 }
3139 } else if (ieee80211_is_ctl(fc)) {
3140 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3141 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3142 stats->ctrl[CONTROL_BACK_REQ]++;
3143 break;
3144 case cpu_to_le16(IEEE80211_STYPE_BACK):
3145 stats->ctrl[CONTROL_BACK]++;
3146 break;
3147 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3148 stats->ctrl[CONTROL_PSPOLL]++;
3149 break;
3150 case cpu_to_le16(IEEE80211_STYPE_RTS):
3151 stats->ctrl[CONTROL_RTS]++;
3152 break;
3153 case cpu_to_le16(IEEE80211_STYPE_CTS):
3154 stats->ctrl[CONTROL_CTS]++;
3155 break;
3156 case cpu_to_le16(IEEE80211_STYPE_ACK):
3157 stats->ctrl[CONTROL_ACK]++;
3158 break;
3159 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3160 stats->ctrl[CONTROL_CFEND]++;
3161 break;
3162 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3163 stats->ctrl[CONTROL_CFENDACK]++;
3164 break;
3165 }
3166 } else {
3167 /* data */
3168 stats->data_cnt++;
3169 stats->data_bytes += len;
3170 }
3171}
3172EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3173#endif
3174
6da3a13e
WYG		 3175#ifdef CONFIG_PM
3176
3177int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3178{
3179 struct iwl_priv *priv = pci_get_drvdata(pdev);
3180
3181 /*
3182 * This function is called when system goes into suspend state
3183 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3184 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3185 * it will not call apm_ops.stop() to stop the DMA operation.
3186 * Calling apm_ops.stop here to make sure we stop the DMA.
3187 */
3188 priv->cfg->ops->lib->apm_ops.stop(priv);
3189
3190 pci_save_state(pdev);
3191 pci_disable_device(pdev);
3192 pci_set_power_state(pdev, PCI_D3hot);
3193
3194 return 0;
3195}
3196EXPORT_SYMBOL(iwl_pci_suspend);
3197
3198int iwl_pci_resume(struct pci_dev *pdev)
3199{
3200 struct iwl_priv *priv = pci_get_drvdata(pdev);
3201 int ret;
3202
3203 pci_set_power_state(pdev, PCI_D0);
3204 ret = pci_enable_device(pdev);
3205 if (ret)
3206 return ret;
3207 pci_restore_state(pdev);
3208 iwl_enable_interrupts(priv);
3209
3210 return 0;
3211}
3212EXPORT_SYMBOL(iwl_pci_resume);
3213
3214#endif /* CONFIG_PM */
Linux kernel - Deliverables
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