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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
1d0a082d 31#include <net/mac80211.h>
df48c323 32
712b6cf5 33struct iwl_priv; /* FIXME: remove */
0a6857e7 34#include "iwl-debug.h"
6bc913bd 35#include "iwl-eeprom.h"
3e0d4cb1 36#include "iwl-dev.h" /* FIXME: remove */
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
ad97edd2 39#include "iwl-rfkill.h"
5da4b55f 40#include "iwl-power.h"
df48c323 41
1d0a082d 42
df48c323
TW		 43MODULE_DESCRIPTION("iwl core");
44MODULE_VERSION(IWLWIFI_VERSION);
45MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 46MODULE_LICENSE("GPL");
df48c323 47
c7de35cd
RR		 48#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
60
61/*
62 * Parameter order:
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
1826dcc0 69const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 70 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
84};
1826dcc0 85EXPORT_SYMBOL(iwl_rates);
c7de35cd 86
e7d326ac
TW		 87/**
88 * translate ucode response to mac80211 tx status control values
89 */
90void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
91 struct ieee80211_tx_info *control)
92{
93 int rate_index;
94
95 control->antenna_sel_tx =
96 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
97 if (rate_n_flags & RATE_MCS_HT_MSK)
98 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
99 if (rate_n_flags & RATE_MCS_GF_MSK)
100 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
101 if (rate_n_flags & RATE_MCS_FAT_MSK)
102 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
103 if (rate_n_flags & RATE_MCS_DUP_MSK)
104 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
105 if (rate_n_flags & RATE_MCS_SGI_MSK)
106 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
107 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
108 if (control->band == IEEE80211_BAND_5GHZ)
109 rate_index -= IWL_FIRST_OFDM_RATE;
110 control->tx_rate_idx = rate_index;
111}
112EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
113
114int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
115{
116 int idx = 0;
117
118 /* HT rate format */
119 if (rate_n_flags & RATE_MCS_HT_MSK) {
120 idx = (rate_n_flags & 0xff);
121
122 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
123 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
124
125 idx += IWL_FIRST_OFDM_RATE;
126 /* skip 9M not supported in ht*/
127 if (idx >= IWL_RATE_9M_INDEX)
128 idx += 1;
129 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
130 return idx;
131
132 /* legacy rate format, search for match in table */
133 } else {
134 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
135 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
136 return idx;
137 }
138
139 return -1;
140}
141EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
142
143
57bd1bea
TW		 144
145const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
146EXPORT_SYMBOL(iwl_bcast_addr);
147
148
1d0a082d
AK		 149/* This function both allocates and initializes hw and priv. */
150struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
151 struct ieee80211_ops *hw_ops)
152{
153 struct iwl_priv *priv;
154
155 /* mac80211 allocates memory for this device instance, including
156 * space for this driver's private structure */
157 struct ieee80211_hw *hw =
158 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
159 if (hw == NULL) {
160 IWL_ERROR("Can not allocate network device\n");
161 goto out;
162 }
163
164 priv = hw->priv;
165 priv->hw = hw;
166
167out:
168 return hw;
169}
170EXPORT_SYMBOL(iwl_alloc_all);
171
b661c819
TW		 172void iwl_hw_detect(struct iwl_priv *priv)
173{
174 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
175 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
176 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
177}
178EXPORT_SYMBOL(iwl_hw_detect);
179
1053d35f
RR		 180/* Tell nic where to find the "keep warm" buffer */
181int iwl_kw_init(struct iwl_priv *priv)
182{
183 unsigned long flags;
184 int ret;
185
186 spin_lock_irqsave(&priv->lock, flags);
187 ret = iwl_grab_nic_access(priv);
188 if (ret)
189 goto out;
190
191 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
192 priv->kw.dma_addr >> 4);
193 iwl_release_nic_access(priv);
194out:
195 spin_unlock_irqrestore(&priv->lock, flags);
196 return ret;
197}
198
199int iwl_kw_alloc(struct iwl_priv *priv)
200{
201 struct pci_dev *dev = priv->pci_dev;
16466903 202 struct iwl_kw *kw = &priv->kw;
1053d35f 203
16466903 204 kw->size = IWL_KW_SIZE;
1053d35f
RR		 205 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
206 if (!kw->v_addr)
207 return -ENOMEM;
208
209 return 0;
210}
211
212/**
213 * iwl_kw_free - Free the "keep warm" buffer
214 */
215void iwl_kw_free(struct iwl_priv *priv)
216{
217 struct pci_dev *dev = priv->pci_dev;
16466903 218 struct iwl_kw *kw = &priv->kw;
1053d35f
RR		 219
220 if (kw->v_addr) {
221 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
222 memset(kw, 0, sizeof(*kw));
223 }
224}
225
226int iwl_hw_nic_init(struct iwl_priv *priv)
227{
228 unsigned long flags;
229 struct iwl_rx_queue *rxq = &priv->rxq;
230 int ret;
231
232 /* nic_init */
1053d35f 233 spin_lock_irqsave(&priv->lock, flags);
1b73af82 234 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 235 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
236 spin_unlock_irqrestore(&priv->lock, flags);
237
238 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
239
240 priv->cfg->ops->lib->apm_ops.config(priv);
241
242 /* Allocate the RX queue, or reset if it is already allocated */
243 if (!rxq->bd) {
244 ret = iwl_rx_queue_alloc(priv);
245 if (ret) {
246 IWL_ERROR("Unable to initialize Rx queue\n");
247 return -ENOMEM;
248 }
249 } else
250 iwl_rx_queue_reset(priv, rxq);
251
252 iwl_rx_replenish(priv);
253
254 iwl_rx_init(priv, rxq);
255
256 spin_lock_irqsave(&priv->lock, flags);
257
258 rxq->need_update = 1;
259 iwl_rx_queue_update_write_ptr(priv, rxq);
260
261 spin_unlock_irqrestore(&priv->lock, flags);
262
263 /* Allocate and init all Tx and Command queues */
264 ret = iwl_txq_ctx_reset(priv);
265 if (ret)
266 return ret;
267
268 set_bit(STATUS_INIT, &priv->status);
269
270 return 0;
271}
272EXPORT_SYMBOL(iwl_hw_nic_init);
273
bf85ea4f 274/**
37deb2a0 275 * iwl_clear_stations_table - Clear the driver's station table
bf85ea4f
AK		 276 *
277 * NOTE: This does not clear or otherwise alter the device's station table.
278 */
37deb2a0 279void iwl_clear_stations_table(struct iwl_priv *priv)
bf85ea4f
AK		 280{
281 unsigned long flags;
282
283 spin_lock_irqsave(&priv->sta_lock, flags);
284
24e5c401 285 if (iwl_is_alive(priv) &&
37deb2a0
EG		 286 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
287 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
24e5c401
EG		 288 IWL_ERROR("Couldn't clear the station table\n");
289
37deb2a0 290 priv->num_stations = 0;
bf85ea4f
AK		 291 memset(priv->stations, 0, sizeof(priv->stations));
292
293 spin_unlock_irqrestore(&priv->sta_lock, flags);
294}
37deb2a0 295EXPORT_SYMBOL(iwl_clear_stations_table);
bf85ea4f 296
c7de35cd 297void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 298{
299 u16 cw_min = 15;
300 u16 cw_max = 1023;
301 u8 aifs = 2;
302 u8 is_legacy = 0;
303 unsigned long flags;
304 int i;
305
306 spin_lock_irqsave(&priv->lock, flags);
307 priv->qos_data.qos_active = 0;
308
309 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
310 if (priv->qos_data.qos_enable)
311 priv->qos_data.qos_active = 1;
312 if (!(priv->active_rate & 0xfff0)) {
313 cw_min = 31;
314 is_legacy = 1;
315 }
316 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
317 if (priv->qos_data.qos_enable)
318 priv->qos_data.qos_active = 1;
319 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
320 cw_min = 31;
321 is_legacy = 1;
322 }
323
324 if (priv->qos_data.qos_active)
325 aifs = 3;
326
327 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
328 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
329 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
330 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
331 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
332
333 if (priv->qos_data.qos_active) {
334 i = 1;
335 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
336 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
337 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
338 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
339 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
340
341 i = 2;
342 priv->qos_data.def_qos_parm.ac[i].cw_min =
343 cpu_to_le16((cw_min + 1) / 2 - 1);
344 priv->qos_data.def_qos_parm.ac[i].cw_max =
345 cpu_to_le16(cw_max);
346 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
347 if (is_legacy)
348 priv->qos_data.def_qos_parm.ac[i].edca_txop =
349 cpu_to_le16(6016);
350 else
351 priv->qos_data.def_qos_parm.ac[i].edca_txop =
352 cpu_to_le16(3008);
353 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
354
355 i = 3;
356 priv->qos_data.def_qos_parm.ac[i].cw_min =
357 cpu_to_le16((cw_min + 1) / 4 - 1);
358 priv->qos_data.def_qos_parm.ac[i].cw_max =
359 cpu_to_le16((cw_max + 1) / 2 - 1);
360 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
361 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
362 if (is_legacy)
363 priv->qos_data.def_qos_parm.ac[i].edca_txop =
364 cpu_to_le16(3264);
365 else
366 priv->qos_data.def_qos_parm.ac[i].edca_txop =
367 cpu_to_le16(1504);
368 } else {
369 for (i = 1; i < 4; i++) {
370 priv->qos_data.def_qos_parm.ac[i].cw_min =
371 cpu_to_le16(cw_min);
372 priv->qos_data.def_qos_parm.ac[i].cw_max =
373 cpu_to_le16(cw_max);
374 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
375 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
376 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
377 }
378 }
379 IWL_DEBUG_QOS("set QoS to default \n");
380
381 spin_unlock_irqrestore(&priv->lock, flags);
382}
c7de35cd
RR		 383EXPORT_SYMBOL(iwl_reset_qos);
384
3ac7f146
TW		 385#define MAX_BIT_RATE_40_MHZ 0x96 /* 150 Mbps */
386#define MAX_BIT_RATE_20_MHZ 0x48 /* 72 Mbps */
c7de35cd
RR		 387static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
388 struct ieee80211_ht_info *ht_info,
389 enum ieee80211_band band)
390{
39130df3
RR		 391 u16 max_bit_rate = 0;
392 u8 rx_chains_num = priv->hw_params.rx_chains_num;
393 u8 tx_chains_num = priv->hw_params.tx_chains_num;
394
c7de35cd
RR		 395 ht_info->cap = 0;
396 memset(ht_info->supp_mcs_set, 0, 16);
397
398 ht_info->ht_supported = 1;
399
39130df3
RR		 400 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
401 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
402 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
403 (IWL_MIMO_PS_NONE << 2));
404
405 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd
RR		 406 if (priv->hw_params.fat_channel & BIT(band)) {
407 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
408 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
409 ht_info->supp_mcs_set[4] = 0x01;
39130df3 410 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 411 }
c7de35cd
RR		 412
413 if (priv->cfg->mod_params->amsdu_size_8K)
414 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
415
416 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
417 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
418
419 ht_info->supp_mcs_set[0] = 0xFF;
39130df3 420 if (rx_chains_num >= 2)
c7de35cd 421 ht_info->supp_mcs_set[1] = 0xFF;
39130df3 422 if (rx_chains_num >= 3)
c7de35cd 423 ht_info->supp_mcs_set[2] = 0xFF;
39130df3
RR		 424
425 /* Highest supported Rx data rate */
426 max_bit_rate *= rx_chains_num;
427 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
428 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
429
430 /* Tx MCS capabilities */
431 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
432 if (tx_chains_num != rx_chains_num) {
433 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
434 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
435 }
c7de35cd 436}
c7de35cd
RR		 437
438static void iwlcore_init_hw_rates(struct iwl_priv *priv,
439 struct ieee80211_rate *rates)
440{
441 int i;
442
443 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 444 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 445 rates[i].hw_value = i; /* Rate scaling will work on indexes */
446 rates[i].hw_value_short = i;
447 rates[i].flags = 0;
448 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
449 /*
450 * If CCK != 1M then set short preamble rate flag.
451 */
452 rates[i].flags |=
1826dcc0 453 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 454 0 : IEEE80211_RATE_SHORT_PREAMBLE;
455 }
456 }
457}
458
459/**
460 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
461 */
462static int iwlcore_init_geos(struct iwl_priv *priv)
463{
464 struct iwl_channel_info *ch;
465 struct ieee80211_supported_band *sband;
466 struct ieee80211_channel *channels;
467 struct ieee80211_channel *geo_ch;
468 struct ieee80211_rate *rates;
469 int i = 0;
470
471 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
472 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
473 IWL_DEBUG_INFO("Geography modes already initialized.\n");
474 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
475 return 0;
476 }
477
478 channels = kzalloc(sizeof(struct ieee80211_channel) *
479 priv->channel_count, GFP_KERNEL);
480 if (!channels)
481 return -ENOMEM;
482
483 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
484 GFP_KERNEL);
485 if (!rates) {
486 kfree(channels);
487 return -ENOMEM;
488 }
489
490 /* 5.2GHz channels start after the 2.4GHz channels */
491 sband = &priv->bands[IEEE80211_BAND_5GHZ];
492 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
493 /* just OFDM */
494 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
495 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
496
49779293
RR		 497 if (priv->cfg->sku & IWL_SKU_N)
498 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
499 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 500
501 sband = &priv->bands[IEEE80211_BAND_2GHZ];
502 sband->channels = channels;
503 /* OFDM & CCK */
504 sband->bitrates = rates;
505 sband->n_bitrates = IWL_RATE_COUNT;
506
49779293
RR		 507 if (priv->cfg->sku & IWL_SKU_N)
508 iwlcore_init_ht_hw_capab(priv, &sband->ht_info,
509 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 510
511 priv->ieee_channels = channels;
512 priv->ieee_rates = rates;
513
514 iwlcore_init_hw_rates(priv, rates);
515
516 for (i = 0; i < priv->channel_count; i++) {
517 ch = &priv->channel_info[i];
518
519 /* FIXME: might be removed if scan is OK */
520 if (!is_channel_valid(ch))
521 continue;
522
523 if (is_channel_a_band(ch))
524 sband = &priv->bands[IEEE80211_BAND_5GHZ];
525 else
526 sband = &priv->bands[IEEE80211_BAND_2GHZ];
527
528 geo_ch = &sband->channels[sband->n_channels++];
529
530 geo_ch->center_freq =
531 ieee80211_channel_to_frequency(ch->channel);
532 geo_ch->max_power = ch->max_power_avg;
533 geo_ch->max_antenna_gain = 0xff;
534 geo_ch->hw_value = ch->channel;
535
536 if (is_channel_valid(ch)) {
537 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
538 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
539
540 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
541 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
542
543 if (ch->flags & EEPROM_CHANNEL_RADAR)
544 geo_ch->flags |= IEEE80211_CHAN_RADAR;
545
963f5517 546 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 547
630fe9b6
TW		 548 if (ch->max_power_avg > priv->tx_power_channel_lmt)
549 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 550 } else {
551 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
552 }
553
554 /* Save flags for reg domain usage */
555 geo_ch->orig_flags = geo_ch->flags;
556
963f5517 557 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 558 ch->channel, geo_ch->center_freq,
559 is_channel_a_band(ch) ? "5.2" : "2.4",
560 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
561 "restricted" : "valid",
562 geo_ch->flags);
563 }
564
565 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
566 priv->cfg->sku & IWL_SKU_A) {
567 printk(KERN_INFO DRV_NAME
568 ": Incorrectly detected BG card as ABG. Please send "
569 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
570 priv->pci_dev->device, priv->pci_dev->subsystem_device);
571 priv->cfg->sku &= ~IWL_SKU_A;
572 }
573
574 printk(KERN_INFO DRV_NAME
575 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
576 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
577 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
578
c7de35cd
RR		 579
580 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
581
582 return 0;
583}
584
585/*
586 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
587 */
6ba87956 588static void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 589{
590 kfree(priv->ieee_channels);
591 kfree(priv->ieee_rates);
592 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
593}
c7de35cd 594
28a6b07a 595static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 596{
597 return !priv->current_ht_config.is_ht ||
598 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
28a6b07a 599 (priv->current_ht_config.supp_mcs_set[2] == 0));
c7de35cd 600}
963f5517 601
47c5196e
TW		 602static u8 iwl_is_channel_extension(struct iwl_priv *priv,
603 enum ieee80211_band band,
604 u16 channel, u8 extension_chan_offset)
605{
606 const struct iwl_channel_info *ch_info;
607
608 ch_info = iwl_get_channel_info(priv, band, channel);
609 if (!is_channel_valid(ch_info))
610 return 0;
611
963f5517
EG		 612 if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
613 return !(ch_info->fat_extension_channel &
614 IEEE80211_CHAN_NO_FAT_ABOVE);
615 else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
616 return !(ch_info->fat_extension_channel &
617 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 618
619 return 0;
620}
621
622u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
623 struct ieee80211_ht_info *sta_ht_inf)
624{
625 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
626
627 if ((!iwl_ht_conf->is_ht) ||
628 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
963f5517 629 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
47c5196e
TW		 630 return 0;
631
632 if (sta_ht_inf) {
633 if ((!sta_ht_inf->ht_supported) ||
634 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
635 return 0;
636 }
637
638 return iwl_is_channel_extension(priv, priv->band,
639 iwl_ht_conf->control_channel,
640 iwl_ht_conf->extension_chan_offset);
641}
642EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
643
644void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
645{
c1adf9fb 646 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 647 u32 val;
648
649 if (!ht_info->is_ht)
650 return;
651
652 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
653 if (iwl_is_fat_tx_allowed(priv, NULL))
654 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
655 else
656 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
657 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
658
659 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
660 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
661 le16_to_cpu(rxon->channel),
662 ht_info->control_channel);
47c5196e
TW		 663 return;
664 }
665
666 /* Note: control channel is opposite of extension channel */
667 switch (ht_info->extension_chan_offset) {
963f5517 668 case IEEE80211_HT_IE_CHA_SEC_ABOVE:
47c5196e
TW		 669 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
670 break;
963f5517 671 case IEEE80211_HT_IE_CHA_SEC_BELOW:
47c5196e
TW		 672 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
673 break;
963f5517 674 case IEEE80211_HT_IE_CHA_SEC_NONE:
47c5196e
TW		 675 default:
676 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
677 break;
678 }
679
680 val = ht_info->ht_protection;
681
682 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
683
684 iwl_set_rxon_chain(priv);
685
686 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
687 "rxon flags 0x%X operation mode :0x%X "
688 "extension channel offset 0x%x "
689 "control chan %d\n",
690 ht_info->supp_mcs_set[0],
691 ht_info->supp_mcs_set[1],
692 ht_info->supp_mcs_set[2],
693 le32_to_cpu(rxon->flags), ht_info->ht_protection,
694 ht_info->extension_chan_offset,
695 ht_info->control_channel);
696 return;
697}
698EXPORT_SYMBOL(iwl_set_rxon_ht);
699
c7de35cd
RR		 700/*
701 * Determine how many receiver/antenna chains to use.
702 * More provides better reception via diversity. Fewer saves power.
703 * MIMO (dual stream) requires at least 2, but works better with 3.
704 * This does not determine *which* chains to use, just how many.
705 */
28a6b07a 706static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 707{
28a6b07a
TW		 708 bool is_single = is_single_rx_stream(priv);
709 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 710
711 /* # of Rx chains to use when expecting MIMO. */
712 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
28a6b07a 713 return 2;
c7de35cd 714 else
28a6b07a
TW		 715 return 3;
716}
c7de35cd 717
28a6b07a
TW		 718static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
719{
720 int idle_cnt;
721 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 722 /* # Rx chains when idling and maybe trying to save power */
723 switch (priv->ps_mode) {
724 case IWL_MIMO_PS_STATIC:
725 case IWL_MIMO_PS_DYNAMIC:
28a6b07a 726 idle_cnt = (is_cam) ? 2 : 1;
c7de35cd
RR		 727 break;
728 case IWL_MIMO_PS_NONE:
28a6b07a 729 idle_cnt = (is_cam) ? active_cnt : 1;
c7de35cd 730 break;
28a6b07a 731 case IWL_MIMO_PS_INVALID:
c7de35cd 732 default:
28a6b07a
TW		 733 IWL_ERROR("invalide mimo ps mode %d\n", priv->ps_mode);
734 WARN_ON(1);
735 idle_cnt = -1;
c7de35cd
RR		 736 break;
737 }
28a6b07a 738 return idle_cnt;
c7de35cd
RR		 739}
740
741/**
742 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
743 *
744 * Selects how many and which Rx receivers/antennas/chains to use.
745 * This should not be used for scan command ... it puts data in wrong place.
746 */
747void iwl_set_rxon_chain(struct iwl_priv *priv)
748{
28a6b07a
TW		 749 bool is_single = is_single_rx_stream(priv);
750 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
751 u8 idle_rx_cnt, active_rx_cnt;
752 u16 rx_chain;
c7de35cd
RR		 753
754 /* Tell uCode which antennas are actually connected.
755 * Before first association, we assume all antennas are connected.
756 * Just after first association, iwl_chain_noise_calibration()
757 * checks which antennas actually *are* connected. */
28a6b07a 758 rx_chain = priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 759
760 /* How many receivers should we use? */
28a6b07a
TW		 761 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
762 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
763
764 /* correct rx chain count accoridng hw settings */
765 if (priv->hw_params.rx_chains_num < active_rx_cnt)
766 active_rx_cnt = priv->hw_params.rx_chains_num;
767
768 if (priv->hw_params.rx_chains_num < idle_rx_cnt)
769 idle_rx_cnt = priv->hw_params.rx_chains_num;
770
771 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
772 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
773
774 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
775
776 if (!is_single && (active_rx_cnt >= 2) && is_cam)
c7de35cd
RR		 777 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
778 else
779 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
780
28a6b07a
TW		 781 IWL_DEBUG_ASSOC("rx_chain=0x%Xi active=%d idle=%d\n",
782 priv->staging_rxon.rx_chain,
783 active_rx_cnt, idle_rx_cnt);
784
785 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
786 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 787}
788EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 789
790/**
791 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
792 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
793 * @channel: Any channel valid for the requested phymode
794
795 * In addition to setting the staging RXON, priv->phymode is also set.
796 *
797 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
798 * in the staging RXON flag structure based on the phymode
799 */
c7de35cd 800int iwl_set_rxon_channel(struct iwl_priv *priv,
bf85ea4f
AK		 801 enum ieee80211_band band,
802 u16 channel)
803{
8622e705 804 if (!iwl_get_channel_info(priv, band, channel)) {
bf85ea4f
AK		 805 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
806 channel, band);
807 return -EINVAL;
808 }
809
810 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
811 (priv->band == band))
812 return 0;
813
814 priv->staging_rxon.channel = cpu_to_le16(channel);
815 if (band == IEEE80211_BAND_5GHZ)
816 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
817 else
818 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
819
820 priv->band = band;
821
822 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
823
824 return 0;
825}
c7de35cd 826EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 827
6ba87956 828int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 829{
6ba87956 830 int ret;
bf85ea4f 831 struct ieee80211_hw *hw = priv->hw;
e227ceac 832 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 833
566bfe5a 834 /* Tell mac80211 our characteristics */
605a0bd6 835 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 836 IEEE80211_HW_NOISE_DBM;
bf85ea4f
AK		 837 /* Default value; 4 EDCA QOS priorities */
838 hw->queues = 4;
49779293
RR		 839 /* queues to support 11n aggregation */
840 if (priv->cfg->sku & IWL_SKU_N)
9f17b318 841 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
6ba87956
TW		 842
843 hw->conf.beacon_int = 100;
b5d7be5e 844 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 845
846 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
847 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
848 &priv->bands[IEEE80211_BAND_2GHZ];
849 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
850 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
851 &priv->bands[IEEE80211_BAND_5GHZ];
852
853 ret = ieee80211_register_hw(priv->hw);
854 if (ret) {
855 IWL_ERROR("Failed to register hw (error %d)\n", ret);
856 return ret;
857 }
858 priv->mac80211_registered = 1;
859
860 return 0;
bf85ea4f 861}
6ba87956 862EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 863
da154e30
RR		 864int iwl_set_hw_params(struct iwl_priv *priv)
865{
866 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
867 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
868 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
869 if (priv->cfg->mod_params->amsdu_size_8K)
870 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
871 else
872 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
873 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
874
49779293
RR		 875 if (priv->cfg->mod_params->disable_11n)
876 priv->cfg->sku &= ~IWL_SKU_N;
877
da154e30
RR		 878 /* Device-specific setup */
879 return priv->cfg->ops->lib->set_hw_params(priv);
880}
881EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 882
883int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 884{
885 int ret;
c7de35cd
RR		 886
887 priv->retry_rate = 1;
888 priv->ibss_beacon = NULL;
889
890 spin_lock_init(&priv->lock);
891 spin_lock_init(&priv->power_data.lock);
892 spin_lock_init(&priv->sta_lock);
893 spin_lock_init(&priv->hcmd_lock);
894 spin_lock_init(&priv->lq_mngr.lock);
895
c7de35cd
RR		 896 INIT_LIST_HEAD(&priv->free_frames);
897
898 mutex_init(&priv->mutex);
899
900 /* Clear the driver's (not device's) station table */
37deb2a0 901 iwl_clear_stations_table(priv);
c7de35cd
RR		 902
903 priv->data_retry_limit = -1;
904 priv->ieee_channels = NULL;
905 priv->ieee_rates = NULL;
906 priv->band = IEEE80211_BAND_2GHZ;
907
908 priv->iw_mode = IEEE80211_IF_TYPE_STA;
909
910 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
911 priv->ps_mode = IWL_MIMO_PS_NONE;
912
913 /* Choose which receivers/antennas to use */
914 iwl_set_rxon_chain(priv);
f53696de 915 iwl_init_scan_params(priv);
c7de35cd 916
6ba87956
TW		 917 if (priv->cfg->mod_params->enable_qos)
918 priv->qos_data.qos_enable = 1;
919
c7de35cd
RR		 920 iwl_reset_qos(priv);
921
922 priv->qos_data.qos_active = 0;
923 priv->qos_data.qos_cap.val = 0;
924
925 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
926
927 priv->rates_mask = IWL_RATES_MASK;
928 /* If power management is turned on, default to AC mode */
929 priv->power_mode = IWL_POWER_AC;
630fe9b6 930 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 931
932 ret = iwl_init_channel_map(priv);
933 if (ret) {
934 IWL_ERROR("initializing regulatory failed: %d\n", ret);
935 goto err;
936 }
937
938 ret = iwlcore_init_geos(priv);
939 if (ret) {
940 IWL_ERROR("initializing geos failed: %d\n", ret);
941 goto err_free_channel_map;
942 }
943
c7de35cd
RR		 944 return 0;
945
c7de35cd
RR		 946err_free_channel_map:
947 iwl_free_channel_map(priv);
948err:
949 return ret;
950}
6ba87956 951EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 952
7c616cba
TW		 953void iwl_free_calib_results(struct iwl_priv *priv)
954{
955 kfree(priv->calib_results.lo_res);
956 priv->calib_results.lo_res = NULL;
957 priv->calib_results.lo_res_len = 0;
958
959 kfree(priv->calib_results.tx_iq_res);
960 priv->calib_results.tx_iq_res = NULL;
961 priv->calib_results.tx_iq_res_len = 0;
962
963 kfree(priv->calib_results.tx_iq_perd_res);
964 priv->calib_results.tx_iq_perd_res = NULL;
965 priv->calib_results.tx_iq_perd_res_len = 0;
966}
967EXPORT_SYMBOL(iwl_free_calib_results);
6ba87956 968
630fe9b6
TW		 969int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
970{
971 int ret = 0;
972 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
973 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
974 priv->tx_power_user_lmt);
975 return -EINVAL;
976 }
977
978 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
979 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
980 priv->tx_power_user_lmt);
981 return -EINVAL;
982 }
983
984 if (priv->tx_power_user_lmt != tx_power)
985 force = true;
986
987 priv->tx_power_user_lmt = tx_power;
988
989 if (force && priv->cfg->ops->lib->send_tx_power)
990 ret = priv->cfg->ops->lib->send_tx_power(priv);
991
992 return ret;
993}
994EXPORT_SYMBOL(iwl_set_tx_power);
995
996
6ba87956 997void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 998{
7c616cba 999 iwl_free_calib_results(priv);
6ba87956
TW		 1000 iwlcore_free_geos(priv);
1001 iwl_free_channel_map(priv);
261415f7 1002 kfree(priv->scan);
bf85ea4f 1003}
6ba87956 1004EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1005
49ea8596
EG		 1006int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1007{
1008 u32 stat_flags = 0;
1009 struct iwl_host_cmd cmd = {
1010 .id = REPLY_STATISTICS_CMD,
1011 .meta.flags = flags,
1012 .len = sizeof(stat_flags),
1013 .data = (u8 *) &stat_flags,
1014 };
1015 return iwl_send_cmd(priv, &cmd);
1016}
1017EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1018
b0692f2f
EG		 1019/**
1020 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1021 * using sample data 100 bytes apart. If these sample points are good,
1022 * it's a pretty good bet that everything between them is good, too.
1023 */
1024static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1025{
1026 u32 val;
1027 int ret = 0;
1028 u32 errcnt = 0;
1029 u32 i;
1030
1031 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1032
1033 ret = iwl_grab_nic_access(priv);
1034 if (ret)
1035 return ret;
1036
1037 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1038 /* read data comes through single port, auto-incr addr */
1039 /* NOTE: Use the debugless read so we don't flood kernel log
1040 * if IWL_DL_IO is set */
1041 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1042 i + RTC_INST_LOWER_BOUND);
1043 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1044 if (val != le32_to_cpu(*image)) {
1045 ret = -EIO;
1046 errcnt++;
1047 if (errcnt >= 3)
1048 break;
1049 }
1050 }
1051
1052 iwl_release_nic_access(priv);
1053
1054 return ret;
1055}
1056
1057/**
1058 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1059 * looking at all data.
1060 */
1061static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1062 u32 len)
1063{
1064 u32 val;
1065 u32 save_len = len;
1066 int ret = 0;
1067 u32 errcnt;
1068
1069 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1070
1071 ret = iwl_grab_nic_access(priv);
1072 if (ret)
1073 return ret;
1074
1075 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1076
1077 errcnt = 0;
1078 for (; len > 0; len -= sizeof(u32), image++) {
1079 /* read data comes through single port, auto-incr addr */
1080 /* NOTE: Use the debugless read so we don't flood kernel log
1081 * if IWL_DL_IO is set */
1082 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1083 if (val != le32_to_cpu(*image)) {
1084 IWL_ERROR("uCode INST section is invalid at "
1085 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1086 save_len - len, val, le32_to_cpu(*image));
1087 ret = -EIO;
1088 errcnt++;
1089 if (errcnt >= 20)
1090 break;
1091 }
1092 }
1093
1094 iwl_release_nic_access(priv);
1095
1096 if (!errcnt)
1097 IWL_DEBUG_INFO
1098 ("ucode image in INSTRUCTION memory is good\n");
1099
1100 return ret;
1101}
1102
1103/**
1104 * iwl_verify_ucode - determine which instruction image is in SRAM,
1105 * and verify its contents
1106 */
1107int iwl_verify_ucode(struct iwl_priv *priv)
1108{
1109 __le32 *image;
1110 u32 len;
1111 int ret;
1112
1113 /* Try bootstrap */
1114 image = (__le32 *)priv->ucode_boot.v_addr;
1115 len = priv->ucode_boot.len;
1116 ret = iwlcore_verify_inst_sparse(priv, image, len);
1117 if (!ret) {
1118 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1119 return 0;
1120 }
1121
1122 /* Try initialize */
1123 image = (__le32 *)priv->ucode_init.v_addr;
1124 len = priv->ucode_init.len;
1125 ret = iwlcore_verify_inst_sparse(priv, image, len);
1126 if (!ret) {
1127 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1128 return 0;
1129 }
1130
1131 /* Try runtime/protocol */
1132 image = (__le32 *)priv->ucode_code.v_addr;
1133 len = priv->ucode_code.len;
1134 ret = iwlcore_verify_inst_sparse(priv, image, len);
1135 if (!ret) {
1136 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1137 return 0;
1138 }
1139
1140 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1141
1142 /* Since nothing seems to match, show first several data entries in
1143 * instruction SRAM, so maybe visual inspection will give a clue.
1144 * Selection of bootstrap image (vs. other images) is arbitrary. */
1145 image = (__le32 *)priv->ucode_boot.v_addr;
1146 len = priv->ucode_boot.len;
1147 ret = iwl_verify_inst_full(priv, image, len);
1148
1149 return ret;
1150}
1151EXPORT_SYMBOL(iwl_verify_ucode);
1152
189a2b59 1153
ede0cba4
EK		 1154static const char *desc_lookup(int i)
1155{
1156 switch (i) {
1157 case 1:
1158 return "FAIL";
1159 case 2:
1160 return "BAD_PARAM";
1161 case 3:
1162 return "BAD_CHECKSUM";
1163 case 4:
1164 return "NMI_INTERRUPT";
1165 case 5:
1166 return "SYSASSERT";
1167 case 6:
1168 return "FATAL_ERROR";
1169 }
1170
1171 return "UNKNOWN";
1172}
1173
1174#define ERROR_START_OFFSET (1 * sizeof(u32))
1175#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1176
1177void iwl_dump_nic_error_log(struct iwl_priv *priv)
1178{
1179 u32 data2, line;
1180 u32 desc, time, count, base, data1;
1181 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1182 int ret;
ede0cba4 1183
e1dfc085
GG		 1184 if (priv->ucode_type == UCODE_INIT)
1185 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1186 else
1187 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1188
1189 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1190 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1191 return;
1192 }
1193
e1dfc085
GG		 1194 ret = iwl_grab_nic_access(priv);
1195 if (ret) {
ede0cba4
EK		 1196 IWL_WARNING("Can not read from adapter at this time.\n");
1197 return;
1198 }
1199
1200 count = iwl_read_targ_mem(priv, base);
1201
1202 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1203 IWL_ERROR("Start IWL Error Log Dump:\n");
1204 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1205 }
1206
1207 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1208 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1209 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1210 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1211 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1212 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1213 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1214 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1215 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1216
1217 IWL_ERROR("Desc Time "
1218 "data1 data2 line\n");
1219 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1220 desc_lookup(desc), desc, time, data1, data2, line);
1221 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1222 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1223 ilink1, ilink2);
1224
1225 iwl_release_nic_access(priv);
1226}
1227EXPORT_SYMBOL(iwl_dump_nic_error_log);
1228
189a2b59
EK		 1229#define EVENT_START_OFFSET (4 * sizeof(u32))
1230
1231/**
1232 * iwl_print_event_log - Dump error event log to syslog
1233 *
1234 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1235 */
1236void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1237 u32 num_events, u32 mode)
1238{
1239 u32 i;
1240 u32 base; /* SRAM byte address of event log header */
1241 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1242 u32 ptr; /* SRAM byte address of log data */
1243 u32 ev, time, data; /* event log data */
1244
1245 if (num_events == 0)
1246 return;
e1dfc085
GG		 1247 if (priv->ucode_type == UCODE_INIT)
1248 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1249 else
1250 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1251
1252 if (mode == 0)
1253 event_size = 2 * sizeof(u32);
1254 else
1255 event_size = 3 * sizeof(u32);
1256
1257 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1258
1259 /* "time" is actually "data" for mode 0 (no timestamp).
1260 * place event id # at far right for easier visual parsing. */
1261 for (i = 0; i < num_events; i++) {
1262 ev = iwl_read_targ_mem(priv, ptr);
1263 ptr += sizeof(u32);
1264 time = iwl_read_targ_mem(priv, ptr);
1265 ptr += sizeof(u32);
77c5d08e
TW		 1266 if (mode == 0) {
1267 /* data, ev */
1268 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1269 } else {
189a2b59
EK		 1270 data = iwl_read_targ_mem(priv, ptr);
1271 ptr += sizeof(u32);
77c5d08e
TW		 1272 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1273 time, data, ev);
189a2b59
EK		 1274 }
1275 }
1276}
1277EXPORT_SYMBOL(iwl_print_event_log);
1278
1279
1280void iwl_dump_nic_event_log(struct iwl_priv *priv)
1281{
e1dfc085 1282 int ret;
189a2b59
EK		 1283 u32 base; /* SRAM byte address of event log header */
1284 u32 capacity; /* event log capacity in # entries */
1285 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1286 u32 num_wraps; /* # times uCode wrapped to top of log */
1287 u32 next_entry; /* index of next entry to be written by uCode */
1288 u32 size; /* # entries that we'll print */
1289
e1dfc085
GG		 1290 if (priv->ucode_type == UCODE_INIT)
1291 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1292 else
1293 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1294
189a2b59
EK		 1295 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1296 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1297 return;
1298 }
1299
e1dfc085
GG		 1300 ret = iwl_grab_nic_access(priv);
1301 if (ret) {
189a2b59
EK		 1302 IWL_WARNING("Can not read from adapter at this time.\n");
1303 return;
1304 }
1305
1306 /* event log header */
1307 capacity = iwl_read_targ_mem(priv, base);
1308 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1309 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1310 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1311
1312 size = num_wraps ? capacity : next_entry;
1313
1314 /* bail out if nothing in log */
1315 if (size == 0) {
1316 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1317 iwl_release_nic_access(priv);
1318 return;
1319 }
1320
1321 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1322 size, num_wraps);
1323
1324 /* if uCode has wrapped back to top of log, start at the oldest entry,
1325 * i.e the next one that uCode would fill. */
1326 if (num_wraps)
1327 iwl_print_event_log(priv, next_entry,
1328 capacity - next_entry, mode);
1329 /* (then/else) start at top of log */
1330 iwl_print_event_log(priv, 0, next_entry, mode);
1331
1332 iwl_release_nic_access(priv);
1333}
1334EXPORT_SYMBOL(iwl_dump_nic_event_log);
1335
47f4a587
EG		 1336void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1337{
1338 struct iwl_ct_kill_config cmd;
1339 unsigned long flags;
1340 int ret = 0;
1341
1342 spin_lock_irqsave(&priv->lock, flags);
1343 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1344 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1345 spin_unlock_irqrestore(&priv->lock, flags);
1346
1347 cmd.critical_temperature_R =
1348 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1349
47f4a587
EG		 1350 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1351 sizeof(cmd), &cmd);
1352 if (ret)
1353 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1354 else
1355 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1356 "critical temperature is %d\n",
1357 cmd.critical_temperature_R);
1358}
1359EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f
EG		 1360
1361/*
1362 * CARD_STATE_CMD
1363 *
1364 * Use: Sets the device's internal card state to enable, disable, or halt
1365 *
1366 * When in the 'enable' state the card operates as normal.
1367 * When in the 'disable' state, the card enters into a low power mode.
1368 * When in the 'halt' state, the card is shut down and must be fully
1369 * restarted to come back on.
1370 */
1371static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1372{
1373 struct iwl_host_cmd cmd = {
1374 .id = REPLY_CARD_STATE_CMD,
1375 .len = sizeof(u32),
1376 .data = &flags,
1377 .meta.flags = meta_flag,
1378 };
1379
1380 return iwl_send_cmd(priv, &cmd);
1381}
1382
1383void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1384{
1385 unsigned long flags;
1386
1387 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1388 return;
1389
1390 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1391
1392 iwl_scan_cancel(priv);
1393 /* FIXME: This is a workaround for AP */
1394 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
1395 spin_lock_irqsave(&priv->lock, flags);
1396 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1397 CSR_UCODE_SW_BIT_RFKILL);
1398 spin_unlock_irqrestore(&priv->lock, flags);
1399 /* call the host command only if no hw rf-kill set */
1400 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1401 iwl_is_ready(priv))
1402 iwl_send_card_state(priv,
1403 CARD_STATE_CMD_DISABLE, 0);
1404 set_bit(STATUS_RF_KILL_SW, &priv->status);
1405 /* make sure mac80211 stop sending Tx frame */
1406 if (priv->mac80211_registered)
1407 ieee80211_stop_queues(priv->hw);
1408 }
1409}
1410EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1411
1412int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1413{
1414 unsigned long flags;
1415
1416 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1417 return 0;
1418
1419 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1420
1421 spin_lock_irqsave(&priv->lock, flags);
1422 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1423
a9efa652
EG		 1424 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1425 * notification where it will clear SW rfkill status.
1426 * Setting it here would break the handler. Only if the
1427 * interface is down we can set here since we don't
1428 * receive any further notification.
1429 */
1430 if (!priv->is_open)
1431 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 1432 spin_unlock_irqrestore(&priv->lock, flags);
1433
1434 /* wake up ucode */
1435 msleep(10);
1436
1437 spin_lock_irqsave(&priv->lock, flags);
1438 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1439 if (!iwl_grab_nic_access(priv))
1440 iwl_release_nic_access(priv);
1441 spin_unlock_irqrestore(&priv->lock, flags);
1442
1443 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1444 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1445 "disabled by HW switch\n");
1446 return 0;
1447 }
1448
a9efa652
EG		 1449 /* If the driver is already loaded, it will receive
1450 * CARD_STATE_NOTIFICATION notifications and the handler will
1451 * call restart to reload the driver.
1452 */
14a08a7f
EG		 1453 return 1;
1454}
1455EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
Linux kernel - Deliverables
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