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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
901069c7 | 5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
d43c36dc | 32 | #include <linux/sched.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
1d0a082d | 34 | #include <net/mac80211.h> |
df48c323 | 35 | |
6bc913bd | 36 | #include "iwl-eeprom.h" |
3e0d4cb1 | 37 | #include "iwl-dev.h" /* FIXME: remove */ |
19335774 | 38 | #include "iwl-debug.h" |
df48c323 | 39 | #include "iwl-core.h" |
b661c819 | 40 | #include "iwl-io.h" |
5da4b55f | 41 | #include "iwl-power.h" |
83dde8c9 | 42 | #include "iwl-sta.h" |
ef850d7c | 43 | #include "iwl-helpers.h" |
9d143e9a | 44 | #include "iwl-agn.h" |
bdfbf092 | 45 | #include "iwl-trans.h" |
df48c323 | 46 | |
a562a9dd | 47 | u32 iwl_debug_level; |
a562a9dd | 48 | |
57bd1bea | 49 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
57bd1bea | 50 | |
d9fe60de JB |
51 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
52 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
c7de35cd | 53 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
d9fe60de | 54 | struct ieee80211_sta_ht_cap *ht_info, |
c7de35cd RR |
55 | enum ieee80211_band band) |
56 | { | |
39130df3 RR |
57 | u16 max_bit_rate = 0; |
58 | u8 rx_chains_num = priv->hw_params.rx_chains_num; | |
59 | u8 tx_chains_num = priv->hw_params.tx_chains_num; | |
60 | ||
c7de35cd | 61 | ht_info->cap = 0; |
d9fe60de | 62 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
c7de35cd | 63 | |
d9fe60de | 64 | ht_info->ht_supported = true; |
c7de35cd | 65 | |
7cb1b088 WYG |
66 | if (priv->cfg->ht_params && |
67 | priv->cfg->ht_params->ht_greenfield_support) | |
b261793d | 68 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; |
d9fe60de | 69 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; |
39130df3 | 70 | max_bit_rate = MAX_BIT_RATE_20_MHZ; |
7aafef1c | 71 | if (priv->hw_params.ht40_channel & BIT(band)) { |
d9fe60de JB |
72 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
73 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
74 | ht_info->mcs.rx_mask[4] = 0x01; | |
39130df3 | 75 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 76 | } |
c7de35cd | 77 | |
9d143e9a | 78 | if (iwlagn_mod_params.amsdu_size_8K) |
d9fe60de | 79 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
c7de35cd RR |
80 | |
81 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
7cb1b088 WYG |
82 | if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_factor) |
83 | ht_info->ampdu_factor = priv->cfg->bt_params->ampdu_factor; | |
c7de35cd | 84 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; |
7cb1b088 WYG |
85 | if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_density) |
86 | ht_info->ampdu_density = priv->cfg->bt_params->ampdu_density; | |
c7de35cd | 87 | |
d9fe60de | 88 | ht_info->mcs.rx_mask[0] = 0xFF; |
39130df3 | 89 | if (rx_chains_num >= 2) |
d9fe60de | 90 | ht_info->mcs.rx_mask[1] = 0xFF; |
39130df3 | 91 | if (rx_chains_num >= 3) |
d9fe60de | 92 | ht_info->mcs.rx_mask[2] = 0xFF; |
39130df3 RR |
93 | |
94 | /* Highest supported Rx data rate */ | |
95 | max_bit_rate *= rx_chains_num; | |
d9fe60de JB |
96 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
97 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
39130df3 RR |
98 | |
99 | /* Tx MCS capabilities */ | |
d9fe60de | 100 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
39130df3 | 101 | if (tx_chains_num != rx_chains_num) { |
d9fe60de JB |
102 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
103 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << | |
104 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
39130df3 | 105 | } |
c7de35cd | 106 | } |
c7de35cd | 107 | |
c7de35cd RR |
108 | /** |
109 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom | |
110 | */ | |
534166de | 111 | int iwlcore_init_geos(struct iwl_priv *priv) |
c7de35cd RR |
112 | { |
113 | struct iwl_channel_info *ch; | |
114 | struct ieee80211_supported_band *sband; | |
115 | struct ieee80211_channel *channels; | |
116 | struct ieee80211_channel *geo_ch; | |
117 | struct ieee80211_rate *rates; | |
118 | int i = 0; | |
75d80cad | 119 | s8 max_tx_power = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
c7de35cd RR |
120 | |
121 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
122 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
e1623446 | 123 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
c7de35cd RR |
124 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
125 | return 0; | |
126 | } | |
127 | ||
128 | channels = kzalloc(sizeof(struct ieee80211_channel) * | |
129 | priv->channel_count, GFP_KERNEL); | |
130 | if (!channels) | |
131 | return -ENOMEM; | |
132 | ||
5027309b | 133 | rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY), |
c7de35cd RR |
134 | GFP_KERNEL); |
135 | if (!rates) { | |
136 | kfree(channels); | |
137 | return -ENOMEM; | |
138 | } | |
139 | ||
140 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
141 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
142 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
143 | /* just OFDM */ | |
144 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
5027309b | 145 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE; |
c7de35cd | 146 | |
88950758 | 147 | if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE) |
d9fe60de | 148 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 149 | IEEE80211_BAND_5GHZ); |
c7de35cd RR |
150 | |
151 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
152 | sband->channels = channels; | |
153 | /* OFDM & CCK */ | |
154 | sband->bitrates = rates; | |
5027309b | 155 | sband->n_bitrates = IWL_RATE_COUNT_LEGACY; |
c7de35cd | 156 | |
88950758 | 157 | if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE) |
d9fe60de | 158 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 159 | IEEE80211_BAND_2GHZ); |
c7de35cd RR |
160 | |
161 | priv->ieee_channels = channels; | |
162 | priv->ieee_rates = rates; | |
163 | ||
c7de35cd RR |
164 | for (i = 0; i < priv->channel_count; i++) { |
165 | ch = &priv->channel_info[i]; | |
166 | ||
167 | /* FIXME: might be removed if scan is OK */ | |
168 | if (!is_channel_valid(ch)) | |
169 | continue; | |
170 | ||
5a3a0352 | 171 | sband = &priv->bands[ch->band]; |
c7de35cd RR |
172 | |
173 | geo_ch = &sband->channels[sband->n_channels++]; | |
174 | ||
175 | geo_ch->center_freq = | |
5a3a0352 | 176 | ieee80211_channel_to_frequency(ch->channel, ch->band); |
c7de35cd RR |
177 | geo_ch->max_power = ch->max_power_avg; |
178 | geo_ch->max_antenna_gain = 0xff; | |
179 | geo_ch->hw_value = ch->channel; | |
180 | ||
181 | if (is_channel_valid(ch)) { | |
182 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
183 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
184 | ||
185 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
186 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
187 | ||
188 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
189 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
190 | ||
7aafef1c | 191 | geo_ch->flags |= ch->ht40_extension_channel; |
4d38c2e8 | 192 | |
75d80cad SG |
193 | if (ch->max_power_avg > max_tx_power) |
194 | max_tx_power = ch->max_power_avg; | |
c7de35cd RR |
195 | } else { |
196 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
197 | } | |
198 | ||
e1623446 | 199 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
200 | ch->channel, geo_ch->center_freq, |
201 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
202 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
203 | "restricted" : "valid", | |
204 | geo_ch->flags); | |
205 | } | |
206 | ||
75d80cad SG |
207 | priv->tx_power_device_lmt = max_tx_power; |
208 | priv->tx_power_user_lmt = max_tx_power; | |
209 | priv->tx_power_next = max_tx_power; | |
210 | ||
c7de35cd | 211 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
88950758 | 212 | priv->cfg->sku & EEPROM_SKU_CAP_BAND_52GHZ) { |
19707bac | 213 | char buf[32]; |
d5934110 | 214 | bus_get_hw_id(priv->bus, buf, sizeof(buf)); |
978785a3 | 215 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
19707bac | 216 | "Please send your %s to maintainer.\n", buf); |
88950758 | 217 | priv->cfg->sku &= ~EEPROM_SKU_CAP_BAND_52GHZ; |
c7de35cd RR |
218 | } |
219 | ||
978785a3 | 220 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
a3139c59 SO |
221 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
222 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
c7de35cd RR |
223 | |
224 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | /* | |
230 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos | |
231 | */ | |
534166de | 232 | void iwlcore_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
233 | { |
234 | kfree(priv->ieee_channels); | |
235 | kfree(priv->ieee_rates); | |
236 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
237 | } | |
c7de35cd | 238 | |
7e6a5886 JB |
239 | static bool iwl_is_channel_extension(struct iwl_priv *priv, |
240 | enum ieee80211_band band, | |
241 | u16 channel, u8 extension_chan_offset) | |
47c5196e TW |
242 | { |
243 | const struct iwl_channel_info *ch_info; | |
244 | ||
245 | ch_info = iwl_get_channel_info(priv, band, channel); | |
246 | if (!is_channel_valid(ch_info)) | |
7e6a5886 | 247 | return false; |
47c5196e | 248 | |
d9fe60de | 249 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
7aafef1c | 250 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 251 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 252 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
7aafef1c | 253 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 254 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e | 255 | |
7e6a5886 | 256 | return false; |
47c5196e TW |
257 | } |
258 | ||
7e6a5886 JB |
259 | bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
260 | struct iwl_rxon_context *ctx, | |
261 | struct ieee80211_sta_ht_cap *ht_cap) | |
47c5196e | 262 | { |
7e6a5886 JB |
263 | if (!ctx->ht.enabled || !ctx->ht.is_40mhz) |
264 | return false; | |
47c5196e | 265 | |
7e6a5886 JB |
266 | /* |
267 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
a2b0f02e WYG |
268 | * the bit will not set if it is pure 40MHz case |
269 | */ | |
7e6a5886 JB |
270 | if (ht_cap && !ht_cap->ht_supported) |
271 | return false; | |
272 | ||
d73e4923 | 273 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1e4247d4 | 274 | if (priv->disable_ht40) |
7e6a5886 | 275 | return false; |
1e4247d4 | 276 | #endif |
7e6a5886 | 277 | |
611d3eb7 | 278 | return iwl_is_channel_extension(priv, priv->band, |
246ed355 | 279 | le16_to_cpu(ctx->staging.channel), |
7e6a5886 | 280 | ctx->ht.extension_chan_offset); |
47c5196e | 281 | } |
47c5196e | 282 | |
2c2f3b33 TW |
283 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
284 | { | |
ea196fdb JB |
285 | u16 new_val; |
286 | u16 beacon_factor; | |
287 | ||
288 | /* | |
289 | * If mac80211 hasn't given us a beacon interval, program | |
290 | * the default into the device (not checking this here | |
291 | * would cause the adjustment below to return the maximum | |
292 | * value, which may break PAN.) | |
293 | */ | |
294 | if (!beacon_val) | |
295 | return DEFAULT_BEACON_INTERVAL; | |
296 | ||
297 | /* | |
298 | * If the beacon interval we obtained from the peer | |
299 | * is too large, we'll have to wake up more often | |
300 | * (and in IBSS case, we'll beacon too much) | |
301 | * | |
302 | * For example, if max_beacon_val is 4096, and the | |
303 | * requested beacon interval is 7000, we'll have to | |
304 | * use 3500 to be able to wake up on the beacons. | |
305 | * | |
306 | * This could badly influence beacon detection stats. | |
307 | */ | |
2c2f3b33 TW |
308 | |
309 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
310 | new_val = beacon_val / beacon_factor; | |
311 | ||
312 | if (!new_val) | |
313 | new_val = max_beacon_val; | |
314 | ||
315 | return new_val; | |
316 | } | |
317 | ||
47313e34 | 318 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
2c2f3b33 TW |
319 | { |
320 | u64 tsf; | |
321 | s32 interval_tm, rem; | |
2c2f3b33 TW |
322 | struct ieee80211_conf *conf = NULL; |
323 | u16 beacon_int; | |
47313e34 | 324 | struct ieee80211_vif *vif = ctx->vif; |
2c2f3b33 TW |
325 | |
326 | conf = ieee80211_get_hw_conf(priv->hw); | |
327 | ||
948f5a2f JB |
328 | lockdep_assert_held(&priv->mutex); |
329 | ||
246ed355 | 330 | memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
948f5a2f | 331 | |
246ed355 JB |
332 | ctx->timing.timestamp = cpu_to_le64(priv->timestamp); |
333 | ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
2c2f3b33 | 334 | |
47313e34 | 335 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; |
2c2f3b33 | 336 | |
47313e34 JB |
337 | /* |
338 | * TODO: For IBSS we need to get atim_window from mac80211, | |
339 | * for now just always use 0 | |
340 | */ | |
341 | ctx->timing.atim_window = 0; | |
2c2f3b33 | 342 | |
bde4530e | 343 | if (ctx->ctxid == IWL_RXON_CTX_PAN && |
f1f270b2 JB |
344 | (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) && |
345 | iwl_is_associated(priv, IWL_RXON_CTX_BSS) && | |
346 | priv->contexts[IWL_RXON_CTX_BSS].vif && | |
347 | priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) { | |
bde4530e JB |
348 | ctx->timing.beacon_interval = |
349 | priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; | |
350 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
f1f270b2 JB |
351 | } else if (ctx->ctxid == IWL_RXON_CTX_BSS && |
352 | iwl_is_associated(priv, IWL_RXON_CTX_PAN) && | |
353 | priv->contexts[IWL_RXON_CTX_PAN].vif && | |
354 | priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int && | |
355 | (!iwl_is_associated_ctx(ctx) || !ctx->vif || | |
356 | !ctx->vif->bss_conf.beacon_int)) { | |
357 | ctx->timing.beacon_interval = | |
358 | priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; | |
359 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
bde4530e JB |
360 | } else { |
361 | beacon_int = iwl_adjust_beacon_interval(beacon_int, | |
f8525e55 | 362 | priv->hw_params.max_beacon_itrvl * TIME_UNIT); |
bde4530e JB |
363 | ctx->timing.beacon_interval = cpu_to_le16(beacon_int); |
364 | } | |
2c2f3b33 TW |
365 | |
366 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ | |
f8525e55 | 367 | interval_tm = beacon_int * TIME_UNIT; |
2c2f3b33 | 368 | rem = do_div(tsf, interval_tm); |
246ed355 | 369 | ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
2c2f3b33 | 370 | |
47313e34 | 371 | ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; |
2491fa42 | 372 | |
2c2f3b33 TW |
373 | IWL_DEBUG_ASSOC(priv, |
374 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
246ed355 JB |
375 | le16_to_cpu(ctx->timing.beacon_interval), |
376 | le32_to_cpu(ctx->timing.beacon_init_val), | |
377 | le16_to_cpu(ctx->timing.atim_window)); | |
948f5a2f | 378 | |
41c50542 | 379 | return trans_send_cmd_pdu(&priv->trans, ctx->rxon_timing_cmd, |
e419d62d | 380 | CMD_SYNC, sizeof(ctx->timing), &ctx->timing); |
2c2f3b33 | 381 | } |
2c2f3b33 | 382 | |
246ed355 JB |
383 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx, |
384 | int hw_decrypt) | |
8ccde88a | 385 | { |
246ed355 | 386 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a SO |
387 | |
388 | if (hw_decrypt) | |
389 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
390 | else | |
391 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
392 | ||
393 | } | |
8ccde88a | 394 | |
dacefedb | 395 | /* validate RXON structure is valid */ |
246ed355 | 396 | int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
8ccde88a | 397 | { |
246ed355 | 398 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
c914ac26 | 399 | u32 errors = 0; |
8ccde88a SO |
400 | |
401 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
dacefedb JB |
402 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { |
403 | IWL_WARN(priv, "check 2.4G: wrong narrow\n"); | |
c914ac26 | 404 | errors |= BIT(0); |
dacefedb JB |
405 | } |
406 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
407 | IWL_WARN(priv, "check 2.4G: wrong radar\n"); | |
c914ac26 | 408 | errors |= BIT(1); |
dacefedb | 409 | } |
8ccde88a | 410 | } else { |
dacefedb JB |
411 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { |
412 | IWL_WARN(priv, "check 5.2G: not short slot!\n"); | |
c914ac26 | 413 | errors |= BIT(2); |
dacefedb JB |
414 | } |
415 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
416 | IWL_WARN(priv, "check 5.2G: CCK!\n"); | |
c914ac26 | 417 | errors |= BIT(3); |
dacefedb JB |
418 | } |
419 | } | |
420 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
421 | IWL_WARN(priv, "mac/bssid mcast!\n"); | |
c914ac26 | 422 | errors |= BIT(4); |
8ccde88a | 423 | } |
8ccde88a SO |
424 | |
425 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
dacefedb JB |
426 | if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 && |
427 | (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) { | |
428 | IWL_WARN(priv, "neither 1 nor 6 are basic\n"); | |
c914ac26 | 429 | errors |= BIT(5); |
dacefedb | 430 | } |
8ccde88a | 431 | |
dacefedb JB |
432 | if (le16_to_cpu(rxon->assoc_id) > 2007) { |
433 | IWL_WARN(priv, "aid > 2007\n"); | |
c914ac26 | 434 | errors |= BIT(6); |
dacefedb | 435 | } |
8ccde88a | 436 | |
dacefedb JB |
437 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) |
438 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
439 | IWL_WARN(priv, "CCK and short slot\n"); | |
c914ac26 | 440 | errors |= BIT(7); |
dacefedb | 441 | } |
8ccde88a | 442 | |
dacefedb JB |
443 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) |
444 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
445 | IWL_WARN(priv, "CCK and auto detect"); | |
c914ac26 | 446 | errors |= BIT(8); |
dacefedb | 447 | } |
8ccde88a | 448 | |
dacefedb JB |
449 | if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | |
450 | RXON_FLG_TGG_PROTECT_MSK)) == | |
451 | RXON_FLG_TGG_PROTECT_MSK) { | |
452 | IWL_WARN(priv, "TGg but no auto-detect\n"); | |
c914ac26 | 453 | errors |= BIT(9); |
dacefedb | 454 | } |
8ccde88a | 455 | |
c914ac26 JB |
456 | if (rxon->channel == 0) { |
457 | IWL_WARN(priv, "zero channel is invalid\n"); | |
458 | errors |= BIT(10); | |
8ccde88a | 459 | } |
c914ac26 JB |
460 | |
461 | WARN(errors, "Invalid RXON (%#x), channel %d", | |
462 | errors, le16_to_cpu(rxon->channel)); | |
463 | ||
464 | return errors ? -EINVAL : 0; | |
8ccde88a | 465 | } |
8ccde88a SO |
466 | |
467 | /** | |
468 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
469 | * @priv: staging_rxon is compared to active_rxon | |
470 | * | |
471 | * If the RXON structure is changing enough to require a new tune, | |
472 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
473 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
474 | */ | |
246ed355 JB |
475 | int iwl_full_rxon_required(struct iwl_priv *priv, |
476 | struct iwl_rxon_context *ctx) | |
8ccde88a | 477 | { |
246ed355 JB |
478 | const struct iwl_rxon_cmd *staging = &ctx->staging; |
479 | const struct iwl_rxon_cmd *active = &ctx->active; | |
480 | ||
481 | #define CHK(cond) \ | |
482 | if ((cond)) { \ | |
483 | IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \ | |
484 | return 1; \ | |
485 | } | |
486 | ||
487 | #define CHK_NEQ(c1, c2) \ | |
488 | if ((c1) != (c2)) { \ | |
489 | IWL_DEBUG_INFO(priv, "need full RXON - " \ | |
490 | #c1 " != " #c2 " - %d != %d\n", \ | |
491 | (c1), (c2)); \ | |
492 | return 1; \ | |
493 | } | |
8ccde88a SO |
494 | |
495 | /* These items are only settable from the full RXON command */ | |
246ed355 JB |
496 | CHK(!iwl_is_associated_ctx(ctx)); |
497 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); | |
498 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
499 | CHK(compare_ether_addr(staging->wlap_bssid_addr, | |
500 | active->wlap_bssid_addr)); | |
501 | CHK_NEQ(staging->dev_type, active->dev_type); | |
502 | CHK_NEQ(staging->channel, active->channel); | |
503 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
504 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
505 | active->ofdm_ht_single_stream_basic_rates); | |
506 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
507 | active->ofdm_ht_dual_stream_basic_rates); | |
508 | CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates, | |
509 | active->ofdm_ht_triple_stream_basic_rates); | |
510 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
8ccde88a SO |
511 | |
512 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
513 | * be updated with the RXON_ASSOC command -- however only some | |
514 | * flag transitions are allowed using RXON_ASSOC */ | |
515 | ||
516 | /* Check if we are not switching bands */ | |
246ed355 JB |
517 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, |
518 | active->flags & RXON_FLG_BAND_24G_MSK); | |
8ccde88a SO |
519 | |
520 | /* Check if we are switching association toggle */ | |
246ed355 JB |
521 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, |
522 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
523 | ||
524 | #undef CHK | |
525 | #undef CHK_NEQ | |
8ccde88a SO |
526 | |
527 | return 0; | |
528 | } | |
8ccde88a | 529 | |
246ed355 JB |
530 | static void _iwl_set_rxon_ht(struct iwl_priv *priv, |
531 | struct iwl_ht_config *ht_conf, | |
532 | struct iwl_rxon_context *ctx) | |
47c5196e | 533 | { |
246ed355 | 534 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
47c5196e | 535 | |
7e6a5886 | 536 | if (!ctx->ht.enabled) { |
a2b0f02e | 537 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 | 538 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
7aafef1c | 539 | RXON_FLG_HT40_PROT_MSK | |
42eb7c64 | 540 | RXON_FLG_HT_PROT_MSK); |
47c5196e | 541 | return; |
42eb7c64 | 542 | } |
47c5196e | 543 | |
7e6a5886 | 544 | /* FIXME: if the definition of ht.protection changed, the "translation" |
a2b0f02e WYG |
545 | * will be needed for rxon->flags |
546 | */ | |
7e6a5886 | 547 | rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); |
a2b0f02e WYG |
548 | |
549 | /* Set up channel bandwidth: | |
7aafef1c | 550 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
a2b0f02e WYG |
551 | /* clear the HT channel mode before set the mode */ |
552 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
553 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
7e6a5886 | 554 | if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) { |
7aafef1c | 555 | /* pure ht40 */ |
7e6a5886 | 556 | if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
a2b0f02e | 557 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
508b08e7 | 558 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 559 | switch (ctx->ht.extension_chan_offset) { |
508b08e7 WYG |
560 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
561 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
562 | break; | |
563 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
564 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
565 | break; | |
566 | } | |
567 | } else { | |
a2b0f02e | 568 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 569 | switch (ctx->ht.extension_chan_offset) { |
a2b0f02e WYG |
570 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
571 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
572 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
573 | break; | |
574 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
575 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
576 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
577 | break; | |
578 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
579 | default: | |
580 | /* channel location only valid if in Mixed mode */ | |
581 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
582 | break; | |
583 | } | |
584 | } | |
585 | } else { | |
586 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
587 | } |
588 | ||
e3f10cea | 589 | iwlagn_set_rxon_chain(priv, ctx); |
47c5196e | 590 | |
02bb1bea | 591 | IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 592 | "extension channel offset 0x%x\n", |
7e6a5886 JB |
593 | le32_to_cpu(rxon->flags), ctx->ht.protection, |
594 | ctx->ht.extension_chan_offset); | |
47c5196e | 595 | } |
246ed355 JB |
596 | |
597 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf) | |
598 | { | |
599 | struct iwl_rxon_context *ctx; | |
600 | ||
601 | for_each_context(priv, ctx) | |
602 | _iwl_set_rxon_ht(priv, ht_conf, ctx); | |
603 | } | |
47c5196e | 604 | |
246ed355 | 605 | /* Return valid, unused, channel for a passive scan to reset the RF */ |
14023641 | 606 | u8 iwl_get_single_channel_number(struct iwl_priv *priv, |
246ed355 | 607 | enum ieee80211_band band) |
14023641 AK |
608 | { |
609 | const struct iwl_channel_info *ch_info; | |
610 | int i; | |
611 | u8 channel = 0; | |
246ed355 JB |
612 | u8 min, max; |
613 | struct iwl_rxon_context *ctx; | |
14023641 | 614 | |
14023641 | 615 | if (band == IEEE80211_BAND_5GHZ) { |
246ed355 JB |
616 | min = 14; |
617 | max = priv->channel_count; | |
14023641 | 618 | } else { |
246ed355 JB |
619 | min = 0; |
620 | max = 14; | |
621 | } | |
622 | ||
623 | for (i = min; i < max; i++) { | |
624 | bool busy = false; | |
625 | ||
626 | for_each_context(priv, ctx) { | |
627 | busy = priv->channel_info[i].channel == | |
628 | le16_to_cpu(ctx->staging.channel); | |
629 | if (busy) | |
630 | break; | |
14023641 | 631 | } |
246ed355 JB |
632 | |
633 | if (busy) | |
634 | continue; | |
635 | ||
636 | channel = priv->channel_info[i].channel; | |
637 | ch_info = iwl_get_channel_info(priv, band, channel); | |
638 | if (is_channel_valid(ch_info)) | |
639 | break; | |
14023641 AK |
640 | } |
641 | ||
642 | return channel; | |
643 | } | |
14023641 | 644 | |
bf85ea4f | 645 | /** |
3edb5fd6 SZ |
646 | * iwl_set_rxon_channel - Set the band and channel values in staging RXON |
647 | * @ch: requested channel as a pointer to struct ieee80211_channel | |
bf85ea4f | 648 | |
bf85ea4f | 649 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
3edb5fd6 | 650 | * in the staging RXON flag structure based on the ch->band |
bf85ea4f | 651 | */ |
246ed355 JB |
652 | int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch, |
653 | struct iwl_rxon_context *ctx) | |
bf85ea4f | 654 | { |
17e72782 | 655 | enum ieee80211_band band = ch->band; |
81e95430 | 656 | u16 channel = ch->hw_value; |
17e72782 | 657 | |
246ed355 | 658 | if ((le16_to_cpu(ctx->staging.channel) == channel) && |
bf85ea4f AK |
659 | (priv->band == band)) |
660 | return 0; | |
661 | ||
246ed355 | 662 | ctx->staging.channel = cpu_to_le16(channel); |
bf85ea4f | 663 | if (band == IEEE80211_BAND_5GHZ) |
246ed355 | 664 | ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK; |
bf85ea4f | 665 | else |
246ed355 | 666 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
bf85ea4f AK |
667 | |
668 | priv->band = band; | |
669 | ||
e1623446 | 670 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f AK |
671 | |
672 | return 0; | |
673 | } | |
bf85ea4f | 674 | |
79d07325 | 675 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
246ed355 | 676 | struct iwl_rxon_context *ctx, |
79d07325 WYG |
677 | enum ieee80211_band band, |
678 | struct ieee80211_vif *vif) | |
8ccde88a SO |
679 | { |
680 | if (band == IEEE80211_BAND_5GHZ) { | |
246ed355 | 681 | ctx->staging.flags &= |
8ccde88a SO |
682 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
683 | | RXON_FLG_CCK_MSK); | |
246ed355 | 684 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a SO |
685 | } else { |
686 | /* Copied from iwl_post_associate() */ | |
c213d745 | 687 | if (vif && vif->bss_conf.use_short_slot) |
246ed355 | 688 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 689 | else |
246ed355 | 690 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 691 | |
246ed355 JB |
692 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
693 | ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
694 | ctx->staging.flags &= ~RXON_FLG_CCK_MSK; | |
8ccde88a SO |
695 | } |
696 | } | |
8ccde88a SO |
697 | |
698 | /* | |
699 | * initialize rxon structure with default values from eeprom | |
700 | */ | |
1dda6d28 | 701 | void iwl_connection_init_rx_config(struct iwl_priv *priv, |
d0fe478c | 702 | struct iwl_rxon_context *ctx) |
8ccde88a SO |
703 | { |
704 | const struct iwl_channel_info *ch_info; | |
705 | ||
246ed355 | 706 | memset(&ctx->staging, 0, sizeof(ctx->staging)); |
8ccde88a | 707 | |
d0fe478c JB |
708 | if (!ctx->vif) { |
709 | ctx->staging.dev_type = ctx->unused_devtype; | |
710 | } else switch (ctx->vif->type) { | |
8ccde88a | 711 | case NL80211_IFTYPE_AP: |
d0fe478c | 712 | ctx->staging.dev_type = ctx->ap_devtype; |
8ccde88a SO |
713 | break; |
714 | ||
715 | case NL80211_IFTYPE_STATION: | |
d0fe478c | 716 | ctx->staging.dev_type = ctx->station_devtype; |
246ed355 | 717 | ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; |
8ccde88a SO |
718 | break; |
719 | ||
720 | case NL80211_IFTYPE_ADHOC: | |
d0fe478c | 721 | ctx->staging.dev_type = ctx->ibss_devtype; |
246ed355 JB |
722 | ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; |
723 | ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
8ccde88a SO |
724 | RXON_FILTER_ACCEPT_GRP_MSK; |
725 | break; | |
726 | ||
8ccde88a | 727 | default: |
d0fe478c JB |
728 | IWL_ERR(priv, "Unsupported interface type %d\n", |
729 | ctx->vif->type); | |
8ccde88a SO |
730 | break; |
731 | } | |
732 | ||
733 | #if 0 | |
734 | /* TODO: Figure out when short_preamble would be set and cache from | |
735 | * that */ | |
736 | if (!hw_to_local(priv->hw)->short_preamble) | |
246ed355 | 737 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a | 738 | else |
246ed355 | 739 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a SO |
740 | #endif |
741 | ||
742 | ch_info = iwl_get_channel_info(priv, priv->band, | |
246ed355 | 743 | le16_to_cpu(ctx->active.channel)); |
8ccde88a SO |
744 | |
745 | if (!ch_info) | |
746 | ch_info = &priv->channel_info[0]; | |
747 | ||
246ed355 | 748 | ctx->staging.channel = cpu_to_le16(ch_info->channel); |
8ccde88a SO |
749 | priv->band = ch_info->band; |
750 | ||
d0fe478c | 751 | iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif); |
8ccde88a | 752 | |
246ed355 | 753 | ctx->staging.ofdm_basic_rates = |
8ccde88a | 754 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
246ed355 | 755 | ctx->staging.cck_basic_rates = |
8ccde88a SO |
756 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
757 | ||
a2b0f02e | 758 | /* clear both MIX and PURE40 mode flag */ |
246ed355 | 759 | ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | |
a2b0f02e | 760 | RXON_FLG_CHANNEL_MODE_PURE_40); |
d0fe478c JB |
761 | if (ctx->vif) |
762 | memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN); | |
7684c408 | 763 | |
246ed355 JB |
764 | ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff; |
765 | ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
766 | ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff; | |
8ccde88a | 767 | } |
8ccde88a | 768 | |
79d07325 | 769 | void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
770 | { |
771 | const struct ieee80211_supported_band *hw = NULL; | |
772 | struct ieee80211_rate *rate; | |
246ed355 | 773 | struct iwl_rxon_context *ctx; |
8ccde88a SO |
774 | int i; |
775 | ||
776 | hw = iwl_get_hw_mode(priv, priv->band); | |
777 | if (!hw) { | |
778 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
779 | return; | |
780 | } | |
781 | ||
782 | priv->active_rate = 0; | |
8ccde88a SO |
783 | |
784 | for (i = 0; i < hw->n_bitrates; i++) { | |
785 | rate = &(hw->bitrates[i]); | |
5027309b | 786 | if (rate->hw_value < IWL_RATE_COUNT_LEGACY) |
8ccde88a SO |
787 | priv->active_rate |= (1 << rate->hw_value); |
788 | } | |
789 | ||
4a02886b | 790 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate); |
8ccde88a | 791 | |
246ed355 JB |
792 | for_each_context(priv, ctx) { |
793 | ctx->staging.cck_basic_rates = | |
794 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
4a02886b | 795 | |
246ed355 JB |
796 | ctx->staging.ofdm_basic_rates = |
797 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
798 | } | |
8ccde88a | 799 | } |
79d07325 WYG |
800 | |
801 | void iwl_chswitch_done(struct iwl_priv *priv, bool is_success) | |
802 | { | |
8bd413e6 JB |
803 | /* |
804 | * MULTI-FIXME | |
805 | * See iwl_mac_channel_switch. | |
806 | */ | |
807 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
808 | ||
79d07325 WYG |
809 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
810 | return; | |
811 | ||
6f213ff1 | 812 | if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status)) |
8bd413e6 | 813 | ieee80211_chswitch_done(ctx->vif, is_success); |
79d07325 | 814 | } |
8ccde88a | 815 | |
8ccde88a | 816 | #ifdef CONFIG_IWLWIFI_DEBUG |
246ed355 JB |
817 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, |
818 | struct iwl_rxon_context *ctx) | |
8ccde88a | 819 | { |
246ed355 | 820 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a | 821 | |
e1623446 | 822 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
3d816c77 | 823 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
824 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
825 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
826 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 827 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
828 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
829 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 830 | rxon->ofdm_basic_rates); |
e1623446 TW |
831 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
832 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
833 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
834 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a | 835 | } |
6686d17e | 836 | #endif |
e649437f | 837 | |
e74fe233 JB |
838 | static void iwlagn_abort_notification_waits(struct iwl_priv *priv) |
839 | { | |
840 | unsigned long flags; | |
841 | struct iwl_notification_wait *wait_entry; | |
842 | ||
843 | spin_lock_irqsave(&priv->_agn.notif_wait_lock, flags); | |
844 | list_for_each_entry(wait_entry, &priv->_agn.notif_waits, list) | |
845 | wait_entry->aborted = true; | |
846 | spin_unlock_irqrestore(&priv->_agn.notif_wait_lock, flags); | |
847 | ||
848 | wake_up_all(&priv->_agn.notif_waitq); | |
849 | } | |
850 | ||
e649437f | 851 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) |
8ccde88a | 852 | { |
491bc292 WYG |
853 | unsigned int reload_msec; |
854 | unsigned long reload_jiffies; | |
855 | ||
8ccde88a SO |
856 | /* Set the FW error flag -- cleared on iwl_down */ |
857 | set_bit(STATUS_FW_ERROR, &priv->status); | |
858 | ||
859 | /* Cancel currently queued command. */ | |
860 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
861 | ||
e74fe233 JB |
862 | iwlagn_abort_notification_waits(priv); |
863 | ||
e649437f JB |
864 | /* Keep the restart process from trying to send host |
865 | * commands by clearing the ready bit */ | |
866 | clear_bit(STATUS_READY, &priv->status); | |
867 | ||
868 | wake_up_interruptible(&priv->wait_command_queue); | |
869 | ||
870 | if (!ondemand) { | |
871 | /* | |
872 | * If firmware keep reloading, then it indicate something | |
873 | * serious wrong and firmware having problem to recover | |
874 | * from it. Instead of keep trying which will fill the syslog | |
875 | * and hang the system, let's just stop it | |
876 | */ | |
877 | reload_jiffies = jiffies; | |
878 | reload_msec = jiffies_to_msecs((long) reload_jiffies - | |
879 | (long) priv->reload_jiffies); | |
880 | priv->reload_jiffies = reload_jiffies; | |
881 | if (reload_msec <= IWL_MIN_RELOAD_DURATION) { | |
882 | priv->reload_count++; | |
883 | if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) { | |
884 | IWL_ERR(priv, "BUG_ON, Stop restarting\n"); | |
885 | return; | |
886 | } | |
887 | } else | |
888 | priv->reload_count = 0; | |
889 | } | |
890 | ||
891 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
9d143e9a | 892 | if (iwlagn_mod_params.restart_fw) { |
e649437f JB |
893 | IWL_DEBUG(priv, IWL_DL_FW_ERRORS, |
894 | "Restarting adapter due to uCode error.\n"); | |
895 | queue_work(priv->workqueue, &priv->restart); | |
896 | } else | |
897 | IWL_DEBUG(priv, IWL_DL_FW_ERRORS, | |
898 | "Detected FW error, but not restarting\n"); | |
899 | } | |
900 | } | |
901 | ||
902 | /** | |
903 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
904 | */ | |
905 | void iwl_irq_handle_error(struct iwl_priv *priv) | |
906 | { | |
50619ac9 WYG |
907 | /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ |
908 | if (priv->cfg->internal_wimax_coex && | |
909 | (!(iwl_read_prph(priv, APMG_CLK_CTRL_REG) & | |
910 | APMS_CLK_VAL_MRB_FUNC_MODE) || | |
911 | (iwl_read_prph(priv, APMG_PS_CTRL_REG) & | |
912 | APMG_PS_CTRL_VAL_RESET_REQ))) { | |
50619ac9 | 913 | /* |
e649437f JB |
914 | * Keep the restart process from trying to send host |
915 | * commands by clearing the ready bit. | |
50619ac9 WYG |
916 | */ |
917 | clear_bit(STATUS_READY, &priv->status); | |
e649437f JB |
918 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
919 | wake_up_interruptible(&priv->wait_command_queue); | |
50619ac9 WYG |
920 | IWL_ERR(priv, "RF is used by WiMAX\n"); |
921 | return; | |
922 | } | |
923 | ||
459bc732 SZ |
924 | IWL_ERR(priv, "Loaded firmware version: %s\n", |
925 | priv->hw->wiphy->fw_version); | |
926 | ||
3ecccbcd WYG |
927 | iwl_dump_nic_error_log(priv); |
928 | iwl_dump_csr(priv); | |
929 | iwl_dump_fh(priv, NULL, false); | |
930 | iwl_dump_nic_event_log(priv, false, NULL, false); | |
8ccde88a | 931 | #ifdef CONFIG_IWLWIFI_DEBUG |
c341ddb2 | 932 | if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) |
246ed355 JB |
933 | iwl_print_rx_config_cmd(priv, |
934 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
8ccde88a SO |
935 | #endif |
936 | ||
e649437f | 937 | iwlagn_fw_error(priv, false); |
8ccde88a | 938 | } |
8ccde88a | 939 | |
f8e200de | 940 | static int iwl_apm_stop_master(struct iwl_priv *priv) |
d68b603c | 941 | { |
5220af0c | 942 | int ret = 0; |
d68b603c | 943 | |
5220af0c | 944 | /* stop device's busmaster DMA activity */ |
d68b603c AK |
945 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
946 | ||
5220af0c | 947 | ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, |
d68b603c | 948 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
5220af0c BC |
949 | if (ret) |
950 | IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n"); | |
d68b603c | 951 | |
d68b603c AK |
952 | IWL_DEBUG_INFO(priv, "stop master\n"); |
953 | ||
5220af0c | 954 | return ret; |
d68b603c | 955 | } |
d68b603c AK |
956 | |
957 | void iwl_apm_stop(struct iwl_priv *priv) | |
958 | { | |
fadb3582 BC |
959 | IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n"); |
960 | ||
9d39e5ba JB |
961 | clear_bit(STATUS_DEVICE_ENABLED, &priv->status); |
962 | ||
5220af0c | 963 | /* Stop device's DMA activity */ |
d68b603c AK |
964 | iwl_apm_stop_master(priv); |
965 | ||
5220af0c | 966 | /* Reset the entire device */ |
d68b603c AK |
967 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
968 | ||
969 | udelay(10); | |
5220af0c BC |
970 | |
971 | /* | |
972 | * Clear "initialization complete" bit to move adapter from | |
973 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
974 | */ | |
d68b603c | 975 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
d68b603c | 976 | } |
d68b603c | 977 | |
fadb3582 BC |
978 | |
979 | /* | |
980 | * Start up NIC's basic functionality after it has been reset | |
981 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
982 | * NOTE: This does not load uCode nor start the embedded processor | |
983 | */ | |
984 | int iwl_apm_init(struct iwl_priv *priv) | |
985 | { | |
986 | int ret = 0; | |
fadb3582 BC |
987 | IWL_DEBUG_INFO(priv, "Init card's basic functions\n"); |
988 | ||
989 | /* | |
990 | * Use "set_bit" below rather than "write", to preserve any hardware | |
991 | * bits already set by default after reset. | |
992 | */ | |
993 | ||
994 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
995 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
996 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
997 | ||
998 | /* | |
999 | * Disable L0s without affecting L1; | |
1000 | * don't wait for ICH L0s (ICH bug W/A) | |
1001 | */ | |
1002 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
1003 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
1004 | ||
1005 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
1006 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
1007 | ||
1008 | /* | |
1009 | * Enable HAP INTA (interrupt from management bus) to | |
1010 | * wake device's PCI Express link L1a -> L0s | |
fadb3582 BC |
1011 | */ |
1012 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1013 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
1014 | ||
d5934110 | 1015 | bus_apm_config(priv->bus); |
fadb3582 BC |
1016 | |
1017 | /* Configure analog phase-lock-loop before activating to D0A */ | |
7cb1b088 WYG |
1018 | if (priv->cfg->base_params->pll_cfg_val) |
1019 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, | |
1020 | priv->cfg->base_params->pll_cfg_val); | |
fadb3582 BC |
1021 | |
1022 | /* | |
1023 | * Set "initialization complete" bit to move adapter from | |
1024 | * D0U* --> D0A* (powered-up active) state. | |
1025 | */ | |
1026 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1027 | ||
1028 | /* | |
1029 | * Wait for clock stabilization; once stabilized, access to | |
1030 | * device-internal resources is supported, e.g. iwl_write_prph() | |
1031 | * and accesses to uCode SRAM. | |
1032 | */ | |
1033 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
1034 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1035 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
1036 | if (ret < 0) { | |
1037 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); | |
1038 | goto out; | |
1039 | } | |
1040 | ||
1041 | /* | |
917b6777 | 1042 | * Enable DMA clock and wait for it to stabilize. |
fadb3582 BC |
1043 | * |
1044 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
1045 | * do not disable clocks. This preserves any hardware bits already | |
1046 | * set by default in "CLK_CTRL_REG" after reset. | |
1047 | */ | |
917b6777 | 1048 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
fadb3582 BC |
1049 | udelay(20); |
1050 | ||
1051 | /* Disable L1-Active */ | |
1052 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
1053 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
1054 | ||
9d39e5ba JB |
1055 | set_bit(STATUS_DEVICE_ENABLED, &priv->status); |
1056 | ||
fadb3582 BC |
1057 | out: |
1058 | return ret; | |
1059 | } | |
fadb3582 BC |
1060 | |
1061 | ||
630fe9b6 TW |
1062 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
1063 | { | |
a25a66ac SG |
1064 | int ret; |
1065 | s8 prev_tx_power; | |
f844a709 SG |
1066 | bool defer; |
1067 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
a25a66ac SG |
1068 | |
1069 | lockdep_assert_held(&priv->mutex); | |
1070 | ||
1071 | if (priv->tx_power_user_lmt == tx_power && !force) | |
1072 | return 0; | |
1073 | ||
b744cb79 WYG |
1074 | if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) { |
1075 | IWL_WARN(priv, | |
1076 | "Requested user TXPOWER %d below lower limit %d.\n", | |
daf518de | 1077 | tx_power, |
b744cb79 | 1078 | IWLAGN_TX_POWER_TARGET_POWER_MIN); |
630fe9b6 TW |
1079 | return -EINVAL; |
1080 | } | |
1081 | ||
dc1b0973 | 1082 | if (tx_power > priv->tx_power_device_lmt) { |
08f2d58d WYG |
1083 | IWL_WARN(priv, |
1084 | "Requested user TXPOWER %d above upper limit %d.\n", | |
dc1b0973 | 1085 | tx_power, priv->tx_power_device_lmt); |
630fe9b6 TW |
1086 | return -EINVAL; |
1087 | } | |
1088 | ||
a25a66ac SG |
1089 | if (!iwl_is_ready_rf(priv)) |
1090 | return -EIO; | |
630fe9b6 | 1091 | |
f844a709 SG |
1092 | /* scan complete and commit_rxon use tx_power_next value, |
1093 | * it always need to be updated for newest request */ | |
a25a66ac | 1094 | priv->tx_power_next = tx_power; |
f844a709 SG |
1095 | |
1096 | /* do not set tx power when scanning or channel changing */ | |
1097 | defer = test_bit(STATUS_SCANNING, &priv->status) || | |
1098 | memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)); | |
1099 | if (defer && !force) { | |
1100 | IWL_DEBUG_INFO(priv, "Deferring tx power set\n"); | |
a25a66ac | 1101 | return 0; |
5eadd94b | 1102 | } |
630fe9b6 | 1103 | |
a25a66ac SG |
1104 | prev_tx_power = priv->tx_power_user_lmt; |
1105 | priv->tx_power_user_lmt = tx_power; | |
1106 | ||
5beaaf37 | 1107 | ret = iwlagn_send_tx_power(priv); |
a25a66ac SG |
1108 | |
1109 | /* if fail to set tx_power, restore the orig. tx power */ | |
1110 | if (ret) { | |
1111 | priv->tx_power_user_lmt = prev_tx_power; | |
1112 | priv->tx_power_next = prev_tx_power; | |
1113 | } | |
630fe9b6 TW |
1114 | return ret; |
1115 | } | |
630fe9b6 | 1116 | |
65b52bde | 1117 | void iwl_send_bt_config(struct iwl_priv *priv) |
17f841cd SO |
1118 | { |
1119 | struct iwl_bt_cmd bt_cmd = { | |
456d0f76 WYG |
1120 | .lead_time = BT_LEAD_TIME_DEF, |
1121 | .max_kill = BT_MAX_KILL_DEF, | |
17f841cd SO |
1122 | .kill_ack_mask = 0, |
1123 | .kill_cts_mask = 0, | |
1124 | }; | |
1125 | ||
b60eec9b | 1126 | if (!iwlagn_mod_params.bt_coex_active) |
06702a73 WYG |
1127 | bt_cmd.flags = BT_COEX_DISABLE; |
1128 | else | |
1129 | bt_cmd.flags = BT_COEX_ENABLE; | |
1130 | ||
f21dd005 | 1131 | priv->bt_enable_flag = bt_cmd.flags; |
06702a73 WYG |
1132 | IWL_DEBUG_INFO(priv, "BT coex %s\n", |
1133 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); | |
1134 | ||
41c50542 | 1135 | if (trans_send_cmd_pdu(&priv->trans, REPLY_BT_CONFIG, |
e419d62d | 1136 | CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd)) |
65b52bde | 1137 | IWL_ERR(priv, "failed to send BT Coex Config\n"); |
17f841cd | 1138 | } |
17f841cd | 1139 | |
ef8d5529 | 1140 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear) |
49ea8596 | 1141 | { |
ef8d5529 WYG |
1142 | struct iwl_statistics_cmd statistics_cmd = { |
1143 | .configuration_flags = | |
1144 | clear ? IWL_STATS_CONF_CLEAR_STATS : 0, | |
49ea8596 | 1145 | }; |
ef8d5529 WYG |
1146 | |
1147 | if (flags & CMD_ASYNC) | |
41c50542 | 1148 | return trans_send_cmd_pdu(&priv->trans, REPLY_STATISTICS_CMD, |
e419d62d | 1149 | CMD_ASYNC, |
ef8d5529 | 1150 | sizeof(struct iwl_statistics_cmd), |
e419d62d | 1151 | &statistics_cmd); |
ef8d5529 | 1152 | else |
41c50542 | 1153 | return trans_send_cmd_pdu(&priv->trans, REPLY_STATISTICS_CMD, |
e419d62d | 1154 | CMD_SYNC, |
ef8d5529 WYG |
1155 | sizeof(struct iwl_statistics_cmd), |
1156 | &statistics_cmd); | |
49ea8596 | 1157 | } |
7e8c519e | 1158 | |
a83b9141 WYG |
1159 | void iwl_clear_isr_stats(struct iwl_priv *priv) |
1160 | { | |
1161 | memset(&priv->isr_stats, 0, sizeof(priv->isr_stats)); | |
1162 | } | |
a83b9141 | 1163 | |
488829f1 AK |
1164 | int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
1165 | const struct ieee80211_tx_queue_params *params) | |
1166 | { | |
1167 | struct iwl_priv *priv = hw->priv; | |
8dfdb9d5 | 1168 | struct iwl_rxon_context *ctx; |
488829f1 AK |
1169 | unsigned long flags; |
1170 | int q; | |
1171 | ||
1172 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
1173 | ||
1174 | if (!iwl_is_ready_rf(priv)) { | |
1175 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
1176 | return -EIO; | |
1177 | } | |
1178 | ||
1179 | if (queue >= AC_NUM) { | |
1180 | IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue); | |
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | q = AC_NUM - 1 - queue; | |
1185 | ||
1186 | spin_lock_irqsave(&priv->lock, flags); | |
1187 | ||
8dfdb9d5 JB |
1188 | /* |
1189 | * MULTI-FIXME | |
1190 | * This may need to be done per interface in nl80211/cfg80211/mac80211. | |
1191 | */ | |
1192 | for_each_context(priv, ctx) { | |
1193 | ctx->qos_data.def_qos_parm.ac[q].cw_min = | |
1194 | cpu_to_le16(params->cw_min); | |
1195 | ctx->qos_data.def_qos_parm.ac[q].cw_max = | |
1196 | cpu_to_le16(params->cw_max); | |
1197 | ctx->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
1198 | ctx->qos_data.def_qos_parm.ac[q].edca_txop = | |
1199 | cpu_to_le16((params->txop * 32)); | |
1200 | ||
1201 | ctx->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
1202 | } | |
488829f1 AK |
1203 | |
1204 | spin_unlock_irqrestore(&priv->lock, flags); | |
1205 | ||
1206 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
1207 | return 0; | |
1208 | } | |
5bbe233b | 1209 | |
a85d7cca JB |
1210 | int iwl_mac_tx_last_beacon(struct ieee80211_hw *hw) |
1211 | { | |
1212 | struct iwl_priv *priv = hw->priv; | |
1213 | ||
1214 | return priv->ibss_manager == IWL_IBSS_MANAGER; | |
1215 | } | |
a85d7cca | 1216 | |
d4daaea6 | 1217 | static int iwl_set_mode(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
727882d6 | 1218 | { |
d0fe478c | 1219 | iwl_connection_init_rx_config(priv, ctx); |
727882d6 | 1220 | |
e3f10cea | 1221 | iwlagn_set_rxon_chain(priv, ctx); |
727882d6 | 1222 | |
805a3b81 | 1223 | return iwlagn_commit_rxon(priv, ctx); |
727882d6 | 1224 | } |
727882d6 | 1225 | |
d4daaea6 JB |
1226 | static int iwl_setup_interface(struct iwl_priv *priv, |
1227 | struct iwl_rxon_context *ctx) | |
1228 | { | |
1229 | struct ieee80211_vif *vif = ctx->vif; | |
1230 | int err; | |
1231 | ||
1232 | lockdep_assert_held(&priv->mutex); | |
1233 | ||
1234 | /* | |
1235 | * This variable will be correct only when there's just | |
1236 | * a single context, but all code using it is for hardware | |
1237 | * that supports only one context. | |
1238 | */ | |
1239 | priv->iw_mode = vif->type; | |
1240 | ||
1241 | ctx->is_active = true; | |
1242 | ||
1243 | err = iwl_set_mode(priv, ctx); | |
1244 | if (err) { | |
1245 | if (!ctx->always_active) | |
1246 | ctx->is_active = false; | |
1247 | return err; | |
1248 | } | |
1249 | ||
1250 | if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist && | |
1251 | vif->type == NL80211_IFTYPE_ADHOC) { | |
1252 | /* | |
1253 | * pretend to have high BT traffic as long as we | |
1254 | * are operating in IBSS mode, as this will cause | |
1255 | * the rate scaling etc. to behave as intended. | |
1256 | */ | |
1257 | priv->bt_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_HIGH; | |
1258 | } | |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | ||
b55e75ed | 1263 | int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
cbb6ab94 AK |
1264 | { |
1265 | struct iwl_priv *priv = hw->priv; | |
246ed355 | 1266 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
d0fe478c | 1267 | struct iwl_rxon_context *tmp, *ctx = NULL; |
d4daaea6 | 1268 | int err; |
f35c0c56 | 1269 | enum nl80211_iftype viftype = ieee80211_vif_type_p2p(vif); |
cbb6ab94 | 1270 | |
3779db10 | 1271 | IWL_DEBUG_MAC80211(priv, "enter: type %d, addr %pM\n", |
f35c0c56 | 1272 | viftype, vif->addr); |
cbb6ab94 | 1273 | |
47e28f41 JB |
1274 | mutex_lock(&priv->mutex); |
1275 | ||
4bd530f3 SG |
1276 | if (!iwl_is_ready_rf(priv)) { |
1277 | IWL_WARN(priv, "Try to add interface when device not ready\n"); | |
b55e75ed JB |
1278 | err = -EINVAL; |
1279 | goto out; | |
1280 | } | |
1281 | ||
d0fe478c JB |
1282 | for_each_context(priv, tmp) { |
1283 | u32 possible_modes = | |
1284 | tmp->interface_modes | tmp->exclusive_interface_modes; | |
1285 | ||
1286 | if (tmp->vif) { | |
1287 | /* check if this busy context is exclusive */ | |
1288 | if (tmp->exclusive_interface_modes & | |
1289 | BIT(tmp->vif->type)) { | |
1290 | err = -EINVAL; | |
1291 | goto out; | |
1292 | } | |
1293 | continue; | |
1294 | } | |
1295 | ||
f35c0c56 | 1296 | if (!(possible_modes & BIT(viftype))) |
d0fe478c JB |
1297 | continue; |
1298 | ||
1299 | /* have maybe usable context w/o interface */ | |
1300 | ctx = tmp; | |
1301 | break; | |
1302 | } | |
1303 | ||
1304 | if (!ctx) { | |
47e28f41 JB |
1305 | err = -EOPNOTSUPP; |
1306 | goto out; | |
cbb6ab94 AK |
1307 | } |
1308 | ||
d0fe478c | 1309 | vif_priv->ctx = ctx; |
8bd413e6 | 1310 | ctx->vif = vif; |
59079949 | 1311 | |
d4daaea6 JB |
1312 | err = iwl_setup_interface(priv, ctx); |
1313 | if (!err) | |
1314 | goto out; | |
cbb6ab94 | 1315 | |
8bd413e6 | 1316 | ctx->vif = NULL; |
b55e75ed | 1317 | priv->iw_mode = NL80211_IFTYPE_STATION; |
47e28f41 | 1318 | out: |
cbb6ab94 AK |
1319 | mutex_unlock(&priv->mutex); |
1320 | ||
1321 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
47e28f41 | 1322 | return err; |
cbb6ab94 | 1323 | } |
cbb6ab94 | 1324 | |
d4daaea6 JB |
1325 | static void iwl_teardown_interface(struct iwl_priv *priv, |
1326 | struct ieee80211_vif *vif, | |
1327 | bool mode_change) | |
d8052319 | 1328 | { |
246ed355 | 1329 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); |
d8052319 | 1330 | |
d4daaea6 | 1331 | lockdep_assert_held(&priv->mutex); |
d0fe478c | 1332 | |
e7e16b90 SG |
1333 | if (priv->scan_vif == vif) { |
1334 | iwl_scan_cancel_timeout(priv, 200); | |
1335 | iwl_force_scan_end(priv); | |
1336 | } | |
8bd413e6 | 1337 | |
d4daaea6 JB |
1338 | if (!mode_change) { |
1339 | iwl_set_mode(priv, ctx); | |
1340 | if (!ctx->always_active) | |
1341 | ctx->is_active = false; | |
1342 | } | |
763cc3bf | 1343 | |
59079949 JB |
1344 | /* |
1345 | * When removing the IBSS interface, overwrite the | |
1346 | * BT traffic load with the stored one from the last | |
1347 | * notification, if any. If this is a device that | |
1348 | * doesn't implement this, this has no effect since | |
1349 | * both values are the same and zero. | |
1350 | */ | |
1351 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
66e863a5 | 1352 | priv->bt_traffic_load = priv->last_bt_traffic_load; |
d4daaea6 JB |
1353 | } |
1354 | ||
1355 | void iwl_mac_remove_interface(struct ieee80211_hw *hw, | |
1356 | struct ieee80211_vif *vif) | |
1357 | { | |
1358 | struct iwl_priv *priv = hw->priv; | |
1359 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); | |
1360 | ||
1361 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
1362 | ||
1363 | mutex_lock(&priv->mutex); | |
1364 | ||
1365 | WARN_ON(ctx->vif != vif); | |
1366 | ctx->vif = NULL; | |
1367 | ||
1368 | iwl_teardown_interface(priv, vif, false); | |
59079949 | 1369 | |
d8052319 AK |
1370 | mutex_unlock(&priv->mutex); |
1371 | ||
1372 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
1373 | ||
1374 | } | |
d8052319 | 1375 | |
20594eb0 WYG |
1376 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1377 | ||
1378 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) | |
1379 | ||
1380 | void iwl_reset_traffic_log(struct iwl_priv *priv) | |
1381 | { | |
1382 | priv->tx_traffic_idx = 0; | |
1383 | priv->rx_traffic_idx = 0; | |
1384 | if (priv->tx_traffic) | |
1385 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1386 | if (priv->rx_traffic) | |
1387 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
1388 | } | |
1389 | ||
1390 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) | |
1391 | { | |
1392 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; | |
1393 | ||
1394 | if (iwl_debug_level & IWL_DL_TX) { | |
1395 | if (!priv->tx_traffic) { | |
1396 | priv->tx_traffic = | |
1397 | kzalloc(traffic_size, GFP_KERNEL); | |
1398 | if (!priv->tx_traffic) | |
1399 | return -ENOMEM; | |
1400 | } | |
1401 | } | |
1402 | if (iwl_debug_level & IWL_DL_RX) { | |
1403 | if (!priv->rx_traffic) { | |
1404 | priv->rx_traffic = | |
1405 | kzalloc(traffic_size, GFP_KERNEL); | |
1406 | if (!priv->rx_traffic) | |
1407 | return -ENOMEM; | |
1408 | } | |
1409 | } | |
1410 | iwl_reset_traffic_log(priv); | |
1411 | return 0; | |
1412 | } | |
20594eb0 WYG |
1413 | |
1414 | void iwl_free_traffic_mem(struct iwl_priv *priv) | |
1415 | { | |
1416 | kfree(priv->tx_traffic); | |
1417 | priv->tx_traffic = NULL; | |
1418 | ||
1419 | kfree(priv->rx_traffic); | |
1420 | priv->rx_traffic = NULL; | |
1421 | } | |
20594eb0 WYG |
1422 | |
1423 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | |
1424 | u16 length, struct ieee80211_hdr *header) | |
1425 | { | |
1426 | __le16 fc; | |
1427 | u16 len; | |
1428 | ||
1429 | if (likely(!(iwl_debug_level & IWL_DL_TX))) | |
1430 | return; | |
1431 | ||
1432 | if (!priv->tx_traffic) | |
1433 | return; | |
1434 | ||
1435 | fc = header->frame_control; | |
1436 | if (ieee80211_is_data(fc)) { | |
1437 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1438 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1439 | memcpy((priv->tx_traffic + | |
1440 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1441 | header, len); | |
1442 | priv->tx_traffic_idx = | |
1443 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1444 | } | |
1445 | } | |
20594eb0 WYG |
1446 | |
1447 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | |
1448 | u16 length, struct ieee80211_hdr *header) | |
1449 | { | |
1450 | __le16 fc; | |
1451 | u16 len; | |
1452 | ||
1453 | if (likely(!(iwl_debug_level & IWL_DL_RX))) | |
1454 | return; | |
1455 | ||
1456 | if (!priv->rx_traffic) | |
1457 | return; | |
1458 | ||
1459 | fc = header->frame_control; | |
1460 | if (ieee80211_is_data(fc)) { | |
1461 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
1462 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
1463 | memcpy((priv->rx_traffic + | |
1464 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
1465 | header, len); | |
1466 | priv->rx_traffic_idx = | |
1467 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
1468 | } | |
1469 | } | |
22fdf3c9 WYG |
1470 | |
1471 | const char *get_mgmt_string(int cmd) | |
1472 | { | |
1473 | switch (cmd) { | |
1474 | IWL_CMD(MANAGEMENT_ASSOC_REQ); | |
1475 | IWL_CMD(MANAGEMENT_ASSOC_RESP); | |
1476 | IWL_CMD(MANAGEMENT_REASSOC_REQ); | |
1477 | IWL_CMD(MANAGEMENT_REASSOC_RESP); | |
1478 | IWL_CMD(MANAGEMENT_PROBE_REQ); | |
1479 | IWL_CMD(MANAGEMENT_PROBE_RESP); | |
1480 | IWL_CMD(MANAGEMENT_BEACON); | |
1481 | IWL_CMD(MANAGEMENT_ATIM); | |
1482 | IWL_CMD(MANAGEMENT_DISASSOC); | |
1483 | IWL_CMD(MANAGEMENT_AUTH); | |
1484 | IWL_CMD(MANAGEMENT_DEAUTH); | |
1485 | IWL_CMD(MANAGEMENT_ACTION); | |
1486 | default: | |
1487 | return "UNKNOWN"; | |
1488 | ||
1489 | } | |
1490 | } | |
1491 | ||
1492 | const char *get_ctrl_string(int cmd) | |
1493 | { | |
1494 | switch (cmd) { | |
1495 | IWL_CMD(CONTROL_BACK_REQ); | |
1496 | IWL_CMD(CONTROL_BACK); | |
1497 | IWL_CMD(CONTROL_PSPOLL); | |
1498 | IWL_CMD(CONTROL_RTS); | |
1499 | IWL_CMD(CONTROL_CTS); | |
1500 | IWL_CMD(CONTROL_ACK); | |
1501 | IWL_CMD(CONTROL_CFEND); | |
1502 | IWL_CMD(CONTROL_CFENDACK); | |
1503 | default: | |
1504 | return "UNKNOWN"; | |
1505 | ||
1506 | } | |
1507 | } | |
1508 | ||
7163b8a4 | 1509 | void iwl_clear_traffic_stats(struct iwl_priv *priv) |
22fdf3c9 WYG |
1510 | { |
1511 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); | |
22fdf3c9 WYG |
1512 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); |
1513 | } | |
1514 | ||
1515 | /* | |
1516 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will | |
1517 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. | |
1518 | * Use debugFs to display the rx/rx_statistics | |
1519 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL | |
1520 | * information will be recorded, but DATA pkt still will be recorded | |
1521 | * for the reason of iwl_led.c need to control the led blinking based on | |
1522 | * number of tx and rx data. | |
1523 | * | |
1524 | */ | |
1525 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) | |
1526 | { | |
1527 | struct traffic_stats *stats; | |
1528 | ||
1529 | if (is_tx) | |
1530 | stats = &priv->tx_stats; | |
1531 | else | |
1532 | stats = &priv->rx_stats; | |
1533 | ||
1534 | if (ieee80211_is_mgmt(fc)) { | |
1535 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1536 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
1537 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
1538 | break; | |
1539 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
1540 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
1541 | break; | |
1542 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
1543 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
1544 | break; | |
1545 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
1546 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
1547 | break; | |
1548 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
1549 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
1550 | break; | |
1551 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
1552 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
1553 | break; | |
1554 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
1555 | stats->mgmt[MANAGEMENT_BEACON]++; | |
1556 | break; | |
1557 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
1558 | stats->mgmt[MANAGEMENT_ATIM]++; | |
1559 | break; | |
1560 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
1561 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
1562 | break; | |
1563 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
1564 | stats->mgmt[MANAGEMENT_AUTH]++; | |
1565 | break; | |
1566 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
1567 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
1568 | break; | |
1569 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
1570 | stats->mgmt[MANAGEMENT_ACTION]++; | |
1571 | break; | |
1572 | } | |
1573 | } else if (ieee80211_is_ctl(fc)) { | |
1574 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1575 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
1576 | stats->ctrl[CONTROL_BACK_REQ]++; | |
1577 | break; | |
1578 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
1579 | stats->ctrl[CONTROL_BACK]++; | |
1580 | break; | |
1581 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
1582 | stats->ctrl[CONTROL_PSPOLL]++; | |
1583 | break; | |
1584 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
1585 | stats->ctrl[CONTROL_RTS]++; | |
1586 | break; | |
1587 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
1588 | stats->ctrl[CONTROL_CTS]++; | |
1589 | break; | |
1590 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
1591 | stats->ctrl[CONTROL_ACK]++; | |
1592 | break; | |
1593 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
1594 | stats->ctrl[CONTROL_CFEND]++; | |
1595 | break; | |
1596 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
1597 | stats->ctrl[CONTROL_CFENDACK]++; | |
1598 | break; | |
1599 | } | |
1600 | } else { | |
1601 | /* data */ | |
1602 | stats->data_cnt++; | |
1603 | stats->data_bytes += len; | |
1604 | } | |
1605 | } | |
20594eb0 WYG |
1606 | #endif |
1607 | ||
a93e7973 | 1608 | static void iwl_force_rf_reset(struct iwl_priv *priv) |
afbdd69a WYG |
1609 | { |
1610 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1611 | return; | |
1612 | ||
246ed355 | 1613 | if (!iwl_is_any_associated(priv)) { |
afbdd69a WYG |
1614 | IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n"); |
1615 | return; | |
1616 | } | |
1617 | /* | |
1618 | * There is no easy and better way to force reset the radio, | |
1619 | * the only known method is switching channel which will force to | |
1620 | * reset and tune the radio. | |
1621 | * Use internal short scan (single channel) operation to should | |
1622 | * achieve this objective. | |
1623 | * Driver should reset the radio when number of consecutive missed | |
1624 | * beacon, or any other uCode error condition detected. | |
1625 | */ | |
1626 | IWL_DEBUG_INFO(priv, "perform radio reset.\n"); | |
1627 | iwl_internal_short_hw_scan(priv); | |
afbdd69a | 1628 | } |
a93e7973 | 1629 | |
a93e7973 | 1630 | |
c04f9f22 | 1631 | int iwl_force_reset(struct iwl_priv *priv, int mode, bool external) |
a93e7973 | 1632 | { |
8a472da4 WYG |
1633 | struct iwl_force_reset *force_reset; |
1634 | ||
a93e7973 WYG |
1635 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1636 | return -EINVAL; | |
1637 | ||
8a472da4 WYG |
1638 | if (mode >= IWL_MAX_FORCE_RESET) { |
1639 | IWL_DEBUG_INFO(priv, "invalid reset request.\n"); | |
1640 | return -EINVAL; | |
1641 | } | |
1642 | force_reset = &priv->force_reset[mode]; | |
1643 | force_reset->reset_request_count++; | |
c04f9f22 WYG |
1644 | if (!external) { |
1645 | if (force_reset->last_force_reset_jiffies && | |
1646 | time_after(force_reset->last_force_reset_jiffies + | |
1647 | force_reset->reset_duration, jiffies)) { | |
1648 | IWL_DEBUG_INFO(priv, "force reset rejected\n"); | |
1649 | force_reset->reset_reject_count++; | |
1650 | return -EAGAIN; | |
1651 | } | |
a93e7973 | 1652 | } |
8a472da4 WYG |
1653 | force_reset->reset_success_count++; |
1654 | force_reset->last_force_reset_jiffies = jiffies; | |
a93e7973 | 1655 | IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode); |
a93e7973 WYG |
1656 | switch (mode) { |
1657 | case IWL_RF_RESET: | |
1658 | iwl_force_rf_reset(priv); | |
1659 | break; | |
1660 | case IWL_FW_RESET: | |
c04f9f22 WYG |
1661 | /* |
1662 | * if the request is from external(ex: debugfs), | |
1663 | * then always perform the request in regardless the module | |
1664 | * parameter setting | |
1665 | * if the request is from internal (uCode error or driver | |
1666 | * detect failure), then fw_restart module parameter | |
1667 | * need to be check before performing firmware reload | |
1668 | */ | |
9d143e9a | 1669 | if (!external && !iwlagn_mod_params.restart_fw) { |
c04f9f22 WYG |
1670 | IWL_DEBUG_INFO(priv, "Cancel firmware reload based on " |
1671 | "module parameter setting\n"); | |
1672 | break; | |
1673 | } | |
a93e7973 | 1674 | IWL_ERR(priv, "On demand firmware reload\n"); |
e649437f | 1675 | iwlagn_fw_error(priv, true); |
a93e7973 | 1676 | break; |
a93e7973 | 1677 | } |
a93e7973 WYG |
1678 | return 0; |
1679 | } | |
b74e31a9 | 1680 | |
d4daaea6 JB |
1681 | int iwl_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1682 | enum nl80211_iftype newtype, bool newp2p) | |
1683 | { | |
1684 | struct iwl_priv *priv = hw->priv; | |
1685 | struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif); | |
ebf8dc80 | 1686 | struct iwl_rxon_context *bss_ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
d4daaea6 | 1687 | struct iwl_rxon_context *tmp; |
5306c080 | 1688 | enum nl80211_iftype newviftype = newtype; |
d4daaea6 JB |
1689 | u32 interface_modes; |
1690 | int err; | |
1691 | ||
1692 | newtype = ieee80211_iftype_p2p(newtype, newp2p); | |
1693 | ||
1694 | mutex_lock(&priv->mutex); | |
1695 | ||
a2b76b3b JB |
1696 | if (!ctx->vif || !iwl_is_ready_rf(priv)) { |
1697 | /* | |
1698 | * Huh? But wait ... this can maybe happen when | |
1699 | * we're in the middle of a firmware restart! | |
1700 | */ | |
1701 | err = -EBUSY; | |
1702 | goto out; | |
1703 | } | |
1704 | ||
d4daaea6 JB |
1705 | interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes; |
1706 | ||
1707 | if (!(interface_modes & BIT(newtype))) { | |
1708 | err = -EBUSY; | |
1709 | goto out; | |
1710 | } | |
1711 | ||
ebf8dc80 JB |
1712 | /* |
1713 | * Refuse a change that should be done by moving from the PAN | |
1714 | * context to the BSS context instead, if the BSS context is | |
1715 | * available and can support the new interface type. | |
1716 | */ | |
1717 | if (ctx->ctxid == IWL_RXON_CTX_PAN && !bss_ctx->vif && | |
1718 | (bss_ctx->interface_modes & BIT(newtype) || | |
1719 | bss_ctx->exclusive_interface_modes & BIT(newtype))) { | |
1720 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | |
1721 | err = -EBUSY; | |
1722 | goto out; | |
1723 | } | |
1724 | ||
d4daaea6 JB |
1725 | if (ctx->exclusive_interface_modes & BIT(newtype)) { |
1726 | for_each_context(priv, tmp) { | |
1727 | if (ctx == tmp) | |
1728 | continue; | |
1729 | ||
1730 | if (!tmp->vif) | |
1731 | continue; | |
1732 | ||
1733 | /* | |
1734 | * The current mode switch would be exclusive, but | |
1735 | * another context is active ... refuse the switch. | |
1736 | */ | |
1737 | err = -EBUSY; | |
1738 | goto out; | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | /* success */ | |
1743 | iwl_teardown_interface(priv, vif, true); | |
5306c080 | 1744 | vif->type = newviftype; |
a2b76b3b | 1745 | vif->p2p = newp2p; |
d4daaea6 JB |
1746 | err = iwl_setup_interface(priv, ctx); |
1747 | WARN_ON(err); | |
1748 | /* | |
1749 | * We've switched internally, but submitting to the | |
1750 | * device may have failed for some reason. Mask this | |
1751 | * error, because otherwise mac80211 will not switch | |
1752 | * (and set the interface type back) and we'll be | |
1753 | * out of sync with it. | |
1754 | */ | |
1755 | err = 0; | |
1756 | ||
1757 | out: | |
1758 | mutex_unlock(&priv->mutex); | |
1759 | return err; | |
1760 | } | |
d4daaea6 | 1761 | |
b74e31a9 | 1762 | /* |
22de94de SG |
1763 | * On every watchdog tick we check (latest) time stamp. If it does not |
1764 | * change during timeout period and queue is not empty we reset firmware. | |
b74e31a9 | 1765 | */ |
b74e31a9 WYG |
1766 | static int iwl_check_stuck_queue(struct iwl_priv *priv, int cnt) |
1767 | { | |
22de94de SG |
1768 | struct iwl_tx_queue *txq = &priv->txq[cnt]; |
1769 | struct iwl_queue *q = &txq->q; | |
1770 | unsigned long timeout; | |
1771 | int ret; | |
b74e31a9 | 1772 | |
22de94de SG |
1773 | if (q->read_ptr == q->write_ptr) { |
1774 | txq->time_stamp = jiffies; | |
7cb1b088 | 1775 | return 0; |
22de94de | 1776 | } |
7cb1b088 | 1777 | |
22de94de SG |
1778 | timeout = txq->time_stamp + |
1779 | msecs_to_jiffies(priv->cfg->base_params->wd_timeout); | |
1780 | ||
1781 | if (time_after(jiffies, timeout)) { | |
1782 | IWL_ERR(priv, "Queue %d stuck for %u ms.\n", | |
1783 | q->id, priv->cfg->base_params->wd_timeout); | |
1784 | ret = iwl_force_reset(priv, IWL_FW_RESET, false); | |
1785 | return (ret == -EAGAIN) ? 0 : 1; | |
b74e31a9 | 1786 | } |
22de94de | 1787 | |
b74e31a9 WYG |
1788 | return 0; |
1789 | } | |
1790 | ||
22de94de SG |
1791 | /* |
1792 | * Making watchdog tick be a quarter of timeout assure we will | |
1793 | * discover the queue hung between timeout and 1.25*timeout | |
1794 | */ | |
1795 | #define IWL_WD_TICK(timeout) ((timeout) / 4) | |
1796 | ||
1797 | /* | |
1798 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
1799 | * we reset the firmware. If everything is fine just rearm the timer. | |
1800 | */ | |
1801 | void iwl_bg_watchdog(unsigned long data) | |
b74e31a9 WYG |
1802 | { |
1803 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
1804 | int cnt; | |
22de94de | 1805 | unsigned long timeout; |
b74e31a9 WYG |
1806 | |
1807 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1808 | return; | |
1809 | ||
22de94de SG |
1810 | timeout = priv->cfg->base_params->wd_timeout; |
1811 | if (timeout == 0) | |
1812 | return; | |
1813 | ||
b74e31a9 | 1814 | /* monitor and check for stuck cmd queue */ |
13bb9483 | 1815 | if (iwl_check_stuck_queue(priv, priv->cmd_queue)) |
b74e31a9 WYG |
1816 | return; |
1817 | ||
1818 | /* monitor and check for other stuck queues */ | |
246ed355 | 1819 | if (iwl_is_any_associated(priv)) { |
b74e31a9 WYG |
1820 | for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) { |
1821 | /* skip as we already checked the command queue */ | |
13bb9483 | 1822 | if (cnt == priv->cmd_queue) |
b74e31a9 WYG |
1823 | continue; |
1824 | if (iwl_check_stuck_queue(priv, cnt)) | |
1825 | return; | |
1826 | } | |
1827 | } | |
22de94de SG |
1828 | |
1829 | mod_timer(&priv->watchdog, jiffies + | |
1830 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
b74e31a9 | 1831 | } |
22de94de SG |
1832 | |
1833 | void iwl_setup_watchdog(struct iwl_priv *priv) | |
1834 | { | |
1835 | unsigned int timeout = priv->cfg->base_params->wd_timeout; | |
afbdd69a | 1836 | |
300d0834 | 1837 | if (timeout && !iwlagn_mod_params.wd_disable) |
22de94de SG |
1838 | mod_timer(&priv->watchdog, |
1839 | jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1840 | else | |
1841 | del_timer(&priv->watchdog); | |
1842 | } | |
a0ee74cf WYG |
1843 | |
1844 | /* | |
1845 | * extended beacon time format | |
1846 | * time in usec will be changed into a 32-bit value in extended:internal format | |
1847 | * the extended part is the beacon counts | |
1848 | * the internal part is the time in usec within one beacon interval | |
1849 | */ | |
1850 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval) | |
1851 | { | |
1852 | u32 quot; | |
1853 | u32 rem; | |
1854 | u32 interval = beacon_interval * TIME_UNIT; | |
1855 | ||
1856 | if (!interval || !usec) | |
1857 | return 0; | |
1858 | ||
1859 | quot = (usec / interval) & | |
1860 | (iwl_beacon_time_mask_high(priv, | |
1861 | priv->hw_params.beacon_time_tsf_bits) >> | |
1862 | priv->hw_params.beacon_time_tsf_bits); | |
1863 | rem = (usec % interval) & iwl_beacon_time_mask_low(priv, | |
1864 | priv->hw_params.beacon_time_tsf_bits); | |
1865 | ||
1866 | return (quot << priv->hw_params.beacon_time_tsf_bits) + rem; | |
1867 | } | |
a0ee74cf WYG |
1868 | |
1869 | /* base is usually what we get from ucode with each received frame, | |
1870 | * the same as HW timer counter counting down | |
1871 | */ | |
1872 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | |
1873 | u32 addon, u32 beacon_interval) | |
1874 | { | |
1875 | u32 base_low = base & iwl_beacon_time_mask_low(priv, | |
1876 | priv->hw_params.beacon_time_tsf_bits); | |
1877 | u32 addon_low = addon & iwl_beacon_time_mask_low(priv, | |
1878 | priv->hw_params.beacon_time_tsf_bits); | |
1879 | u32 interval = beacon_interval * TIME_UNIT; | |
1880 | u32 res = (base & iwl_beacon_time_mask_high(priv, | |
1881 | priv->hw_params.beacon_time_tsf_bits)) + | |
1882 | (addon & iwl_beacon_time_mask_high(priv, | |
1883 | priv->hw_params.beacon_time_tsf_bits)); | |
1884 | ||
1885 | if (base_low > addon_low) | |
1886 | res += base_low - addon_low; | |
1887 | else if (base_low < addon_low) { | |
1888 | res += interval + base_low - addon_low; | |
1889 | res += (1 << priv->hw_params.beacon_time_tsf_bits); | |
1890 | } else | |
1891 | res += (1 << priv->hw_params.beacon_time_tsf_bits); | |
1892 | ||
1893 | return cpu_to_le32(res); | |
1894 | } | |
a0ee74cf | 1895 | |
6da3a13e WYG |
1896 | #ifdef CONFIG_PM |
1897 | ||
48d1a211 | 1898 | int iwl_suspend(struct iwl_priv *priv) |
6da3a13e | 1899 | { |
6da3a13e WYG |
1900 | /* |
1901 | * This function is called when system goes into suspend state | |
1902 | * mac80211 will call iwl_mac_stop() from the mac80211 suspend function | |
1903 | * first but since iwl_mac_stop() has no knowledge of who the caller is, | |
1904 | * it will not call apm_ops.stop() to stop the DMA operation. | |
1905 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
1906 | */ | |
14e8e4af | 1907 | iwl_apm_stop(priv); |
6da3a13e | 1908 | |
6da3a13e WYG |
1909 | return 0; |
1910 | } | |
6da3a13e | 1911 | |
48d1a211 | 1912 | int iwl_resume(struct iwl_priv *priv) |
6da3a13e | 1913 | { |
0ab84cff | 1914 | bool hw_rfkill = false; |
6da3a13e | 1915 | |
6da3a13e WYG |
1916 | iwl_enable_interrupts(priv); |
1917 | ||
0ab84cff JB |
1918 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
1919 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1920 | hw_rfkill = true; | |
1921 | ||
1922 | if (hw_rfkill) | |
1923 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1924 | else | |
1925 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
1926 | ||
1927 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rfkill); | |
1928 | ||
6da3a13e WYG |
1929 | return 0; |
1930 | } | |
6da3a13e WYG |
1931 | |
1932 | #endif /* CONFIG_PM */ |