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iwlwifi: control led while update tx/rx bytes counts
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
1933ac4d
WYG		 49static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
50 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
51 0, COEX_UNASSOC_IDLE_FLAGS},
52 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
53 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
54 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
55 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
56 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
57 0, COEX_CALIBRATION_FLAGS},
58 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
59 0, COEX_PERIODIC_CALIBRATION_FLAGS},
60 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
61 0, COEX_CONNECTION_ESTAB_FLAGS},
62 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
63 0, COEX_ASSOCIATED_IDLE_FLAGS},
64 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
65 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
66 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
67 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
68 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
69 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
70 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
71 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
72 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
73 0, COEX_STAND_ALONE_DEBUG_FLAGS},
74 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
75 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
76 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
77 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
78};
79
c7de35cd
RR		 80#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
81 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
82 IWL_RATE_SISO_##s##M_PLCP, \
83 IWL_RATE_MIMO2_##s##M_PLCP,\
84 IWL_RATE_MIMO3_##s##M_PLCP,\
85 IWL_RATE_##r##M_IEEE, \
86 IWL_RATE_##ip##M_INDEX, \
87 IWL_RATE_##in##M_INDEX, \
88 IWL_RATE_##rp##M_INDEX, \
89 IWL_RATE_##rn##M_INDEX, \
90 IWL_RATE_##pp##M_INDEX, \
91 IWL_RATE_##np##M_INDEX }
92
a562a9dd
RC		 93u32 iwl_debug_level;
94EXPORT_SYMBOL(iwl_debug_level);
95
ef850d7c
MA		 96static irqreturn_t iwl_isr(int irq, void *data);
97
c7de35cd
RR		 98/*
99 * Parameter order:
100 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
101 *
102 * If there isn't a valid next or previous rate then INV is used which
103 * maps to IWL_RATE_INVALID
104 *
105 */
1826dcc0 106const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 107 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
108 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
109 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
110 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
111 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
112 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
113 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
114 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
115 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
116 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
117 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
118 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
119 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
120 /* FIXME:RS: ^^ should be INV (legacy) */
121};
1826dcc0 122EXPORT_SYMBOL(iwl_rates);
c7de35cd 123
e7d326ac
TW		 124/**
125 * translate ucode response to mac80211 tx status control values
126 */
127void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 128 struct ieee80211_tx_info *info)
e7d326ac 129{
e6a9854b 130 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 131
e6a9854b 132 info->antenna_sel_tx =
e7d326ac
TW		 133 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
134 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 135 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 136 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 137 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 138 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 139 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 140 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 141 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 142 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 143 r->flags |= IEEE80211_TX_RC_SHORT_GI;
31513be8 144 r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
e7d326ac
TW		 145}
146EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
147
148int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
149{
150 int idx = 0;
151
152 /* HT rate format */
153 if (rate_n_flags & RATE_MCS_HT_MSK) {
154 idx = (rate_n_flags & 0xff);
155
60d32215
DH		 156 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
157 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
158 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 159 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
160
161 idx += IWL_FIRST_OFDM_RATE;
162 /* skip 9M not supported in ht*/
163 if (idx >= IWL_RATE_9M_INDEX)
164 idx += 1;
165 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
166 return idx;
167
168 /* legacy rate format, search for match in table */
169 } else {
170 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
171 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
172 return idx;
173 }
174
175 return -1;
176}
177EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
178
31513be8
DH		 179int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
180{
181 int idx = 0;
182 int band_offset = 0;
183
184 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
185 if (rate_n_flags & RATE_MCS_HT_MSK) {
186 idx = (rate_n_flags & 0xff);
187 return idx;
188 /* Legacy rate format, search for match in table */
189 } else {
190 if (band == IEEE80211_BAND_5GHZ)
191 band_offset = IWL_FIRST_OFDM_RATE;
192 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
193 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
194 return idx - band_offset;
195 }
196
197 return -1;
198}
199
76eff18b
TW		 200u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
201{
202 int i;
203 u8 ind = ant;
204 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
205 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
206 if (priv->hw_params.valid_tx_ant & BIT(ind))
207 return ind;
208 }
209 return ant;
210}
47ff65c4 211EXPORT_SYMBOL(iwl_toggle_tx_ant);
57bd1bea
TW		 212
213const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
214EXPORT_SYMBOL(iwl_bcast_addr);
215
216
1d0a082d
AK		 217/* This function both allocates and initializes hw and priv. */
218struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
219 struct ieee80211_ops *hw_ops)
220{
221 struct iwl_priv *priv;
222
223 /* mac80211 allocates memory for this device instance, including
224 * space for this driver's private structure */
225 struct ieee80211_hw *hw =
226 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
227 if (hw == NULL) {
a3139c59
SO		 228 printk(KERN_ERR "%s: Can not allocate network device\n",
229 cfg->name);
1d0a082d
AK		 230 goto out;
231 }
232
233 priv = hw->priv;
234 priv->hw = hw;
235
236out:
237 return hw;
238}
239EXPORT_SYMBOL(iwl_alloc_all);
240
b661c819
TW		 241void iwl_hw_detect(struct iwl_priv *priv)
242{
243 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
244 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
245 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
246}
247EXPORT_SYMBOL(iwl_hw_detect);
248
1053d35f
RR		 249int iwl_hw_nic_init(struct iwl_priv *priv)
250{
251 unsigned long flags;
252 struct iwl_rx_queue *rxq = &priv->rxq;
253 int ret;
254
255 /* nic_init */
1053d35f 256 spin_lock_irqsave(&priv->lock, flags);
1b73af82 257 priv->cfg->ops->lib->apm_ops.init(priv);
74ba67ed
BC		 258
259 /* Set interrupt coalescing timer to 512 usecs */
260 iwl_write8(priv, CSR_INT_COALESCING, 512 / 32);
261
1053d35f
RR		 262 spin_unlock_irqrestore(&priv->lock, flags);
263
264 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
265
266 priv->cfg->ops->lib->apm_ops.config(priv);
267
268 /* Allocate the RX queue, or reset if it is already allocated */
269 if (!rxq->bd) {
270 ret = iwl_rx_queue_alloc(priv);
271 if (ret) {
15b1687c 272 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 273 return -ENOMEM;
274 }
275 } else
276 iwl_rx_queue_reset(priv, rxq);
277
278 iwl_rx_replenish(priv);
279
280 iwl_rx_init(priv, rxq);
281
282 spin_lock_irqsave(&priv->lock, flags);
283
284 rxq->need_update = 1;
285 iwl_rx_queue_update_write_ptr(priv, rxq);
286
287 spin_unlock_irqrestore(&priv->lock, flags);
288
289 /* Allocate and init all Tx and Command queues */
290 ret = iwl_txq_ctx_reset(priv);
291 if (ret)
292 return ret;
293
294 set_bit(STATUS_INIT, &priv->status);
295
296 return 0;
297}
298EXPORT_SYMBOL(iwl_hw_nic_init);
299
14d2aac5
AK		 300/*
301 * QoS support
302*/
303void iwl_activate_qos(struct iwl_priv *priv, u8 force)
304{
305 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
306 return;
307
308 priv->qos_data.def_qos_parm.qos_flags = 0;
309
310 if (priv->qos_data.qos_cap.q_AP.queue_request &&
311 !priv->qos_data.qos_cap.q_AP.txop_request)
312 priv->qos_data.def_qos_parm.qos_flags |=
313 QOS_PARAM_FLG_TXOP_TYPE_MSK;
314 if (priv->qos_data.qos_active)
315 priv->qos_data.def_qos_parm.qos_flags |=
316 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
317
318 if (priv->current_ht_config.is_ht)
319 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
320
321 if (force || iwl_is_associated(priv)) {
322 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
323 priv->qos_data.qos_active,
324 priv->qos_data.def_qos_parm.qos_flags);
325
326 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
327 sizeof(struct iwl_qosparam_cmd),
328 &priv->qos_data.def_qos_parm, NULL);
329 }
330}
331EXPORT_SYMBOL(iwl_activate_qos);
332
f2c95b04
WYG		 333/*
334 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
335 * (802.11b) (802.11a/g)
336 * AC_BK 15 1023 7 0 0
337 * AC_BE 15 1023 3 0 0
338 * AC_VI 7 15 2 6.016ms 3.008ms
339 * AC_VO 3 7 2 3.264ms 1.504ms
340 */
c7de35cd 341void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 342{
343 u16 cw_min = 15;
344 u16 cw_max = 1023;
345 u8 aifs = 2;
30dab79e 346 bool is_legacy = false;
bf85ea4f
AK		 347 unsigned long flags;
348 int i;
349
350 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 351 /* QoS always active in AP and ADHOC mode
352 * In STA mode wait for association
353 */
354 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
355 priv->iw_mode == NL80211_IFTYPE_AP)
356 priv->qos_data.qos_active = 1;
357 else
358 priv->qos_data.qos_active = 0;
bf85ea4f 359
30dab79e
WT		 360 /* check for legacy mode */
361 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
362 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
363 (priv->iw_mode == NL80211_IFTYPE_STATION &&
364 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 365 cw_min = 31;
366 is_legacy = 1;
367 }
368
369 if (priv->qos_data.qos_active)
370 aifs = 3;
371
f2c95b04 372 /* AC_BE */
bf85ea4f
AK		 373 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
374 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
375 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
376 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
377 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
378
379 if (priv->qos_data.qos_active) {
f2c95b04 380 /* AC_BK */
bf85ea4f
AK		 381 i = 1;
382 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
383 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
384 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
385 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
386 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
387
f2c95b04 388 /* AC_VI */
bf85ea4f
AK		 389 i = 2;
390 priv->qos_data.def_qos_parm.ac[i].cw_min =
391 cpu_to_le16((cw_min + 1) / 2 - 1);
392 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 393 cpu_to_le16(cw_min);
bf85ea4f
AK		 394 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
395 if (is_legacy)
396 priv->qos_data.def_qos_parm.ac[i].edca_txop =
397 cpu_to_le16(6016);
398 else
399 priv->qos_data.def_qos_parm.ac[i].edca_txop =
400 cpu_to_le16(3008);
401 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
402
f2c95b04 403 /* AC_VO */
bf85ea4f
AK		 404 i = 3;
405 priv->qos_data.def_qos_parm.ac[i].cw_min =
406 cpu_to_le16((cw_min + 1) / 4 - 1);
407 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 408 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 409 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
410 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
411 if (is_legacy)
412 priv->qos_data.def_qos_parm.ac[i].edca_txop =
413 cpu_to_le16(3264);
414 else
415 priv->qos_data.def_qos_parm.ac[i].edca_txop =
416 cpu_to_le16(1504);
417 } else {
418 for (i = 1; i < 4; i++) {
419 priv->qos_data.def_qos_parm.ac[i].cw_min =
420 cpu_to_le16(cw_min);
421 priv->qos_data.def_qos_parm.ac[i].cw_max =
422 cpu_to_le16(cw_max);
423 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
424 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
425 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
426 }
427 }
e1623446 428 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 429
430 spin_unlock_irqrestore(&priv->lock, flags);
431}
c7de35cd
RR		 432EXPORT_SYMBOL(iwl_reset_qos);
433
d9fe60de
JB		 434#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
435#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 436static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 437 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 438 enum ieee80211_band band)
439{
39130df3
RR		 440 u16 max_bit_rate = 0;
441 u8 rx_chains_num = priv->hw_params.rx_chains_num;
442 u8 tx_chains_num = priv->hw_params.tx_chains_num;
443
c7de35cd 444 ht_info->cap = 0;
d9fe60de 445 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 446
d9fe60de 447 ht_info->ht_supported = true;
c7de35cd 448
b261793d
DH		 449 if (priv->cfg->ht_greenfield_support)
450 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de 451 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3f3e0376
WYG		 452 if (priv->cfg->support_sm_ps)
453 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
454 (WLAN_HT_CAP_SM_PS_DYNAMIC << 2));
455 else
456 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
457 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 458
459 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 460 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 461 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
462 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
463 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 464 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 465 }
c7de35cd
RR		 466
467 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 468 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 469
470 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
471 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
472
d9fe60de 473 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 474 if (rx_chains_num >= 2)
d9fe60de 475 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 476 if (rx_chains_num >= 3)
d9fe60de 477 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 478
479 /* Highest supported Rx data rate */
480 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 481 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
482 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 483
484 /* Tx MCS capabilities */
d9fe60de 485 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 486 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 487 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
488 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
489 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 490 }
c7de35cd 491}
c7de35cd 492
c7de35cd
RR		 493/**
494 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
495 */
534166de 496int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 497{
498 struct iwl_channel_info *ch;
499 struct ieee80211_supported_band *sband;
500 struct ieee80211_channel *channels;
501 struct ieee80211_channel *geo_ch;
502 struct ieee80211_rate *rates;
503 int i = 0;
504
505 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
506 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 507 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 508 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
509 return 0;
510 }
511
512 channels = kzalloc(sizeof(struct ieee80211_channel) *
513 priv->channel_count, GFP_KERNEL);
514 if (!channels)
515 return -ENOMEM;
516
5027309b 517 rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
c7de35cd
RR		 518 GFP_KERNEL);
519 if (!rates) {
520 kfree(channels);
521 return -ENOMEM;
522 }
523
524 /* 5.2GHz channels start after the 2.4GHz channels */
525 sband = &priv->bands[IEEE80211_BAND_5GHZ];
526 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
527 /* just OFDM */
528 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 529 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 530
49779293 531 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 532 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 533 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 534
535 sband = &priv->bands[IEEE80211_BAND_2GHZ];
536 sband->channels = channels;
537 /* OFDM & CCK */
538 sband->bitrates = rates;
5027309b 539 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 540
49779293 541 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 542 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 543 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 544
545 priv->ieee_channels = channels;
546 priv->ieee_rates = rates;
547
c7de35cd
RR		 548 for (i = 0; i < priv->channel_count; i++) {
549 ch = &priv->channel_info[i];
550
551 /* FIXME: might be removed if scan is OK */
552 if (!is_channel_valid(ch))
553 continue;
554
555 if (is_channel_a_band(ch))
556 sband = &priv->bands[IEEE80211_BAND_5GHZ];
557 else
558 sband = &priv->bands[IEEE80211_BAND_2GHZ];
559
560 geo_ch = &sband->channels[sband->n_channels++];
561
562 geo_ch->center_freq =
563 ieee80211_channel_to_frequency(ch->channel);
564 geo_ch->max_power = ch->max_power_avg;
565 geo_ch->max_antenna_gain = 0xff;
566 geo_ch->hw_value = ch->channel;
567
568 if (is_channel_valid(ch)) {
569 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
570 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
571
572 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
573 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
574
575 if (ch->flags & EEPROM_CHANNEL_RADAR)
576 geo_ch->flags |= IEEE80211_CHAN_RADAR;
577
7aafef1c 578 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 579
dc1b0973
WYG		 580 if (ch->max_power_avg > priv->tx_power_device_lmt)
581 priv->tx_power_device_lmt = ch->max_power_avg;
c7de35cd
RR		 582 } else {
583 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
584 }
585
e1623446 586 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 587 ch->channel, geo_ch->center_freq,
588 is_channel_a_band(ch) ? "5.2" : "2.4",
589 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
590 "restricted" : "valid",
591 geo_ch->flags);
592 }
593
594 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
595 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 596 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
597 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 598 priv->pci_dev->device,
599 priv->pci_dev->subsystem_device);
c7de35cd
RR		 600 priv->cfg->sku &= ~IWL_SKU_A;
601 }
602
978785a3 603 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 604 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
605 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 606
607 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
608
609 return 0;
610}
534166de 611EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 612
613/*
614 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
615 */
534166de 616void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 617{
618 kfree(priv->ieee_channels);
619 kfree(priv->ieee_rates);
620 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
621}
534166de 622EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 623
37dc70fe
AK		 624/*
625 * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
626 * function.
627 */
628void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
629 __le32 *tx_flags)
630{
631 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
632 *tx_flags |= TX_CMD_FLG_RTS_MSK;
633 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
634 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
635 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
636 *tx_flags |= TX_CMD_FLG_CTS_MSK;
637 }
638}
639EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
640
28a6b07a 641static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 642{
643 return !priv->current_ht_config.is_ht ||
02bb1bea 644 priv->current_ht_config.single_chain_sufficient;
c7de35cd 645}
963f5517 646
47c5196e
TW		 647static u8 iwl_is_channel_extension(struct iwl_priv *priv,
648 enum ieee80211_band band,
649 u16 channel, u8 extension_chan_offset)
650{
651 const struct iwl_channel_info *ch_info;
652
653 ch_info = iwl_get_channel_info(priv, band, channel);
654 if (!is_channel_valid(ch_info))
655 return 0;
656
d9fe60de 657 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 658 return !(ch_info->ht40_extension_channel &
689da1b3 659 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 660 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 661 return !(ch_info->ht40_extension_channel &
689da1b3 662 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 663
664 return 0;
665}
666
7aafef1c 667u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 668 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e 669{
fad95bf5 670 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
47c5196e 671
fad95bf5 672 if (!ht_conf->is_ht || !ht_conf->is_40mhz)
47c5196e
TW		 673 return 0;
674
a2b0f02e
WYG		 675 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
676 * the bit will not set if it is pure 40MHz case
677 */
47c5196e 678 if (sta_ht_inf) {
a2b0f02e 679 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 680 return 0;
681 }
1e4247d4
WYG		 682#ifdef CONFIG_IWLWIFI_DEBUG
683 if (priv->disable_ht40)
684 return 0;
685#endif
611d3eb7
WYG		 686 return iwl_is_channel_extension(priv, priv->band,
687 le16_to_cpu(priv->staging_rxon.channel),
fad95bf5 688 ht_conf->extension_chan_offset);
47c5196e 689}
7aafef1c 690EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 691
2c2f3b33
TW		 692static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
693{
694 u16 new_val = 0;
695 u16 beacon_factor = 0;
696
697 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
698 new_val = beacon_val / beacon_factor;
699
700 if (!new_val)
701 new_val = max_beacon_val;
702
703 return new_val;
704}
705
706void iwl_setup_rxon_timing(struct iwl_priv *priv)
707{
708 u64 tsf;
709 s32 interval_tm, rem;
710 unsigned long flags;
711 struct ieee80211_conf *conf = NULL;
712 u16 beacon_int;
713
714 conf = ieee80211_get_hw_conf(priv->hw);
715
716 spin_lock_irqsave(&priv->lock, flags);
717 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
718 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
719
720 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
721 beacon_int = priv->beacon_int;
722 priv->rxon_timing.atim_window = 0;
723 } else {
724 beacon_int = priv->vif->bss_conf.beacon_int;
725
726 /* TODO: we need to get atim_window from upper stack
727 * for now we set to 0 */
728 priv->rxon_timing.atim_window = 0;
729 }
730
731 beacon_int = iwl_adjust_beacon_interval(beacon_int,
732 priv->hw_params.max_beacon_itrvl * 1024);
733 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
734
735 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
736 interval_tm = beacon_int * 1024;
737 rem = do_div(tsf, interval_tm);
738 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
739
740 spin_unlock_irqrestore(&priv->lock, flags);
741 IWL_DEBUG_ASSOC(priv,
742 "beacon interval %d beacon timer %d beacon tim %d\n",
743 le16_to_cpu(priv->rxon_timing.beacon_interval),
744 le32_to_cpu(priv->rxon_timing.beacon_init_val),
745 le16_to_cpu(priv->rxon_timing.atim_window));
746}
747EXPORT_SYMBOL(iwl_setup_rxon_timing);
748
8ccde88a
SO		 749void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
750{
751 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
752
753 if (hw_decrypt)
754 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
755 else
756 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
757
758}
759EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
760
761/**
762 * iwl_check_rxon_cmd - validate RXON structure is valid
763 *
764 * NOTE: This is really only useful during development and can eventually
765 * be #ifdef'd out once the driver is stable and folks aren't actively
766 * making changes
767 */
768int iwl_check_rxon_cmd(struct iwl_priv *priv)
769{
770 int error = 0;
771 int counter = 1;
772 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
773
774 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
775 error |= le32_to_cpu(rxon->flags &
776 (RXON_FLG_TGJ_NARROW_BAND_MSK |
777 RXON_FLG_RADAR_DETECT_MSK));
778 if (error)
779 IWL_WARN(priv, "check 24G fields %d | %d\n",
780 counter++, error);
781 } else {
782 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
783 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
784 if (error)
785 IWL_WARN(priv, "check 52 fields %d | %d\n",
786 counter++, error);
787 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
788 if (error)
789 IWL_WARN(priv, "check 52 CCK %d | %d\n",
790 counter++, error);
791 }
792 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
793 if (error)
794 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
795
796 /* make sure basic rates 6Mbps and 1Mbps are supported */
797 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
798 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
799 if (error)
800 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
801
802 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
803 if (error)
804 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
805
806 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
807 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
808 if (error)
809 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
810 counter++, error);
811
812 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
813 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
814 if (error)
815 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
816 counter++, error);
817
818 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
819 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
820 if (error)
821 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
822 counter++, error);
823
824 if (error)
825 IWL_WARN(priv, "Tuning to channel %d\n",
826 le16_to_cpu(rxon->channel));
827
828 if (error) {
829 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
830 return -1;
831 }
832 return 0;
833}
834EXPORT_SYMBOL(iwl_check_rxon_cmd);
835
836/**
837 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
838 * @priv: staging_rxon is compared to active_rxon
839 *
840 * If the RXON structure is changing enough to require a new tune,
841 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
842 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
843 */
844int iwl_full_rxon_required(struct iwl_priv *priv)
845{
846
847 /* These items are only settable from the full RXON command */
848 if (!(iwl_is_associated(priv)) ||
849 compare_ether_addr(priv->staging_rxon.bssid_addr,
850 priv->active_rxon.bssid_addr) ||
851 compare_ether_addr(priv->staging_rxon.node_addr,
852 priv->active_rxon.node_addr) ||
853 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
854 priv->active_rxon.wlap_bssid_addr) ||
855 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
856 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
857 (priv->staging_rxon.air_propagation !=
858 priv->active_rxon.air_propagation) ||
859 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
860 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
861 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
862 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 863 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
864 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 865 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
866 return 1;
867
868 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
869 * be updated with the RXON_ASSOC command -- however only some
870 * flag transitions are allowed using RXON_ASSOC */
871
872 /* Check if we are not switching bands */
873 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
874 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
875 return 1;
876
877 /* Check if we are switching association toggle */
878 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
879 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
880 return 1;
881
882 return 0;
883}
884EXPORT_SYMBOL(iwl_full_rxon_required);
885
886u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
887{
888 int i;
889 int rate_mask;
890
891 /* Set rate mask*/
892 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
893 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
894 else
895 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
896
897 /* Find lowest valid rate */
898 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
899 i = iwl_rates[i].next_ieee) {
900 if (rate_mask & (1 << i))
901 return iwl_rates[i].plcp;
902 }
903
904 /* No valid rate was found. Assign the lowest one */
905 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
906 return IWL_RATE_1M_PLCP;
907 else
908 return IWL_RATE_6M_PLCP;
909}
910EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
911
fad95bf5 912void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
47c5196e 913{
c1adf9fb 914 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 915
fad95bf5 916 if (!ht_conf->is_ht) {
a2b0f02e 917 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 918 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 919 RXON_FLG_HT40_PROT_MSK |
42eb7c64 920 RXON_FLG_HT_PROT_MSK);
47c5196e 921 return;
42eb7c64 922 }
47c5196e 923
a2b0f02e
WYG		 924 /* FIXME: if the definition of ht_protection changed, the "translation"
925 * will be needed for rxon->flags
926 */
fad95bf5 927 rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 928
929 /* Set up channel bandwidth:
7aafef1c 930 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 931 /* clear the HT channel mode before set the mode */
932 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
933 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 934 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
935 /* pure ht40 */
fad95bf5 936 if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 937 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 938 /* Note: control channel is opposite of extension channel */
fad95bf5 939 switch (ht_conf->extension_chan_offset) {
508b08e7
WYG		 940 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
941 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
942 break;
943 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
944 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
945 break;
946 }
947 } else {
a2b0f02e 948 /* Note: control channel is opposite of extension channel */
fad95bf5 949 switch (ht_conf->extension_chan_offset) {
a2b0f02e
WYG		 950 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
951 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
952 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
953 break;
954 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
955 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
956 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
957 break;
958 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
959 default:
960 /* channel location only valid if in Mixed mode */
961 IWL_ERR(priv, "invalid extension channel offset\n");
962 break;
963 }
964 }
965 } else {
966 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 967 }
968
45823531
AK		 969 if (priv->cfg->ops->hcmd->set_rxon_chain)
970 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 971
02bb1bea 972 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 973 "extension channel offset 0x%x\n",
fad95bf5
JB		 974 le32_to_cpu(rxon->flags), ht_conf->ht_protection,
975 ht_conf->extension_chan_offset);
47c5196e
TW		 976 return;
977}
978EXPORT_SYMBOL(iwl_set_rxon_ht);
979
9e5e6c32
TW		 980#define IWL_NUM_RX_CHAINS_MULTIPLE 3
981#define IWL_NUM_RX_CHAINS_SINGLE 2
982#define IWL_NUM_IDLE_CHAINS_DUAL 2
983#define IWL_NUM_IDLE_CHAINS_SINGLE 1
984
2b396a12
JB		 985/*
986 * Determine how many receiver/antenna chains to use.
987 *
988 * More provides better reception via diversity. Fewer saves power
989 * at the expense of throughput, but only when not in powersave to
990 * start with.
991 *
c7de35cd
RR		 992 * MIMO (dual stream) requires at least 2, but works better with 3.
993 * This does not determine *which* chains to use, just how many.
994 */
28a6b07a 995static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 996{
c7de35cd 997 /* # of Rx chains to use when expecting MIMO. */
02bb1bea 998 if (is_single_rx_stream(priv))
9e5e6c32 999 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 1000 else
9e5e6c32 1001 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 1002}
c7de35cd 1003
2b396a12 1004/*
3f3e0376
WYG		 1005 * When we are in power saving mode, unless device support spatial
1006 * multiplexing power save, use the active count for rx chain count.
2b396a12 1007 */
28a6b07a
TW		 1008static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1009{
3f3e0376
WYG		 1010 int idle_cnt = active_cnt;
1011 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
1012
1013 if (priv->cfg->support_sm_ps) {
1014 /* # Rx chains when idling and maybe trying to save power */
1015 switch (priv->current_ht_config.sm_ps) {
1016 case WLAN_HT_CAP_SM_PS_STATIC:
1017 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1018 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
1019 IWL_NUM_IDLE_CHAINS_SINGLE;
1020 break;
1021 case WLAN_HT_CAP_SM_PS_DISABLED:
1022 idle_cnt = (is_cam) ? active_cnt :
1023 IWL_NUM_IDLE_CHAINS_SINGLE;
1024 break;
1025 case WLAN_HT_CAP_SM_PS_INVALID:
1026 default:
1027 IWL_ERR(priv, "invalid sm_ps mode %d\n",
1028 priv->current_ht_config.sm_ps);
1029 WARN_ON(1);
1030 break;
1031 }
1032 }
1033 return idle_cnt;
c7de35cd
RR		 1034}
1035
04816448
GE		 1036/* up to 4 chains */
1037static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1038{
1039 u8 res;
1040 res = (chain_bitmap & BIT(0)) >> 0;
1041 res += (chain_bitmap & BIT(1)) >> 1;
1042 res += (chain_bitmap & BIT(2)) >> 2;
9bddbab3 1043 res += (chain_bitmap & BIT(3)) >> 3;
04816448
GE		 1044 return res;
1045}
1046
4c4df78f
CR		 1047/**
1048 * iwl_is_monitor_mode - Determine if interface in monitor mode
1049 *
1050 * priv->iw_mode is set in add_interface, but add_interface is
1051 * never called for monitor mode. The only way mac80211 informs us about
1052 * monitor mode is through configuring filters (call to configure_filter).
1053 */
279b05d4 1054bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1055{
1056 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1057}
279b05d4 1058EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1059
c7de35cd
RR		 1060/**
1061 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1062 *
1063 * Selects how many and which Rx receivers/antennas/chains to use.
1064 * This should not be used for scan command ... it puts data in wrong place.
1065 */
1066void iwl_set_rxon_chain(struct iwl_priv *priv)
1067{
28a6b07a
TW		 1068 bool is_single = is_single_rx_stream(priv);
1069 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1070 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1071 u32 active_chains;
28a6b07a 1072 u16 rx_chain;
c7de35cd
RR		 1073
1074 /* Tell uCode which antennas are actually connected.
1075 * Before first association, we assume all antennas are connected.
1076 * Just after first association, iwl_chain_noise_calibration()
1077 * checks which antennas actually *are* connected. */
04816448
GE		 1078 if (priv->chain_noise_data.active_chains)
1079 active_chains = priv->chain_noise_data.active_chains;
1080 else
1081 active_chains = priv->hw_params.valid_rx_ant;
1082
1083 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1084
1085 /* How many receivers should we use? */
28a6b07a
TW		 1086 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1087 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1088
28a6b07a 1089
04816448
GE		 1090 /* correct rx chain count according hw settings
1091 * and chain noise calibration
1092 */
1093 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1094 if (valid_rx_cnt < active_rx_cnt)
1095 active_rx_cnt = valid_rx_cnt;
1096
1097 if (valid_rx_cnt < idle_rx_cnt)
1098 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1099
1100 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1101 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1102
7b841727
RF		 1103 /* copied from 'iwl_bg_request_scan()' */
1104 /* Force use of chains B and C (0x6) for Rx for 4965
1105 * Avoid A (0x1) because of its off-channel reception on A-band.
1106 * MIMO is not used here, but value is required */
1107 if (iwl_is_monitor_mode(priv) &&
1108 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1109 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1110 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1111 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1112 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1113 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1114 }
1115
28a6b07a
TW		 1116 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1117
9e5e6c32 1118 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1119 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1120 else
1121 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1122
e1623446 1123 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1124 priv->staging_rxon.rx_chain,
1125 active_rx_cnt, idle_rx_cnt);
1126
1127 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1128 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1129}
1130EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1131
1132/**
17e72782 1133 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1134 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1135 * @channel: Any channel valid for the requested phymode
1136
1137 * In addition to setting the staging RXON, priv->phymode is also set.
1138 *
1139 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1140 * in the staging RXON flag structure based on the phymode
1141 */
17e72782 1142int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1143{
17e72782
TW		 1144 enum ieee80211_band band = ch->band;
1145 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1146
8622e705 1147 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1148 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1149 channel, band);
1150 return -EINVAL;
1151 }
1152
1153 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1154 (priv->band == band))
1155 return 0;
1156
1157 priv->staging_rxon.channel = cpu_to_le16(channel);
1158 if (band == IEEE80211_BAND_5GHZ)
1159 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1160 else
1161 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1162
1163 priv->band = band;
1164
e1623446 1165 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1166
1167 return 0;
1168}
c7de35cd 1169EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1170
8ccde88a
SO		 1171void iwl_set_flags_for_band(struct iwl_priv *priv,
1172 enum ieee80211_band band)
1173{
1174 if (band == IEEE80211_BAND_5GHZ) {
1175 priv->staging_rxon.flags &=
1176 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1177 | RXON_FLG_CCK_MSK);
1178 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1179 } else {
1180 /* Copied from iwl_post_associate() */
1181 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1182 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1183 else
1184 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1185
1186 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1187 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1188
1189 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1190 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1191 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1192 }
1193}
8ccde88a
SO		 1194
1195/*
1196 * initialize rxon structure with default values from eeprom
1197 */
1198void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1199{
1200 const struct iwl_channel_info *ch_info;
1201
1202 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1203
1204 switch (mode) {
1205 case NL80211_IFTYPE_AP:
1206 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1207 break;
1208
1209 case NL80211_IFTYPE_STATION:
1210 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1211 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1212 break;
1213
1214 case NL80211_IFTYPE_ADHOC:
1215 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1216 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1217 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1218 RXON_FILTER_ACCEPT_GRP_MSK;
1219 break;
1220
8ccde88a
SO		 1221 default:
1222 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1223 break;
1224 }
1225
1226#if 0
1227 /* TODO: Figure out when short_preamble would be set and cache from
1228 * that */
1229 if (!hw_to_local(priv->hw)->short_preamble)
1230 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1231 else
1232 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1233#endif
1234
1235 ch_info = iwl_get_channel_info(priv, priv->band,
1236 le16_to_cpu(priv->active_rxon.channel));
1237
1238 if (!ch_info)
1239 ch_info = &priv->channel_info[0];
1240
1241 /*
1242 * in some case A channels are all non IBSS
1243 * in this case force B/G channel
1244 */
1245 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1246 !(is_channel_ibss(ch_info)))
1247 ch_info = &priv->channel_info[0];
1248
1249 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1250 priv->band = ch_info->band;
1251
1252 iwl_set_flags_for_band(priv, priv->band);
1253
1254 priv->staging_rxon.ofdm_basic_rates =
1255 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1256 priv->staging_rxon.cck_basic_rates =
1257 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1258
a2b0f02e
WYG		 1259 /* clear both MIX and PURE40 mode flag */
1260 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1261 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1262 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1263 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1264 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1265 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1266 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1267}
1268EXPORT_SYMBOL(iwl_connection_init_rx_config);
1269
782571f4 1270static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1271{
1272 const struct ieee80211_supported_band *hw = NULL;
1273 struct ieee80211_rate *rate;
1274 int i;
1275
1276 hw = iwl_get_hw_mode(priv, priv->band);
1277 if (!hw) {
1278 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1279 return;
1280 }
1281
1282 priv->active_rate = 0;
1283 priv->active_rate_basic = 0;
1284
1285 for (i = 0; i < hw->n_bitrates; i++) {
1286 rate = &(hw->bitrates[i]);
5027309b 1287 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 1288 priv->active_rate |= (1 << rate->hw_value);
1289 }
1290
e1623446 1291 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1292 priv->active_rate, priv->active_rate_basic);
1293
1294 /*
1295 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1296 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1297 * OFDM
1298 */
1299 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1300 priv->staging_rxon.cck_basic_rates =
1301 ((priv->active_rate_basic &
1302 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1303 else
1304 priv->staging_rxon.cck_basic_rates =
1305 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1306
1307 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1308 priv->staging_rxon.ofdm_basic_rates =
1309 ((priv->active_rate_basic &
1310 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1311 IWL_FIRST_OFDM_RATE) & 0xFF;
1312 else
1313 priv->staging_rxon.ofdm_basic_rates =
1314 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1315}
8ccde88a
SO		 1316
1317void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1318{
2f301227 1319 struct iwl_rx_packet *pkt = rxb_addr(rxb);
8ccde88a
SO		 1320 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1321 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
4a56e965 1322
0924e519
WYG		 1323 if (priv->switch_rxon.switch_in_progress) {
1324 if (!le32_to_cpu(csa->status) &&
1325 (csa->channel == priv->switch_rxon.channel)) {
1326 rxon->channel = csa->channel;
1327 priv->staging_rxon.channel = csa->channel;
1328 IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
1329 le16_to_cpu(csa->channel));
1330 } else
1331 IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
1332 le16_to_cpu(csa->channel));
1333
1334 priv->switch_rxon.switch_in_progress = false;
1335 }
8ccde88a
SO		 1336}
1337EXPORT_SYMBOL(iwl_rx_csa);
1338
1339#ifdef CONFIG_IWLWIFI_DEBUG
a643565e 1340void iwl_print_rx_config_cmd(struct iwl_priv *priv)
8ccde88a
SO		 1341{
1342 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1343
e1623446 1344 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1345 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1346 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1347 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1348 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1349 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1350 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1351 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1352 rxon->ofdm_basic_rates);
e1623446
TW		 1353 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1354 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1355 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1356 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1357}
a643565e 1358EXPORT_SYMBOL(iwl_print_rx_config_cmd);
6686d17e 1359#endif
8ccde88a
SO		 1360/**
1361 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1362 */
1363void iwl_irq_handle_error(struct iwl_priv *priv)
1364{
1365 /* Set the FW error flag -- cleared on iwl_down */
1366 set_bit(STATUS_FW_ERROR, &priv->status);
1367
1368 /* Cancel currently queued command. */
1369 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1370
1371#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1372 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
b7a79404
RC		 1373 priv->cfg->ops->lib->dump_nic_error_log(priv);
1374 priv->cfg->ops->lib->dump_nic_event_log(priv);
8ccde88a
SO		 1375 iwl_print_rx_config_cmd(priv);
1376 }
1377#endif
1378
1379 wake_up_interruptible(&priv->wait_command_queue);
1380
1381 /* Keep the restart process from trying to send host
1382 * commands by clearing the INIT status bit */
1383 clear_bit(STATUS_READY, &priv->status);
1384
1385 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1386 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1387 "Restarting adapter due to uCode error.\n");
1388
8ccde88a
SO		 1389 if (priv->cfg->mod_params->restart_fw)
1390 queue_work(priv->workqueue, &priv->restart);
1391 }
1392}
1393EXPORT_SYMBOL(iwl_irq_handle_error);
1394
d68b603c
AK		 1395int iwl_apm_stop_master(struct iwl_priv *priv)
1396{
5220af0c 1397 int ret = 0;
d68b603c 1398
5220af0c 1399 /* stop device's busmaster DMA activity */
d68b603c
AK		 1400 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1401
5220af0c 1402 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c 1403 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
5220af0c
BC		 1404 if (ret)
1405 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
d68b603c 1406
d68b603c
AK		 1407 IWL_DEBUG_INFO(priv, "stop master\n");
1408
5220af0c 1409 return ret;
d68b603c
AK		 1410}
1411EXPORT_SYMBOL(iwl_apm_stop_master);
1412
1413void iwl_apm_stop(struct iwl_priv *priv)
1414{
fadb3582
BC		 1415 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1416
5220af0c 1417 /* Stop device's DMA activity */
d68b603c
AK		 1418 iwl_apm_stop_master(priv);
1419
5220af0c 1420 /* Reset the entire device */
d68b603c
AK		 1421 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1422
1423 udelay(10);
5220af0c
BC		 1424
1425 /*
1426 * Clear "initialization complete" bit to move adapter from
1427 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
1428 */
d68b603c 1429 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
d68b603c
AK		 1430}
1431EXPORT_SYMBOL(iwl_apm_stop);
1432
fadb3582
BC		 1433
1434/*
1435 * Start up NIC's basic functionality after it has been reset
1436 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1437 * NOTE: This does not load uCode nor start the embedded processor
1438 */
1439int iwl_apm_init(struct iwl_priv *priv)
1440{
1441 int ret = 0;
1442 u16 lctl;
1443
1444 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1445
1446 /*
1447 * Use "set_bit" below rather than "write", to preserve any hardware
1448 * bits already set by default after reset.
1449 */
1450
1451 /* Disable L0S exit timer (platform NMI Work/Around) */
1452 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1453 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1454
1455 /*
1456 * Disable L0s without affecting L1;
1457 * don't wait for ICH L0s (ICH bug W/A)
1458 */
1459 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1460 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1461
1462 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1463 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1464
1465 /*
1466 * Enable HAP INTA (interrupt from management bus) to
1467 * wake device's PCI Express link L1a -> L0s
1468 * NOTE: This is no-op for 3945 (non-existant bit)
1469 */
1470 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1471 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1472
1473 /*
a6c5c731
BC		 1474 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1475 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1476 * If so (likely), disable L0S, so device moves directly L0->L1;
1477 * costs negligible amount of power savings.
1478 * If not (unlikely), enable L0S, so there is at least some
1479 * power savings, even without L1.
fadb3582
BC		 1480 */
1481 if (priv->cfg->set_l0s) {
1482 lctl = iwl_pcie_link_ctl(priv);
1483 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1484 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1485 /* L1-ASPM enabled; disable(!) L0S */
1486 iwl_set_bit(priv, CSR_GIO_REG,
1487 CSR_GIO_REG_VAL_L0S_ENABLED);
1488 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1489 } else {
1490 /* L1-ASPM disabled; enable(!) L0S */
1491 iwl_clear_bit(priv, CSR_GIO_REG,
1492 CSR_GIO_REG_VAL_L0S_ENABLED);
1493 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1494 }
1495 }
1496
1497 /* Configure analog phase-lock-loop before activating to D0A */
1498 if (priv->cfg->pll_cfg_val)
1499 iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
1500
1501 /*
1502 * Set "initialization complete" bit to move adapter from
1503 * D0U* --> D0A* (powered-up active) state.
1504 */
1505 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1506
1507 /*
1508 * Wait for clock stabilization; once stabilized, access to
1509 * device-internal resources is supported, e.g. iwl_write_prph()
1510 * and accesses to uCode SRAM.
1511 */
1512 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1513 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1514 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1515 if (ret < 0) {
1516 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1517 goto out;
1518 }
1519
1520 /*
1521 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
1522 * BSM (Boostrap State Machine) is only in 3945 and 4965;
1523 * later devices (i.e. 5000 and later) have non-volatile SRAM,
1524 * and don't need BSM to restore data after power-saving sleep.
1525 *
1526 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1527 * do not disable clocks. This preserves any hardware bits already
1528 * set by default in "CLK_CTRL_REG" after reset.
1529 */
1530 if (priv->cfg->use_bsm)
1531 iwl_write_prph(priv, APMG_CLK_EN_REG,
1532 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
1533 else
1534 iwl_write_prph(priv, APMG_CLK_EN_REG,
1535 APMG_CLK_VAL_DMA_CLK_RQT);
1536 udelay(20);
1537
1538 /* Disable L1-Active */
1539 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1540 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1541
1542out:
1543 return ret;
1544}
1545EXPORT_SYMBOL(iwl_apm_init);
1546
1547
1548
8ccde88a
SO		 1549void iwl_configure_filter(struct ieee80211_hw *hw,
1550 unsigned int changed_flags,
1551 unsigned int *total_flags,
3ac64bee 1552 u64 multicast)
8ccde88a
SO		 1553{
1554 struct iwl_priv *priv = hw->priv;
1555 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1556
e1623446 1557 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1558 changed_flags, *total_flags);
1559
1560 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1561 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1562 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1563 else
1564 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1565 }
1566 if (changed_flags & FIF_ALLMULTI) {
1567 if (*total_flags & FIF_ALLMULTI)
1568 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1569 else
1570 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1571 }
1572 if (changed_flags & FIF_CONTROL) {
1573 if (*total_flags & FIF_CONTROL)
1574 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1575 else
1576 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1577 }
1578 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1579 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1580 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1581 else
1582 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1583 }
1584
1585 /* We avoid iwl_commit_rxon here to commit the new filter flags
1586 * since mac80211 will call ieee80211_hw_config immediately.
1587 * (mc_list is not supported at this time). Otherwise, we need to
1588 * queue a background iwl_commit_rxon work.
1589 */
1590
1591 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1592 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1593}
1594EXPORT_SYMBOL(iwl_configure_filter);
1595
da154e30
RR		 1596int iwl_set_hw_params(struct iwl_priv *priv)
1597{
da154e30
RR		 1598 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1599 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1600 if (priv->cfg->mod_params->amsdu_size_8K)
2f301227 1601 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
da154e30 1602 else
2f301227 1603 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
da154e30 1604
2c2f3b33
TW		 1605 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1606
49779293
RR		 1607 if (priv->cfg->mod_params->disable_11n)
1608 priv->cfg->sku &= ~IWL_SKU_N;
1609
da154e30
RR		 1610 /* Device-specific setup */
1611 return priv->cfg->ops->lib->set_hw_params(priv);
1612}
1613EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956 1614
630fe9b6
TW		 1615int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1616{
1617 int ret = 0;
5eadd94b
WYG		 1618 s8 prev_tx_power = priv->tx_power_user_lmt;
1619
630fe9b6 1620 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1621 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1622 tx_power,
1623 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1624 return -EINVAL;
1625 }
1626
dc1b0973 1627 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1628 IWL_WARN(priv,
1629 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1630 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1631 return -EINVAL;
1632 }
1633
1634 if (priv->tx_power_user_lmt != tx_power)
1635 force = true;
1636
019fb97d 1637 /* if nic is not up don't send command */
5eadd94b
WYG		 1638 if (iwl_is_ready_rf(priv)) {
1639 priv->tx_power_user_lmt = tx_power;
1640 if (force && priv->cfg->ops->lib->send_tx_power)
1641 ret = priv->cfg->ops->lib->send_tx_power(priv);
1642 else if (!priv->cfg->ops->lib->send_tx_power)
1643 ret = -EOPNOTSUPP;
1644 /*
1645 * if fail to set tx_power, restore the orig. tx power
1646 */
1647 if (ret)
1648 priv->tx_power_user_lmt = prev_tx_power;
1649 }
630fe9b6 1650
5eadd94b
WYG		 1651 /*
1652 * Even this is an async host command, the command
1653 * will always report success from uCode
1654 * So once driver can placing the command into the queue
1655 * successfully, driver can use priv->tx_power_user_lmt
1656 * to reflect the current tx power
1657 */
630fe9b6
TW		 1658 return ret;
1659}
1660EXPORT_SYMBOL(iwl_set_tx_power);
1661
ef850d7c
MA		 1662#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1663
1664/* Free dram table */
1665void iwl_free_isr_ict(struct iwl_priv *priv)
1666{
1667 if (priv->ict_tbl_vir) {
1668 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1669 PAGE_SIZE, priv->ict_tbl_vir,
1670 priv->ict_tbl_dma);
1671 priv->ict_tbl_vir = NULL;
1672 }
1673}
1674EXPORT_SYMBOL(iwl_free_isr_ict);
1675
1676
1677/* allocate dram shared table it is a PAGE_SIZE aligned
1678 * also reset all data related to ICT table interrupt.
1679 */
1680int iwl_alloc_isr_ict(struct iwl_priv *priv)
1681{
1682
1683 if (priv->cfg->use_isr_legacy)
1684 return 0;
1685 /* allocate shrared data table */
1686 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1687 ICT_COUNT) + PAGE_SIZE,
1688 &priv->ict_tbl_dma);
1689 if (!priv->ict_tbl_vir)
1690 return -ENOMEM;
1691
1692 /* align table to PAGE_SIZE boundry */
1693 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1694
1695 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1696 (unsigned long long)priv->ict_tbl_dma,
1697 (unsigned long long)priv->aligned_ict_tbl_dma,
1698 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1699
1700 priv->ict_tbl = priv->ict_tbl_vir +
1701 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1702
1703 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1704 priv->ict_tbl, priv->ict_tbl_vir,
1705 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1706
1707 /* reset table and index to all 0 */
1708 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1709 priv->ict_index = 0;
1710
40cefda9
MA		 1711 /* add periodic RX interrupt */
1712 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1713 return 0;
1714}
1715EXPORT_SYMBOL(iwl_alloc_isr_ict);
1716
1717/* Device is going up inform it about using ICT interrupt table,
1718 * also we need to tell the driver to start using ICT interrupt.
1719 */
1720int iwl_reset_ict(struct iwl_priv *priv)
1721{
1722 u32 val;
1723 unsigned long flags;
1724
1725 if (!priv->ict_tbl_vir)
1726 return 0;
1727
1728 spin_lock_irqsave(&priv->lock, flags);
1729 iwl_disable_interrupts(priv);
1730
1303dcfd 1731 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
ef850d7c
MA		 1732
1733 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1734
1735 val |= CSR_DRAM_INT_TBL_ENABLE;
1736 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1737
1738 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1739 "aligned dma address %Lx\n",
1740 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1741
1742 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1743 priv->use_ict = true;
1744 priv->ict_index = 0;
40cefda9 1745 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1746 iwl_enable_interrupts(priv);
1747 spin_unlock_irqrestore(&priv->lock, flags);
1748
1749 return 0;
1750}
1751EXPORT_SYMBOL(iwl_reset_ict);
1752
1753/* Device is going down disable ict interrupt usage */
1754void iwl_disable_ict(struct iwl_priv *priv)
1755{
1756 unsigned long flags;
1757
1758 spin_lock_irqsave(&priv->lock, flags);
1759 priv->use_ict = false;
1760 spin_unlock_irqrestore(&priv->lock, flags);
1761}
1762EXPORT_SYMBOL(iwl_disable_ict);
1763
1764/* interrupt handler using ict table, with this interrupt driver will
1765 * stop using INTA register to get device's interrupt, reading this register
1766 * is expensive, device will write interrupts in ICT dram table, increment
1767 * index then will fire interrupt to driver, driver will OR all ICT table
1768 * entries from current index up to table entry with 0 value. the result is
1769 * the interrupt we need to service, driver will set the entries back to 0 and
1770 * set index.
1771 */
1772irqreturn_t iwl_isr_ict(int irq, void *data)
1773{
1774 struct iwl_priv *priv = data;
1775 u32 inta, inta_mask;
1776 u32 val = 0;
1777
1778 if (!priv)
1779 return IRQ_NONE;
1780
1781 /* dram interrupt table not set yet,
1782 * use legacy interrupt.
1783 */
1784 if (!priv->use_ict)
1785 return iwl_isr(irq, data);
1786
1787 spin_lock(&priv->lock);
1788
1789 /* Disable (but don't clear!) interrupts here to avoid
1790 * back-to-back ISRs and sporadic interrupts from our NIC.
1791 * If we have something to service, the tasklet will re-enable ints.
1792 * If we *don't* have something, we'll re-enable before leaving here.
1793 */
1794 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1795 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1796
1797
1798 /* Ignore interrupt if there's nothing in NIC to service.
1799 * This may be due to IRQ shared with another device,
1800 * or due to sporadic interrupts thrown from our NIC. */
1801 if (!priv->ict_tbl[priv->ict_index]) {
1802 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1803 goto none;
1804 }
1805
1806 /* read all entries that not 0 start with ict_index */
1807 while (priv->ict_tbl[priv->ict_index]) {
1808
1303dcfd 1809 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
ef850d7c 1810 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1303dcfd
JB		 1811 priv->ict_index,
1812 le32_to_cpu(priv->ict_tbl[priv->ict_index]));
ef850d7c
MA		 1813 priv->ict_tbl[priv->ict_index] = 0;
1814 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1303dcfd 1815 ICT_COUNT);
ef850d7c
MA		 1816
1817 }
1818
1819 /* We should not get this value, just ignore it. */
1820 if (val == 0xffffffff)
1821 val = 0;
1822
1823 inta = (0xff & val) | ((0xff00 & val) << 16);
1824 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1825 inta, inta_mask, val);
1826
40cefda9 1827 inta &= priv->inta_mask;
ef850d7c
MA		 1828 priv->inta |= inta;
1829
1830 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1831 if (likely(inta))
1832 tasklet_schedule(&priv->irq_tasklet);
1833 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1834 /* Allow interrupt if was disabled by this handler and
1835 * no tasklet was schedules, We should not enable interrupt,
1836 * tasklet will enable it.
1837 */
1838 iwl_enable_interrupts(priv);
1839 }
1840
1841 spin_unlock(&priv->lock);
1842 return IRQ_HANDLED;
1843
1844 none:
1845 /* re-enable interrupts here since we don't have anything to service.
1846 * only Re-enable if disabled by irq.
1847 */
1848 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1849 iwl_enable_interrupts(priv);
1850
1851 spin_unlock(&priv->lock);
1852 return IRQ_NONE;
1853}
1854EXPORT_SYMBOL(iwl_isr_ict);
1855
1856
1857static irqreturn_t iwl_isr(int irq, void *data)
1858{
1859 struct iwl_priv *priv = data;
1860 u32 inta, inta_mask;
d651ae32 1861#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1862 u32 inta_fh;
d651ae32 1863#endif
ef850d7c
MA		 1864 if (!priv)
1865 return IRQ_NONE;
1866
1867 spin_lock(&priv->lock);
1868
1869 /* Disable (but don't clear!) interrupts here to avoid
1870 * back-to-back ISRs and sporadic interrupts from our NIC.
1871 * If we have something to service, the tasklet will re-enable ints.
1872 * If we *don't* have something, we'll re-enable before leaving here. */
1873 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1874 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1875
1876 /* Discover which interrupts are active/pending */
1877 inta = iwl_read32(priv, CSR_INT);
1878
1879 /* Ignore interrupt if there's nothing in NIC to service.
1880 * This may be due to IRQ shared with another device,
1881 * or due to sporadic interrupts thrown from our NIC. */
1882 if (!inta) {
1883 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1884 goto none;
1885 }
1886
1887 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1888 /* Hardware disappeared. It might have already raised
1889 * an interrupt */
1890 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1891 goto unplugged;
1892 }
1893
1894#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1895 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1896 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1897 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1898 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1899 }
1900#endif
1901
1902 priv->inta |= inta;
1903 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1904 if (likely(inta))
1905 tasklet_schedule(&priv->irq_tasklet);
1906 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1907 iwl_enable_interrupts(priv);
1908
1909 unplugged:
1910 spin_unlock(&priv->lock);
1911 return IRQ_HANDLED;
1912
1913 none:
1914 /* re-enable interrupts here since we don't have anything to service. */
1915 /* only Re-enable if diabled by irq and no schedules tasklet. */
1916 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1917 iwl_enable_interrupts(priv);
1918
1919 spin_unlock(&priv->lock);
1920 return IRQ_NONE;
1921}
1922
1923irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1924{
1925 struct iwl_priv *priv = data;
1926 u32 inta, inta_mask;
1927 u32 inta_fh;
1928 if (!priv)
1929 return IRQ_NONE;
1930
1931 spin_lock(&priv->lock);
1932
1933 /* Disable (but don't clear!) interrupts here to avoid
1934 * back-to-back ISRs and sporadic interrupts from our NIC.
1935 * If we have something to service, the tasklet will re-enable ints.
1936 * If we *don't* have something, we'll re-enable before leaving here. */
1937 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1938 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1939
1940 /* Discover which interrupts are active/pending */
1941 inta = iwl_read32(priv, CSR_INT);
1942 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1943
1944 /* Ignore interrupt if there's nothing in NIC to service.
1945 * This may be due to IRQ shared with another device,
1946 * or due to sporadic interrupts thrown from our NIC. */
1947 if (!inta && !inta_fh) {
1948 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1949 goto none;
1950 }
1951
1952 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1953 /* Hardware disappeared. It might have already raised
1954 * an interrupt */
1955 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1956 goto unplugged;
1957 }
1958
1959 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1960 inta, inta_mask, inta_fh);
1961
1962 inta &= ~CSR_INT_BIT_SCD;
1963
1964 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1965 if (likely(inta || inta_fh))
1966 tasklet_schedule(&priv->irq_tasklet);
1967
1968 unplugged:
1969 spin_unlock(&priv->lock);
1970 return IRQ_HANDLED;
1971
1972 none:
1973 /* re-enable interrupts here since we don't have anything to service. */
1974 /* only Re-enable if diabled by irq */
1975 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1976 iwl_enable_interrupts(priv);
1977 spin_unlock(&priv->lock);
1978 return IRQ_NONE;
1979}
ef850d7c 1980EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1981
17f841cd
SO		 1982int iwl_send_bt_config(struct iwl_priv *priv)
1983{
1984 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 1985 .flags = BT_COEX_MODE_4W,
1986 .lead_time = BT_LEAD_TIME_DEF,
1987 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 1988 .kill_ack_mask = 0,
1989 .kill_cts_mask = 0,
1990 };
1991
1992 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1993 sizeof(struct iwl_bt_cmd), &bt_cmd);
1994}
1995EXPORT_SYMBOL(iwl_send_bt_config);
1996
ef8d5529 1997int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
49ea8596 1998{
ef8d5529
WYG		 1999 struct iwl_statistics_cmd statistics_cmd = {
2000 .configuration_flags =
2001 clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
49ea8596 2002 };
ef8d5529
WYG		 2003
2004 if (flags & CMD_ASYNC)
2005 return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
2006 sizeof(struct iwl_statistics_cmd),
2007 &statistics_cmd, NULL);
2008 else
2009 return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
2010 sizeof(struct iwl_statistics_cmd),
2011 &statistics_cmd);
49ea8596
EG		 2012}
2013EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2014
b0692f2f
EG		 2015/**
2016 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2017 * using sample data 100 bytes apart. If these sample points are good,
2018 * it's a pretty good bet that everything between them is good, too.
2019 */
2020static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2021{
2022 u32 val;
2023 int ret = 0;
2024 u32 errcnt = 0;
2025 u32 i;
2026
e1623446 2027 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2028
b0692f2f
EG		 2029 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2030 /* read data comes through single port, auto-incr addr */
2031 /* NOTE: Use the debugless read so we don't flood kernel log
2032 * if IWL_DL_IO is set */
2033 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2034 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2035 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2036 if (val != le32_to_cpu(*image)) {
2037 ret = -EIO;
2038 errcnt++;
2039 if (errcnt >= 3)
2040 break;
2041 }
2042 }
2043
b0692f2f
EG		 2044 return ret;
2045}
2046
2047/**
2048 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2049 * looking at all data.
2050 */
2051static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2052 u32 len)
2053{
2054 u32 val;
2055 u32 save_len = len;
2056 int ret = 0;
2057 u32 errcnt;
2058
e1623446 2059 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2060
250bdd21
SO		 2061 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2062 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2063
2064 errcnt = 0;
2065 for (; len > 0; len -= sizeof(u32), image++) {
2066 /* read data comes through single port, auto-incr addr */
2067 /* NOTE: Use the debugless read so we don't flood kernel log
2068 * if IWL_DL_IO is set */
2069 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2070 if (val != le32_to_cpu(*image)) {
15b1687c 2071 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2072 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2073 save_len - len, val, le32_to_cpu(*image));
2074 ret = -EIO;
2075 errcnt++;
2076 if (errcnt >= 20)
2077 break;
2078 }
2079 }
2080
b0692f2f 2081 if (!errcnt)
e1623446
TW		 2082 IWL_DEBUG_INFO(priv,
2083 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2084
2085 return ret;
2086}
2087
2088/**
2089 * iwl_verify_ucode - determine which instruction image is in SRAM,
2090 * and verify its contents
2091 */
2092int iwl_verify_ucode(struct iwl_priv *priv)
2093{
2094 __le32 *image;
2095 u32 len;
2096 int ret;
2097
2098 /* Try bootstrap */
2099 image = (__le32 *)priv->ucode_boot.v_addr;
2100 len = priv->ucode_boot.len;
2101 ret = iwlcore_verify_inst_sparse(priv, image, len);
2102 if (!ret) {
e1623446 2103 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2104 return 0;
2105 }
2106
2107 /* Try initialize */
2108 image = (__le32 *)priv->ucode_init.v_addr;
2109 len = priv->ucode_init.len;
2110 ret = iwlcore_verify_inst_sparse(priv, image, len);
2111 if (!ret) {
e1623446 2112 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2113 return 0;
2114 }
2115
2116 /* Try runtime/protocol */
2117 image = (__le32 *)priv->ucode_code.v_addr;
2118 len = priv->ucode_code.len;
2119 ret = iwlcore_verify_inst_sparse(priv, image, len);
2120 if (!ret) {
e1623446 2121 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2122 return 0;
2123 }
2124
15b1687c 2125 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2126
2127 /* Since nothing seems to match, show first several data entries in
2128 * instruction SRAM, so maybe visual inspection will give a clue.
2129 * Selection of bootstrap image (vs. other images) is arbitrary. */
2130 image = (__le32 *)priv->ucode_boot.v_addr;
2131 len = priv->ucode_boot.len;
2132 ret = iwl_verify_inst_full(priv, image, len);
2133
2134 return ret;
2135}
2136EXPORT_SYMBOL(iwl_verify_ucode);
2137
56e12615 2138
47f4a587
EG		 2139void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2140{
2141 struct iwl_ct_kill_config cmd;
672639de 2142 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2143 unsigned long flags;
2144 int ret = 0;
2145
2146 spin_lock_irqsave(&priv->lock, flags);
2147 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2148 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2149 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2150 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2151
480e8407 2152 if (priv->cfg->support_ct_kill_exit) {
672639de
WYG		 2153 adv_cmd.critical_temperature_enter =
2154 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2155 adv_cmd.critical_temperature_exit =
2156 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2157
2158 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2159 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2160 if (ret)
2161 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2162 else
2163 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2164 "succeeded, "
2165 "critical temperature enter is %d,"
2166 "exit is %d\n",
2167 priv->hw_params.ct_kill_threshold,
2168 priv->hw_params.ct_kill_exit_threshold);
480e8407 2169 } else {
672639de
WYG		 2170 cmd.critical_temperature_R =
2171 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2172
672639de
WYG		 2173 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2174 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2175 if (ret)
2176 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2177 else
2178 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2179 "succeeded, "
2180 "critical temperature is %d\n",
2181 priv->hw_params.ct_kill_threshold);
672639de 2182 }
47f4a587
EG		 2183}
2184EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2185
0ad91a35 2186
14a08a7f
EG		 2187/*
2188 * CARD_STATE_CMD
2189 *
2190 * Use: Sets the device's internal card state to enable, disable, or halt
2191 *
2192 * When in the 'enable' state the card operates as normal.
2193 * When in the 'disable' state, the card enters into a low power mode.
2194 * When in the 'halt' state, the card is shut down and must be fully
2195 * restarted to come back on.
2196 */
c496294e 2197int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2198{
2199 struct iwl_host_cmd cmd = {
2200 .id = REPLY_CARD_STATE_CMD,
2201 .len = sizeof(u32),
2202 .data = &flags,
c2acea8e 2203 .flags = meta_flag,
14a08a7f
EG		 2204 };
2205
2206 return iwl_send_cmd(priv, &cmd);
2207}
2208
030f05ed
AK		 2209void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2210 struct iwl_rx_mem_buffer *rxb)
2211{
2212#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 2213 struct iwl_rx_packet *pkt = rxb_addr(rxb);
030f05ed
AK		 2214 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2215 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2216 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2217#endif
2218}
2219EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2220
2221void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2222 struct iwl_rx_mem_buffer *rxb)
2223{
2f301227 2224 struct iwl_rx_packet *pkt = rxb_addr(rxb);
396887a2 2225 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
030f05ed 2226 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
396887a2
DH		 2227 "notification for %s:\n", len,
2228 get_cmd_string(pkt->hdr.cmd));
2229 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
030f05ed
AK		 2230}
2231EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2232
2233void iwl_rx_reply_error(struct iwl_priv *priv,
2234 struct iwl_rx_mem_buffer *rxb)
2235{
2f301227 2236 struct iwl_rx_packet *pkt = rxb_addr(rxb);
261b9c33
AK		 2237
2238 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2239 "seq 0x%04X ser 0x%08X\n",
2240 le32_to_cpu(pkt->u.err_resp.error_type),
2241 get_cmd_string(pkt->u.err_resp.cmd_id),
2242 pkt->u.err_resp.cmd_id,
2243 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2244 le32_to_cpu(pkt->u.err_resp.error_info));
2245}
2246EXPORT_SYMBOL(iwl_rx_reply_error);
2247
a83b9141
WYG		 2248void iwl_clear_isr_stats(struct iwl_priv *priv)
2249{
2250 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2251}
a83b9141 2252
488829f1
AK		 2253int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2254 const struct ieee80211_tx_queue_params *params)
2255{
2256 struct iwl_priv *priv = hw->priv;
2257 unsigned long flags;
2258 int q;
2259
2260 IWL_DEBUG_MAC80211(priv, "enter\n");
2261
2262 if (!iwl_is_ready_rf(priv)) {
2263 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2264 return -EIO;
2265 }
2266
2267 if (queue >= AC_NUM) {
2268 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2269 return 0;
2270 }
2271
2272 q = AC_NUM - 1 - queue;
2273
2274 spin_lock_irqsave(&priv->lock, flags);
2275
2276 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2277 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2278 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2279 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2280 cpu_to_le16((params->txop * 32));
2281
2282 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2283 priv->qos_data.qos_active = 1;
2284
2285 if (priv->iw_mode == NL80211_IFTYPE_AP)
2286 iwl_activate_qos(priv, 1);
2287 else if (priv->assoc_id && iwl_is_associated(priv))
2288 iwl_activate_qos(priv, 0);
2289
2290 spin_unlock_irqrestore(&priv->lock, flags);
2291
2292 IWL_DEBUG_MAC80211(priv, "leave\n");
2293 return 0;
2294}
2295EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2296
2297static void iwl_ht_conf(struct iwl_priv *priv,
02bb1bea 2298 struct ieee80211_bss_conf *bss_conf)
5bbe233b 2299{
fad95bf5 2300 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
5bbe233b
AK		 2301 struct ieee80211_sta *sta;
2302
2303 IWL_DEBUG_MAC80211(priv, "enter: \n");
2304
fad95bf5 2305 if (!ht_conf->is_ht)
5bbe233b
AK		 2306 return;
2307
fad95bf5 2308 ht_conf->ht_protection =
9ed6bcce 2309 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
fad95bf5 2310 ht_conf->non_GF_STA_present =
9ed6bcce 2311 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b 2312
02bb1bea
JB		 2313 ht_conf->single_chain_sufficient = false;
2314
2315 switch (priv->iw_mode) {
2316 case NL80211_IFTYPE_STATION:
2317 rcu_read_lock();
5ed176e1 2318 sta = ieee80211_find_sta(priv->vif, priv->bssid);
02bb1bea
JB		 2319 if (sta) {
2320 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2321 int maxstreams;
2322
2323 maxstreams = (ht_cap->mcs.tx_params &
2324 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
2325 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2326 maxstreams += 1;
2327
2328 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2329 (ht_cap->mcs.rx_mask[2] == 0))
2330 ht_conf->single_chain_sufficient = true;
2331 if (maxstreams <= 1)
2332 ht_conf->single_chain_sufficient = true;
2333 } else {
2334 /*
2335 * If at all, this can only happen through a race
2336 * when the AP disconnects us while we're still
2337 * setting up the connection, in that case mac80211
2338 * will soon tell us about that.
2339 */
2340 ht_conf->single_chain_sufficient = true;
2341 }
2342 rcu_read_unlock();
2343 break;
2344 case NL80211_IFTYPE_ADHOC:
2345 ht_conf->single_chain_sufficient = true;
2346 break;
2347 default:
2348 break;
2349 }
5bbe233b
AK		 2350
2351 IWL_DEBUG_MAC80211(priv, "leave\n");
2352}
2353
2354#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2355void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2356 struct ieee80211_vif *vif,
2357 struct ieee80211_bss_conf *bss_conf,
2358 u32 changes)
5bbe233b
AK		 2359{
2360 struct iwl_priv *priv = hw->priv;
3a650292 2361 int ret;
5bbe233b
AK		 2362
2363 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2364
2d0ddec5
JB		 2365 if (!iwl_is_alive(priv))
2366 return;
2367
2368 mutex_lock(&priv->mutex);
2369
2370 if (changes & BSS_CHANGED_BEACON &&
2371 priv->iw_mode == NL80211_IFTYPE_AP) {
2372 dev_kfree_skb(priv->ibss_beacon);
2373 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2374 }
2375
d7129e19
JB		 2376 if (changes & BSS_CHANGED_BEACON_INT) {
2377 priv->beacon_int = bss_conf->beacon_int;
2378 /* TODO: in AP mode, do something to make this take effect */
2379 }
2380
2381 if (changes & BSS_CHANGED_BSSID) {
2382 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2383
2384 /*
2385 * If there is currently a HW scan going on in the
2386 * background then we need to cancel it else the RXON
2387 * below/in post_associate will fail.
2388 */
2d0ddec5 2389 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2390 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2391 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2392 mutex_unlock(&priv->mutex);
2393 return;
2394 }
2d0ddec5 2395
d7129e19
JB		 2396 /* mac80211 only sets assoc when in STATION mode */
2397 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2398 bss_conf->assoc) {
2399 memcpy(priv->staging_rxon.bssid_addr,
2400 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2401
d7129e19
JB		 2402 /* currently needed in a few places */
2403 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2404 } else {
2405 priv->staging_rxon.filter_flags &=
2406 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2407 }
d7129e19 2408
2d0ddec5
JB		 2409 }
2410
d7129e19
JB		 2411 /*
2412 * This needs to be after setting the BSSID in case
2413 * mac80211 decides to do both changes at once because
2414 * it will invoke post_associate.
2415 */
2d0ddec5
JB		 2416 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2417 changes & BSS_CHANGED_BEACON) {
2418 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2419
2420 if (beacon)
2421 iwl_mac_beacon_update(hw, beacon);
2422 }
2423
5bbe233b
AK		 2424 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2425 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2426 bss_conf->use_short_preamble);
2427 if (bss_conf->use_short_preamble)
2428 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2429 else
2430 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2431 }
2432
2433 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2434 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2435 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2436 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2437 else
2438 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2439 }
2440
d7129e19
JB		 2441 if (changes & BSS_CHANGED_BASIC_RATES) {
2442 /* XXX use this information
2443 *
2444 * To do that, remove code from iwl_set_rate() and put something
2445 * like this here:
2446 *
2447 if (A-band)
2448 priv->staging_rxon.ofdm_basic_rates =
2449 bss_conf->basic_rates;
2450 else
2451 priv->staging_rxon.ofdm_basic_rates =
2452 bss_conf->basic_rates >> 4;
2453 priv->staging_rxon.cck_basic_rates =
2454 bss_conf->basic_rates & 0xF;
2455 */
2456 }
2457
5bbe233b
AK		 2458 if (changes & BSS_CHANGED_HT) {
2459 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2460
2461 if (priv->cfg->ops->hcmd->set_rxon_chain)
2462 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2463 }
2464
2465 if (changes & BSS_CHANGED_ASSOC) {
2466 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2467 if (bss_conf->assoc) {
2468 priv->assoc_id = bss_conf->aid;
2469 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2470 priv->timestamp = bss_conf->timestamp;
2471 priv->assoc_capability = bss_conf->assoc_capability;
2472
e932a609
JB		 2473 iwl_led_associate(priv);
2474
d7129e19
JB		 2475 /*
2476 * We have just associated, don't start scan too early
2477 * leave time for EAPOL exchange to complete.
2478 *
2479 * XXX: do this in mac80211
5bbe233b
AK		 2480 */
2481 priv->next_scan_jiffies = jiffies +
2482 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2483 if (!iwl_is_rfkill(priv))
2484 priv->cfg->ops->lib->post_associate(priv);
e932a609 2485 } else {
5bbe233b 2486 priv->assoc_id = 0;
e932a609
JB		 2487 iwl_led_disassociate(priv);
2488 }
d7129e19
JB		 2489 }
2490
2491 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2492 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2493 changes);
2494 ret = iwl_send_rxon_assoc(priv);
2495 if (!ret) {
2496 /* Sync active_rxon with latest change. */
2497 memcpy((void *)&priv->active_rxon,
2498 &priv->staging_rxon,
2499 sizeof(struct iwl_rxon_cmd));
5bbe233b 2500 }
5bbe233b 2501 }
d7129e19 2502
f513dfff
DH		 2503 if ((changes & BSS_CHANGED_BEACON_ENABLED) &&
2504 vif->bss_conf.enable_beacon) {
2505 memcpy(priv->staging_rxon.bssid_addr,
2506 bss_conf->bssid, ETH_ALEN);
2507 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2508 iwlcore_config_ap(priv);
2509 }
2510
d7129e19
JB		 2511 mutex_unlock(&priv->mutex);
2512
2d0ddec5 2513 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2514}
2515EXPORT_SYMBOL(iwl_bss_info_changed);
2516
9944b938
AK		 2517int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2518{
2519 struct iwl_priv *priv = hw->priv;
2520 unsigned long flags;
2521 __le64 timestamp;
2522
2523 IWL_DEBUG_MAC80211(priv, "enter\n");
2524
2525 if (!iwl_is_ready_rf(priv)) {
2526 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2527 return -EIO;
2528 }
2529
2530 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2531 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2532 return -EIO;
2533 }
2534
2535 spin_lock_irqsave(&priv->lock, flags);
2536
2537 if (priv->ibss_beacon)
2538 dev_kfree_skb(priv->ibss_beacon);
2539
2540 priv->ibss_beacon = skb;
2541
2542 priv->assoc_id = 0;
2543 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2544 priv->timestamp = le64_to_cpu(timestamp);
2545
2546 IWL_DEBUG_MAC80211(priv, "leave\n");
2547 spin_unlock_irqrestore(&priv->lock, flags);
2548
2549 iwl_reset_qos(priv);
2550
2551 priv->cfg->ops->lib->post_associate(priv);
2552
2553
2554 return 0;
2555}
2556EXPORT_SYMBOL(iwl_mac_beacon_update);
2557
727882d6
AK		 2558int iwl_set_mode(struct iwl_priv *priv, int mode)
2559{
2560 if (mode == NL80211_IFTYPE_ADHOC) {
2561 const struct iwl_channel_info *ch_info;
2562
2563 ch_info = iwl_get_channel_info(priv,
2564 priv->band,
2565 le16_to_cpu(priv->staging_rxon.channel));
2566
2567 if (!ch_info || !is_channel_ibss(ch_info)) {
2568 IWL_ERR(priv, "channel %d not IBSS channel\n",
2569 le16_to_cpu(priv->staging_rxon.channel));
2570 return -EINVAL;
2571 }
2572 }
2573
2574 iwl_connection_init_rx_config(priv, mode);
2575
2576 if (priv->cfg->ops->hcmd->set_rxon_chain)
2577 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2578
2579 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2580
c587de0b 2581 iwl_clear_stations_table(priv);
727882d6
AK		 2582
2583 /* dont commit rxon if rf-kill is on*/
2584 if (!iwl_is_ready_rf(priv))
2585 return -EAGAIN;
2586
727882d6
AK		 2587 iwlcore_commit_rxon(priv);
2588
2589 return 0;
2590}
2591EXPORT_SYMBOL(iwl_set_mode);
2592
cbb6ab94
AK		 2593int iwl_mac_add_interface(struct ieee80211_hw *hw,
2594 struct ieee80211_if_init_conf *conf)
2595{
2596 struct iwl_priv *priv = hw->priv;
2597 unsigned long flags;
2598
2599 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2600
2601 if (priv->vif) {
2602 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2603 return -EOPNOTSUPP;
2604 }
2605
2606 spin_lock_irqsave(&priv->lock, flags);
2607 priv->vif = conf->vif;
2608 priv->iw_mode = conf->type;
2609
2610 spin_unlock_irqrestore(&priv->lock, flags);
2611
2612 mutex_lock(&priv->mutex);
2613
2614 if (conf->mac_addr) {
2615 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2616 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2617 }
2618
2619 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2620 /* we are not ready, will run again when ready */
2621 set_bit(STATUS_MODE_PENDING, &priv->status);
2622
2623 mutex_unlock(&priv->mutex);
2624
2625 IWL_DEBUG_MAC80211(priv, "leave\n");
2626 return 0;
2627}
2628EXPORT_SYMBOL(iwl_mac_add_interface);
2629
d8052319
AK		 2630void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2631 struct ieee80211_if_init_conf *conf)
2632{
2633 struct iwl_priv *priv = hw->priv;
2634
2635 IWL_DEBUG_MAC80211(priv, "enter\n");
2636
2637 mutex_lock(&priv->mutex);
2638
2639 if (iwl_is_ready_rf(priv)) {
2640 iwl_scan_cancel_timeout(priv, 100);
2641 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2642 iwlcore_commit_rxon(priv);
2643 }
2644 if (priv->vif == conf->vif) {
2645 priv->vif = NULL;
2646 memset(priv->bssid, 0, ETH_ALEN);
2647 }
2648 mutex_unlock(&priv->mutex);
2649
2650 IWL_DEBUG_MAC80211(priv, "leave\n");
2651
2652}
2653EXPORT_SYMBOL(iwl_mac_remove_interface);
2654
4808368d
AK		 2655/**
2656 * iwl_mac_config - mac80211 config callback
2657 *
2658 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2659 * be set inappropriately and the driver currently sets the hardware up to
2660 * use it whenever needed.
2661 */
2662int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2663{
2664 struct iwl_priv *priv = hw->priv;
2665 const struct iwl_channel_info *ch_info;
2666 struct ieee80211_conf *conf = &hw->conf;
fad95bf5 2667 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
4808368d
AK		 2668 unsigned long flags = 0;
2669 int ret = 0;
2670 u16 ch;
2671 int scan_active = 0;
2672
2673 mutex_lock(&priv->mutex);
2674
4808368d
AK		 2675 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2676 conf->channel->hw_value, changed);
2677
2678 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2679 test_bit(STATUS_SCANNING, &priv->status))) {
2680 scan_active = 1;
2681 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2682 }
2683
2684
2685 /* during scanning mac80211 will delay channel setting until
2686 * scan finish with changed = 0
2687 */
2688 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2689 if (scan_active)
2690 goto set_ch_out;
2691
2692 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2693 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2694 if (!is_channel_valid(ch_info)) {
2695 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2696 ret = -EINVAL;
2697 goto set_ch_out;
2698 }
2699
2700 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2701 !is_channel_ibss(ch_info)) {
2702 IWL_ERR(priv, "channel %d in band %d not "
2703 "IBSS channel\n",
2704 conf->channel->hw_value, conf->channel->band);
2705 ret = -EINVAL;
2706 goto set_ch_out;
2707 }
2708
4808368d
AK		 2709 spin_lock_irqsave(&priv->lock, flags);
2710
28bd723b
DH		 2711 /* Configure HT40 channels */
2712 ht_conf->is_ht = conf_is_ht(conf);
2713 if (ht_conf->is_ht) {
2714 if (conf_is_ht40_minus(conf)) {
2715 ht_conf->extension_chan_offset =
2716 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
c812ee24 2717 ht_conf->is_40mhz = true;
28bd723b
DH		 2718 } else if (conf_is_ht40_plus(conf)) {
2719 ht_conf->extension_chan_offset =
2720 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
c812ee24 2721 ht_conf->is_40mhz = true;
28bd723b
DH		 2722 } else {
2723 ht_conf->extension_chan_offset =
2724 IEEE80211_HT_PARAM_CHA_SEC_NONE;
c812ee24 2725 ht_conf->is_40mhz = false;
28bd723b
DH		 2726 }
2727 } else
c812ee24 2728 ht_conf->is_40mhz = false;
28bd723b
DH		 2729 /* Default to no protection. Protection mode will later be set
2730 * from BSS config in iwl_ht_conf */
2731 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2732
2733 /* if we are switching from ht to 2.4 clear flags
2734 * from any ht related info since 2.4 does not
2735 * support ht */
2736 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2737 priv->staging_rxon.flags = 0;
2738
2739 iwl_set_rxon_channel(priv, conf->channel);
2740
2741 iwl_set_flags_for_band(priv, conf->channel->band);
2742 spin_unlock_irqrestore(&priv->lock, flags);
0924e519
WYG		 2743 if (iwl_is_associated(priv) &&
2744 (le16_to_cpu(priv->active_rxon.channel) != ch) &&
2745 priv->cfg->ops->lib->set_channel_switch) {
2746 iwl_set_rate(priv);
2747 /*
2748 * at this point, staging_rxon has the
2749 * configuration for channel switch
2750 */
2751 ret = priv->cfg->ops->lib->set_channel_switch(priv,
2752 ch);
2753 if (!ret) {
2754 iwl_print_rx_config_cmd(priv);
2755 goto out;
2756 }
2757 priv->switch_rxon.switch_in_progress = false;
2758 }
4808368d
AK		 2759 set_ch_out:
2760 /* The list of supported rates and rate mask can be different
2761 * for each band; since the band may have changed, reset
2762 * the rate mask to what mac80211 lists */
2763 iwl_set_rate(priv);
2764 }
2765
78f5fb7f
JB		 2766 if (changed & (IEEE80211_CONF_CHANGE_PS |
2767 IEEE80211_CONF_CHANGE_IDLE)) {
e312c24c 2768 ret = iwl_power_update_mode(priv, false);
4808368d 2769 if (ret)
e312c24c 2770 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2771 }
2772
2773 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2774 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2775 priv->tx_power_user_lmt, conf->power_level);
2776
2777 iwl_set_tx_power(priv, conf->power_level, false);
2778 }
2779
2780 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2781 if (priv->cfg->ops->hcmd->set_rxon_chain)
2782 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2783
0cf4c01e
MA		 2784 if (!iwl_is_ready(priv)) {
2785 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2786 goto out;
2787 }
2788
4808368d
AK		 2789 if (scan_active)
2790 goto out;
2791
2792 if (memcmp(&priv->active_rxon,
2793 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2794 iwlcore_commit_rxon(priv);
2795 else
2796 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2797
2798
2799out:
2800 IWL_DEBUG_MAC80211(priv, "leave\n");
2801 mutex_unlock(&priv->mutex);
2802 return ret;
2803}
2804EXPORT_SYMBOL(iwl_mac_config);
2805
aa89f31e
AK		 2806int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2807 struct ieee80211_tx_queue_stats *stats)
2808{
2809 struct iwl_priv *priv = hw->priv;
2810 int i, avail;
2811 struct iwl_tx_queue *txq;
2812 struct iwl_queue *q;
2813 unsigned long flags;
2814
2815 IWL_DEBUG_MAC80211(priv, "enter\n");
2816
2817 if (!iwl_is_ready_rf(priv)) {
2818 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2819 return -EIO;
2820 }
2821
2822 spin_lock_irqsave(&priv->lock, flags);
2823
2824 for (i = 0; i < AC_NUM; i++) {
2825 txq = &priv->txq[i];
2826 q = &txq->q;
2827 avail = iwl_queue_space(q);
2828
2829 stats[i].len = q->n_window - avail;
2830 stats[i].limit = q->n_window - q->high_mark;
2831 stats[i].count = q->n_window;
2832
2833 }
2834 spin_unlock_irqrestore(&priv->lock, flags);
2835
2836 IWL_DEBUG_MAC80211(priv, "leave\n");
2837
2838 return 0;
2839}
2840EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2841
bd564261
AK		 2842void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2843{
2844 struct iwl_priv *priv = hw->priv;
2845 unsigned long flags;
2846
2847 mutex_lock(&priv->mutex);
2848 IWL_DEBUG_MAC80211(priv, "enter\n");
2849
2850 spin_lock_irqsave(&priv->lock, flags);
fad95bf5 2851 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
bd564261
AK		 2852 spin_unlock_irqrestore(&priv->lock, flags);
2853
2854 iwl_reset_qos(priv);
2855
2856 spin_lock_irqsave(&priv->lock, flags);
2857 priv->assoc_id = 0;
2858 priv->assoc_capability = 0;
2859 priv->assoc_station_added = 0;
2860
2861 /* new association get rid of ibss beacon skb */
2862 if (priv->ibss_beacon)
2863 dev_kfree_skb(priv->ibss_beacon);
2864
2865 priv->ibss_beacon = NULL;
2866
57c4d7b4 2867 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2868 priv->timestamp = 0;
2869 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2870 priv->beacon_int = 0;
2871
2872 spin_unlock_irqrestore(&priv->lock, flags);
2873
2874 if (!iwl_is_ready_rf(priv)) {
2875 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2876 mutex_unlock(&priv->mutex);
2877 return;
2878 }
2879
2880 /* we are restarting association process
2881 * clear RXON_FILTER_ASSOC_MSK bit
2882 */
2883 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2884 iwl_scan_cancel_timeout(priv, 100);
2885 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2886 iwlcore_commit_rxon(priv);
2887 }
2888
bd564261 2889 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2890 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2891 mutex_unlock(&priv->mutex);
2892 return;
2893 }
2894
2895 iwl_set_rate(priv);
2896
2897 mutex_unlock(&priv->mutex);
2898
2899 IWL_DEBUG_MAC80211(priv, "leave\n");
2900}
2901EXPORT_SYMBOL(iwl_mac_reset_tsf);
2902
88804e2b
WYG		 2903int iwl_alloc_txq_mem(struct iwl_priv *priv)
2904{
2905 if (!priv->txq)
2906 priv->txq = kzalloc(
2907 sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
2908 GFP_KERNEL);
2909 if (!priv->txq) {
2910 IWL_ERR(priv, "Not enough memory for txq \n");
2911 return -ENOMEM;
2912 }
2913 return 0;
2914}
2915EXPORT_SYMBOL(iwl_alloc_txq_mem);
2916
2917void iwl_free_txq_mem(struct iwl_priv *priv)
2918{
2919 kfree(priv->txq);
2920 priv->txq = NULL;
2921}
2922EXPORT_SYMBOL(iwl_free_txq_mem);
2923
1933ac4d
WYG		 2924int iwl_send_wimax_coex(struct iwl_priv *priv)
2925{
2926 struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
2927
2928 if (priv->cfg->support_wimax_coexist) {
2929 /* UnMask wake up src at associated sleep */
2930 coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
2931
2932 /* UnMask wake up src at unassociated sleep */
2933 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
2934 memcpy(coex_cmd.sta_prio, cu_priorities,
2935 sizeof(struct iwl_wimax_coex_event_entry) *
2936 COEX_NUM_OF_EVENTS);
2937
2938 /* enabling the coexistence feature */
2939 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
2940
2941 /* enabling the priorities tables */
2942 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
2943 } else {
2944 /* coexistence is disabled */
2945 memset(&coex_cmd, 0, sizeof(coex_cmd));
2946 }
2947 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
2948 sizeof(coex_cmd), &coex_cmd);
2949}
2950EXPORT_SYMBOL(iwl_send_wimax_coex);
2951
20594eb0
WYG		 2952#ifdef CONFIG_IWLWIFI_DEBUGFS
2953
2954#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2955
2956void iwl_reset_traffic_log(struct iwl_priv *priv)
2957{
2958 priv->tx_traffic_idx = 0;
2959 priv->rx_traffic_idx = 0;
2960 if (priv->tx_traffic)
2961 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2962 if (priv->rx_traffic)
2963 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2964}
2965
2966int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2967{
2968 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2969
2970 if (iwl_debug_level & IWL_DL_TX) {
2971 if (!priv->tx_traffic) {
2972 priv->tx_traffic =
2973 kzalloc(traffic_size, GFP_KERNEL);
2974 if (!priv->tx_traffic)
2975 return -ENOMEM;
2976 }
2977 }
2978 if (iwl_debug_level & IWL_DL_RX) {
2979 if (!priv->rx_traffic) {
2980 priv->rx_traffic =
2981 kzalloc(traffic_size, GFP_KERNEL);
2982 if (!priv->rx_traffic)
2983 return -ENOMEM;
2984 }
2985 }
2986 iwl_reset_traffic_log(priv);
2987 return 0;
2988}
2989EXPORT_SYMBOL(iwl_alloc_traffic_mem);
2990
2991void iwl_free_traffic_mem(struct iwl_priv *priv)
2992{
2993 kfree(priv->tx_traffic);
2994 priv->tx_traffic = NULL;
2995
2996 kfree(priv->rx_traffic);
2997 priv->rx_traffic = NULL;
2998}
2999EXPORT_SYMBOL(iwl_free_traffic_mem);
3000
3001void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
3002 u16 length, struct ieee80211_hdr *header)
3003{
3004 __le16 fc;
3005 u16 len;
3006
3007 if (likely(!(iwl_debug_level & IWL_DL_TX)))
3008 return;
3009
3010 if (!priv->tx_traffic)
3011 return;
3012
3013 fc = header->frame_control;
3014 if (ieee80211_is_data(fc)) {
3015 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3016 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3017 memcpy((priv->tx_traffic +
3018 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3019 header, len);
3020 priv->tx_traffic_idx =
3021 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3022 }
3023}
3024EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
3025
3026void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
3027 u16 length, struct ieee80211_hdr *header)
3028{
3029 __le16 fc;
3030 u16 len;
3031
3032 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3033 return;
3034
3035 if (!priv->rx_traffic)
3036 return;
3037
3038 fc = header->frame_control;
3039 if (ieee80211_is_data(fc)) {
3040 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3041 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3042 memcpy((priv->rx_traffic +
3043 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3044 header, len);
3045 priv->rx_traffic_idx =
3046 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3047 }
3048}
3049EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 3050
3051const char *get_mgmt_string(int cmd)
3052{
3053 switch (cmd) {
3054 IWL_CMD(MANAGEMENT_ASSOC_REQ);
3055 IWL_CMD(MANAGEMENT_ASSOC_RESP);
3056 IWL_CMD(MANAGEMENT_REASSOC_REQ);
3057 IWL_CMD(MANAGEMENT_REASSOC_RESP);
3058 IWL_CMD(MANAGEMENT_PROBE_REQ);
3059 IWL_CMD(MANAGEMENT_PROBE_RESP);
3060 IWL_CMD(MANAGEMENT_BEACON);
3061 IWL_CMD(MANAGEMENT_ATIM);
3062 IWL_CMD(MANAGEMENT_DISASSOC);
3063 IWL_CMD(MANAGEMENT_AUTH);
3064 IWL_CMD(MANAGEMENT_DEAUTH);
3065 IWL_CMD(MANAGEMENT_ACTION);
3066 default:
3067 return "UNKNOWN";
3068
3069 }
3070}
3071
3072const char *get_ctrl_string(int cmd)
3073{
3074 switch (cmd) {
3075 IWL_CMD(CONTROL_BACK_REQ);
3076 IWL_CMD(CONTROL_BACK);
3077 IWL_CMD(CONTROL_PSPOLL);
3078 IWL_CMD(CONTROL_RTS);
3079 IWL_CMD(CONTROL_CTS);
3080 IWL_CMD(CONTROL_ACK);
3081 IWL_CMD(CONTROL_CFEND);
3082 IWL_CMD(CONTROL_CFENDACK);
3083 default:
3084 return "UNKNOWN";
3085
3086 }
3087}
3088
3089void iwl_clear_tx_stats(struct iwl_priv *priv)
3090{
3091 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
3092
3093}
3094
3095void iwl_clear_rx_stats(struct iwl_priv *priv)
3096{
3097 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
3098}
3099
3100/*
3101 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3102 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3103 * Use debugFs to display the rx/rx_statistics
3104 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3105 * information will be recorded, but DATA pkt still will be recorded
3106 * for the reason of iwl_led.c need to control the led blinking based on
3107 * number of tx and rx data.
3108 *
3109 */
3110void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3111{
3112 struct traffic_stats *stats;
3113
3114 if (is_tx)
3115 stats = &priv->tx_stats;
3116 else
3117 stats = &priv->rx_stats;
3118
3119 if (ieee80211_is_mgmt(fc)) {
3120 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3121 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3122 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3123 break;
3124 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3125 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3126 break;
3127 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3128 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3129 break;
3130 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3131 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3132 break;
3133 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3134 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3135 break;
3136 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3137 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3138 break;
3139 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3140 stats->mgmt[MANAGEMENT_BEACON]++;
3141 break;
3142 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3143 stats->mgmt[MANAGEMENT_ATIM]++;
3144 break;
3145 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3146 stats->mgmt[MANAGEMENT_DISASSOC]++;
3147 break;
3148 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3149 stats->mgmt[MANAGEMENT_AUTH]++;
3150 break;
3151 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3152 stats->mgmt[MANAGEMENT_DEAUTH]++;
3153 break;
3154 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3155 stats->mgmt[MANAGEMENT_ACTION]++;
3156 break;
3157 }
3158 } else if (ieee80211_is_ctl(fc)) {
3159 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3160 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3161 stats->ctrl[CONTROL_BACK_REQ]++;
3162 break;
3163 case cpu_to_le16(IEEE80211_STYPE_BACK):
3164 stats->ctrl[CONTROL_BACK]++;
3165 break;
3166 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3167 stats->ctrl[CONTROL_PSPOLL]++;
3168 break;
3169 case cpu_to_le16(IEEE80211_STYPE_RTS):
3170 stats->ctrl[CONTROL_RTS]++;
3171 break;
3172 case cpu_to_le16(IEEE80211_STYPE_CTS):
3173 stats->ctrl[CONTROL_CTS]++;
3174 break;
3175 case cpu_to_le16(IEEE80211_STYPE_ACK):
3176 stats->ctrl[CONTROL_ACK]++;
3177 break;
3178 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3179 stats->ctrl[CONTROL_CFEND]++;
3180 break;
3181 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3182 stats->ctrl[CONTROL_CFENDACK]++;
3183 break;
3184 }
3185 } else {
3186 /* data */
3187 stats->data_cnt++;
3188 stats->data_bytes += len;
3189 }
d5f4cf71 3190 iwl_leds_background(priv);
22fdf3c9
WYG		 3191}
3192EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3193#endif
3194
6da3a13e
WYG		 3195#ifdef CONFIG_PM
3196
3197int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3198{
3199 struct iwl_priv *priv = pci_get_drvdata(pdev);
3200
3201 /*
3202 * This function is called when system goes into suspend state
3203 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3204 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3205 * it will not call apm_ops.stop() to stop the DMA operation.
3206 * Calling apm_ops.stop here to make sure we stop the DMA.
3207 */
3208 priv->cfg->ops->lib->apm_ops.stop(priv);
3209
3210 pci_save_state(pdev);
3211 pci_disable_device(pdev);
3212 pci_set_power_state(pdev, PCI_D3hot);
3213
3214 return 0;
3215}
3216EXPORT_SYMBOL(iwl_pci_suspend);
3217
3218int iwl_pci_resume(struct pci_dev *pdev)
3219{
3220 struct iwl_priv *priv = pci_get_drvdata(pdev);
3221 int ret;
3222
3223 pci_set_power_state(pdev, PCI_D0);
3224 ret = pci_enable_device(pdev);
3225 if (ret)
3226 return ret;
3227 pci_restore_state(pdev);
3228 iwl_enable_interrupts(priv);
3229
3230 return 0;
3231}
3232EXPORT_SYMBOL(iwl_pci_resume);
3233
3234#endif /* CONFIG_PM */
Linux kernel - Deliverables
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