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mac80211: update injection documentation
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
ad97edd2 39#include "iwl-rfkill.h"
5da4b55f 40#include "iwl-power.h"
83dde8c9 41#include "iwl-sta.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
62/*
63 * Parameter order:
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
1826dcc0 70const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
85};
1826dcc0 86EXPORT_SYMBOL(iwl_rates);
c7de35cd 87
e7d326ac
TW		 88/**
89 * translate ucode response to mac80211 tx status control values
90 */
91void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 92 struct ieee80211_tx_info *info)
e7d326ac
TW		 93{
94 int rate_index;
e6a9854b 95 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 96
e6a9854b 97 info->antenna_sel_tx =
e7d326ac
TW		 98 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
99 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 100 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 101 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 102 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
e7d326ac 103 if (rate_n_flags & RATE_MCS_FAT_MSK)
e6a9854b 104 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 105 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 106 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 107 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 108 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 109 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 110 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 111 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 112 r->idx = rate_index;
e7d326ac
TW		 113}
114EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
115
116int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
117{
118 int idx = 0;
119
120 /* HT rate format */
121 if (rate_n_flags & RATE_MCS_HT_MSK) {
122 idx = (rate_n_flags & 0xff);
123
60d32215
DH		 124 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
125 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
126 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 127 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
128
129 idx += IWL_FIRST_OFDM_RATE;
130 /* skip 9M not supported in ht*/
131 if (idx >= IWL_RATE_9M_INDEX)
132 idx += 1;
133 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
134 return idx;
135
136 /* legacy rate format, search for match in table */
137 } else {
138 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
139 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
140 return idx;
141 }
142
143 return -1;
144}
145EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
146
76eff18b
TW		 147u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
148{
149 int i;
150 u8 ind = ant;
151 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
152 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
153 if (priv->hw_params.valid_tx_ant & BIT(ind))
154 return ind;
155 }
156 return ant;
157}
57bd1bea
TW		 158
159const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
160EXPORT_SYMBOL(iwl_bcast_addr);
161
162
1d0a082d
AK		 163/* This function both allocates and initializes hw and priv. */
164struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
165 struct ieee80211_ops *hw_ops)
166{
167 struct iwl_priv *priv;
168
169 /* mac80211 allocates memory for this device instance, including
170 * space for this driver's private structure */
171 struct ieee80211_hw *hw =
172 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
173 if (hw == NULL) {
a3139c59
SO		 174 printk(KERN_ERR "%s: Can not allocate network device\n",
175 cfg->name);
1d0a082d
AK		 176 goto out;
177 }
178
179 priv = hw->priv;
180 priv->hw = hw;
181
182out:
183 return hw;
184}
185EXPORT_SYMBOL(iwl_alloc_all);
186
b661c819
TW		 187void iwl_hw_detect(struct iwl_priv *priv)
188{
189 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
190 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
191 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
192}
193EXPORT_SYMBOL(iwl_hw_detect);
194
1053d35f
RR		 195int iwl_hw_nic_init(struct iwl_priv *priv)
196{
197 unsigned long flags;
198 struct iwl_rx_queue *rxq = &priv->rxq;
199 int ret;
200
201 /* nic_init */
1053d35f 202 spin_lock_irqsave(&priv->lock, flags);
1b73af82 203 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 204 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
205 spin_unlock_irqrestore(&priv->lock, flags);
206
207 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
208
209 priv->cfg->ops->lib->apm_ops.config(priv);
210
211 /* Allocate the RX queue, or reset if it is already allocated */
212 if (!rxq->bd) {
213 ret = iwl_rx_queue_alloc(priv);
214 if (ret) {
15b1687c 215 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 216 return -ENOMEM;
217 }
218 } else
219 iwl_rx_queue_reset(priv, rxq);
220
221 iwl_rx_replenish(priv);
222
223 iwl_rx_init(priv, rxq);
224
225 spin_lock_irqsave(&priv->lock, flags);
226
227 rxq->need_update = 1;
228 iwl_rx_queue_update_write_ptr(priv, rxq);
229
230 spin_unlock_irqrestore(&priv->lock, flags);
231
232 /* Allocate and init all Tx and Command queues */
233 ret = iwl_txq_ctx_reset(priv);
234 if (ret)
235 return ret;
236
237 set_bit(STATUS_INIT, &priv->status);
238
239 return 0;
240}
241EXPORT_SYMBOL(iwl_hw_nic_init);
242
14d2aac5
AK		 243/*
244 * QoS support
245*/
246void iwl_activate_qos(struct iwl_priv *priv, u8 force)
247{
248 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
249 return;
250
251 priv->qos_data.def_qos_parm.qos_flags = 0;
252
253 if (priv->qos_data.qos_cap.q_AP.queue_request &&
254 !priv->qos_data.qos_cap.q_AP.txop_request)
255 priv->qos_data.def_qos_parm.qos_flags |=
256 QOS_PARAM_FLG_TXOP_TYPE_MSK;
257 if (priv->qos_data.qos_active)
258 priv->qos_data.def_qos_parm.qos_flags |=
259 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
260
261 if (priv->current_ht_config.is_ht)
262 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
263
264 if (force || iwl_is_associated(priv)) {
265 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
266 priv->qos_data.qos_active,
267 priv->qos_data.def_qos_parm.qos_flags);
268
269 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
270 sizeof(struct iwl_qosparam_cmd),
271 &priv->qos_data.def_qos_parm, NULL);
272 }
273}
274EXPORT_SYMBOL(iwl_activate_qos);
275
c7de35cd 276void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 277{
278 u16 cw_min = 15;
279 u16 cw_max = 1023;
280 u8 aifs = 2;
30dab79e 281 bool is_legacy = false;
bf85ea4f
AK		 282 unsigned long flags;
283 int i;
284
285 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 286 /* QoS always active in AP and ADHOC mode
287 * In STA mode wait for association
288 */
289 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
290 priv->iw_mode == NL80211_IFTYPE_AP)
291 priv->qos_data.qos_active = 1;
292 else
293 priv->qos_data.qos_active = 0;
bf85ea4f 294
30dab79e
WT		 295 /* check for legacy mode */
296 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
297 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
298 (priv->iw_mode == NL80211_IFTYPE_STATION &&
299 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 300 cw_min = 31;
301 is_legacy = 1;
302 }
303
304 if (priv->qos_data.qos_active)
305 aifs = 3;
306
307 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
308 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
309 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
310 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
311 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
312
313 if (priv->qos_data.qos_active) {
314 i = 1;
315 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
316 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
317 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
318 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
319 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
320
321 i = 2;
322 priv->qos_data.def_qos_parm.ac[i].cw_min =
323 cpu_to_le16((cw_min + 1) / 2 - 1);
324 priv->qos_data.def_qos_parm.ac[i].cw_max =
325 cpu_to_le16(cw_max);
326 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
327 if (is_legacy)
328 priv->qos_data.def_qos_parm.ac[i].edca_txop =
329 cpu_to_le16(6016);
330 else
331 priv->qos_data.def_qos_parm.ac[i].edca_txop =
332 cpu_to_le16(3008);
333 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
334
335 i = 3;
336 priv->qos_data.def_qos_parm.ac[i].cw_min =
337 cpu_to_le16((cw_min + 1) / 4 - 1);
338 priv->qos_data.def_qos_parm.ac[i].cw_max =
339 cpu_to_le16((cw_max + 1) / 2 - 1);
340 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
341 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
342 if (is_legacy)
343 priv->qos_data.def_qos_parm.ac[i].edca_txop =
344 cpu_to_le16(3264);
345 else
346 priv->qos_data.def_qos_parm.ac[i].edca_txop =
347 cpu_to_le16(1504);
348 } else {
349 for (i = 1; i < 4; i++) {
350 priv->qos_data.def_qos_parm.ac[i].cw_min =
351 cpu_to_le16(cw_min);
352 priv->qos_data.def_qos_parm.ac[i].cw_max =
353 cpu_to_le16(cw_max);
354 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
355 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
356 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
357 }
358 }
e1623446 359 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 360
361 spin_unlock_irqrestore(&priv->lock, flags);
362}
c7de35cd
RR		 363EXPORT_SYMBOL(iwl_reset_qos);
364
d9fe60de
JB		 365#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
366#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 367static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 368 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 369 enum ieee80211_band band)
370{
39130df3
RR		 371 u16 max_bit_rate = 0;
372 u8 rx_chains_num = priv->hw_params.rx_chains_num;
373 u8 tx_chains_num = priv->hw_params.tx_chains_num;
374
c7de35cd 375 ht_info->cap = 0;
d9fe60de 376 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 377
d9fe60de 378 ht_info->ht_supported = true;
c7de35cd 379
d9fe60de
JB		 380 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
381 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
382 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 383 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 384
385 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 386 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 387 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
388 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
389 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 390 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 391 }
c7de35cd
RR		 392
393 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 394 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 395
396 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
397 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
398
d9fe60de 399 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 400 if (rx_chains_num >= 2)
d9fe60de 401 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 402 if (rx_chains_num >= 3)
d9fe60de 403 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 404
405 /* Highest supported Rx data rate */
406 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 407 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
408 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 409
410 /* Tx MCS capabilities */
d9fe60de 411 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 412 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 413 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
414 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
415 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 416 }
c7de35cd 417}
c7de35cd
RR		 418
419static void iwlcore_init_hw_rates(struct iwl_priv *priv,
420 struct ieee80211_rate *rates)
421{
422 int i;
423
424 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 425 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 426 rates[i].hw_value = i; /* Rate scaling will work on indexes */
427 rates[i].hw_value_short = i;
428 rates[i].flags = 0;
429 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
430 /*
431 * If CCK != 1M then set short preamble rate flag.
432 */
433 rates[i].flags |=
1826dcc0 434 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 435 0 : IEEE80211_RATE_SHORT_PREAMBLE;
436 }
437 }
438}
439
8ccde88a 440
c7de35cd
RR		 441/**
442 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
443 */
534166de 444int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 445{
446 struct iwl_channel_info *ch;
447 struct ieee80211_supported_band *sband;
448 struct ieee80211_channel *channels;
449 struct ieee80211_channel *geo_ch;
450 struct ieee80211_rate *rates;
451 int i = 0;
452
453 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
454 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 455 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 456 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
457 return 0;
458 }
459
460 channels = kzalloc(sizeof(struct ieee80211_channel) *
461 priv->channel_count, GFP_KERNEL);
462 if (!channels)
463 return -ENOMEM;
464
465 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
466 GFP_KERNEL);
467 if (!rates) {
468 kfree(channels);
469 return -ENOMEM;
470 }
471
472 /* 5.2GHz channels start after the 2.4GHz channels */
473 sband = &priv->bands[IEEE80211_BAND_5GHZ];
474 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
475 /* just OFDM */
476 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
477 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
478
49779293 479 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 480 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 481 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 482
483 sband = &priv->bands[IEEE80211_BAND_2GHZ];
484 sband->channels = channels;
485 /* OFDM & CCK */
486 sband->bitrates = rates;
487 sband->n_bitrates = IWL_RATE_COUNT;
488
49779293 489 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 490 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 491 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 492
493 priv->ieee_channels = channels;
494 priv->ieee_rates = rates;
495
c7de35cd
RR		 496 for (i = 0; i < priv->channel_count; i++) {
497 ch = &priv->channel_info[i];
498
499 /* FIXME: might be removed if scan is OK */
500 if (!is_channel_valid(ch))
501 continue;
502
503 if (is_channel_a_band(ch))
504 sband = &priv->bands[IEEE80211_BAND_5GHZ];
505 else
506 sband = &priv->bands[IEEE80211_BAND_2GHZ];
507
508 geo_ch = &sband->channels[sband->n_channels++];
509
510 geo_ch->center_freq =
511 ieee80211_channel_to_frequency(ch->channel);
512 geo_ch->max_power = ch->max_power_avg;
513 geo_ch->max_antenna_gain = 0xff;
514 geo_ch->hw_value = ch->channel;
515
516 if (is_channel_valid(ch)) {
517 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
518 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
519
520 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
521 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
522
523 if (ch->flags & EEPROM_CHANNEL_RADAR)
524 geo_ch->flags |= IEEE80211_CHAN_RADAR;
525
963f5517 526 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 527
630fe9b6
TW		 528 if (ch->max_power_avg > priv->tx_power_channel_lmt)
529 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 530 } else {
531 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
532 }
533
534 /* Save flags for reg domain usage */
535 geo_ch->orig_flags = geo_ch->flags;
536
e1623446 537 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 538 ch->channel, geo_ch->center_freq,
539 is_channel_a_band(ch) ? "5.2" : "2.4",
540 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
541 "restricted" : "valid",
542 geo_ch->flags);
543 }
544
545 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
546 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 547 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
548 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 549 priv->pci_dev->device,
550 priv->pci_dev->subsystem_device);
c7de35cd
RR		 551 priv->cfg->sku &= ~IWL_SKU_A;
552 }
553
978785a3 554 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 555 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
556 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 557
558 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
559
560 return 0;
561}
534166de 562EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 563
564/*
565 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
566 */
534166de 567void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 568{
569 kfree(priv->ieee_channels);
570 kfree(priv->ieee_rates);
571 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
572}
534166de 573EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 574
28a6b07a 575static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 576{
577 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 578 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
579 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 580}
963f5517 581
47c5196e
TW		 582static u8 iwl_is_channel_extension(struct iwl_priv *priv,
583 enum ieee80211_band band,
584 u16 channel, u8 extension_chan_offset)
585{
586 const struct iwl_channel_info *ch_info;
587
588 ch_info = iwl_get_channel_info(priv, band, channel);
589 if (!is_channel_valid(ch_info))
590 return 0;
591
d9fe60de 592 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517
EG		 593 return !(ch_info->fat_extension_channel &
594 IEEE80211_CHAN_NO_FAT_ABOVE);
d9fe60de 595 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517
EG		 596 return !(ch_info->fat_extension_channel &
597 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 598
599 return 0;
600}
601
602u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 603 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 604{
605 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
606
607 if ((!iwl_ht_conf->is_ht) ||
608 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
d9fe60de 609 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
47c5196e
TW		 610 return 0;
611
612 if (sta_ht_inf) {
613 if ((!sta_ht_inf->ht_supported) ||
d9fe60de 614 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
47c5196e
TW		 615 return 0;
616 }
617
618 return iwl_is_channel_extension(priv, priv->band,
ae5eb026
JB		 619 le16_to_cpu(priv->staging_rxon.channel),
620 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 621}
622EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
623
8ccde88a
SO		 624void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
625{
626 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
627
628 if (hw_decrypt)
629 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
630 else
631 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
632
633}
634EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
635
636/**
637 * iwl_check_rxon_cmd - validate RXON structure is valid
638 *
639 * NOTE: This is really only useful during development and can eventually
640 * be #ifdef'd out once the driver is stable and folks aren't actively
641 * making changes
642 */
643int iwl_check_rxon_cmd(struct iwl_priv *priv)
644{
645 int error = 0;
646 int counter = 1;
647 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
648
649 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
650 error |= le32_to_cpu(rxon->flags &
651 (RXON_FLG_TGJ_NARROW_BAND_MSK |
652 RXON_FLG_RADAR_DETECT_MSK));
653 if (error)
654 IWL_WARN(priv, "check 24G fields %d | %d\n",
655 counter++, error);
656 } else {
657 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
658 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
659 if (error)
660 IWL_WARN(priv, "check 52 fields %d | %d\n",
661 counter++, error);
662 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
663 if (error)
664 IWL_WARN(priv, "check 52 CCK %d | %d\n",
665 counter++, error);
666 }
667 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
668 if (error)
669 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
670
671 /* make sure basic rates 6Mbps and 1Mbps are supported */
672 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
673 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
674 if (error)
675 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
676
677 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
678 if (error)
679 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
680
681 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
682 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
683 if (error)
684 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
685 counter++, error);
686
687 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
688 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
689 if (error)
690 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
691 counter++, error);
692
693 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
694 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
695 if (error)
696 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
697 counter++, error);
698
699 if (error)
700 IWL_WARN(priv, "Tuning to channel %d\n",
701 le16_to_cpu(rxon->channel));
702
703 if (error) {
704 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
705 return -1;
706 }
707 return 0;
708}
709EXPORT_SYMBOL(iwl_check_rxon_cmd);
710
711/**
712 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
713 * @priv: staging_rxon is compared to active_rxon
714 *
715 * If the RXON structure is changing enough to require a new tune,
716 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
717 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
718 */
719int iwl_full_rxon_required(struct iwl_priv *priv)
720{
721
722 /* These items are only settable from the full RXON command */
723 if (!(iwl_is_associated(priv)) ||
724 compare_ether_addr(priv->staging_rxon.bssid_addr,
725 priv->active_rxon.bssid_addr) ||
726 compare_ether_addr(priv->staging_rxon.node_addr,
727 priv->active_rxon.node_addr) ||
728 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
729 priv->active_rxon.wlap_bssid_addr) ||
730 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
731 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
732 (priv->staging_rxon.air_propagation !=
733 priv->active_rxon.air_propagation) ||
734 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
735 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
736 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
737 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
738 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
739 return 1;
740
741 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
742 * be updated with the RXON_ASSOC command -- however only some
743 * flag transitions are allowed using RXON_ASSOC */
744
745 /* Check if we are not switching bands */
746 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
747 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
748 return 1;
749
750 /* Check if we are switching association toggle */
751 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
752 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
753 return 1;
754
755 return 0;
756}
757EXPORT_SYMBOL(iwl_full_rxon_required);
758
759u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
760{
761 int i;
762 int rate_mask;
763
764 /* Set rate mask*/
765 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
766 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
767 else
768 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
769
770 /* Find lowest valid rate */
771 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
772 i = iwl_rates[i].next_ieee) {
773 if (rate_mask & (1 << i))
774 return iwl_rates[i].plcp;
775 }
776
777 /* No valid rate was found. Assign the lowest one */
778 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
779 return IWL_RATE_1M_PLCP;
780 else
781 return IWL_RATE_6M_PLCP;
782}
783EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
784
47c5196e
TW		 785void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
786{
c1adf9fb 787 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 788 u32 val;
789
42eb7c64
EG		 790 if (!ht_info->is_ht) {
791 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
792 RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
793 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
794 RXON_FLG_FAT_PROT_MSK |
795 RXON_FLG_HT_PROT_MSK);
47c5196e 796 return;
42eb7c64 797 }
47c5196e
TW		 798
799 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
800 if (iwl_is_fat_tx_allowed(priv, NULL))
801 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
802 else
803 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
804 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
805
47c5196e
TW		 806 /* Note: control channel is opposite of extension channel */
807 switch (ht_info->extension_chan_offset) {
d9fe60de 808 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
47c5196e
TW		 809 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
810 break;
d9fe60de 811 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
47c5196e
TW		 812 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
813 break;
d9fe60de 814 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
47c5196e
TW		 815 default:
816 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
817 break;
818 }
819
820 val = ht_info->ht_protection;
821
822 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
823
824 iwl_set_rxon_chain(priv);
825
e1623446 826 IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
47c5196e 827 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 828 "extension channel offset 0x%x\n",
d9fe60de
JB		 829 ht_info->mcs.rx_mask[0],
830 ht_info->mcs.rx_mask[1],
831 ht_info->mcs.rx_mask[2],
47c5196e 832 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 833 ht_info->extension_chan_offset);
47c5196e
TW		 834 return;
835}
836EXPORT_SYMBOL(iwl_set_rxon_ht);
837
9e5e6c32
TW		 838#define IWL_NUM_RX_CHAINS_MULTIPLE 3
839#define IWL_NUM_RX_CHAINS_SINGLE 2
840#define IWL_NUM_IDLE_CHAINS_DUAL 2
841#define IWL_NUM_IDLE_CHAINS_SINGLE 1
842
843/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 844 * More provides better reception via diversity. Fewer saves power.
845 * MIMO (dual stream) requires at least 2, but works better with 3.
846 * This does not determine *which* chains to use, just how many.
847 */
28a6b07a 848static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 849{
28a6b07a
TW		 850 bool is_single = is_single_rx_stream(priv);
851 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 852
853 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 854 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
855 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 856 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 857 else
9e5e6c32 858 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 859}
c7de35cd 860
28a6b07a
TW		 861static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
862{
863 int idle_cnt;
864 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 865 /* # Rx chains when idling and maybe trying to save power */
12837be1 866 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 867 case WLAN_HT_CAP_SM_PS_STATIC:
868 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 869 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
870 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 871 break;
00c5ae2f 872 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 873 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 874 break;
00c5ae2f 875 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 876 default:
15b1687c 877 IWL_ERR(priv, "invalid mimo ps mode %d\n",
12837be1 878 priv->current_ht_config.sm_ps);
28a6b07a
TW		 879 WARN_ON(1);
880 idle_cnt = -1;
c7de35cd
RR		 881 break;
882 }
28a6b07a 883 return idle_cnt;
c7de35cd
RR		 884}
885
04816448
GE		 886/* up to 4 chains */
887static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
888{
889 u8 res;
890 res = (chain_bitmap & BIT(0)) >> 0;
891 res += (chain_bitmap & BIT(1)) >> 1;
892 res += (chain_bitmap & BIT(2)) >> 2;
893 res += (chain_bitmap & BIT(4)) >> 4;
894 return res;
895}
896
4c4df78f
CR		 897/**
898 * iwl_is_monitor_mode - Determine if interface in monitor mode
899 *
900 * priv->iw_mode is set in add_interface, but add_interface is
901 * never called for monitor mode. The only way mac80211 informs us about
902 * monitor mode is through configuring filters (call to configure_filter).
903 */
904static bool iwl_is_monitor_mode(struct iwl_priv *priv)
905{
906 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
907}
908
c7de35cd
RR		 909/**
910 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
911 *
912 * Selects how many and which Rx receivers/antennas/chains to use.
913 * This should not be used for scan command ... it puts data in wrong place.
914 */
915void iwl_set_rxon_chain(struct iwl_priv *priv)
916{
28a6b07a
TW		 917 bool is_single = is_single_rx_stream(priv);
918 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 919 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
920 u32 active_chains;
28a6b07a 921 u16 rx_chain;
c7de35cd
RR		 922
923 /* Tell uCode which antennas are actually connected.
924 * Before first association, we assume all antennas are connected.
925 * Just after first association, iwl_chain_noise_calibration()
926 * checks which antennas actually *are* connected. */
04816448
GE		 927 if (priv->chain_noise_data.active_chains)
928 active_chains = priv->chain_noise_data.active_chains;
929 else
930 active_chains = priv->hw_params.valid_rx_ant;
931
932 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 933
934 /* How many receivers should we use? */
28a6b07a
TW		 935 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
936 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
937
28a6b07a 938
04816448
GE		 939 /* correct rx chain count according hw settings
940 * and chain noise calibration
941 */
942 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
943 if (valid_rx_cnt < active_rx_cnt)
944 active_rx_cnt = valid_rx_cnt;
945
946 if (valid_rx_cnt < idle_rx_cnt)
947 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 948
949 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
950 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
951
7b841727
RF		 952 /* copied from 'iwl_bg_request_scan()' */
953 /* Force use of chains B and C (0x6) for Rx for 4965
954 * Avoid A (0x1) because of its off-channel reception on A-band.
955 * MIMO is not used here, but value is required */
956 if (iwl_is_monitor_mode(priv) &&
957 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
958 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
959 rx_chain = 0x07 << RXON_RX_CHAIN_VALID_POS;
960 rx_chain |= 0x06 << RXON_RX_CHAIN_FORCE_SEL_POS;
961 rx_chain |= 0x07 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
962 rx_chain |= 0x01 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
963 }
964
28a6b07a
TW		 965 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
966
9e5e6c32 967 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 968 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
969 else
970 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
971
e1623446 972 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 973 priv->staging_rxon.rx_chain,
974 active_rx_cnt, idle_rx_cnt);
975
976 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
977 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 978}
979EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 980
981/**
17e72782 982 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 983 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
984 * @channel: Any channel valid for the requested phymode
985
986 * In addition to setting the staging RXON, priv->phymode is also set.
987 *
988 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
989 * in the staging RXON flag structure based on the phymode
990 */
17e72782 991int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 992{
17e72782
TW		 993 enum ieee80211_band band = ch->band;
994 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
995
8622e705 996 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 997 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 998 channel, band);
999 return -EINVAL;
1000 }
1001
1002 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1003 (priv->band == band))
1004 return 0;
1005
1006 priv->staging_rxon.channel = cpu_to_le16(channel);
1007 if (band == IEEE80211_BAND_5GHZ)
1008 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1009 else
1010 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1011
1012 priv->band = band;
1013
e1623446 1014 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1015
1016 return 0;
1017}
c7de35cd 1018EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1019
8ccde88a
SO		 1020void iwl_set_flags_for_band(struct iwl_priv *priv,
1021 enum ieee80211_band band)
1022{
1023 if (band == IEEE80211_BAND_5GHZ) {
1024 priv->staging_rxon.flags &=
1025 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1026 | RXON_FLG_CCK_MSK);
1027 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1028 } else {
1029 /* Copied from iwl_post_associate() */
1030 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1031 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1032 else
1033 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1034
1035 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1036 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1037
1038 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1039 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1040 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1041 }
1042}
1043EXPORT_SYMBOL(iwl_set_flags_for_band);
1044
1045/*
1046 * initialize rxon structure with default values from eeprom
1047 */
1048void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1049{
1050 const struct iwl_channel_info *ch_info;
1051
1052 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1053
1054 switch (mode) {
1055 case NL80211_IFTYPE_AP:
1056 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1057 break;
1058
1059 case NL80211_IFTYPE_STATION:
1060 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1061 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1062 break;
1063
1064 case NL80211_IFTYPE_ADHOC:
1065 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1066 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1067 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1068 RXON_FILTER_ACCEPT_GRP_MSK;
1069 break;
1070
1071 case NL80211_IFTYPE_MONITOR:
1072 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
1073 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
1074 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
1075 break;
1076 default:
1077 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1078 break;
1079 }
1080
1081#if 0
1082 /* TODO: Figure out when short_preamble would be set and cache from
1083 * that */
1084 if (!hw_to_local(priv->hw)->short_preamble)
1085 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1086 else
1087 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1088#endif
1089
1090 ch_info = iwl_get_channel_info(priv, priv->band,
1091 le16_to_cpu(priv->active_rxon.channel));
1092
1093 if (!ch_info)
1094 ch_info = &priv->channel_info[0];
1095
1096 /*
1097 * in some case A channels are all non IBSS
1098 * in this case force B/G channel
1099 */
1100 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1101 !(is_channel_ibss(ch_info)))
1102 ch_info = &priv->channel_info[0];
1103
1104 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1105 priv->band = ch_info->band;
1106
1107 iwl_set_flags_for_band(priv, priv->band);
1108
1109 priv->staging_rxon.ofdm_basic_rates =
1110 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1111 priv->staging_rxon.cck_basic_rates =
1112 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1113
1114 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
1115 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
1116 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1117 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1118 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1119 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1120 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1121}
1122EXPORT_SYMBOL(iwl_connection_init_rx_config);
1123
1124void iwl_set_rate(struct iwl_priv *priv)
1125{
1126 const struct ieee80211_supported_band *hw = NULL;
1127 struct ieee80211_rate *rate;
1128 int i;
1129
1130 hw = iwl_get_hw_mode(priv, priv->band);
1131 if (!hw) {
1132 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1133 return;
1134 }
1135
1136 priv->active_rate = 0;
1137 priv->active_rate_basic = 0;
1138
1139 for (i = 0; i < hw->n_bitrates; i++) {
1140 rate = &(hw->bitrates[i]);
1141 if (rate->hw_value < IWL_RATE_COUNT)
1142 priv->active_rate |= (1 << rate->hw_value);
1143 }
1144
e1623446 1145 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1146 priv->active_rate, priv->active_rate_basic);
1147
1148 /*
1149 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1150 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1151 * OFDM
1152 */
1153 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1154 priv->staging_rxon.cck_basic_rates =
1155 ((priv->active_rate_basic &
1156 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1157 else
1158 priv->staging_rxon.cck_basic_rates =
1159 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1160
1161 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1162 priv->staging_rxon.ofdm_basic_rates =
1163 ((priv->active_rate_basic &
1164 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1165 IWL_FIRST_OFDM_RATE) & 0xFF;
1166 else
1167 priv->staging_rxon.ofdm_basic_rates =
1168 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1169}
1170EXPORT_SYMBOL(iwl_set_rate);
1171
1172void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1173{
1174 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1175 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1176 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
e1623446 1177 IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
8ccde88a
SO		 1178 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
1179 rxon->channel = csa->channel;
1180 priv->staging_rxon.channel = csa->channel;
1181}
1182EXPORT_SYMBOL(iwl_rx_csa);
1183
1184#ifdef CONFIG_IWLWIFI_DEBUG
1185static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1186{
1187 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1188
e1623446 1189 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
8ccde88a 1190 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1191 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1192 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1193 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1194 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1195 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1196 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1197 rxon->ofdm_basic_rates);
e1623446
TW		 1198 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1199 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1200 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1201 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a
SO		 1202}
1203#endif
1204
1205/**
1206 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1207 */
1208void iwl_irq_handle_error(struct iwl_priv *priv)
1209{
1210 /* Set the FW error flag -- cleared on iwl_down */
1211 set_bit(STATUS_FW_ERROR, &priv->status);
1212
1213 /* Cancel currently queued command. */
1214 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1215
1216#ifdef CONFIG_IWLWIFI_DEBUG
1217 if (priv->debug_level & IWL_DL_FW_ERRORS) {
1218 iwl_dump_nic_error_log(priv);
1219 iwl_dump_nic_event_log(priv);
1220 iwl_print_rx_config_cmd(priv);
1221 }
1222#endif
1223
1224 wake_up_interruptible(&priv->wait_command_queue);
1225
1226 /* Keep the restart process from trying to send host
1227 * commands by clearing the INIT status bit */
1228 clear_bit(STATUS_READY, &priv->status);
1229
1230 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1231 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1232 "Restarting adapter due to uCode error.\n");
1233
1234 if (iwl_is_associated(priv)) {
1235 memcpy(&priv->recovery_rxon, &priv->active_rxon,
1236 sizeof(priv->recovery_rxon));
1237 priv->error_recovering = 1;
1238 }
1239 if (priv->cfg->mod_params->restart_fw)
1240 queue_work(priv->workqueue, &priv->restart);
1241 }
1242}
1243EXPORT_SYMBOL(iwl_irq_handle_error);
1244
1245void iwl_configure_filter(struct ieee80211_hw *hw,
1246 unsigned int changed_flags,
1247 unsigned int *total_flags,
1248 int mc_count, struct dev_addr_list *mc_list)
1249{
1250 struct iwl_priv *priv = hw->priv;
1251 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1252
e1623446 1253 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1254 changed_flags, *total_flags);
1255
1256 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1257 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1258 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1259 else
1260 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1261 }
1262 if (changed_flags & FIF_ALLMULTI) {
1263 if (*total_flags & FIF_ALLMULTI)
1264 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1265 else
1266 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1267 }
1268 if (changed_flags & FIF_CONTROL) {
1269 if (*total_flags & FIF_CONTROL)
1270 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1271 else
1272 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1273 }
1274 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1275 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1276 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1277 else
1278 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1279 }
1280
1281 /* We avoid iwl_commit_rxon here to commit the new filter flags
1282 * since mac80211 will call ieee80211_hw_config immediately.
1283 * (mc_list is not supported at this time). Otherwise, we need to
1284 * queue a background iwl_commit_rxon work.
1285 */
1286
1287 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1288 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1289}
1290EXPORT_SYMBOL(iwl_configure_filter);
1291
6ba87956 1292int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 1293{
6ba87956 1294 int ret;
bf85ea4f 1295 struct ieee80211_hw *hw = priv->hw;
e227ceac 1296 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 1297
566bfe5a 1298 /* Tell mac80211 our characteristics */
605a0bd6 1299 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe 1300 IEEE80211_HW_NOISE_DBM |
4be8c387 1301 IEEE80211_HW_AMPDU_AGGREGATION |
b1c6019b 1302 IEEE80211_HW_SPECTRUM_MGMT |
4be8c387 1303 IEEE80211_HW_SUPPORTS_PS;
f59ac048 1304 hw->wiphy->interface_modes =
f59ac048
LR		 1305 BIT(NL80211_IFTYPE_STATION) |
1306 BIT(NL80211_IFTYPE_ADHOC);
ea4a82dc 1307
2a44f911 1308 hw->wiphy->custom_regulatory = true;
2a519311 1309 hw->wiphy->max_scan_ssids = 1;
18a83659 1310 hw->wiphy->max_scan_ie_len = 0; /* XXX for now */
ea4a82dc 1311
bf85ea4f
AK		 1312 /* Default value; 4 EDCA QOS priorities */
1313 hw->queues = 4;
6ba87956
TW		 1314
1315 hw->conf.beacon_int = 100;
b5d7be5e 1316 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 1317
1318 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
1319 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1320 &priv->bands[IEEE80211_BAND_2GHZ];
1321 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
1322 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1323 &priv->bands[IEEE80211_BAND_5GHZ];
1324
1325 ret = ieee80211_register_hw(priv->hw);
1326 if (ret) {
15b1687c 1327 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
6ba87956
TW		 1328 return ret;
1329 }
1330 priv->mac80211_registered = 1;
1331
1332 return 0;
bf85ea4f 1333}
6ba87956 1334EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 1335
da154e30
RR		 1336int iwl_set_hw_params(struct iwl_priv *priv)
1337{
1338 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
1339 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1340 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1341 if (priv->cfg->mod_params->amsdu_size_8K)
1342 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1343 else
1344 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1345 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1346
49779293
RR		 1347 if (priv->cfg->mod_params->disable_11n)
1348 priv->cfg->sku &= ~IWL_SKU_N;
1349
da154e30
RR		 1350 /* Device-specific setup */
1351 return priv->cfg->ops->lib->set_hw_params(priv);
1352}
1353EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 1354
1355int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 1356{
1357 int ret;
c7de35cd 1358
c7de35cd
RR		 1359 priv->ibss_beacon = NULL;
1360
1361 spin_lock_init(&priv->lock);
1362 spin_lock_init(&priv->power_data.lock);
1363 spin_lock_init(&priv->sta_lock);
1364 spin_lock_init(&priv->hcmd_lock);
c7de35cd 1365
c7de35cd
RR		 1366 INIT_LIST_HEAD(&priv->free_frames);
1367
1368 mutex_init(&priv->mutex);
1369
1370 /* Clear the driver's (not device's) station table */
37deb2a0 1371 iwl_clear_stations_table(priv);
c7de35cd
RR		 1372
1373 priv->data_retry_limit = -1;
1374 priv->ieee_channels = NULL;
1375 priv->ieee_rates = NULL;
1376 priv->band = IEEE80211_BAND_2GHZ;
1377
05c914fe 1378 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 1379
12837be1 1380 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 1381
1382 /* Choose which receivers/antennas to use */
1383 iwl_set_rxon_chain(priv);
f53696de 1384 iwl_init_scan_params(priv);
c7de35cd
RR		 1385
1386 iwl_reset_qos(priv);
1387
1388 priv->qos_data.qos_active = 0;
1389 priv->qos_data.qos_cap.val = 0;
1390
c7de35cd 1391 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT		 1392 /* If power management is turned on, default to CAM mode */
1393 priv->power_mode = IWL_POWER_MODE_CAM;
630fe9b6 1394 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 1395
1396 ret = iwl_init_channel_map(priv);
1397 if (ret) {
15b1687c 1398 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
c7de35cd
RR		 1399 goto err;
1400 }
1401
1402 ret = iwlcore_init_geos(priv);
1403 if (ret) {
15b1687c 1404 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
c7de35cd
RR		 1405 goto err_free_channel_map;
1406 }
534166de 1407 iwlcore_init_hw_rates(priv, priv->ieee_rates);
c7de35cd 1408
c7de35cd
RR		 1409 return 0;
1410
c7de35cd
RR		 1411err_free_channel_map:
1412 iwl_free_channel_map(priv);
1413err:
1414 return ret;
1415}
6ba87956 1416EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 1417
630fe9b6
TW		 1418int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1419{
1420 int ret = 0;
1421 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1422 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1423 tx_power,
1424 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1425 return -EINVAL;
1426 }
1427
1428 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
daf518de
WF		 1429 IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
1430 tx_power,
1431 IWL_TX_POWER_TARGET_POWER_MAX);
630fe9b6
TW		 1432 return -EINVAL;
1433 }
1434
1435 if (priv->tx_power_user_lmt != tx_power)
1436 force = true;
1437
1438 priv->tx_power_user_lmt = tx_power;
1439
019fb97d
MA		 1440 /* if nic is not up don't send command */
1441 if (!iwl_is_ready_rf(priv))
1442 return ret;
1443
630fe9b6
TW		 1444 if (force && priv->cfg->ops->lib->send_tx_power)
1445 ret = priv->cfg->ops->lib->send_tx_power(priv);
1446
1447 return ret;
1448}
1449EXPORT_SYMBOL(iwl_set_tx_power);
1450
6ba87956 1451void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1452{
6e21f2c1 1453 iwl_calib_free_results(priv);
6ba87956
TW		 1454 iwlcore_free_geos(priv);
1455 iwl_free_channel_map(priv);
261415f7 1456 kfree(priv->scan);
bf85ea4f 1457}
6ba87956 1458EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1459
0ad91a35
WT		 1460
1461void iwl_disable_interrupts(struct iwl_priv *priv)
1462{
1463 clear_bit(STATUS_INT_ENABLED, &priv->status);
1464
1465 /* disable interrupts from uCode/NIC to host */
1466 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1467
1468 /* acknowledge/clear/reset any interrupts still pending
1469 * from uCode or flow handler (Rx/Tx DMA) */
1470 iwl_write32(priv, CSR_INT, 0xffffffff);
1471 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
e1623446 1472 IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
0ad91a35
WT		 1473}
1474EXPORT_SYMBOL(iwl_disable_interrupts);
1475
1476void iwl_enable_interrupts(struct iwl_priv *priv)
1477{
e1623446 1478 IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
0ad91a35
WT		 1479 set_bit(STATUS_INT_ENABLED, &priv->status);
1480 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
1481}
1482EXPORT_SYMBOL(iwl_enable_interrupts);
1483
f17d08a6
AK		 1484irqreturn_t iwl_isr(int irq, void *data)
1485{
1486 struct iwl_priv *priv = data;
1487 u32 inta, inta_mask;
1488 u32 inta_fh;
1489 if (!priv)
1490 return IRQ_NONE;
1491
1492 spin_lock(&priv->lock);
1493
1494 /* Disable (but don't clear!) interrupts here to avoid
1495 * back-to-back ISRs and sporadic interrupts from our NIC.
1496 * If we have something to service, the tasklet will re-enable ints.
1497 * If we *don't* have something, we'll re-enable before leaving here. */
1498 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1499 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1500
1501 /* Discover which interrupts are active/pending */
1502 inta = iwl_read32(priv, CSR_INT);
1503 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1504
1505 /* Ignore interrupt if there's nothing in NIC to service.
1506 * This may be due to IRQ shared with another device,
1507 * or due to sporadic interrupts thrown from our NIC. */
1508 if (!inta && !inta_fh) {
1509 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1510 goto none;
1511 }
1512
1513 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1514 /* Hardware disappeared. It might have already raised
1515 * an interrupt */
1516 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1517 goto unplugged;
1518 }
1519
1520 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1521 inta, inta_mask, inta_fh);
1522
1523 inta &= ~CSR_INT_BIT_SCD;
1524
1525 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1526 if (likely(inta || inta_fh))
1527 tasklet_schedule(&priv->irq_tasklet);
1528
1529 unplugged:
1530 spin_unlock(&priv->lock);
1531 return IRQ_HANDLED;
1532
1533 none:
1534 /* re-enable interrupts here since we don't have anything to service. */
1535 /* only Re-enable if diabled by irq */
1536 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1537 iwl_enable_interrupts(priv);
1538 spin_unlock(&priv->lock);
1539 return IRQ_NONE;
1540}
1541EXPORT_SYMBOL(iwl_isr);
1542
17f841cd
SO		 1543int iwl_send_bt_config(struct iwl_priv *priv)
1544{
1545 struct iwl_bt_cmd bt_cmd = {
1546 .flags = 3,
1547 .lead_time = 0xAA,
1548 .max_kill = 1,
1549 .kill_ack_mask = 0,
1550 .kill_cts_mask = 0,
1551 };
1552
1553 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1554 sizeof(struct iwl_bt_cmd), &bt_cmd);
1555}
1556EXPORT_SYMBOL(iwl_send_bt_config);
1557
49ea8596
EG		 1558int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1559{
1560 u32 stat_flags = 0;
1561 struct iwl_host_cmd cmd = {
1562 .id = REPLY_STATISTICS_CMD,
1563 .meta.flags = flags,
1564 .len = sizeof(stat_flags),
1565 .data = (u8 *) &stat_flags,
1566 };
1567 return iwl_send_cmd(priv, &cmd);
1568}
1569EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1570
b0692f2f
EG		 1571/**
1572 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1573 * using sample data 100 bytes apart. If these sample points are good,
1574 * it's a pretty good bet that everything between them is good, too.
1575 */
1576static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1577{
1578 u32 val;
1579 int ret = 0;
1580 u32 errcnt = 0;
1581 u32 i;
1582
e1623446 1583 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f
EG		 1584
1585 ret = iwl_grab_nic_access(priv);
1586 if (ret)
1587 return ret;
1588
1589 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1590 /* read data comes through single port, auto-incr addr */
1591 /* NOTE: Use the debugless read so we don't flood kernel log
1592 * if IWL_DL_IO is set */
1593 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1594 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1595 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1596 if (val != le32_to_cpu(*image)) {
1597 ret = -EIO;
1598 errcnt++;
1599 if (errcnt >= 3)
1600 break;
1601 }
1602 }
1603
1604 iwl_release_nic_access(priv);
1605
1606 return ret;
1607}
1608
1609/**
1610 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1611 * looking at all data.
1612 */
1613static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1614 u32 len)
1615{
1616 u32 val;
1617 u32 save_len = len;
1618 int ret = 0;
1619 u32 errcnt;
1620
e1623446 1621 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f
EG		 1622
1623 ret = iwl_grab_nic_access(priv);
1624 if (ret)
1625 return ret;
1626
250bdd21
SO		 1627 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1628 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1629
1630 errcnt = 0;
1631 for (; len > 0; len -= sizeof(u32), image++) {
1632 /* read data comes through single port, auto-incr addr */
1633 /* NOTE: Use the debugless read so we don't flood kernel log
1634 * if IWL_DL_IO is set */
1635 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1636 if (val != le32_to_cpu(*image)) {
15b1687c 1637 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 1638 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1639 save_len - len, val, le32_to_cpu(*image));
1640 ret = -EIO;
1641 errcnt++;
1642 if (errcnt >= 20)
1643 break;
1644 }
1645 }
1646
1647 iwl_release_nic_access(priv);
1648
1649 if (!errcnt)
e1623446
TW		 1650 IWL_DEBUG_INFO(priv,
1651 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 1652
1653 return ret;
1654}
1655
1656/**
1657 * iwl_verify_ucode - determine which instruction image is in SRAM,
1658 * and verify its contents
1659 */
1660int iwl_verify_ucode(struct iwl_priv *priv)
1661{
1662 __le32 *image;
1663 u32 len;
1664 int ret;
1665
1666 /* Try bootstrap */
1667 image = (__le32 *)priv->ucode_boot.v_addr;
1668 len = priv->ucode_boot.len;
1669 ret = iwlcore_verify_inst_sparse(priv, image, len);
1670 if (!ret) {
e1623446 1671 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 1672 return 0;
1673 }
1674
1675 /* Try initialize */
1676 image = (__le32 *)priv->ucode_init.v_addr;
1677 len = priv->ucode_init.len;
1678 ret = iwlcore_verify_inst_sparse(priv, image, len);
1679 if (!ret) {
e1623446 1680 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 1681 return 0;
1682 }
1683
1684 /* Try runtime/protocol */
1685 image = (__le32 *)priv->ucode_code.v_addr;
1686 len = priv->ucode_code.len;
1687 ret = iwlcore_verify_inst_sparse(priv, image, len);
1688 if (!ret) {
e1623446 1689 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 1690 return 0;
1691 }
1692
15b1687c 1693 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 1694
1695 /* Since nothing seems to match, show first several data entries in
1696 * instruction SRAM, so maybe visual inspection will give a clue.
1697 * Selection of bootstrap image (vs. other images) is arbitrary. */
1698 image = (__le32 *)priv->ucode_boot.v_addr;
1699 len = priv->ucode_boot.len;
1700 ret = iwl_verify_inst_full(priv, image, len);
1701
1702 return ret;
1703}
1704EXPORT_SYMBOL(iwl_verify_ucode);
1705
56e12615
JS		 1706
1707static const char *desc_lookup_text[] = {
1708 "OK",
1709 "FAIL",
1710 "BAD_PARAM",
1711 "BAD_CHECKSUM",
1712 "NMI_INTERRUPT_WDG",
1713 "SYSASSERT",
1714 "FATAL_ERROR",
1715 "BAD_COMMAND",
1716 "HW_ERROR_TUNE_LOCK",
1717 "HW_ERROR_TEMPERATURE",
1718 "ILLEGAL_CHAN_FREQ",
1719 "VCC_NOT_STABLE",
1720 "FH_ERROR",
1721 "NMI_INTERRUPT_HOST",
1722 "NMI_INTERRUPT_ACTION_PT",
1723 "NMI_INTERRUPT_UNKNOWN",
1724 "UCODE_VERSION_MISMATCH",
1725 "HW_ERROR_ABS_LOCK",
1726 "HW_ERROR_CAL_LOCK_FAIL",
1727 "NMI_INTERRUPT_INST_ACTION_PT",
1728 "NMI_INTERRUPT_DATA_ACTION_PT",
1729 "NMI_TRM_HW_ER",
1730 "NMI_INTERRUPT_TRM",
1731 "NMI_INTERRUPT_BREAK_POINT"
1732 "DEBUG_0",
1733 "DEBUG_1",
1734 "DEBUG_2",
1735 "DEBUG_3",
1736 "UNKNOWN"
1737};
1738
ede0cba4
EK		 1739static const char *desc_lookup(int i)
1740{
56e12615
JS		 1741 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1742
1743 if (i < 0 || i > max)
1744 i = max;
ede0cba4 1745
56e12615 1746 return desc_lookup_text[i];
ede0cba4
EK		 1747}
1748
1749#define ERROR_START_OFFSET (1 * sizeof(u32))
1750#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1751
1752void iwl_dump_nic_error_log(struct iwl_priv *priv)
1753{
1754 u32 data2, line;
1755 u32 desc, time, count, base, data1;
1756 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1757 int ret;
ede0cba4 1758
e1dfc085
GG		 1759 if (priv->ucode_type == UCODE_INIT)
1760 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1761 else
1762 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1763
1764 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 1765 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
ede0cba4
EK		 1766 return;
1767 }
1768
e1dfc085
GG		 1769 ret = iwl_grab_nic_access(priv);
1770 if (ret) {
39aadf8c 1771 IWL_WARN(priv, "Can not read from adapter at this time.\n");
ede0cba4
EK		 1772 return;
1773 }
1774
1775 count = iwl_read_targ_mem(priv, base);
1776
1777 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT		 1778 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1779 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1780 priv->status, count);
ede0cba4
EK		 1781 }
1782
1783 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1784 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1785 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1786 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1787 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1788 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1789 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1790 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1791 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1792
15b1687c 1793 IWL_ERR(priv, "Desc Time "
ede0cba4 1794 "data1 data2 line\n");
15b1687c 1795 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
ede0cba4 1796 desc_lookup(desc), desc, time, data1, data2, line);
15b1687c
WT		 1797 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1798 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
ede0cba4
EK		 1799 ilink1, ilink2);
1800
1801 iwl_release_nic_access(priv);
1802}
1803EXPORT_SYMBOL(iwl_dump_nic_error_log);
1804
189a2b59
EK		 1805#define EVENT_START_OFFSET (4 * sizeof(u32))
1806
1807/**
1808 * iwl_print_event_log - Dump error event log to syslog
1809 *
a33c2f47 1810 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
189a2b59 1811 */
a33c2f47 1812static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 1813 u32 num_events, u32 mode)
1814{
1815 u32 i;
1816 u32 base; /* SRAM byte address of event log header */
1817 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1818 u32 ptr; /* SRAM byte address of log data */
1819 u32 ev, time, data; /* event log data */
1820
1821 if (num_events == 0)
1822 return;
e1dfc085
GG		 1823 if (priv->ucode_type == UCODE_INIT)
1824 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1825 else
1826 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1827
1828 if (mode == 0)
1829 event_size = 2 * sizeof(u32);
1830 else
1831 event_size = 3 * sizeof(u32);
1832
1833 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1834
1835 /* "time" is actually "data" for mode 0 (no timestamp).
1836 * place event id # at far right for easier visual parsing. */
1837 for (i = 0; i < num_events; i++) {
1838 ev = iwl_read_targ_mem(priv, ptr);
1839 ptr += sizeof(u32);
1840 time = iwl_read_targ_mem(priv, ptr);
1841 ptr += sizeof(u32);
77c5d08e
TW		 1842 if (mode == 0) {
1843 /* data, ev */
15b1687c 1844 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
77c5d08e 1845 } else {
189a2b59
EK		 1846 data = iwl_read_targ_mem(priv, ptr);
1847 ptr += sizeof(u32);
15b1687c 1848 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
77c5d08e 1849 time, data, ev);
189a2b59
EK		 1850 }
1851 }
1852}
189a2b59
EK		 1853
1854void iwl_dump_nic_event_log(struct iwl_priv *priv)
1855{
e1dfc085 1856 int ret;
189a2b59
EK		 1857 u32 base; /* SRAM byte address of event log header */
1858 u32 capacity; /* event log capacity in # entries */
1859 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1860 u32 num_wraps; /* # times uCode wrapped to top of log */
1861 u32 next_entry; /* index of next entry to be written by uCode */
1862 u32 size; /* # entries that we'll print */
1863
e1dfc085
GG		 1864 if (priv->ucode_type == UCODE_INIT)
1865 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1866 else
1867 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1868
189a2b59 1869 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 1870 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
189a2b59
EK		 1871 return;
1872 }
1873
e1dfc085
GG		 1874 ret = iwl_grab_nic_access(priv);
1875 if (ret) {
39aadf8c 1876 IWL_WARN(priv, "Can not read from adapter at this time.\n");
189a2b59
EK		 1877 return;
1878 }
1879
1880 /* event log header */
1881 capacity = iwl_read_targ_mem(priv, base);
1882 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1883 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1884 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1885
1886 size = num_wraps ? capacity : next_entry;
1887
1888 /* bail out if nothing in log */
1889 if (size == 0) {
15b1687c 1890 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
189a2b59
EK		 1891 iwl_release_nic_access(priv);
1892 return;
1893 }
1894
15b1687c 1895 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
189a2b59
EK		 1896 size, num_wraps);
1897
1898 /* if uCode has wrapped back to top of log, start at the oldest entry,
1899 * i.e the next one that uCode would fill. */
1900 if (num_wraps)
1901 iwl_print_event_log(priv, next_entry,
1902 capacity - next_entry, mode);
1903 /* (then/else) start at top of log */
1904 iwl_print_event_log(priv, 0, next_entry, mode);
1905
1906 iwl_release_nic_access(priv);
1907}
1908EXPORT_SYMBOL(iwl_dump_nic_event_log);
1909
47f4a587
EG		 1910void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1911{
1912 struct iwl_ct_kill_config cmd;
1913 unsigned long flags;
1914 int ret = 0;
1915
1916 spin_lock_irqsave(&priv->lock, flags);
1917 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1918 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1919 spin_unlock_irqrestore(&priv->lock, flags);
1920
1921 cmd.critical_temperature_R =
1922 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1923
47f4a587
EG		 1924 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1925 sizeof(cmd), &cmd);
1926 if (ret)
15b1687c 1927 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
47f4a587 1928 else
e1623446 1929 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
47f4a587
EG		 1930 "critical temperature is %d\n",
1931 cmd.critical_temperature_R);
1932}
1933EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 1934
0ad91a35 1935
14a08a7f
EG		 1936/*
1937 * CARD_STATE_CMD
1938 *
1939 * Use: Sets the device's internal card state to enable, disable, or halt
1940 *
1941 * When in the 'enable' state the card operates as normal.
1942 * When in the 'disable' state, the card enters into a low power mode.
1943 * When in the 'halt' state, the card is shut down and must be fully
1944 * restarted to come back on.
1945 */
c496294e 1946int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 1947{
1948 struct iwl_host_cmd cmd = {
1949 .id = REPLY_CARD_STATE_CMD,
1950 .len = sizeof(u32),
1951 .data = &flags,
1952 .meta.flags = meta_flag,
1953 };
1954
1955 return iwl_send_cmd(priv, &cmd);
1956}
c496294e 1957EXPORT_SYMBOL(iwl_send_card_state);
14a08a7f
EG		 1958
1959void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1960{
1961 unsigned long flags;
1962
1963 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1964 return;
1965
e1623446 1966 IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO OFF\n");
14a08a7f
EG		 1967
1968 iwl_scan_cancel(priv);
1969 /* FIXME: This is a workaround for AP */
05c914fe 1970 if (priv->iw_mode != NL80211_IFTYPE_AP) {
14a08a7f
EG		 1971 spin_lock_irqsave(&priv->lock, flags);
1972 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1973 CSR_UCODE_SW_BIT_RFKILL);
1974 spin_unlock_irqrestore(&priv->lock, flags);
1975 /* call the host command only if no hw rf-kill set */
1976 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1977 iwl_is_ready(priv))
1978 iwl_send_card_state(priv,
1979 CARD_STATE_CMD_DISABLE, 0);
1980 set_bit(STATUS_RF_KILL_SW, &priv->status);
1981 /* make sure mac80211 stop sending Tx frame */
1982 if (priv->mac80211_registered)
1983 ieee80211_stop_queues(priv->hw);
1984 }
1985}
1986EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1987
1988int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1989{
1990 unsigned long flags;
1991
1992 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1993 return 0;
1994
e1623446 1995 IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO ON\n");
14a08a7f
EG		 1996
1997 spin_lock_irqsave(&priv->lock, flags);
1998 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1999
a9efa652
EG		 2000 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
2001 * notification where it will clear SW rfkill status.
2002 * Setting it here would break the handler. Only if the
2003 * interface is down we can set here since we don't
2004 * receive any further notification.
2005 */
2006 if (!priv->is_open)
2007 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 2008 spin_unlock_irqrestore(&priv->lock, flags);
2009
2010 /* wake up ucode */
2011 msleep(10);
2012
2013 spin_lock_irqsave(&priv->lock, flags);
2014 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2015 if (!iwl_grab_nic_access(priv))
2016 iwl_release_nic_access(priv);
2017 spin_unlock_irqrestore(&priv->lock, flags);
2018
2019 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
e1623446 2020 IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - "
14a08a7f
EG		 2021 "disabled by HW switch\n");
2022 return 0;
2023 }
2024
edb34228
MA		 2025 /* when driver is up while rfkill is on, it wont receive
2026 * any CARD_STATE_NOTIFICATION notifications so we have to
2027 * restart it in here
2028 */
2029 if (priv->is_open && !test_bit(STATUS_ALIVE, &priv->status)) {
2030 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2031 if (!iwl_is_rfkill(priv))
2032 queue_work(priv->workqueue, &priv->up);
2033 }
2034
a9efa652
EG		 2035 /* If the driver is already loaded, it will receive
2036 * CARD_STATE_NOTIFICATION notifications and the handler will
2037 * call restart to reload the driver.
2038 */
14a08a7f
EG		 2039 return 1;
2040}
2041EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
c0af96a6
SO		 2042
2043void iwl_bg_rf_kill(struct work_struct *work)
2044{
2045 struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
2046
2047 wake_up_interruptible(&priv->wait_command_queue);
2048
2049 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2050 return;
2051
2052 mutex_lock(&priv->mutex);
2053
2054 if (!iwl_is_rfkill(priv)) {
e1623446 2055 IWL_DEBUG_RF_KILL(priv,
c0af96a6
SO		 2056 "HW and/or SW RF Kill no longer active, restarting "
2057 "device\n");
2058 if (!test_bit(STATUS_EXIT_PENDING, &priv->status) &&
55a3757a 2059 priv->is_open)
c0af96a6
SO		 2060 queue_work(priv->workqueue, &priv->restart);
2061 } else {
2062 /* make sure mac80211 stop sending Tx frame */
2063 if (priv->mac80211_registered)
2064 ieee80211_stop_queues(priv->hw);
2065
2066 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
e1623446 2067 IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - "
c0af96a6
SO		 2068 "disabled by SW switch\n");
2069 else
2070 IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
2071 "Kill switch must be turned off for "
2072 "wireless networking to work.\n");
2073 }
2074 mutex_unlock(&priv->mutex);
2075 iwl_rfkill_set_hw_state(priv);
2076}
2077EXPORT_SYMBOL(iwl_bg_rf_kill);
030f05ed
AK		 2078
2079void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2080 struct iwl_rx_mem_buffer *rxb)
2081{
2082#ifdef CONFIG_IWLWIFI_DEBUG
2083 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2084 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2085 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2086 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2087#endif
2088}
2089EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2090
2091void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2092 struct iwl_rx_mem_buffer *rxb)
2093{
2094 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2095 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
2096 "notification for %s:\n",
2097 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
2098 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
2099}
2100EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2101
2102void iwl_rx_reply_error(struct iwl_priv *priv,
2103 struct iwl_rx_mem_buffer *rxb)
2104{
2105 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2106
2107 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2108 "seq 0x%04X ser 0x%08X\n",
2109 le32_to_cpu(pkt->u.err_resp.error_type),
2110 get_cmd_string(pkt->u.err_resp.cmd_id),
2111 pkt->u.err_resp.cmd_id,
2112 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2113 le32_to_cpu(pkt->u.err_resp.error_info));
2114}
2115EXPORT_SYMBOL(iwl_rx_reply_error);
2116
488829f1
AK		 2117int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2118 const struct ieee80211_tx_queue_params *params)
2119{
2120 struct iwl_priv *priv = hw->priv;
2121 unsigned long flags;
2122 int q;
2123
2124 IWL_DEBUG_MAC80211(priv, "enter\n");
2125
2126 if (!iwl_is_ready_rf(priv)) {
2127 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2128 return -EIO;
2129 }
2130
2131 if (queue >= AC_NUM) {
2132 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2133 return 0;
2134 }
2135
2136 q = AC_NUM - 1 - queue;
2137
2138 spin_lock_irqsave(&priv->lock, flags);
2139
2140 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2141 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2142 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2143 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2144 cpu_to_le16((params->txop * 32));
2145
2146 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2147 priv->qos_data.qos_active = 1;
2148
2149 if (priv->iw_mode == NL80211_IFTYPE_AP)
2150 iwl_activate_qos(priv, 1);
2151 else if (priv->assoc_id && iwl_is_associated(priv))
2152 iwl_activate_qos(priv, 0);
2153
2154 spin_unlock_irqrestore(&priv->lock, flags);
2155
2156 IWL_DEBUG_MAC80211(priv, "leave\n");
2157 return 0;
2158}
2159EXPORT_SYMBOL(iwl_mac_conf_tx);
6da3a13e
WYG		 2160#ifdef CONFIG_PM
2161
2162int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2163{
2164 struct iwl_priv *priv = pci_get_drvdata(pdev);
2165
2166 /*
2167 * This function is called when system goes into suspend state
2168 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
2169 * first but since iwl_mac_stop() has no knowledge of who the caller is,
2170 * it will not call apm_ops.stop() to stop the DMA operation.
2171 * Calling apm_ops.stop here to make sure we stop the DMA.
2172 */
2173 priv->cfg->ops->lib->apm_ops.stop(priv);
2174
2175 pci_save_state(pdev);
2176 pci_disable_device(pdev);
2177 pci_set_power_state(pdev, PCI_D3hot);
2178
2179 return 0;
2180}
2181EXPORT_SYMBOL(iwl_pci_suspend);
2182
2183int iwl_pci_resume(struct pci_dev *pdev)
2184{
2185 struct iwl_priv *priv = pci_get_drvdata(pdev);
2186 int ret;
2187
2188 pci_set_power_state(pdev, PCI_D0);
2189 ret = pci_enable_device(pdev);
2190 if (ret)
2191 return ret;
2192 pci_restore_state(pdev);
2193 iwl_enable_interrupts(priv);
2194
2195 return 0;
2196}
2197EXPORT_SYMBOL(iwl_pci_resume);
2198
2199#endif /* CONFIG_PM */
Linux kernel - Deliverables
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