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6f83eaa1 TW |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
6f83eaa1 TW |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
6f83eaa1 TW |
27 | * |
28 | * Contact Information: | |
759ef89f | 29 | * Intel Linux Wireless <ilw@linux.intel.com> |
6f83eaa1 TW |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
6f83eaa1 TW |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
65a0667b TW |
65 | #ifndef __iwl_csr_h__ |
66 | #define __iwl_csr_h__ | |
9e595d24 BC |
67 | /* |
68 | * CSR (control and status registers) | |
69 | * | |
70 | * CSR registers are mapped directly into PCI bus space, and are accessible | |
71 | * whenever platform supplies power to device, even when device is in | |
72 | * low power states due to driver-invoked device resets | |
73 | * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. | |
74 | * | |
75 | * Use iwl_write32() and iwl_read32() family to access these registers; | |
76 | * these provide simple PCI bus access, without waking up the MAC. | |
77 | * Do not use iwl_write_direct32() family for these registers; | |
78 | * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. | |
79 | * The MAC (uCode processor, etc.) does not need to be powered up for accessing | |
80 | * the CSR registers. | |
81 | * | |
f8701fe3 | 82 | * NOTE: Device does need to be awake in order to read this memory |
9e595d24 BC |
83 | * via CSR_EEPROM and CSR_OTP registers |
84 | */ | |
6f83eaa1 TW |
85 | #define CSR_BASE (0x000) |
86 | ||
87 | #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ | |
9e595d24 | 88 | #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ |
6f83eaa1 TW |
89 | #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ |
90 | #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ | |
91 | #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ | |
92 | #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ | |
93 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ | |
94 | #define CSR_GP_CNTRL (CSR_BASE+0x024) | |
95 | ||
9e595d24 BC |
96 | /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ |
97 | #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) | |
98 | ||
6f83eaa1 TW |
99 | /* |
100 | * Hardware revision info | |
101 | * Bit fields: | |
08838cde EG |
102 | * 31-16: Reserved |
103 | * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions | |
6f83eaa1 | 104 | * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D |
9e595d24 | 105 | * 1-0: "Dash" (-) value, as in A-1, etc. |
6f83eaa1 TW |
106 | */ |
107 | #define CSR_HW_REV (CSR_BASE+0x028) | |
108 | ||
9e595d24 BC |
109 | /* |
110 | * EEPROM and OTP (one-time-programmable) memory reads | |
111 | * | |
f8701fe3 RC |
112 | * NOTE: Device must be awake, initialized via apm_ops.init(), |
113 | * in order to read. | |
9e595d24 | 114 | */ |
6f83eaa1 TW |
115 | #define CSR_EEPROM_REG (CSR_BASE+0x02c) |
116 | #define CSR_EEPROM_GP (CSR_BASE+0x030) | |
0848e297 | 117 | #define CSR_OTP_GP_REG (CSR_BASE+0x034) |
9e595d24 | 118 | |
8f061891 | 119 | #define CSR_GIO_REG (CSR_BASE+0x03C) |
65b7998a WYG |
120 | #define CSR_GP_UCODE_REG (CSR_BASE+0x048) |
121 | #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) | |
9e595d24 BC |
122 | |
123 | /* | |
124 | * UCODE-DRIVER GP (general purpose) mailbox registers. | |
125 | * SET/CLR registers set/clear bit(s) if "1" is written. | |
126 | */ | |
6f83eaa1 TW |
127 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) |
128 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) | |
129 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) | |
130 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) | |
9e595d24 | 131 | |
ab53d8af | 132 | #define CSR_LED_REG (CSR_BASE+0x094) |
ef850d7c | 133 | #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) |
f81c1f48 WYG |
134 | #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */ |
135 | ||
9e595d24 BC |
136 | |
137 | /* GIO Chicken Bits (PCI Express bus link power management) */ | |
8f061891 | 138 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
6f83eaa1 | 139 | |
a693f187 | 140 | /* Analog phase-lock-loop configuration */ |
6f83eaa1 | 141 | #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) |
9e595d24 | 142 | |
a812cba9 AB |
143 | /* |
144 | * CSR HW resources monitor registers | |
145 | */ | |
146 | #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) | |
147 | #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) | |
148 | #define CSR_MONITOR_XTAL_RESOURCES (0x00000010) | |
149 | ||
6f83eaa1 | 150 | /* |
9e595d24 BC |
151 | * CSR Hardware Revision Workaround Register. Indicates hardware rev; |
152 | * "step" determines CCK backoff for txpower calculation. Used for 4965 only. | |
153 | * See also CSR_HW_REV register. | |
6f83eaa1 TW |
154 | * Bit fields: |
155 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step | |
9e595d24 | 156 | * 1-0: "Dash" (-) value, as in C-1, etc. |
6f83eaa1 | 157 | */ |
32004ee4 | 158 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
9e595d24 | 159 | |
32004ee4 WYG |
160 | #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) |
161 | #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) | |
6f83eaa1 TW |
162 | |
163 | /* Bits for CSR_HW_IF_CONFIG_REG */ | |
7b6a2be9 EG |
164 | #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) |
165 | #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) | |
166 | #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) | |
167 | #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) | |
a395b920 | 168 | #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
7b6a2be9 EG |
169 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) |
170 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) | |
171 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) | |
172 | ||
173 | #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) | |
174 | #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) | |
175 | #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) | |
176 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) | |
177 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) | |
178 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) | |
6f83eaa1 | 179 | |
9e595d24 BC |
180 | #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
181 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | |
182 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ | |
183 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ | |
184 | #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ | |
a812cba9 | 185 | #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ |
4c43e0d0 | 186 | |
74ba67ed BC |
187 | #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ |
188 | #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ | |
6f83eaa1 TW |
189 | |
190 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | |
191 | * acknowledged (reset) by host writing "1" to flagged bits. */ | |
192 | #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ | |
193 | #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ | |
40cefda9 | 194 | #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ |
6f83eaa1 TW |
195 | #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ |
196 | #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ | |
197 | #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ | |
198 | #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ | |
199 | #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ | |
f7d046f9 | 200 | #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ |
6f83eaa1 TW |
201 | #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
202 | #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ | |
203 | ||
204 | #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ | |
205 | CSR_INT_BIT_HW_ERR | \ | |
206 | CSR_INT_BIT_FH_TX | \ | |
207 | CSR_INT_BIT_SW_ERR | \ | |
208 | CSR_INT_BIT_RF_KILL | \ | |
209 | CSR_INT_BIT_SW_RX | \ | |
210 | CSR_INT_BIT_WAKEUP | \ | |
eef31718 EG |
211 | CSR_INT_BIT_ALIVE | \ |
212 | CSR_INT_BIT_RX_PERIODIC) | |
6f83eaa1 TW |
213 | |
214 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | |
215 | #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ | |
216 | #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ | |
6f83eaa1 TW |
217 | #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ |
218 | #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ | |
6f83eaa1 TW |
219 | #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ |
220 | #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ | |
221 | ||
f7d046f9 WYG |
222 | #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ |
223 | CSR_FH_INT_BIT_RX_CHNL1 | \ | |
224 | CSR_FH_INT_BIT_RX_CHNL0) | |
6f83eaa1 | 225 | |
f7d046f9 WYG |
226 | #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ |
227 | CSR_FH_INT_BIT_TX_CHNL0) | |
6f83eaa1 | 228 | |
6f4083aa TW |
229 | /* GPIO */ |
230 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) | |
231 | #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) | |
232 | #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) | |
6f83eaa1 TW |
233 | |
234 | /* RESET */ | |
235 | #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) | |
236 | #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) | |
237 | #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) | |
238 | #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) | |
239 | #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) | |
32004ee4 | 240 | #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) |
6f83eaa1 | 241 | |
9e595d24 BC |
242 | /* |
243 | * GP (general purpose) CONTROL REGISTER | |
244 | * Bit fields: | |
245 | * 27: HW_RF_KILL_SW | |
246 | * Indicates state of (platform's) hardware RF-Kill switch | |
247 | * 26-24: POWER_SAVE_TYPE | |
248 | * Indicates current power-saving mode: | |
249 | * 000 -- No power saving | |
250 | * 001 -- MAC power-down | |
251 | * 010 -- PHY (radio) power-down | |
252 | * 011 -- Error | |
a812cba9 | 253 | * 10: XTAL ON request |
9e595d24 BC |
254 | * 9-6: SYS_CONFIG |
255 | * Indicates current system configuration, reflecting pins on chip | |
256 | * as forced high/low by device circuit board. | |
257 | * 4: GOING_TO_SLEEP | |
258 | * Indicates MAC is entering a power-saving sleep power-down. | |
259 | * Not a good time to access device-internal resources. | |
260 | * 3: MAC_ACCESS_REQ | |
261 | * Host sets this to request and maintain MAC wakeup, to allow host | |
262 | * access to device-internal resources. Host must wait for | |
263 | * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR | |
264 | * device registers. | |
265 | * 2: INIT_DONE | |
266 | * Host sets this to put device into fully operational D0 power mode. | |
267 | * Host resets this after SW_RESET to put device into low power mode. | |
268 | * 0: MAC_CLOCK_READY | |
269 | * Indicates MAC (ucode processor, etc.) is powered up and can run. | |
270 | * Internal resources are accessible. | |
271 | * NOTE: This does not indicate that the processor is actually running. | |
f7d046f9 | 272 | * NOTE: This does not indicate that device has completed |
9e595d24 BC |
273 | * init or post-power-down restore of internal SRAM memory. |
274 | * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that | |
275 | * SRAM is restored and uCode is in normal operation mode. | |
276 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and | |
277 | * do not need to save/restore it. | |
278 | * NOTE: After device reset, this bit remains "0" until host sets | |
279 | * INIT_DONE | |
280 | */ | |
6f83eaa1 TW |
281 | #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) |
282 | #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) | |
283 | #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) | |
284 | #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) | |
a812cba9 | 285 | #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) |
6f83eaa1 TW |
286 | |
287 | #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) | |
288 | ||
289 | #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) | |
290 | #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) | |
291 | #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) | |
292 | ||
293 | ||
b661c819 | 294 | /* HW REV */ |
08838cde EG |
295 | #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) |
296 | #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) | |
297 | ||
298 | #define CSR_HW_REV_TYPE_MSK (0x000FFF0) | |
fcf623df TW |
299 | #define CSR_HW_REV_TYPE_5300 (0x0000020) |
300 | #define CSR_HW_REV_TYPE_5350 (0x0000030) | |
301 | #define CSR_HW_REV_TYPE_5100 (0x0000050) | |
302 | #define CSR_HW_REV_TYPE_5150 (0x0000040) | |
77dcb6a9 | 303 | #define CSR_HW_REV_TYPE_1000 (0x0000060) |
2264596d JS |
304 | #define CSR_HW_REV_TYPE_6x00 (0x0000070) |
305 | #define CSR_HW_REV_TYPE_6x50 (0x0000080) | |
14a75766 WYG |
306 | #define CSR_HW_REV_TYPE_6150 (0x0000084) |
307 | #define CSR_HW_REV_TYPE_6x05 (0x00000B0) | |
308 | #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 | |
fcdf1f73 WYG |
309 | #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 |
310 | #define CSR_HW_REV_TYPE_2x30 (0x00000C0) | |
311 | #define CSR_HW_REV_TYPE_2x00 (0x0000100) | |
8c3d1161 WYG |
312 | #define CSR_HW_REV_TYPE_105 (0x0000110) |
313 | #define CSR_HW_REV_TYPE_135 (0x0000120) | |
fcdf1f73 | 314 | #define CSR_HW_REV_TYPE_NONE (0x00001F0) |
b661c819 | 315 | |
6f83eaa1 TW |
316 | /* EEPROM REG */ |
317 | #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) | |
318 | #define CSR_EEPROM_REG_BIT_CMD (0x00000002) | |
3d5717ad ZY |
319 | #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) |
320 | #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) | |
6f83eaa1 TW |
321 | |
322 | /* EEPROM GP */ | |
9e595d24 | 323 | #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ |
6f83eaa1 | 324 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
9e595d24 BC |
325 | #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) |
326 | #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) | |
327 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) | |
328 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) | |
329 | ||
330 | /* One-time-programmable memory general purpose reg */ | |
0848e297 WYG |
331 | #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ |
332 | #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ | |
333 | #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ | |
334 | #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ | |
9e595d24 BC |
335 | |
336 | /* GP REG */ | |
c09430ab WYG |
337 | #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ |
338 | #define CSR_GP_REG_NO_POWER_SAVE (0x00000000) | |
339 | #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) | |
340 | #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) | |
341 | #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) | |
6f83eaa1 | 342 | |
f41bb897 | 343 | |
8f061891 TW |
344 | /* CSR GIO */ |
345 | #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) | |
346 | ||
9e595d24 BC |
347 | /* |
348 | * UCODE-DRIVER GP (general purpose) mailbox register 1 | |
349 | * Host driver and uCode write and/or read this register to communicate with | |
350 | * each other. | |
351 | * Bit fields: | |
352 | * 4: UCODE_DISABLE | |
353 | * Host sets this to request permanent halt of uCode, same as | |
354 | * sending CARD_STATE command with "halt" bit set. | |
355 | * 3: CT_KILL_EXIT | |
356 | * Host sets this to request exit from CT_KILL state, i.e. host thinks | |
357 | * device temperature is low enough to continue normal operation. | |
358 | * 2: CMD_BLOCKED | |
359 | * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) | |
360 | * to release uCode to clear all Tx and command queues, enter | |
361 | * unassociated mode, and power down. | |
362 | * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. | |
363 | * 1: SW_BIT_RFKILL | |
364 | * Host sets this when issuing CARD_STATE command to request | |
365 | * device sleep. | |
366 | * 0: MAC_SLEEP | |
367 | * uCode sets this when preparing a power-saving power-down. | |
368 | * uCode resets this when power-up is complete and SRAM is sane. | |
f7d046f9 | 369 | * NOTE: device saves internal SRAM data to host when powering down, |
9e595d24 BC |
370 | * and must restore this data after powering back up. |
371 | * MAC_SLEEP is the best indication that restore is complete. | |
372 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and | |
373 | * do not need to save/restore it. | |
374 | */ | |
6f83eaa1 TW |
375 | #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) |
376 | #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) | |
377 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) | |
378 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) | |
c8ac61cf | 379 | #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) |
6f83eaa1 | 380 | |
65b7998a WYG |
381 | /* GP Driver */ |
382 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) | |
383 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) | |
384 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) | |
385 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) | |
02796d77 SZ |
386 | #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) |
387 | #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) | |
65b7998a | 388 | |
52e6b85f WYG |
389 | #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) |
390 | ||
9e595d24 | 391 | /* GIO Chicken Bits (PCI Express bus link power management) */ |
6f83eaa1 TW |
392 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
393 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) | |
394 | ||
ab53d8af MA |
395 | /* LED */ |
396 | #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) | |
c8f9b0fe EL |
397 | #define CSR_LED_REG_TURN_ON (0x60) |
398 | #define CSR_LED_REG_TURN_OFF (0x20) | |
ab53d8af | 399 | |
a693f187 | 400 | /* ANA_PLL */ |
a693f187 TW |
401 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) |
402 | ||
4c43e0d0 TW |
403 | /* HPET MEM debug */ |
404 | #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) | |
ef850d7c MA |
405 | |
406 | /* DRAM INT TABLE */ | |
407 | #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) | |
408 | #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) | |
409 | ||
a812cba9 AB |
410 | /* |
411 | * SHR target access (Shared block memory space) | |
412 | * | |
413 | * Shared internal registers can be accessed directly from PCI bus through SHR | |
414 | * arbiter without need for the MAC HW to be powered up. This is possible due to | |
415 | * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and | |
416 | * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. | |
417 | * | |
418 | * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW | |
419 | * need not be powered up so no "grab inc access" is required. | |
420 | */ | |
421 | ||
422 | /* | |
423 | * Registers for accessing shared registers (e.g. SHR_APMG_GP1, | |
424 | * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), | |
425 | * first, write to the control register: | |
426 | * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) | |
427 | * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) | |
428 | * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. | |
429 | * | |
430 | * To write the register, first, write to the data register | |
431 | * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: | |
432 | * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) | |
433 | * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) | |
434 | */ | |
435 | #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) | |
436 | #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) | |
437 | ||
9e595d24 BC |
438 | /* |
439 | * HBUS (Host-side Bus) | |
440 | * | |
441 | * HBUS registers are mapped directly into PCI bus space, but are used | |
442 | * to indirectly access device's internal memory or registers that | |
443 | * may be powered-down. | |
444 | * | |
445 | * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; | |
446 | * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ | |
447 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing | |
448 | * internal resources. | |
449 | * | |
450 | * Do not use iwl_write32()/iwl_read32() family to access these registers; | |
451 | * these provide only simple PCI bus access, without waking up the MAC. | |
452 | */ | |
750fe639 | 453 | #define HBUS_BASE (0x400) |
9e595d24 | 454 | |
750fe639 TW |
455 | /* |
456 | * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM | |
457 | * structures, error log, event log, verifying uCode load). | |
458 | * First write to address register, then read from or write to data register | |
459 | * to complete the job. Once the address register is set up, accesses to | |
460 | * data registers auto-increment the address by one dword. | |
461 | * Bit usage for address registers (read or write): | |
462 | * 0-31: memory address within device | |
463 | */ | |
464 | #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) | |
465 | #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) | |
466 | #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) | |
467 | #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) | |
468 | ||
9e595d24 BC |
469 | /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ |
470 | #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) | |
471 | #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) | |
472 | ||
750fe639 TW |
473 | /* |
474 | * Registers for accessing device's internal peripheral registers | |
475 | * (e.g. SCD, BSM, etc.). First write to address register, | |
476 | * then read from or write to data register to complete the job. | |
477 | * Bit usage for address registers (read or write): | |
478 | * 0-15: register address (offset) within device | |
479 | * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) | |
480 | */ | |
481 | #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) | |
482 | #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) | |
483 | #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) | |
484 | #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) | |
485 | ||
f8c6c6b5 AB |
486 | /* Used to enable DBGM */ |
487 | #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) | |
488 | ||
750fe639 | 489 | /* |
9e595d24 | 490 | * Per-Tx-queue write pointer (index, really!) |
750fe639 TW |
491 | * Indicates index to next TFD that driver will fill (1 past latest filled). |
492 | * Bit usage: | |
493 | * 0-7: queue write index | |
494 | * 11-8: queue selector | |
495 | */ | |
496 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) | |
750fe639 | 497 | |
7a10e3e4 EG |
498 | /********************************************************** |
499 | * CSR values | |
500 | **********************************************************/ | |
501 | /* | |
502 | * host interrupt timeout value | |
503 | * used with setting interrupt coalescing timer | |
504 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
505 | * | |
506 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
7a10e3e4 EG |
507 | */ |
508 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | |
509 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | |
510 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | |
6960a059 | 511 | #define IWL_HOST_INT_OPER_MODE BIT(31) |
7a10e3e4 | 512 | |
9ee718aa EL |
513 | /***************************************************************************** |
514 | * 7000/3000 series SHR DTS addresses * | |
515 | *****************************************************************************/ | |
516 | ||
517 | /* Diode Results Register Structure: */ | |
518 | enum dtd_diode_reg { | |
519 | DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ | |
520 | DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ | |
521 | DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ | |
522 | DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ | |
523 | DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ | |
524 | DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ | |
525 | /* Those are the masks INSIDE the flags bit-field: */ | |
526 | DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, | |
527 | DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ | |
528 | DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, | |
529 | DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ | |
530 | }; | |
531 | ||
65a0667b | 532 | #endif /* !__iwl_csr_h__ */ |