[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-csr.h

/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
#ifndef __iwl_csr_h__
#define __iwl_csr_h__
/*
 * CSR (control and status registers)
 *
 * CSR registers are mapped directly into PCI bus space, and are accessible
 * whenever platform supplies power to device, even when device is in
 * low power states due to driver-invoked device resets
 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
 *
 * Use iwl_write32() and iwl_read32() family to access these registers;
 * these provide simple PCI bus access, without waking up the MAC.
 * Do not use iwl_write_direct32() family for these registers;
 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
 * the CSR registers.
 *
 * NOTE:  Device does need to be awake in order to read this memory
 *        via CSR_EEPROM and CSR_OTP registers
 */
#define CSR_BASE    (0x000)

#define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
#define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
#define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
#define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
#define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
#define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
#define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
#define CSR_GP_CNTRL            (CSR_BASE+0x024)

/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
#define CSR_INT_PERIODIC_REG	(CSR_BASE+0x005)

/*
 * Hardware revision info
 * Bit fields:
 * 31-8:  Reserved
 *  7-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
 *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 *  1-0:  "Dash" (-) value, as in A-1, etc.
 *
 * NOTE:  Revision step affects calculation of CCK txpower for 4965.
 * NOTE:  See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
 */
#define CSR_HW_REV              (CSR_BASE+0x028)

/*
 * EEPROM and OTP (one-time-programmable) memory reads
 *
 * NOTE:  Device must be awake, initialized via apm_ops.init(),
 *        in order to read.
 */
#define CSR_EEPROM_REG          (CSR_BASE+0x02c)
#define CSR_EEPROM_GP           (CSR_BASE+0x030)
#define CSR_OTP_GP_REG   	(CSR_BASE+0x034)

#define CSR_GIO_REG		(CSR_BASE+0x03C)
#define CSR_GP_UCODE_REG	(CSR_BASE+0x048)
#define CSR_GP_DRIVER_REG	(CSR_BASE+0x050)

/*
 * UCODE-DRIVER GP (general purpose) mailbox registers.
 * SET/CLR registers set/clear bit(s) if "1" is written.
 */
#define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
#define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
#define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
#define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)

#define CSR_LED_REG             (CSR_BASE+0x094)
#define CSR_DRAM_INT_TBL_REG	(CSR_BASE+0x0A0)
#define CSR_MAC_SHADOW_REG_CTRL	(CSR_BASE+0x0A8) /* 6000 and up */


/* GIO Chicken Bits (PCI Express bus link power management) */
#define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)

/* Analog phase-lock-loop configuration  */
#define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)

/*
 * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
 * "step" determines CCK backoff for txpower calculation.  Used for 4965 only.
 * See also CSR_HW_REV register.
 * Bit fields:
 *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 *  1-0:  "Dash" (-) value, as in C-1, etc.
 */
#define CSR_HW_REV_WA_REG		(CSR_BASE+0x22C)

#define CSR_DBG_HPET_MEM_REG		(CSR_BASE+0x240)
#define CSR_DBG_LINK_PWR_MGMT_REG	(CSR_BASE+0x250)

/* Bits for CSR_HW_IF_CONFIG_REG */
#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER	(0x00000C00)
#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI 	(0x00000100)
#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI	(0x00000200)

#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A	(0x00080000)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM	(0x00200000)
#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY	(0x00400000) /* PCI_OWN_SEM */
#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
#define CSR_HW_IF_CONFIG_REG_PREPARE		  (0x08000000) /* WAKE_ME */

#define CSR_INT_PERIODIC_DIS			(0x00) /* disable periodic int*/
#define CSR_INT_PERIODIC_ENA			(0xFF) /* 255*32 usec ~ 8 msec*/

/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 * acknowledged (reset) by host writing "1" to flagged bits. */
#define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
#define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
#define CSR_INT_BIT_RX_PERIODIC	 (1 << 28) /* Rx periodic */
#define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
#define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
#define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
#define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
#define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
#define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses */
#define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
#define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */

#define CSR_INI_SET_MASK	(CSR_INT_BIT_FH_RX   | \
				 CSR_INT_BIT_HW_ERR  | \
				 CSR_INT_BIT_FH_TX   | \
				 CSR_INT_BIT_SW_ERR  | \
				 CSR_INT_BIT_RF_KILL | \
				 CSR_INT_BIT_SW_RX   | \
				 CSR_INT_BIT_WAKEUP  | \
				 CSR_INT_BIT_ALIVE)

/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
#define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
#define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
#define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
#define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
#define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
#define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */

#define CSR_FH_INT_RX_MASK	(CSR_FH_INT_BIT_HI_PRIOR | \
				CSR_FH_INT_BIT_RX_CHNL1 | \
				CSR_FH_INT_BIT_RX_CHNL0)

#define CSR_FH_INT_TX_MASK	(CSR_FH_INT_BIT_TX_CHNL1 | \
				CSR_FH_INT_BIT_TX_CHNL0)

/* GPIO */
#define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)

/* RESET */
#define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
#define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
#define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
#define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
#define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
#define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)

/*
 * GP (general purpose) CONTROL REGISTER
 * Bit fields:
 *    27:  HW_RF_KILL_SW
 *         Indicates state of (platform's) hardware RF-Kill switch
 * 26-24:  POWER_SAVE_TYPE
 *         Indicates current power-saving mode:
 *         000 -- No power saving
 *         001 -- MAC power-down
 *         010 -- PHY (radio) power-down
 *         011 -- Error
 *   9-6:  SYS_CONFIG
 *         Indicates current system configuration, reflecting pins on chip
 *         as forced high/low by device circuit board.
 *     4:  GOING_TO_SLEEP
 *         Indicates MAC is entering a power-saving sleep power-down.
 *         Not a good time to access device-internal resources.
 *     3:  MAC_ACCESS_REQ
 *         Host sets this to request and maintain MAC wakeup, to allow host
 *         access to device-internal resources.  Host must wait for
 *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
 *         device registers.
 *     2:  INIT_DONE
 *         Host sets this to put device into fully operational D0 power mode.
 *         Host resets this after SW_RESET to put device into low power mode.
 *     0:  MAC_CLOCK_READY
 *         Indicates MAC (ucode processor, etc.) is powered up and can run.
 *         Internal resources are accessible.
 *         NOTE:  This does not indicate that the processor is actually running.
 *         NOTE:  This does not indicate that device has completed
 *                init or post-power-down restore of internal SRAM memory.
 *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
 *                SRAM is restored and uCode is in normal operation mode.
 *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 *                do not need to save/restore it.
 *         NOTE:  After device reset, this bit remains "0" until host sets
 *                INIT_DONE
 */
#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)

#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)

#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)


/* HW REV */
#define CSR_HW_REV_TYPE_MSK            (0x00001F0)
#define CSR_HW_REV_TYPE_5300           (0x0000020)
#define CSR_HW_REV_TYPE_5350           (0x0000030)
#define CSR_HW_REV_TYPE_5100           (0x0000050)
#define CSR_HW_REV_TYPE_5150           (0x0000040)
#define CSR_HW_REV_TYPE_1000           (0x0000060)
#define CSR_HW_REV_TYPE_6x00           (0x0000070)
#define CSR_HW_REV_TYPE_6x50           (0x0000080)
#define CSR_HW_REV_TYPE_6150           (0x0000084)
#define CSR_HW_REV_TYPE_6x05	       (0x00000B0)
#define CSR_HW_REV_TYPE_6x30	       CSR_HW_REV_TYPE_6x05
#define CSR_HW_REV_TYPE_6x35	       CSR_HW_REV_TYPE_6x05
#define CSR_HW_REV_TYPE_2x30	       (0x00000C0)
#define CSR_HW_REV_TYPE_2x00	       (0x0000100)
#define CSR_HW_REV_TYPE_200	       (0x0000110)
#define CSR_HW_REV_TYPE_230	       (0x0000120)
#define CSR_HW_REV_TYPE_NONE           (0x00001F0)

/* EEPROM REG */
#define CSR_EEPROM_REG_READ_VALID_MSK	(0x00000001)
#define CSR_EEPROM_REG_BIT_CMD		(0x00000002)
#define CSR_EEPROM_REG_MSK_ADDR		(0x0000FFFC)
#define CSR_EEPROM_REG_MSK_DATA		(0xFFFF0000)

/* EEPROM GP */
#define CSR_EEPROM_GP_VALID_MSK		(0x00000007) /* signature */
#define CSR_EEPROM_GP_IF_OWNER_MSK	(0x00000180)
#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP	(0x00000000)
#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP		(0x00000001)
#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K		(0x00000002)
#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K		(0x00000004)

/* One-time-programmable memory general purpose reg */
#define CSR_OTP_GP_REG_DEVICE_SELECT	(0x00010000) /* 0 - EEPROM, 1 - OTP */
#define CSR_OTP_GP_REG_OTP_ACCESS_MODE	(0x00020000) /* 0 - absolute, 1 - relative */
#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */

/* GP REG */
#define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
#define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
#define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
#define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
#define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)


/* CSR GIO */
#define CSR_GIO_REG_VAL_L0S_ENABLED	(0x00000002)

/*
 * UCODE-DRIVER GP (general purpose) mailbox register 1
 * Host driver and uCode write and/or read this register to communicate with
 * each other.
 * Bit fields:
 *     4:  UCODE_DISABLE
 *         Host sets this to request permanent halt of uCode, same as
 *         sending CARD_STATE command with "halt" bit set.
 *     3:  CT_KILL_EXIT
 *         Host sets this to request exit from CT_KILL state, i.e. host thinks
 *         device temperature is low enough to continue normal operation.
 *     2:  CMD_BLOCKED
 *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
 *         to release uCode to clear all Tx and command queues, enter
 *         unassociated mode, and power down.
 *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
 *     1:  SW_BIT_RFKILL
 *         Host sets this when issuing CARD_STATE command to request
 *         device sleep.
 *     0:  MAC_SLEEP
 *         uCode sets this when preparing a power-saving power-down.
 *         uCode resets this when power-up is complete and SRAM is sane.
 *         NOTE:  device saves internal SRAM data to host when powering down,
 *                and must restore this data after powering back up.
 *                MAC_SLEEP is the best indication that restore is complete.
 *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 *                do not need to save/restore it.
 */
#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
#define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)

/* GP Driver */
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK	    (0x00000003)
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB	    (0x00000000)
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB	    (0x00000001)
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA	    (0x00000002)
#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6	    (0x00000004)
#define CSR_GP_DRIVER_REG_BIT_6050_1x2		    (0x00000008)

#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER	    (0x00000080)

/* GIO Chicken Bits (PCI Express bus link power management) */
#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)

/* LED */
#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
#define CSR_LED_REG_TRUN_ON (0x78)
#define CSR_LED_REG_TRUN_OFF (0x38)

/* ANA_PLL */
#define CSR50_ANA_PLL_CFG_VAL        (0x00880300)

/* HPET MEM debug */
#define CSR_DBG_HPET_MEM_REG_VAL	(0xFFFF0000)

/* DRAM INT TABLE */
#define CSR_DRAM_INT_TBL_ENABLE		(1 << 31)
#define CSR_DRAM_INIT_TBL_WRAP_CHECK	(1 << 27)

/*
 * HBUS (Host-side Bus)
 *
 * HBUS registers are mapped directly into PCI bus space, but are used
 * to indirectly access device's internal memory or registers that
 * may be powered-down.
 *
 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
 * internal resources.
 *
 * Do not use iwl_write32()/iwl_read32() family to access these registers;
 * these provide only simple PCI bus access, without waking up the MAC.
 */
#define HBUS_BASE	(0x400)

/*
 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 * structures, error log, event log, verifying uCode load).
 * First write to address register, then read from or write to data register
 * to complete the job.  Once the address register is set up, accesses to
 * data registers auto-increment the address by one dword.
 * Bit usage for address registers (read or write):
 *  0-31:  memory address within device
 */
#define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
#define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
#define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
#define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)

/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
#define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)

/*
 * Registers for accessing device's internal peripheral registers
 * (e.g. SCD, BSM, etc.).  First write to address register,
 * then read from or write to data register to complete the job.
 * Bit usage for address registers (read or write):
 *  0-15:  register address (offset) within device
 * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 */
#define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
#define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
#define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
#define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)

/*
 * Per-Tx-queue write pointer (index, really!)
 * Indicates index to next TFD that driver will fill (1 past latest filled).
 * Bit usage:
 *  0-7:  queue write index
 * 11-8:  queue selector
 */
#define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)

#endif /* !__iwl_csr_h__ */
Commit	Line	Data
6f83eaa1 TW	1	/******************************************************************************
	2	*
	3	* This file is provided under a dual BSD/GPLv2 license. When using or
	4	* redistributing this file, you may do so under either license.
	5	*
	6	* GPL LICENSE SUMMARY
	7	*
901069c7	8	* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
6f83eaa1 TW	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of version 2 of the GNU General Public License as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	22	* USA
	23	*
	24	* The full GNU General Public License is included in this distribution
	25	* in the file called LICENSE.GPL.
	26	*
	27	* Contact Information:
759ef89f	28	* Intel Linux Wireless <ilw@linux.intel.com>
6f83eaa1 TW	29	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	30	*
	31	* BSD LICENSE
	32	*
901069c7	33	* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
6f83eaa1 TW	34	* All rights reserved.
	35	*
	36	* Redistribution and use in source and binary forms, with or without
	37	* modification, are permitted provided that the following conditions
	38	* are met:
	39	*
	40	* * Redistributions of source code must retain the above copyright
	41	* notice, this list of conditions and the following disclaimer.
	42	* * Redistributions in binary form must reproduce the above copyright
	43	* notice, this list of conditions and the following disclaimer in
	44	* the documentation and/or other materials provided with the
	45	* distribution.
	46	* * Neither the name Intel Corporation nor the names of its
	47	* contributors may be used to endorse or promote products derived
	48	* from this software without specific prior written permission.
	49	*
	50	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	51	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	52	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	53	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	54	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	55	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	56	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	57	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	58	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	59	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	60	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	61	*
	62	*****************************************************************************/
65a0667b TW	63	#ifndef __iwl_csr_h__
65a0667b TW	64	#define __iwl_csr_h__
9e595d24 BC	65	/*
	66	* CSR (control and status registers)
	67	*
	68	* CSR registers are mapped directly into PCI bus space, and are accessible
	69	* whenever platform supplies power to device, even when device is in
	70	* low power states due to driver-invoked device resets
	71	* (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
	72	*
	73	* Use iwl_write32() and iwl_read32() family to access these registers;
	74	* these provide simple PCI bus access, without waking up the MAC.
	75	* Do not use iwl_write_direct32() family for these registers;
	76	* no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
	77	* The MAC (uCode processor, etc.) does not need to be powered up for accessing
	78	* the CSR registers.
	79	*
f8701fe3	80	* NOTE: Device does need to be awake in order to read this memory
9e595d24 BC	81	* via CSR_EEPROM and CSR_OTP registers
9e595d24 BC	82	*/
6f83eaa1 TW	83	#define CSR_BASE (0x000)
	84
	85	#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
9e595d24	86	#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
6f83eaa1 TW	87	#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
	88	#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
	89	#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
	90	#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
	91	#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
	92	#define CSR_GP_CNTRL (CSR_BASE+0x024)
	93
9e595d24 BC	94	/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
	95	#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
	96
6f83eaa1 TW	97	/*
	98	* Hardware revision info
	99	* Bit fields:
	100	* 31-8: Reserved
9e595d24	101	* 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
6f83eaa1	102	* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
9e595d24	103	* 1-0: "Dash" (-) value, as in A-1, etc.
6f83eaa1 TW	104	*
6f83eaa1 TW	105	* NOTE: Revision step affects calculation of CCK txpower for 4965.
9e595d24	106	* NOTE: See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
6f83eaa1 TW	107	*/
	108	#define CSR_HW_REV (CSR_BASE+0x028)
	109
9e595d24 BC	110	/*
	111	* EEPROM and OTP (one-time-programmable) memory reads
	112	*
f8701fe3 RC	113	* NOTE: Device must be awake, initialized via apm_ops.init(),
f8701fe3 RC	114	* in order to read.
9e595d24	115	*/
6f83eaa1 TW	116	#define CSR_EEPROM_REG (CSR_BASE+0x02c)
6f83eaa1 TW	117	#define CSR_EEPROM_GP (CSR_BASE+0x030)
0848e297	118	#define CSR_OTP_GP_REG (CSR_BASE+0x034)
9e595d24	119
8f061891	120	#define CSR_GIO_REG (CSR_BASE+0x03C)
65b7998a WYG	121	#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
65b7998a WYG	122	#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
9e595d24 BC	123
	124	/*
	125	* UCODE-DRIVER GP (general purpose) mailbox registers.
	126	* SET/CLR registers set/clear bit(s) if "1" is written.
	127	*/
6f83eaa1 TW	128	#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
	129	#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
	130	#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
	131	#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
9e595d24	132
ab53d8af	133	#define CSR_LED_REG (CSR_BASE+0x094)
ef850d7c	134	#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
f81c1f48 WYG	135	#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
f81c1f48 WYG	136
9e595d24 BC	137
9e595d24 BC	138	/* GIO Chicken Bits (PCI Express bus link power management) */
8f061891	139	#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
6f83eaa1	140
a693f187	141	/* Analog phase-lock-loop configuration */
6f83eaa1	142	#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
9e595d24	143
6f83eaa1	144	/*
9e595d24 BC	145	* CSR Hardware Revision Workaround Register. Indicates hardware rev;
	146	* "step" determines CCK backoff for txpower calculation. Used for 4965 only.
	147	* See also CSR_HW_REV register.
6f83eaa1 TW	148	* Bit fields:
6f83eaa1 TW	149	* 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
9e595d24	150	* 1-0: "Dash" (-) value, as in C-1, etc.
6f83eaa1	151	*/
32004ee4	152	#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
9e595d24	153
32004ee4 WYG	154	#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
32004ee4 WYG	155	#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
6f83eaa1 TW	156
6f83eaa1 TW	157	/* Bits for CSR_HW_IF_CONFIG_REG */
a395b920 TW	158	#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
	159	#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
	160	#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
6f83eaa1	161
9e595d24 BC	162	#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
	163	#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
	164	#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
	165	#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
	166	#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
4c43e0d0	167
74ba67ed BC	168	#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
74ba67ed BC	169	#define CSR_INT_PERIODIC_ENA (0xFF) /* 25532 usec ~ 8 msec/
6f83eaa1 TW	170
	171	/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
	172	* acknowledged (reset) by host writing "1" to flagged bits. */
	173	#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
	174	#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
40cefda9	175	#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
6f83eaa1 TW	176	#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
	177	#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
	178	#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
	179	#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
	180	#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
f7d046f9	181	#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
6f83eaa1 TW	182	#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
	183	#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
	184
	185	#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX \| \
	186	CSR_INT_BIT_HW_ERR \| \
	187	CSR_INT_BIT_FH_TX \| \
	188	CSR_INT_BIT_SW_ERR \| \
	189	CSR_INT_BIT_RF_KILL \| \
	190	CSR_INT_BIT_SW_RX \| \
	191	CSR_INT_BIT_WAKEUP \| \
	192	CSR_INT_BIT_ALIVE)
	193
	194	/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
	195	#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
	196	#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
6f83eaa1 TW	197	#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
6f83eaa1 TW	198	#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
6f83eaa1 TW	199	#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
	200	#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
	201
f7d046f9 WYG	202	#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR \| \
	203	CSR_FH_INT_BIT_RX_CHNL1 \| \
	204	CSR_FH_INT_BIT_RX_CHNL0)
6f83eaa1	205
f7d046f9 WYG	206	#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 \| \
f7d046f9 WYG	207	CSR_FH_INT_BIT_TX_CHNL0)
6f83eaa1	208
6f4083aa TW	209	/* GPIO */
	210	#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
	211	#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
	212	#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
6f83eaa1 TW	213
	214	/* RESET */
	215	#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
	216	#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
	217	#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
	218	#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
	219	#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
32004ee4	220	#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
6f83eaa1	221
9e595d24 BC	222	/*
	223	* GP (general purpose) CONTROL REGISTER
	224	* Bit fields:
	225	* 27: HW_RF_KILL_SW
	226	* Indicates state of (platform's) hardware RF-Kill switch
	227	* 26-24: POWER_SAVE_TYPE
	228	* Indicates current power-saving mode:
	229	* 000 -- No power saving
	230	* 001 -- MAC power-down
	231	* 010 -- PHY (radio) power-down
	232	* 011 -- Error
	233	* 9-6: SYS_CONFIG
	234	* Indicates current system configuration, reflecting pins on chip
	235	* as forced high/low by device circuit board.
	236	* 4: GOING_TO_SLEEP
	237	* Indicates MAC is entering a power-saving sleep power-down.
	238	* Not a good time to access device-internal resources.
	239	* 3: MAC_ACCESS_REQ
	240	* Host sets this to request and maintain MAC wakeup, to allow host
	241	* access to device-internal resources. Host must wait for
	242	* MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
	243	* device registers.
	244	* 2: INIT_DONE
	245	* Host sets this to put device into fully operational D0 power mode.
	246	* Host resets this after SW_RESET to put device into low power mode.
	247	* 0: MAC_CLOCK_READY
	248	* Indicates MAC (ucode processor, etc.) is powered up and can run.
	249	* Internal resources are accessible.
	250	* NOTE: This does not indicate that the processor is actually running.
f7d046f9	251	* NOTE: This does not indicate that device has completed
9e595d24 BC	252	* init or post-power-down restore of internal SRAM memory.
	253	* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
	254	* SRAM is restored and uCode is in normal operation mode.
	255	* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
	256	* do not need to save/restore it.
	257	* NOTE: After device reset, this bit remains "0" until host sets
	258	* INIT_DONE
	259	*/
6f83eaa1 TW	260	#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
	261	#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
	262	#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
	263	#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
	264
	265	#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
	266
	267	#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
	268	#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
	269	#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
	270
	271
b661c819	272	/* HW REV */
fcdf1f73	273	#define CSR_HW_REV_TYPE_MSK (0x00001F0)
fcf623df TW	274	#define CSR_HW_REV_TYPE_5300 (0x0000020)
	275	#define CSR_HW_REV_TYPE_5350 (0x0000030)
	276	#define CSR_HW_REV_TYPE_5100 (0x0000050)
	277	#define CSR_HW_REV_TYPE_5150 (0x0000040)
77dcb6a9	278	#define CSR_HW_REV_TYPE_1000 (0x0000060)
2264596d JS	279	#define CSR_HW_REV_TYPE_6x00 (0x0000070)
2264596d JS	280	#define CSR_HW_REV_TYPE_6x50 (0x0000080)
14a75766 WYG	281	#define CSR_HW_REV_TYPE_6150 (0x0000084)
	282	#define CSR_HW_REV_TYPE_6x05 (0x00000B0)
	283	#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
fcdf1f73 WYG	284	#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
	285	#define CSR_HW_REV_TYPE_2x30 (0x00000C0)
	286	#define CSR_HW_REV_TYPE_2x00 (0x0000100)
	287	#define CSR_HW_REV_TYPE_200 (0x0000110)
	288	#define CSR_HW_REV_TYPE_230 (0x0000120)
	289	#define CSR_HW_REV_TYPE_NONE (0x00001F0)
b661c819	290
6f83eaa1 TW	291	/* EEPROM REG */
	292	#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
	293	#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
3d5717ad ZY	294	#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
3d5717ad ZY	295	#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
6f83eaa1 TW	296
6f83eaa1 TW	297	/* EEPROM GP */
9e595d24	298	#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
6f83eaa1	299	#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
9e595d24 BC	300	#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
	301	#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
	302	#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
	303	#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
	304
	305	/* One-time-programmable memory general purpose reg */
0848e297 WYG	306	#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
	307	#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
	308	#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
	309	#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
9e595d24 BC	310
9e595d24 BC	311	/* GP REG */
c09430ab WYG	312	#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
	313	#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
	314	#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
	315	#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
	316	#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
6f83eaa1	317
f41bb897	318
8f061891 TW	319	/* CSR GIO */
	320	#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
	321
9e595d24 BC	322	/*
	323	* UCODE-DRIVER GP (general purpose) mailbox register 1
	324	* Host driver and uCode write and/or read this register to communicate with
	325	* each other.
	326	* Bit fields:
	327	* 4: UCODE_DISABLE
	328	* Host sets this to request permanent halt of uCode, same as
	329	* sending CARD_STATE command with "halt" bit set.
	330	* 3: CT_KILL_EXIT
	331	* Host sets this to request exit from CT_KILL state, i.e. host thinks
	332	* device temperature is low enough to continue normal operation.
	333	* 2: CMD_BLOCKED
	334	* Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
	335	* to release uCode to clear all Tx and command queues, enter
	336	* unassociated mode, and power down.
	337	* NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
	338	* 1: SW_BIT_RFKILL
	339	* Host sets this when issuing CARD_STATE command to request
	340	* device sleep.
	341	* 0: MAC_SLEEP
	342	* uCode sets this when preparing a power-saving power-down.
	343	* uCode resets this when power-up is complete and SRAM is sane.
f7d046f9	344	* NOTE: device saves internal SRAM data to host when powering down,
9e595d24 BC	345	* and must restore this data after powering back up.
	346	* MAC_SLEEP is the best indication that restore is complete.
	347	* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
	348	* do not need to save/restore it.
	349	*/
6f83eaa1 TW	350	#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
	351	#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
	352	#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
	353	#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
	354
65b7998a WYG	355	/* GP Driver */
	356	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
	357	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
	358	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
	359	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
02796d77 SZ	360	#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
02796d77 SZ	361	#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
65b7998a	362
52e6b85f WYG	363	#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
52e6b85f WYG	364
9e595d24	365	/* GIO Chicken Bits (PCI Express bus link power management) */
6f83eaa1 TW	366	#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
	367	#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
	368
ab53d8af MA	369	/* LED */
	370	#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
	371	#define CSR_LED_REG_TRUN_ON (0x78)
	372	#define CSR_LED_REG_TRUN_OFF (0x38)
	373
a693f187	374	/* ANA_PLL */
a693f187 TW	375	#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
a693f187 TW	376
4c43e0d0 TW	377	/* HPET MEM debug */
4c43e0d0 TW	378	#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
ef850d7c MA	379
	380	/* DRAM INT TABLE */
	381	#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
	382	#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
	383
9e595d24 BC	384	/*
	385	* HBUS (Host-side Bus)
	386	*
	387	* HBUS registers are mapped directly into PCI bus space, but are used
	388	* to indirectly access device's internal memory or registers that
	389	* may be powered-down.
	390	*
	391	* Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
	392	* host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
	393	* to make sure the MAC (uCode processor, etc.) is powered up for accessing
	394	* internal resources.
	395	*
	396	* Do not use iwl_write32()/iwl_read32() family to access these registers;
	397	* these provide only simple PCI bus access, without waking up the MAC.
	398	*/
750fe639	399	#define HBUS_BASE (0x400)
9e595d24	400
750fe639 TW	401	/*
	402	* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
	403	* structures, error log, event log, verifying uCode load).
	404	* First write to address register, then read from or write to data register
	405	* to complete the job. Once the address register is set up, accesses to
	406	* data registers auto-increment the address by one dword.
	407	* Bit usage for address registers (read or write):
	408	* 0-31: memory address within device
	409	*/
	410	#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
	411	#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
	412	#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
	413	#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
	414
9e595d24 BC	415	/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
	416	#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
	417	#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
	418
750fe639 TW	419	/*
	420	* Registers for accessing device's internal peripheral registers
	421	* (e.g. SCD, BSM, etc.). First write to address register,
	422	* then read from or write to data register to complete the job.
	423	* Bit usage for address registers (read or write):
	424	* 0-15: register address (offset) within device
	425	* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
	426	*/
	427	#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
	428	#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
	429	#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
	430	#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
	431
	432	/*
9e595d24	433	* Per-Tx-queue write pointer (index, really!)
750fe639 TW	434	* Indicates index to next TFD that driver will fill (1 past latest filled).
	435	* Bit usage:
	436	* 0-7: queue write index
	437	* 11-8: queue selector
	438	*/
	439	#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
750fe639	440
65a0667b	441	#endif /* !__iwl_csr_h__ */