iwlagn: introduce iwl-shared.h
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 */
30
be1f3ab6
EG
31#ifndef __iwl_dev_h__
32#define __iwl_dev_h__
b481de9c 33
a6b7a407 34#include <linux/interrupt.h>
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
7194207c 37#include <linux/wait.h>
5ed540ae 38#include <linux/leds.h>
5d08cd1d
CH
39#include <net/ieee80211_radiotap.h>
40
6bc913bd 41#include "iwl-eeprom.h"
6f83eaa1 42#include "iwl-csr.h"
5d08cd1d 43#include "iwl-prph.h"
dbb6654c 44#include "iwl-fh.h"
0a6857e7 45#include "iwl-debug.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
0975cc8f 50#include "iwl-agn-tt.h"
d5934110 51#include "iwl-bus.h"
41c50542 52#include "iwl-trans.h"
48f20d35 53#include "iwl-shared.h"
5d08cd1d 54
48d1a211
EG
55#define DRV_NAME "iwlagn"
56
672639de
WYG
57struct iwl_tx_queue;
58
099b40b7 59/* CT-KILL constants */
672639de
WYG
60#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
61#define CT_KILL_THRESHOLD 114 /* in Celsius */
62#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 63
5d08cd1d
CH
64/* Default noise level to report when noise measurement is not available.
65 * This may be because we're:
66 * 1) Not associated (4965, no beacon statistics being sent to driver)
67 * 2) Scanning (noise measurement does not apply to associated channel)
68 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
69 * Use default noise value of -127 ... this is below the range of measurable
70 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
71 * Also, -127 works better than 0 when averaging frames with/without
72 * noise info (e.g. averaging might be done in app); measured dBm values are
73 * always negative ... using a negative value as the default keeps all
74 * averages within an s8's (used in some apps) range of negative values. */
75#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
76
5d08cd1d
CH
77/*
78 * RTS threshold here is total size [2347] minus 4 FCS bytes
79 * Per spec:
80 * a value of 0 means RTS on all data/management packets
81 * a value > max MSDU size means no RTS
82 * else RTS for data/management frames where MPDU is larger
83 * than RTS value.
84 */
85#define DEFAULT_RTS_THRESHOLD 2347U
86#define MIN_RTS_THRESHOLD 0U
87#define MAX_RTS_THRESHOLD 2347U
88#define MAX_MSDU_SIZE 2304U
89#define MAX_MPDU_SIZE 2346U
51b7ef05 90#define DEFAULT_BEACON_INTERVAL 200U
5d08cd1d
CH
91#define DEFAULT_SHORT_RETRY_LIMIT 7U
92#define DEFAULT_LONG_RETRY_LIMIT 4U
93
a55360e4 94struct iwl_rx_mem_buffer {
2f301227
ZY
95 dma_addr_t page_dma;
96 struct page *page;
5d08cd1d
CH
97 struct list_head list;
98};
99
2f301227
ZY
100#define rxb_addr(r) page_address(r->page)
101
c2acea8e
JB
102/* defined below */
103struct iwl_device_cmd;
104
105struct iwl_cmd_meta {
106 /* only for SYNC commands, iff the reply skb is wanted */
107 struct iwl_host_cmd *source;
108 /*
109 * only for ASYNC commands
110 * (which is somewhat stupid -- look at iwl-sta.c for instance
111 * which duplicates a bunch of code because the callback isn't
112 * invoked for SYNC commands, if it were and its result passed
113 * through it would be simpler...)
114 */
5696aea6
JB
115 void (*callback)(struct iwl_priv *priv,
116 struct iwl_device_cmd *cmd,
2f301227 117 struct iwl_rx_packet *pkt);
c2acea8e 118
c2acea8e
JB
119 u32 flags;
120
2e724443
FT
121 DEFINE_DMA_UNMAP_ADDR(mapping);
122 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
123};
124
5d08cd1d
CH
125/*
126 * Generic queue structure
127 *
4ce7cc2b
JB
128 * Contains common data for Rx and Tx queues.
129 *
130 * Note the difference between n_bd and n_window: the hardware
131 * always assumes 256 descriptors, so n_bd is always 256 (unless
132 * there might be HW changes in the future). For the normal TX
133 * queues, n_window, which is the size of the software queue data
134 * is also 256; however, for the command queue, n_window is only
135 * 32 since we don't need so many commands pending. Since the HW
136 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
137 * the software buffers (in the variables @meta, @txb in struct
138 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
139 * in the same struct) have 256.
140 * This means that we end up with the following:
141 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
142 * SW entries: | 0 | ... | 31 |
143 * where N is a number between 0 and 7. This means that the SW
144 * data is a window overlayed over the HW queue.
5d08cd1d 145 */
443cfd45 146struct iwl_queue {
5d08cd1d
CH
147 int n_bd; /* number of BDs in this queue */
148 int write_ptr; /* 1-st empty entry (index) host_w*/
149 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 150 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
151 dma_addr_t dma_addr; /* physical addr for BD's */
152 int n_window; /* safe queue window */
153 u32 id;
154 int low_mark; /* low watermark, resume queue if free
155 * space more than this */
156 int high_mark; /* high watermark, stop queue if free
157 * space less than this */
a839cf69 158};
5d08cd1d 159
bc47279f 160/* One for each TFD */
8567c63e 161struct iwl_tx_info {
ff0d91c3 162 struct sk_buff *skb;
c90cbbbd 163 struct iwl_rxon_context *ctx;
5d08cd1d
CH
164};
165
166/**
16466903 167 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
168 * @q: generic Rx/Tx queue descriptor
169 * @bd: base of circular buffer of TFDs
c2acea8e
JB
170 * @cmd: array of command/TX buffer pointers
171 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
172 * @dma_addr_cmd: physical address of cmd/tx buffer array
173 * @txb: array of per-TFD driver data
22de94de 174 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
175 * @need_update: indicates need to update read/write index
176 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 177 *
bc47279f
BC
178 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
179 * descriptors) and required locking structures.
5d08cd1d 180 */
188cf6c7
SO
181#define TFD_TX_CMD_SLOTS 256
182#define TFD_CMD_SLOTS 32
183
16466903 184struct iwl_tx_queue {
443cfd45 185 struct iwl_queue q;
4ce7cc2b 186 struct iwl_tfd *tfds;
c2acea8e
JB
187 struct iwl_device_cmd **cmd;
188 struct iwl_cmd_meta *meta;
8567c63e 189 struct iwl_tx_info *txb;
22de94de 190 unsigned long time_stamp;
3fd07a1e
TW
191 u8 need_update;
192 u8 sched_retry;
193 u8 active;
194 u8 swq_id;
5d08cd1d
CH
195};
196
197#define IWL_NUM_SCAN_RATES (2)
198
5d08cd1d
CH
199/*
200 * One for each channel, holds all channel setup data
201 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
202 * with one another!
203 */
bf85ea4f 204struct iwl_channel_info {
073d3f5f 205 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
206 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
207 * HT40 channel */
5d08cd1d
CH
208
209 u8 channel; /* channel number */
210 u8 flags; /* flags copied from EEPROM */
211 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 212 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
213 s8 min_power; /* always 0 */
214 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
215
216 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
217 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 218 enum ieee80211_band band;
5d08cd1d 219
7aafef1c
WYG
220 /* HT40 channel info */
221 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
222 u8 ht40_flags; /* flags copied from EEPROM */
223 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
224};
225
751ca305 226#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 227#define IWL_TX_FIFO_BE 1
751ca305 228#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 229#define IWL_TX_FIFO_VO 3
751ca305
JB
230#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
231#define IWL_TX_FIFO_BE_IPAN 4
232#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
233#define IWL_TX_FIFO_VO_IPAN 5
72c04ce0
JB
234/* re-uses the VO FIFO, uCode will properly flush/schedule */
235#define IWL_TX_FIFO_AUX 5
edc1a3a0 236#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 237
72c04ce0
JB
238/* AUX (TX during scan dwell) queue */
239#define IWL_AUX_QUEUE 10
240
241/*
242 * Minimum number of queues. MAX_NUM is defined in hw specific files.
243 * Set the minimum to accommodate
244 * - 4 standard TX queues
245 * - the command queue
246 * - 4 PAN TX queues
247 * - the PAN multicast queue, and
248 * - the AUX (TX during scan dwell) queue.
249 */
250#define IWL_MIN_NUM_QUEUES 11
5d08cd1d 251
bd35f150 252/*
13bb9483 253 * Command queue depends on iPAN support.
bd35f150 254 */
13bb9483
JB
255#define IWL_DEFAULT_CMD_QUEUE_NUM 4
256#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 257
751ca305
JB
258/*
259 * This queue number is required for proper operation
260 * because the ucode will stop/start the scheduler as
261 * required.
262 */
263#define IWL_IPAN_MCAST_QUEUE 8
264
5d08cd1d
CH
265#define IEEE80211_DATA_LEN 2304
266#define IEEE80211_4ADDR_LEN 30
267#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
268#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
269
5d08cd1d 270
5d08cd1d
CH
271#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
272#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
273#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
274
275enum {
c587de0b 276 CMD_SYNC = 0,
e419d62d
EG
277 CMD_ASYNC = BIT(0),
278 CMD_WANT_SKB = BIT(1),
c7c1115b 279 CMD_ON_DEMAND = BIT(2),
5d08cd1d
CH
280};
281
c8c24872 282#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 283
bc47279f 284/**
c2acea8e 285 * struct iwl_device_cmd
bc47279f
BC
286 *
287 * For allocation of the command and tx queues, this establishes the overall
4ce7cc2b
JB
288 * size of the largest command we send to uCode, except for commands that
289 * aren't fully copied and use other TFD space.
bc47279f 290 */
c2acea8e 291struct iwl_device_cmd {
857485c0 292 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 293 union {
5d08cd1d
CH
294 u32 flags;
295 u8 val8;
296 u16 val16;
297 u32 val32;
83d527d9 298 struct iwl_tx_cmd tx;
c8c24872
WYG
299 struct iwl6000_channel_switch_cmd chswitch;
300 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
301 } __packed cmd;
302} __packed;
5d08cd1d 303
c2acea8e
JB
304#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
305
4ce7cc2b
JB
306#define IWL_MAX_CMD_TFDS 2
307
308enum iwl_hcmd_dataflag {
309 IWL_HCMD_DFL_NOCOPY = BIT(0),
310};
3257e5d4 311
e419d62d
EG
312/**
313 * struct iwl_host_cmd - Host command to the uCode
314 * @data: array of chunks that composes the data of the host command
315 * @reply_page: pointer to the page that holds the response to the host command
316 * @callback:
317 * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC
318 * @len: array of the lenths of the chunks in data
319 * @dataflags:
320 * @id: id of the host command
321 */
857485c0 322struct iwl_host_cmd {
3fa50738 323 const void *data[IWL_MAX_CMD_TFDS];
2f301227 324 unsigned long reply_page;
5696aea6
JB
325 void (*callback)(struct iwl_priv *priv,
326 struct iwl_device_cmd *cmd,
2f301227 327 struct iwl_rx_packet *pkt);
c2acea8e 328 u32 flags;
3fa50738 329 u16 len[IWL_MAX_CMD_TFDS];
4ce7cc2b 330 u8 dataflags[IWL_MAX_CMD_TFDS];
c2acea8e 331 u8 id;
5d08cd1d
CH
332};
333
5d08cd1d
CH
334#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
335#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
336#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
337
338/**
a55360e4 339 * struct iwl_rx_queue - Rx queue
df833b1d 340 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 341 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
342 * @read: Shared index to newest available Rx buffer
343 * @write: Shared index to oldest written Rx packet
344 * @free_count: Number of pre-allocated buffers in rx_free
345 * @rx_free: list of free SKBs for use
346 * @rx_used: List of Rx buffers with no SKB
347 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
348 * @rb_stts: driver's pointer to receive buffer status
349 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 350 *
a55360e4 351 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 352 */
a55360e4 353struct iwl_rx_queue {
5d08cd1d 354 __le32 *bd;
d5b25c90 355 dma_addr_t bd_dma;
a55360e4
TW
356 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
357 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
358 u32 read;
359 u32 write;
360 u32 free_count;
4752c93c 361 u32 write_actual;
5d08cd1d
CH
362 struct list_head rx_free;
363 struct list_head rx_used;
364 int need_update;
8d86422a
WT
365 struct iwl_rb_status *rb_stts;
366 dma_addr_t rb_stts_dma;
5d08cd1d
CH
367 spinlock_t lock;
368};
369
370#define IWL_SUPPORTED_RATES_IE_LEN 8
371
5d08cd1d
CH
372#define MAX_TID_COUNT 9
373
374#define IWL_INVALID_RATE 0xFF
375#define IWL_INVALID_VALUE -1
376
bc47279f 377/**
6def9761 378 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
379 * @txq_id: Tx queue used for Tx attempt
380 * @frame_count: # frames attempted by Tx command
381 * @wait_for_ba: Expect block-ack before next Tx reply
382 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
383 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
384 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
385 * @rate_n_flags: Rate at which Tx was attempted
386 *
387 * If REPLY_TX indicates that aggregation was attempted, driver must wait
388 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
389 * until block ack arrives.
390 */
6def9761 391struct iwl_ht_agg {
5d08cd1d
CH
392 u16 txq_id;
393 u16 frame_count;
394 u16 wait_for_ba;
395 u16 start_idx;
fe01b477 396 u64 bitmap;
5d08cd1d 397 u32 rate_n_flags;
fe01b477
RR
398#define IWL_AGG_OFF 0
399#define IWL_AGG_ON 1
400#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
401#define IWL_EMPTYING_HW_QUEUE_DELBA 3
402 u8 state;
c8823ec1 403 u8 tx_fifo;
5d08cd1d 404};
fe01b477 405
5d08cd1d 406
6def9761 407struct iwl_tid_data {
f862a236 408 u16 seq_number; /* agn only */
fe01b477 409 u16 tfds_in_queue;
6def9761 410 struct iwl_ht_agg agg;
5d08cd1d
CH
411};
412
a78fe754 413union iwl_ht_rate_supp {
5d08cd1d
CH
414 u16 rates;
415 struct {
416 u8 siso_rate;
417 u8 mimo_rate;
418 };
419};
420
172c1d11
WYG
421#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
422#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
423#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
424#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
425#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
426#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
427#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
428
429/*
430 * Maximal MPDU density for TX aggregation
431 * 4 - 2us density
432 * 5 - 4us density
433 * 6 - 8us density
434 * 7 - 16us density
435 */
172c1d11 436#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 437#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
438#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
439#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 440#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
441#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
442#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 443
fad95bf5 444struct iwl_ht_config {
02bb1bea 445 bool single_chain_sufficient;
ba37a3d0 446 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 447};
5d08cd1d 448
5d08cd1d 449/* QoS structures */
1ff50bda 450struct iwl_qos_info {
5d08cd1d 451 int qos_active;
1ff50bda 452 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 453};
5d08cd1d 454
fe6b23dd
RC
455/*
456 * Structure should be accessed with sta_lock held. When station addition
457 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
458 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
459 * held.
460 */
6def9761 461struct iwl_station_entry {
133636de 462 struct iwl_addsta_cmd sta;
6def9761 463 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 464 u8 used, ctxid;
fe6b23dd 465 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
466};
467
fd1af15d 468struct iwl_station_priv_common {
238d781d 469 struct iwl_rxon_context *ctx;
fd1af15d
JB
470 u8 sta_id;
471};
472
8d9698b3
RC
473/*
474 * iwl_station_priv: Driver's private station information
475 *
476 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
477 * in the structure for use by driver. This structure is places in that
478 * space.
8d9698b3
RC
479 */
480struct iwl_station_priv {
fd1af15d 481 struct iwl_station_priv_common common;
8d9698b3 482 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
483 atomic_t pending_frames;
484 bool client;
485 bool asleep;
7b090687 486 u8 max_agg_bufsize;
8d9698b3
RC
487};
488
fd1af15d
JB
489/**
490 * struct iwl_vif_priv - driver's private per-interface information
491 *
492 * When mac80211 allocates a virtual interface, it can allocate
493 * space for us to put data into.
494 */
495struct iwl_vif_priv {
246ed355 496 struct iwl_rxon_context *ctx;
fd1af15d
JB
497 u8 ibss_bssid_sta_id;
498};
499
5d08cd1d
CH
500/* one for each uCode image (inst/data, boot/init/runtime) */
501struct fw_desc {
502 void *v_addr; /* access by driver */
503 dma_addr_t p_addr; /* access by card's busmaster DMA */
504 u32 len; /* bytes */
505};
506
dbf28e21
JB
507struct fw_img {
508 struct fw_desc code, data;
509};
510
dd7a2509 511/* v1/v2 uCode file layout */
cc0f555d
JS
512struct iwl_ucode_header {
513 __le32 ver; /* major/minor/API/serial */
514 union {
515 struct {
516 __le32 inst_size; /* bytes of runtime code */
517 __le32 data_size; /* bytes of runtime data */
518 __le32 init_size; /* bytes of init code */
519 __le32 init_data_size; /* bytes of init data */
520 __le32 boot_size; /* bytes of bootstrap code */
521 u8 data[0]; /* in same order as sizes */
522 } v1;
523 struct {
524 __le32 build; /* build number */
525 __le32 inst_size; /* bytes of runtime code */
526 __le32 data_size; /* bytes of runtime data */
527 __le32 init_size; /* bytes of init code */
528 __le32 init_data_size; /* bytes of init data */
529 __le32 boot_size; /* bytes of bootstrap code */
530 u8 data[0]; /* in same order as sizes */
531 } v2;
532 } u;
5d08cd1d
CH
533};
534
dd7a2509
JB
535/*
536 * new TLV uCode file layout
537 *
538 * The new TLV file format contains TLVs, that each specify
539 * some piece of data. To facilitate "groups", for example
540 * different instruction image with different capabilities,
541 * bundled with the same init image, an alternative mechanism
542 * is provided:
543 * When the alternative field is 0, that means that the item
544 * is always valid. When it is non-zero, then it is only
545 * valid in conjunction with items of the same alternative,
546 * in which case the driver (user) selects one alternative
547 * to use.
548 */
549
550enum iwl_ucode_tlv_type {
551 IWL_UCODE_TLV_INVALID = 0, /* unused */
552 IWL_UCODE_TLV_INST = 1,
553 IWL_UCODE_TLV_DATA = 2,
554 IWL_UCODE_TLV_INIT = 3,
555 IWL_UCODE_TLV_INIT_DATA = 4,
556 IWL_UCODE_TLV_BOOT = 5,
557 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 558 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
559 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
560 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
561 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
562 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
563 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
564 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 565 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 566 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
c8ac61cf
JB
567 IWL_UCODE_TLV_WOWLAN_INST = 16,
568 IWL_UCODE_TLV_WOWLAN_DATA = 17,
3997ff39
JB
569 IWL_UCODE_TLV_FLAGS = 18,
570};
571
572/**
573 * enum iwl_ucode_tlv_flag - ucode API flags
574 * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
575 * was a separate TLV but moved here to save space.
d2690c0d
JB
576 * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
577 * treats good CRC threshold as a boolean
3997ff39 578 * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
c6baf7fb 579 * @IWL_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
3997ff39
JB
580 */
581enum iwl_ucode_tlv_flag {
582 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
d2690c0d 583 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
3997ff39 584 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
c6baf7fb 585 IWL_UCODE_TLV_FLAGS_P2P = BIT(3),
dd7a2509
JB
586};
587
588struct iwl_ucode_tlv {
589 __le16 type; /* see above */
590 __le16 alternative; /* see comment */
591 __le32 length; /* not including type/length fields */
592 u8 data[0];
ba2d3587 593} __packed;
dd7a2509
JB
594
595#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
596
597struct iwl_tlv_ucode_header {
598 /*
599 * The TLV style ucode header is distinguished from
600 * the v1/v2 style header by first four bytes being
601 * zero, as such is an invalid combination of
602 * major/minor/API/serial versions.
603 */
604 __le32 zero;
605 __le32 magic;
606 u8 human_readable[64];
607 __le32 ver; /* major/minor/API/serial */
608 __le32 build;
609 __le64 alternatives; /* bitmask of valid alternatives */
610 /*
611 * The data contained herein has a TLV layout,
612 * see above for the TLV header and types.
613 * Note that each TLV is padded to a length
614 * that is a multiple of 4 for alignment.
615 */
616 u8 data[0];
617};
618
f0832f13
EG
619struct iwl_sensitivity_ranges {
620 u16 min_nrg_cck;
621 u16 max_nrg_cck;
622
623 u16 nrg_th_cck;
624 u16 nrg_th_ofdm;
625
626 u16 auto_corr_min_ofdm;
627 u16 auto_corr_min_ofdm_mrc;
628 u16 auto_corr_min_ofdm_x1;
629 u16 auto_corr_min_ofdm_mrc_x1;
630
631 u16 auto_corr_max_ofdm;
632 u16 auto_corr_max_ofdm_mrc;
633 u16 auto_corr_max_ofdm_x1;
634 u16 auto_corr_max_ofdm_mrc_x1;
635
636 u16 auto_corr_max_cck;
637 u16 auto_corr_max_cck_mrc;
638 u16 auto_corr_min_cck;
639 u16 auto_corr_min_cck_mrc;
55036d66
WYG
640
641 u16 barker_corr_th_min;
642 u16 barker_corr_th_min_mrc;
643 u16 nrg_th_cca;
f0832f13
EG
644};
645
099b40b7 646
b5047f78
TW
647#define KELVIN_TO_CELSIUS(x) ((x)-273)
648#define CELSIUS_TO_KELVIN(x) ((x)+273)
649
650
bc47279f 651/**
5425e490 652 * struct iwl_hw_params
bc47279f 653 * @max_txq_num: Max # Tx queues supported
4ddbb7d0 654 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 655 * @tfd_size: TFD size
099b40b7
RR
656 * @tx/rx_chains_num: Number of TX/RX chains
657 * @valid_tx/rx_ant: usable antennas
bc47279f 658 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 659 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 660 * @rx_page_order: Rx buffer page order
141c43a3 661 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 662 * @max_stations:
7aafef1c 663 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
664 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
665 * @sw_crypto: 0 for hw, 1 for sw
666 * @max_xxx_size: for ucode uses
667 * @ct_kill_threshold: temperature threshold
a0ee74cf 668 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 669 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 670 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 671 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 672 */
5425e490 673struct iwl_hw_params {
f3f911d1 674 u8 max_txq_num;
4ddbb7d0 675 u16 scd_bc_tbls_size;
a8e74e27 676 u32 tfd_size;
ec35cf2a
TW
677 u8 tx_chains_num;
678 u8 rx_chains_num;
679 u8 valid_tx_ant;
680 u8 valid_rx_ant;
5d08cd1d 681 u16 max_rxq_size;
ec35cf2a 682 u16 max_rxq_log;
2f301227 683 u32 rx_page_order;
5d08cd1d 684 u8 max_stations;
7aafef1c 685 u8 ht40_channel;
2c2f3b33 686 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
687 u32 max_inst_size;
688 u32 max_data_size;
099b40b7 689 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
690 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
691 /* for 1000, 6000 series and up */
a0ee74cf 692 u16 beacon_time_tsf_bits;
be5d56ed 693 u32 calib_init_cfg;
6d6a1afd 694 u32 calib_rt_cfg;
f0832f13 695 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
696};
697
5d08cd1d 698
5d08cd1d
CH
699/******************************************************************************
700 *
a33c2f47
EG
701 * Functions implemented in core module which are forward declared here
702 * for use by iwl-[4-5].c
5d08cd1d 703 *
a33c2f47
EG
704 * NOTE: The implementation of these functions are not hardware specific
705 * which is why they are in the core module files.
5d08cd1d
CH
706 *
707 * Naming convention --
a33c2f47 708 * iwl_ <-- Is part of iwlwifi
5d08cd1d 709 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
5d08cd1d
CH
710 *
711 ****************************************************************************/
5b9f8cd3 712extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 713extern const u8 iwl_bcast_addr[ETH_ALEN];
443cfd45 714extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
715static inline int iwl_queue_used(const struct iwl_queue *q, int i)
716{
c8106d76 717 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
718 (i >= q->read_ptr && i < q->write_ptr) :
719 !(i < q->read_ptr && i >= q->write_ptr);
720}
721
722
4ce7cc2b 723static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
fd4abac5 724{
fd4abac5
TW
725 return index & (q->n_window - 1);
726}
727
728
4ddbb7d0
TW
729struct iwl_dma_ptr {
730 dma_addr_t dma;
731 void *addr;
b481de9c
ZY
732 size_t size;
733};
734
b481de9c
ZY
735#define IWL_OPERATION_MODE_AUTO 0
736#define IWL_OPERATION_MODE_HT_ONLY 1
737#define IWL_OPERATION_MODE_MIXED 2
738#define IWL_OPERATION_MODE_20MHZ 3
739
3195cdb7
TW
740#define IWL_TX_CRC_SIZE 4
741#define IWL_TX_DELIMITER_SIZE 4
b481de9c 742
b481de9c 743#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 744
b481de9c 745/* Sensitivity and chain noise calibration */
b481de9c 746#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a 747#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
748#define MAXIMUM_ALLOWED_PATHLOSS 15
749
b481de9c
ZY
750#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
751
752#define MAX_FA_OFDM 50
753#define MIN_FA_OFDM 5
754#define MAX_FA_CCK 50
755#define MIN_FA_CCK 5
756
b481de9c
ZY
757#define AUTO_CORR_STEP_OFDM 1
758
b481de9c
ZY
759#define AUTO_CORR_STEP_CCK 3
760#define AUTO_CORR_MAX_TH_CCK 160
761
b481de9c
ZY
762#define NRG_DIFF 2
763#define NRG_STEP_CCK 2
764#define NRG_MARGIN 8
765#define MAX_NUMBER_CCK_NO_FA 100
766
767#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
768
769#define CHAIN_A 0
770#define CHAIN_B 1
771#define CHAIN_C 2
772#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
773#define ALL_BAND_FILTER 0xFF00
774#define IN_BAND_FILTER 0xFF
775#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
776
3195cdb7
TW
777#define NRG_NUM_PREV_STAT_L 20
778#define NUM_RX_CHAINS 3
779
3240cab3 780enum iwlagn_false_alarm_state {
b481de9c
ZY
781 IWL_FA_TOO_MANY = 0,
782 IWL_FA_TOO_FEW = 1,
783 IWL_FA_GOOD_RANGE = 2,
784};
785
3240cab3 786enum iwlagn_chain_noise_state {
b481de9c 787 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
788 IWL_CHAIN_NOISE_ACCUMULATE,
789 IWL_CHAIN_NOISE_CALIBRATED,
790 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
791};
792
f69f42a6
TW
793
794/*
795 * enum iwl_calib
796 * defines the order in which results of initial calibrations
797 * should be sent to the runtime uCode
798 */
799enum iwl_calib {
800 IWL_CALIB_XTAL,
819500c5 801 IWL_CALIB_DC,
f69f42a6
TW
802 IWL_CALIB_LO,
803 IWL_CALIB_TX_IQ,
804 IWL_CALIB_TX_IQ_PERD,
201706ac 805 IWL_CALIB_BASE_BAND,
bf53f939 806 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
807 IWL_CALIB_MAX
808};
809
6e21f2c1
TW
810/* Opaque calibration results */
811struct iwl_calib_result {
812 void *buf;
813 size_t buf_len;
7c616cba
TW
814};
815
b481de9c 816/* Sensitivity calib data */
f0832f13 817struct iwl_sensitivity_data {
b481de9c
ZY
818 u32 auto_corr_ofdm;
819 u32 auto_corr_ofdm_mrc;
820 u32 auto_corr_ofdm_x1;
821 u32 auto_corr_ofdm_mrc_x1;
822 u32 auto_corr_cck;
823 u32 auto_corr_cck_mrc;
824
825 u32 last_bad_plcp_cnt_ofdm;
826 u32 last_fa_cnt_ofdm;
827 u32 last_bad_plcp_cnt_cck;
828 u32 last_fa_cnt_cck;
829
830 u32 nrg_curr_state;
831 u32 nrg_prev_state;
832 u32 nrg_value[10];
833 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
834 u32 nrg_silence_ref;
835 u32 nrg_energy_idx;
836 u32 nrg_silence_idx;
837 u32 nrg_th_cck;
838 s32 nrg_auto_corr_silence_diff;
839 u32 num_in_cck_no_fa;
840 u32 nrg_th_ofdm;
55036d66
WYG
841
842 u16 barker_corr_th_min;
843 u16 barker_corr_th_min_mrc;
844 u16 nrg_th_cca;
b481de9c
ZY
845};
846
847/* Chain noise (differential Rx gain) calib data */
f0832f13 848struct iwl_chain_noise_data {
04816448 849 u32 active_chains;
b481de9c
ZY
850 u32 chain_noise_a;
851 u32 chain_noise_b;
852 u32 chain_noise_c;
853 u32 chain_signal_a;
854 u32 chain_signal_b;
855 u32 chain_signal_c;
04816448 856 u16 beacon_count;
b481de9c
ZY
857 u8 disconn_array[NUM_RX_CHAINS];
858 u8 delta_gain_code[NUM_RX_CHAINS];
859 u8 radio_write;
04816448 860 u8 state;
b481de9c
ZY
861};
862
abceddb4
BC
863#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
864#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 865
20594eb0
WYG
866#define IWL_TRAFFIC_ENTRIES (256)
867#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 868
5d08cd1d
CH
869enum {
870 MEASUREMENT_READY = (1 << 0),
871 MEASUREMENT_ACTIVE = (1 << 1),
872};
873
0848e297
WYG
874enum iwl_nvm_type {
875 NVM_DEVICE_TYPE_EEPROM = 0,
876 NVM_DEVICE_TYPE_OTP,
877};
878
415e4993
WYG
879/*
880 * Two types of OTP memory access modes
881 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
882 * based on physical memory addressing
883 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
884 * based on logical memory addressing
885 */
886enum iwl_access_mode {
887 IWL_OTP_ACCESS_ABSOLUTE,
888 IWL_OTP_ACCESS_RELATIVE,
889};
65b7998a
WYG
890
891/**
892 * enum iwl_pa_type - Power Amplifier type
893 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
894 * @IWL_PA_INTERNAL: use Internal only
895 */
896enum iwl_pa_type {
897 IWL_PA_SYSTEM = 0,
740e7f51 898 IWL_PA_INTERNAL = 1,
65b7998a
WYG
899};
900
a83b9141
WYG
901/* interrupt statistics */
902struct isr_statistics {
903 u32 hw;
904 u32 sw;
6e6ebf4b 905 u32 err_code;
a83b9141
WYG
906 u32 sch;
907 u32 alive;
908 u32 rfkill;
909 u32 ctkill;
910 u32 wakeup;
911 u32 rx;
912 u32 rx_handlers[REPLY_MAX];
913 u32 tx;
914 u32 unhandled;
915};
5d08cd1d 916
91835ba4
WYG
917/* reply_tx_statistics (for _agn devices) */
918struct reply_tx_error_statistics {
919 u32 pp_delay;
920 u32 pp_few_bytes;
921 u32 pp_bt_prio;
922 u32 pp_quiet_period;
923 u32 pp_calc_ttak;
924 u32 int_crossed_retry;
925 u32 short_limit;
926 u32 long_limit;
927 u32 fifo_underrun;
928 u32 drain_flow;
929 u32 rfkill_flush;
930 u32 life_expire;
931 u32 dest_ps;
932 u32 host_abort;
933 u32 bt_retry;
934 u32 sta_invalid;
935 u32 frag_drop;
936 u32 tid_disable;
937 u32 fifo_flush;
938 u32 insuff_cf_poll;
939 u32 fail_hw_drop;
940 u32 sta_color_mismatch;
941 u32 unknown;
942};
943
814665fe
WYG
944/* reply_agg_tx_statistics (for _agn devices) */
945struct reply_agg_tx_error_statistics {
946 u32 underrun;
947 u32 bt_prio;
948 u32 few_bytes;
949 u32 abort;
950 u32 last_sent_ttl;
951 u32 last_sent_try;
952 u32 last_sent_bt_kill;
953 u32 scd_query;
954 u32 bad_crc32;
955 u32 response;
956 u32 dump_tx;
957 u32 delay_tx;
958 u32 unknown;
959};
960
22fdf3c9
WYG
961/* management statistics */
962enum iwl_mgmt_stats {
963 MANAGEMENT_ASSOC_REQ = 0,
964 MANAGEMENT_ASSOC_RESP,
965 MANAGEMENT_REASSOC_REQ,
966 MANAGEMENT_REASSOC_RESP,
967 MANAGEMENT_PROBE_REQ,
968 MANAGEMENT_PROBE_RESP,
969 MANAGEMENT_BEACON,
970 MANAGEMENT_ATIM,
971 MANAGEMENT_DISASSOC,
972 MANAGEMENT_AUTH,
973 MANAGEMENT_DEAUTH,
974 MANAGEMENT_ACTION,
975 MANAGEMENT_MAX,
976};
977/* control statistics */
978enum iwl_ctrl_stats {
979 CONTROL_BACK_REQ = 0,
980 CONTROL_BACK,
981 CONTROL_PSPOLL,
982 CONTROL_RTS,
983 CONTROL_CTS,
984 CONTROL_ACK,
985 CONTROL_CFEND,
986 CONTROL_CFENDACK,
987 CONTROL_MAX,
988};
989
990struct traffic_stats {
5ed540ae 991#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
992 u32 mgmt[MANAGEMENT_MAX];
993 u32 ctrl[CONTROL_MAX];
994 u32 data_cnt;
995 u64 data_bytes;
22fdf3c9 996#endif
5ed540ae 997};
22fdf3c9 998
a9e1cb6a
WYG
999/*
1000 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
1001 * to perform continuous uCode event logging operation if enabled
1002 */
1003#define UCODE_TRACE_PERIOD (100)
1004
1005/*
1006 * iwl_event_log: current uCode event log position
1007 *
1008 * @ucode_trace: enable/disable ucode continuous trace timer
1009 * @num_wraps: how many times the event buffer wraps
1010 * @next_entry: the entry just before the next one that uCode would fill
1011 * @non_wraps_count: counter for no wrap detected when dump ucode events
1012 * @wraps_once_count: counter for wrap once detected when dump ucode events
1013 * @wraps_more_count: counter for wrap more than once detected
1014 * when dump ucode events
1015 */
1016struct iwl_event_log {
1017 bool ucode_trace;
1018 u32 num_wraps;
1019 u32 next_entry;
1020 int non_wraps_count;
1021 int wraps_once_count;
1022 int wraps_more_count;
1023};
1024
2be76703
WYG
1025/*
1026 * host interrupt timeout value
1027 * used with setting interrupt coalescing timer
1028 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1029 *
1030 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1031 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1032 */
1033#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1034#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1035#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1036#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1037#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1038#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1039
3e4fb5fa
TAN
1040/*
1041 * This is the threshold value of plcp error rate per 100mSecs. It is
1042 * used to set and check for the validity of plcp_delta.
1043 */
680788ac 1044#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1045#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1046#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1047#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1048#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1049#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1050
8a472da4
WYG
1051#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1052#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1053
22de94de
SG
1054/* TX queue watchdog timeouts in mSecs */
1055#define IWL_DEF_WD_TIMEOUT (2000)
1056#define IWL_LONG_WD_TIMEOUT (10000)
1057#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1058
bee008b7
WYG
1059/* BT Antenna Coupling Threshold (dB) */
1060#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1061
491bc292
WYG
1062/* Firmware reload counter and Timestamp */
1063#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1064#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1065
1066
a93e7973
WYG
1067enum iwl_reset {
1068 IWL_RF_RESET = 0,
1069 IWL_FW_RESET,
8a472da4
WYG
1070 IWL_MAX_FORCE_RESET,
1071};
1072
1073struct iwl_force_reset {
1074 int reset_request_count;
1075 int reset_success_count;
1076 int reset_reject_count;
1077 unsigned long reset_duration;
1078 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1079};
1080
a0ee74cf 1081/* extend beacon time format bit shifting */
a0ee74cf
WYG
1082/*
1083 * for _agn devices
1084 * bits 31:22 - extended
1085 * bits 21:0 - interval
1086 */
1087#define IWLAGN_EXT_BEACON_TIME_POS 22
1088
7194207c
JB
1089/**
1090 * struct iwl_notification_wait - notification wait entry
1091 * @list: list head for global list
1092 * @fn: function called with the notification
1093 * @cmd: command ID
1094 *
1095 * This structure is not used directly, to wait for a
1096 * notification declare it on the stack, and call
1097 * iwlagn_init_notification_wait() with appropriate
1098 * parameters. Then do whatever will cause the ucode
1099 * to notify the driver, and to wait for that then
1100 * call iwlagn_wait_notification().
1101 *
1102 * Each notification is one-shot. If at some point we
1103 * need to support multi-shot notifications (which
1104 * can't be allocated on the stack) we need to modify
1105 * the code for them.
1106 */
1107struct iwl_notification_wait {
1108 struct list_head list;
1109
09f18afe
JB
1110 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt,
1111 void *data);
1112 void *fn_data;
7194207c
JB
1113
1114 u8 cmd;
e74fe233 1115 bool triggered, aborted;
7194207c
JB
1116};
1117
246ed355
JB
1118enum iwl_rxon_context_id {
1119 IWL_RXON_CTX_BSS,
ece9c4ee 1120 IWL_RXON_CTX_PAN,
246ed355
JB
1121
1122 NUM_IWL_RXON_CTX
1123};
1124
1125struct iwl_rxon_context {
8bd413e6 1126 struct ieee80211_vif *vif;
e72f368b
JB
1127
1128 const u8 *ac_to_fifo;
1129 const u8 *ac_to_queue;
1130 u8 mcast_queue;
1131
763cc3bf
JB
1132 /*
1133 * We could use the vif to indicate active, but we
1134 * also need it to be active during disabling when
1135 * we already removed the vif for type setting.
1136 */
1137 bool always_active, is_active;
1138
2295c66b
JB
1139 bool ht_need_multiple_chains;
1140
246ed355 1141 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1142
1143 u32 interface_modes, exclusive_interface_modes;
1144 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1145
246ed355
JB
1146 /*
1147 * We declare this const so it can only be
1148 * changed via explicit cast within the
1149 * routines that actually update the physical
1150 * hardware.
1151 */
1152 const struct iwl_rxon_cmd active;
1153 struct iwl_rxon_cmd staging;
1154
1155 struct iwl_rxon_time_cmd timing;
a194e324 1156
8dfdb9d5
JB
1157 struct iwl_qos_info qos_data;
1158
2995bafa 1159 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1160
1161 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1162 u8 qos_cmd;
c10afb6e
JB
1163 u8 wep_key_cmd;
1164
1165 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1166 u8 key_mapping_keys;
770e13bd
JB
1167
1168 __le32 station_flags;
7e6a5886 1169
bbb05cb5
JB
1170 int beacon_int;
1171
7e6a5886
JB
1172 struct {
1173 bool non_gf_sta_present;
1174 u8 protection;
1175 bool enabled, is_40mhz;
1176 u8 extension_chan_offset;
1177 } ht;
68b99311
GT
1178
1179 bool last_tx_rejected;
246ed355
JB
1180};
1181
266af4c7
JB
1182enum iwl_scan_type {
1183 IWL_SCAN_NORMAL,
1184 IWL_SCAN_RADIO_RESET,
c6baf7fb 1185 IWL_SCAN_ROC,
266af4c7
JB
1186};
1187
872907bb
JB
1188enum iwlagn_ucode_type {
1189 IWL_UCODE_NONE,
1190 IWL_UCODE_REGULAR,
1191 IWL_UCODE_INIT,
1192 IWL_UCODE_WOWLAN,
1193};
1194
7a4e5281
WYG
1195#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1196struct iwl_testmode_trace {
49b72100
WYG
1197 u32 buff_size;
1198 u32 total_size;
eb64dca0 1199 u32 num_chunks;
7a4e5281
WYG
1200 u8 *cpu_addr;
1201 u8 *trace_addr;
1202 dma_addr_t dma_addr;
1203 bool trace_enabled;
1204};
1205#endif
a48709c5 1206
e98a1939
WYG
1207/* uCode ownership */
1208#define IWL_OWNERSHIP_DRIVER 0
1209#define IWL_OWNERSHIP_TM 1
1210
c79dd5b5 1211struct iwl_priv {
5d08cd1d
CH
1212
1213 /* ieee device used by generic ieee processing code */
1214 struct ieee80211_hw *hw;
1215 struct ieee80211_channel *ieee_channels;
1216 struct ieee80211_rate *ieee_rates;
82b9a121 1217 struct iwl_cfg *cfg;
5d08cd1d 1218
8318d78a 1219 enum ieee80211_band band;
5d08cd1d 1220
4613e72d
CK
1221 void (*pre_rx_handler)(struct iwl_priv *priv,
1222 struct iwl_rx_mem_buffer *rxb);
c79dd5b5 1223 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1224 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1225
8318d78a 1226 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1227
5d08cd1d 1228 /* spectrum measurement report caching */
2aa6ab86 1229 struct iwl_spectrum_notification measure_report;
5d08cd1d 1230 u8 measurement_status;
81963d68 1231
5d08cd1d
CH
1232 /* ucode beacon time */
1233 u32 ucode_beacon_time;
a13d276f 1234 int missed_beacon_threshold;
5d08cd1d 1235
a85d7cca
JB
1236 /* track IBSS manager (last beacon) status */
1237 u32 ibss_manager;
1238
410f2bb3
SG
1239 /* jiffies when last recovery from statistics was performed */
1240 unsigned long rx_statistics_jiffies;
3e4fb5fa 1241
a93e7973 1242 /* force reset */
8a472da4 1243 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1244
491bc292
WYG
1245 /* firmware reload counter and timestamp */
1246 unsigned long reload_jiffies;
1247 int reload_count;
1248
5a2a780c 1249 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1250 * Access via channel # using indirect index array */
bf85ea4f 1251 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1252 u8 channel_count; /* # of channels */
1253
5d08cd1d
CH
1254 /* thermal calibration */
1255 s32 temperature; /* degrees Kelvin */
1256 s32 last_temperature;
1257
7c616cba 1258 /* init calibration results */
6e21f2c1 1259 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1260
5d08cd1d 1261 /* Scan related variables */
5d08cd1d 1262 unsigned long scan_start;
5d08cd1d 1263 unsigned long scan_start_tsf;
811ecc99 1264 void *scan_cmd;
00700ee0 1265 enum ieee80211_band scan_band;
1ecf9fc1 1266 struct cfg80211_scan_request *scan_request;
f84b29ec 1267 struct ieee80211_vif *scan_vif;
266af4c7 1268 enum iwl_scan_type scan_type;
76eff18b
TW
1269 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1270 u8 mgmt_tx_ant;
5d08cd1d
CH
1271
1272 /* spinlock */
1273 spinlock_t lock; /* protect general shared data */
1274 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1275 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d
CH
1276 struct mutex mutex;
1277
d5934110 1278 struct iwl_bus *bus; /* bus specific data */
c85eb619 1279 struct iwl_trans trans;
5d08cd1d 1280
246ed355
JB
1281 /* microcode/device supports multiple contexts */
1282 u8 valid_contexts;
1283
13bb9483
JB
1284 /* command queue number */
1285 u8 cmd_queue;
1286
c10afb6e
JB
1287 /* max number of station keys */
1288 u8 sta_key_max_num;
1289
d2690c0d
JB
1290 bool new_scan_threshold_behaviour;
1291
c6fa17ed
WYG
1292 /* EEPROM MAC addresses */
1293 struct mac_address addresses[2];
1294
5d08cd1d 1295 /* uCode images, save to reload in case of failure */
b08dfd04 1296 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1297 u32 ucode_ver; /* version of ucode, copy of
1298 iwl_ucode.ver */
e98a1939
WYG
1299
1300 /* uCode owner: default: IWL_OWNERSHIP_DRIVER */
1301 u8 ucode_owner;
1302
dbf28e21
JB
1303 struct fw_img ucode_rt;
1304 struct fw_img ucode_init;
c8ac61cf 1305 struct fw_img ucode_wowlan;
dbf28e21 1306
872907bb 1307 enum iwlagn_ucode_type ucode_type;
dbb983b7 1308 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1309 char firmware_name[25];
5d08cd1d 1310
246ed355 1311 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1312
6f213ff1 1313 __le16 switch_channel;
0924e519 1314
d7d5783c
JB
1315 struct {
1316 u32 error_event_table;
1317 u32 log_event_table;
1318 } device_pointers;
5d08cd1d 1319
5d08cd1d 1320 u16 active_rate;
5d08cd1d 1321
5d08cd1d 1322 u8 start_calib;
f0832f13
EG
1323 struct iwl_sensitivity_data sensitivity_data;
1324 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1325 bool enhance_sensitivity_table;
5d08cd1d 1326 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1327 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1328
fad95bf5 1329 struct iwl_ht_config current_ht_config;
5d08cd1d 1330
5d08cd1d 1331 /* Rate scaling data */
5d08cd1d
CH
1332 u8 retry_rate;
1333
1334 wait_queue_head_t wait_command_queue;
1335
1336 int activity_timer_active;
1337
1338 /* Rx and Tx DMA processing queues */
a55360e4 1339 struct iwl_rx_queue rxq;
88804e2b 1340 struct iwl_tx_queue *txq;
5d08cd1d 1341 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1342 struct iwl_dma_ptr kw; /* keep warm address */
1343 struct iwl_dma_ptr scd_bc_tbls;
1344
5d08cd1d
CH
1345 u32 scd_base_addr; /* scheduler sram base address */
1346
1347 unsigned long status;
5d08cd1d 1348
19758bef 1349 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1350 struct traffic_stats tx_stats;
1351 struct traffic_stats rx_stats;
19758bef 1352
a83b9141
WYG
1353 /* counts interrupts */
1354 struct isr_statistics isr_stats;
1355
5da4b55f 1356 struct iwl_power_mgr power_data;
3ad3b92a 1357 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1358
9c5ac091
RC
1359 /* station table variables */
1360
1361 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1362 spinlock_t sta_lock;
1363 int num_stations;
3240cab3 1364 struct iwl_station_entry stations[IWLAGN_STATION_COUNT];
80fb47a1 1365 unsigned long ucode_key_table;
5d08cd1d 1366
e4e72fb4
JB
1367 /* queue refcounts */
1368#define IWL_MAX_HW_QUEUES 32
1369 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1370 /* for each AC */
1371 atomic_t queue_stop_count[4];
1372
5d08cd1d 1373 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1374 u8 is_open;
5d08cd1d
CH
1375
1376 u8 mac80211_registered;
5d08cd1d 1377
c8ac61cf
JB
1378 bool wowlan;
1379
af6b8ee3 1380 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1381 u8 *eeprom;
0848e297 1382 int nvm_device_type;
073d3f5f 1383 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1384
05c914fe 1385 enum nl80211_iftype iw_mode;
5d08cd1d 1386
5d08cd1d 1387 /* Last Rx'd beacon timestamp */
3109ece1 1388 u64 timestamp;
5d08cd1d 1389
0da0e5bf
JB
1390 struct {
1391 __le32 flag;
1392 struct statistics_general_common common;
1393 struct statistics_rx_non_phy rx_non_phy;
1394 struct statistics_rx_phy rx_ofdm;
1395 struct statistics_rx_ht_phy rx_ofdm_ht;
1396 struct statistics_rx_phy rx_cck;
1397 struct statistics_tx tx;
1398#ifdef CONFIG_IWLWIFI_DEBUGFS
1399 struct statistics_bt_activity bt_activity;
1400 __le32 num_bt_kills, accum_num_bt_kills;
1401#endif
1402 } statistics;
1403#ifdef CONFIG_IWLWIFI_DEBUGFS
1404 struct {
1405 struct statistics_general_common common;
1406 struct statistics_rx_non_phy rx_non_phy;
1407 struct statistics_rx_phy rx_ofdm;
1408 struct statistics_rx_ht_phy rx_ofdm_ht;
1409 struct statistics_rx_phy rx_cck;
1410 struct statistics_tx tx;
1411 struct statistics_bt_activity bt_activity;
1412 } accum_stats, delta_stats, max_delta_stats;
1413#endif
1414
898ed67b
WYG
1415 /* INT ICT Table */
1416 __le32 *ict_tbl;
1417 void *ict_tbl_vir;
1418 dma_addr_t ict_tbl_dma;
1419 dma_addr_t aligned_ict_tbl_dma;
1420 int ict_index;
1421 u32 inta;
1422 bool use_ict;
1423 /*
1424 * reporting the number of tids has AGG on. 0 means
1425 * no AGGREGATION
1426 */
1427 u8 agg_tids_count;
1428
1429 struct iwl_rx_phy_res last_phy_res;
1430 bool last_phy_res_valid;
1431
1432 struct completion firmware_loading_complete;
1433
1434 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1435 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1436
1437 /*
1438 * chain noise reset and gain commands are the
1439 * two extra calibration commands follows the standard
1440 * phy calibration commands
1441 */
1442 u8 phy_calib_chain_noise_reset_cmd;
1443 u8 phy_calib_chain_noise_gain_cmd;
1444
1445 /* counts reply_tx error */
1446 struct reply_tx_error_statistics reply_tx_stats;
1447 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
1448 /* notification wait support */
1449 struct list_head notif_waits;
1450 spinlock_t notif_wait_lock;
1451 wait_queue_head_t notif_waitq;
1452
1453 /* remain-on-channel offload support */
1454 struct ieee80211_channel *hw_roc_channel;
c6baf7fb 1455 struct delayed_work hw_roc_disable_work;
898ed67b
WYG
1456 enum nl80211_channel_type hw_roc_chantype;
1457 int hw_roc_duration;
1458 bool hw_roc_setup;
1459
22bf59a0 1460 /* bt coex */
f21dd005 1461 u8 bt_enable_flag;
da5dbb97 1462 u8 bt_status;
66e863a5 1463 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1464 bool bt_ch_announce;
bee008b7
WYG
1465 bool bt_full_concurrent;
1466 bool bt_ant_couple_ok;
fbba9410
WYG
1467 __le32 kill_ack_mask;
1468 __le32 kill_cts_mask;
1469 __le16 bt_valid;
22bf59a0
WYG
1470 u16 bt_on_thresh;
1471 u16 bt_duration;
1472 u16 dynamic_frag_thresh;
bee008b7 1473 u8 bt_ci_compliance;
9e4afc21 1474 struct work_struct bt_traffic_change_work;
207ecc5e
MV
1475 bool bt_enable_pspoll;
1476 struct iwl_rxon_context *cur_rssi_ctx;
1477 bool bt_is_sco;
9e4afc21 1478
5425e490 1479 struct iwl_hw_params hw_params;
4ddbb7d0 1480
40cefda9 1481 u32 inta_mask;
5d08cd1d 1482
5d08cd1d
CH
1483 struct workqueue_struct *workqueue;
1484
5d08cd1d 1485 struct work_struct restart;
5d08cd1d
CH
1486 struct work_struct scan_completed;
1487 struct work_struct rx_replenish;
5d08cd1d 1488 struct work_struct abort_scan;
12e934dc 1489
5d08cd1d 1490 struct work_struct beacon_update;
76d04815 1491 struct iwl_rxon_context *beacon_ctx;
12e934dc 1492 struct sk_buff *beacon_skb;
4ce7cc2b 1493 void *beacon_cmd;
76d04815 1494
a28027cd
WYG
1495 struct work_struct tt_work;
1496 struct work_struct ct_enter;
1497 struct work_struct ct_exit;
88be0264 1498 struct work_struct start_internal_scan;
65550636 1499 struct work_struct tx_flush;
bee008b7 1500 struct work_struct bt_full_concurrency;
fbba9410 1501 struct work_struct bt_runtime_config;
5d08cd1d
CH
1502
1503 struct tasklet_struct irq_tasklet;
1504
5d08cd1d 1505 struct delayed_work scan_check;
4a8a4322 1506
630fe9b6
TW
1507 /* TX Power */
1508 s8 tx_power_user_lmt;
dc1b0973 1509 s8 tx_power_device_lmt;
ae16fc3c 1510 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1511 s8 tx_power_next;
5d08cd1d 1512
5d08cd1d 1513
d08853a3 1514#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1515 /* debugging info */
3d816c77 1516 u32 debug_level; /* per device debugging will override global
48f20d35 1517 iwlagn_mod_params.debug_level if set */
d73e4923 1518#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1519#ifdef CONFIG_IWLWIFI_DEBUGFS
1520 /* debugfs */
20594eb0
WYG
1521 u16 tx_traffic_idx;
1522 u16 rx_traffic_idx;
1523 u8 *tx_traffic;
1524 u8 *rx_traffic;
4c84a8f1
JB
1525 struct dentry *debugfs_dir;
1526 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1527 bool disable_ht40;
c8ac61cf 1528 void *wowlan_sram;
712b6cf5 1529#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1530
1531 struct work_struct txpower_work;
445c2dff
TW
1532 u32 disable_sens_cal;
1533 u32 disable_chain_noise_cal;
16e727e8 1534 struct work_struct run_time_calib_work;
5d08cd1d 1535 struct timer_list statistics_periodic;
a9e1cb6a 1536 struct timer_list ucode_trace;
22de94de 1537 struct timer_list watchdog;
a9e1cb6a
WYG
1538
1539 struct iwl_event_log event_log;
5ed540ae
WYG
1540
1541 struct led_classdev led;
1542 unsigned long blink_on, blink_off;
1543 bool led_registered;
7a4e5281
WYG
1544#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1545 struct iwl_testmode_trace testmode_trace;
4e308119 1546 u32 tm_fixed_rate;
c10e2c10 1547#endif
6489854b 1548
c8ac61cf
JB
1549 /* WoWLAN GTK rekey data */
1550 u8 kck[NL80211_KCK_LEN], kek[NL80211_KEK_LEN];
1551 __le64 replay_ctr;
1552 __le16 last_seq_ctl;
1553 bool have_rekey_data;
c79dd5b5 1554}; /*iwl_priv */
5d08cd1d 1555
36470749
RR
1556static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1557{
1558 set_bit(txq_id, &priv->txq_ctx_active_msk);
1559}
1560
1561static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1562{
1563 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1564}
1565
48f20d35
EG
1566extern struct iwl_mod_params iwlagn_mod_params;
1567
994d31f7 1568#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1569/*
1570 * iwl_get_debug_level: Return active debug level for device
1571 *
1572 * Using sysfs it is possible to set per device debug level. This debug
1573 * level will be used if set, otherwise the global debug level which can be
1574 * set via module parameter is used.
1575 */
1576static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1577{
1578 if (priv->debug_level)
1579 return priv->debug_level;
1580 else
48f20d35 1581 return iwlagn_mod_params.debug_level;
3d816c77 1582}
a332f8d6 1583#else
3d816c77
RC
1584static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1585{
48f20d35 1586 return iwlagn_mod_params.debug_level;
3d816c77 1587}
a332f8d6
TW
1588#endif
1589
1590
a332f8d6
TW
1591static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1592 int txq_id, int idx)
1593{
ff0d91c3 1594 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1595 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1596 txb[idx].skb->data;
a332f8d6
TW
1597 return NULL;
1598}
a332f8d6 1599
246ed355
JB
1600static inline struct iwl_rxon_context *
1601iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1602{
1603 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1604
1605 return vif_priv->ctx;
1606}
1607
1608#define for_each_context(priv, ctx) \
1609 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1610 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1611 if (priv->valid_contexts & BIT(ctx->ctxid))
1612
054ec924 1613static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
246ed355 1614{
054ec924 1615 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
246ed355
JB
1616}
1617
054ec924
JB
1618static inline int iwl_is_associated(struct iwl_priv *priv,
1619 enum iwl_rxon_context_id ctxid)
246ed355 1620{
054ec924 1621 return iwl_is_associated_ctx(&priv->contexts[ctxid]);
246ed355 1622}
a332f8d6 1623
054ec924 1624static inline int iwl_is_any_associated(struct iwl_priv *priv)
5d08cd1d 1625{
054ec924
JB
1626 struct iwl_rxon_context *ctx;
1627 for_each_context(priv, ctx)
1628 if (iwl_is_associated_ctx(ctx))
1629 return true;
1630 return false;
5d08cd1d
CH
1631}
1632
bf85ea4f 1633static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1634{
1635 if (ch_info == NULL)
1636 return 0;
1637 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1638}
1639
bf85ea4f 1640static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1641{
1642 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1643}
1644
bf85ea4f 1645static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1646{
8318d78a 1647 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1648}
1649
bf85ea4f 1650static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1651{
8318d78a 1652 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1653}
1654
bf85ea4f 1655static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1656{
1657 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1658}
1659
bf85ea4f 1660static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1661{
1662 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1663}
1664
64a76b50
ZY
1665static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1666{
1667 __free_pages(page, priv->hw_params.rx_page_order);
64a76b50
ZY
1668}
1669
1670static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1671{
1672 free_pages(page, priv->hw_params.rx_page_order);
64a76b50 1673}
be1f3ab6 1674#endif /* __iwl_dev_h__ */
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