iwl3945: cleanup number of queues settings
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
46#include "iwl-3945-led.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
5d08cd1d 50
fed9017e
RR
51/* configuration for the iwl4965 */
52extern struct iwl_cfg iwl4965_agn_cfg;
5a6a256e
TW
53extern struct iwl_cfg iwl5300_agn_cfg;
54extern struct iwl_cfg iwl5100_agn_cfg;
55extern struct iwl_cfg iwl5350_agn_cfg;
47408639
EK
56extern struct iwl_cfg iwl5100_bg_cfg;
57extern struct iwl_cfg iwl5100_abg_cfg;
7100e924 58extern struct iwl_cfg iwl5150_agn_cfg;
e1228374
JS
59extern struct iwl_cfg iwl6000_2ag_cfg;
60extern struct iwl_cfg iwl6000_2agn_cfg;
61extern struct iwl_cfg iwl6000_3agn_cfg;
62extern struct iwl_cfg iwl6050_2agn_cfg;
63extern struct iwl_cfg iwl6050_3agn_cfg;
77dcb6a9 64extern struct iwl_cfg iwl1000_bgn_cfg;
fed9017e 65
cec2d3f3
JS
66/* shared structures from iwl-5000.c */
67extern struct iwl_mod_params iwl50_mod_params;
68extern struct iwl_ops iwl5000_ops;
e8c00dcb
JS
69extern struct iwl_lib_ops iwl5000_lib;
70extern struct iwl_hcmd_ops iwl5000_hcmd;
71extern struct iwl_hcmd_utils_ops iwl5000_hcmd_utils;
72
73/* shared functions from iwl-5000.c */
74extern u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len);
75extern u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd,
76 u8 *data);
77extern void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
78 __le32 *tx_flags);
79extern int iwl5000_calc_rssi(struct iwl_priv *priv,
80 struct iwl_rx_phy_res *rx_resp);
cec2d3f3 81
099b40b7
RR
82/* CT-KILL constants */
83#define CT_KILL_THRESHOLD 110 /* in Celsius */
4bf775cd 84
5d08cd1d
CH
85/* Default noise level to report when noise measurement is not available.
86 * This may be because we're:
87 * 1) Not associated (4965, no beacon statistics being sent to driver)
88 * 2) Scanning (noise measurement does not apply to associated channel)
89 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
90 * Use default noise value of -127 ... this is below the range of measurable
91 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
92 * Also, -127 works better than 0 when averaging frames with/without
93 * noise info (e.g. averaging might be done in app); measured dBm values are
94 * always negative ... using a negative value as the default keeps all
95 * averages within an s8's (used in some apps) range of negative values. */
96#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
97
5d08cd1d
CH
98/*
99 * RTS threshold here is total size [2347] minus 4 FCS bytes
100 * Per spec:
101 * a value of 0 means RTS on all data/management packets
102 * a value > max MSDU size means no RTS
103 * else RTS for data/management frames where MPDU is larger
104 * than RTS value.
105 */
106#define DEFAULT_RTS_THRESHOLD 2347U
107#define MIN_RTS_THRESHOLD 0U
108#define MAX_RTS_THRESHOLD 2347U
109#define MAX_MSDU_SIZE 2304U
110#define MAX_MPDU_SIZE 2346U
111#define DEFAULT_BEACON_INTERVAL 100U
112#define DEFAULT_SHORT_RETRY_LIMIT 7U
113#define DEFAULT_LONG_RETRY_LIMIT 4U
114
a55360e4 115struct iwl_rx_mem_buffer {
4018517a
JB
116 dma_addr_t real_dma_addr;
117 dma_addr_t aligned_dma_addr;
5d08cd1d
CH
118 struct sk_buff *skb;
119 struct list_head list;
120};
121
5d08cd1d
CH
122/*
123 * Generic queue structure
124 *
125 * Contains common data for Rx and Tx queues
126 */
443cfd45 127struct iwl_queue {
5d08cd1d
CH
128 int n_bd; /* number of BDs in this queue */
129 int write_ptr; /* 1-st empty entry (index) host_w*/
130 int read_ptr; /* last used entry (index) host_r*/
131 dma_addr_t dma_addr; /* physical addr for BD's */
132 int n_window; /* safe queue window */
133 u32 id;
134 int low_mark; /* low watermark, resume queue if free
135 * space more than this */
136 int high_mark; /* high watermark, stop queue if free
137 * space less than this */
138} __attribute__ ((packed));
139
bc47279f 140/* One for each TFD */
8567c63e 141struct iwl_tx_info {
499b1883 142 struct sk_buff *skb[IWL_NUM_OF_TBS - 1];
5d08cd1d
CH
143};
144
145/**
16466903 146 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
147 * @q: generic Rx/Tx queue descriptor
148 * @bd: base of circular buffer of TFDs
149 * @cmd: array of command/Tx buffers
150 * @dma_addr_cmd: physical address of cmd/tx buffer array
151 * @txb: array of per-TFD driver data
152 * @need_update: indicates need to update read/write index
153 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 154 *
bc47279f
BC
155 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
156 * descriptors) and required locking structures.
5d08cd1d 157 */
188cf6c7
SO
158#define TFD_TX_CMD_SLOTS 256
159#define TFD_CMD_SLOTS 32
160
16466903 161struct iwl_tx_queue {
443cfd45 162 struct iwl_queue q;
59606ffa 163 void *tfds;
da99c4b6 164 struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS];
8567c63e 165 struct iwl_tx_info *txb;
3fd07a1e
TW
166 u8 need_update;
167 u8 sched_retry;
168 u8 active;
169 u8 swq_id;
5d08cd1d
CH
170};
171
172#define IWL_NUM_SCAN_RATES (2)
173
bb8c093b 174struct iwl4965_channel_tgd_info {
5d08cd1d
CH
175 u8 type;
176 s8 max_power;
177};
178
bb8c093b 179struct iwl4965_channel_tgh_info {
5d08cd1d
CH
180 s64 last_radar_time;
181};
182
d20b3c65
SO
183#define IWL4965_MAX_RATE (33)
184
85d41495
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185struct iwl3945_clip_group {
186 /* maximum power level to prevent clipping for each rate, derived by
187 * us from this band's saturation power in EEPROM */
188 const s8 clip_powers[IWL_MAX_RATES];
189};
190
d20b3c65
SO
191/* current Tx power values to use, one for each rate for each channel.
192 * requested power is limited by:
193 * -- regulatory EEPROM limits for this channel
194 * -- hardware capabilities (clip-powers)
195 * -- spectrum management
196 * -- user preference (e.g. iwconfig)
197 * when requested power is set, base power index must also be set. */
198struct iwl3945_channel_power_info {
199 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
200 s8 power_table_index; /* actual (compenst'd) index into gain table */
201 s8 base_power_index; /* gain index for power at factory temp. */
202 s8 requested_power; /* power (dBm) requested for this chnl/rate */
203};
204
205/* current scan Tx power values to use, one for each scan rate for each
206 * channel. */
207struct iwl3945_scan_power_info {
208 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
209 s8 power_table_index; /* actual (compenst'd) index into gain table */
210 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
211};
212
5d08cd1d
CH
213/*
214 * One for each channel, holds all channel setup data
215 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
216 * with one another!
217 */
bf85ea4f 218struct iwl_channel_info {
bb8c093b
CH
219 struct iwl4965_channel_tgd_info tgd;
220 struct iwl4965_channel_tgh_info tgh;
073d3f5f
TW
221 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
222 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
223 * FAT channel */
5d08cd1d
CH
224
225 u8 channel; /* channel number */
226 u8 flags; /* flags copied from EEPROM */
227 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 228 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
229 s8 min_power; /* always 0 */
230 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
231
232 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
233 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 234 enum ieee80211_band band;
5d08cd1d 235
5d08cd1d
CH
236 /* FAT channel info */
237 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
238 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
239 s8 fat_min_power; /* always 0 */
240 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */
241 u8 fat_flags; /* flags copied from EEPROM */
fcd427bb 242 u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
243
244 /* Radio/DSP gain settings for each "normal" data Tx rate.
245 * These include, in addition to RF and DSP gain, a few fields for
246 * remembering/modifying gain settings (indexes). */
247 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
248
249 /* Radio/DSP gain settings for each scan rate, for directed scans. */
250 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
251};
252
5d08cd1d
CH
253#define IWL_TX_FIFO_AC0 0
254#define IWL_TX_FIFO_AC1 1
255#define IWL_TX_FIFO_AC2 2
256#define IWL_TX_FIFO_AC3 3
257#define IWL_TX_FIFO_HCCA_1 5
258#define IWL_TX_FIFO_HCCA_2 6
259#define IWL_TX_FIFO_NONE 7
260
261/* Minimum number of queues. MAX_NUM is defined in hw specific files */
262#define IWL_MIN_NUM_QUEUES 4
263
264/* Power management (not Tx power) structures */
265
6f4083aa
TW
266enum iwl_pwr_src {
267 IWL_PWR_SRC_VMAIN,
268 IWL_PWR_SRC_VAUX,
269};
270
5d08cd1d
CH
271#define IEEE80211_DATA_LEN 2304
272#define IEEE80211_4ADDR_LEN 30
273#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
274#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
275
fcab423d 276struct iwl_frame {
5d08cd1d
CH
277 union {
278 struct ieee80211_hdr frame;
4bf64efd 279 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
280 u8 raw[IEEE80211_FRAME_LEN];
281 u8 cmd[360];
282 } u;
283 struct list_head list;
284};
285
5d08cd1d
CH
286#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
287#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
288#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
289
290enum {
c587de0b
TW
291 CMD_SYNC = 0,
292 CMD_SIZE_NORMAL = 0,
293 CMD_NO_SKB = 0,
5d08cd1d 294 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 295 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
296 CMD_WANT_SKB = (1 << 2),
297};
298
857485c0 299struct iwl_cmd;
c79dd5b5 300struct iwl_priv;
5d08cd1d 301
857485c0
TW
302struct iwl_cmd_meta {
303 struct iwl_cmd_meta *source;
5d08cd1d
CH
304 union {
305 struct sk_buff *skb;
c79dd5b5 306 int (*callback)(struct iwl_priv *priv,
857485c0 307 struct iwl_cmd *cmd, struct sk_buff *skb);
5d08cd1d
CH
308 } __attribute__ ((packed)) u;
309
310 /* The CMD_SIZE_HUGE flag bit indicates that the command
311 * structure is stored at the end of the shared queue memory. */
312 u32 flags;
499b1883
TW
313 DECLARE_PCI_UNMAP_ADDR(mapping)
314 DECLARE_PCI_UNMAP_LEN(len)
5d08cd1d
CH
315} __attribute__ ((packed));
316
d2f18bfd 317#define IWL_CMD_MAX_PAYLOAD 320
bd68fb6f 318
bc47279f 319/**
857485c0 320 * struct iwl_cmd
bc47279f
BC
321 *
322 * For allocation of the command and tx queues, this establishes the overall
323 * size of the largest command we send to uCode, except for a scan command
324 * (which is relatively huge; space is allocated separately).
325 */
857485c0
TW
326struct iwl_cmd {
327 struct iwl_cmd_meta meta; /* driver data */
328 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 329 union {
5d08cd1d
CH
330 u32 flags;
331 u8 val8;
332 u16 val16;
333 u32 val32;
83d527d9 334 struct iwl_tx_cmd tx;
bd68fb6f 335 u8 payload[IWL_CMD_MAX_PAYLOAD];
5d08cd1d
CH
336 } __attribute__ ((packed)) cmd;
337} __attribute__ ((packed));
338
3257e5d4 339
857485c0 340struct iwl_host_cmd {
5d08cd1d
CH
341 u8 id;
342 u16 len;
857485c0 343 struct iwl_cmd_meta meta;
5d08cd1d
CH
344 const void *data;
345};
346
857485c0
TW
347#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
348 sizeof(struct iwl_cmd_meta))
5d08cd1d
CH
349
350/*
351 * RX related structures and functions
352 */
353#define RX_FREE_BUFFERS 64
354#define RX_LOW_WATERMARK 8
355
356#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
357#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
358#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
359
360/**
a55360e4 361 * struct iwl_rx_queue - Rx queue
df833b1d
RC
362 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
363 * @dma_addr: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
364 * @read: Shared index to newest available Rx buffer
365 * @write: Shared index to oldest written Rx packet
366 * @free_count: Number of pre-allocated buffers in rx_free
367 * @rx_free: list of free SKBs for use
368 * @rx_used: List of Rx buffers with no SKB
369 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
370 * @rb_stts: driver's pointer to receive buffer status
371 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 372 *
a55360e4 373 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 374 */
a55360e4 375struct iwl_rx_queue {
5d08cd1d
CH
376 __le32 *bd;
377 dma_addr_t dma_addr;
a55360e4
TW
378 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
379 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
380 u32 read;
381 u32 write;
382 u32 free_count;
4752c93c 383 u32 write_actual;
5d08cd1d
CH
384 struct list_head rx_free;
385 struct list_head rx_used;
386 int need_update;
8d86422a
WT
387 struct iwl_rb_status *rb_stts;
388 dma_addr_t rb_stts_dma;
5d08cd1d
CH
389 spinlock_t lock;
390};
391
392#define IWL_SUPPORTED_RATES_IE_LEN 8
393
5d08cd1d
CH
394#define MAX_TID_COUNT 9
395
396#define IWL_INVALID_RATE 0xFF
397#define IWL_INVALID_VALUE -1
398
bc47279f 399/**
6def9761 400 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
401 * @txq_id: Tx queue used for Tx attempt
402 * @frame_count: # frames attempted by Tx command
403 * @wait_for_ba: Expect block-ack before next Tx reply
404 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
405 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
406 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
407 * @rate_n_flags: Rate at which Tx was attempted
408 *
409 * If REPLY_TX indicates that aggregation was attempted, driver must wait
410 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
411 * until block ack arrives.
412 */
6def9761 413struct iwl_ht_agg {
5d08cd1d
CH
414 u16 txq_id;
415 u16 frame_count;
416 u16 wait_for_ba;
417 u16 start_idx;
fe01b477 418 u64 bitmap;
5d08cd1d 419 u32 rate_n_flags;
fe01b477
RR
420#define IWL_AGG_OFF 0
421#define IWL_AGG_ON 1
422#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
423#define IWL_EMPTYING_HW_QUEUE_DELBA 3
424 u8 state;
5d08cd1d 425};
fe01b477 426
5d08cd1d 427
6def9761 428struct iwl_tid_data {
5d08cd1d 429 u16 seq_number;
fe01b477 430 u16 tfds_in_queue;
6def9761 431 struct iwl_ht_agg agg;
5d08cd1d
CH
432};
433
6def9761 434struct iwl_hw_key {
5d08cd1d
CH
435 enum ieee80211_key_alg alg;
436 int keylen;
0211ddda 437 u8 keyidx;
5d08cd1d
CH
438 u8 key[32];
439};
440
a78fe754 441union iwl_ht_rate_supp {
5d08cd1d
CH
442 u16 rates;
443 struct {
444 u8 siso_rate;
445 u8 mimo_rate;
446 };
447};
448
5d08cd1d 449#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
5d08cd1d
CH
450#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
451#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
452
9e0cc6de
RR
453struct iwl_ht_info {
454 /* self configuration data */
5d08cd1d 455 u8 is_ht;
9e0cc6de 456 u8 supported_chan_width;
12837be1 457 u8 sm_ps;
9e0cc6de 458 u8 is_green_field;
bb54244b 459 u8 sgf; /* HT_SHORT_GI_* short guard interval */
5d08cd1d
CH
460 u8 max_amsdu_size;
461 u8 ampdu_factor;
462 u8 mpdu_density;
d9fe60de 463 struct ieee80211_mcs_info mcs;
9e0cc6de 464 /* BSS related data */
5d08cd1d 465 u8 extension_chan_offset;
5d08cd1d 466 u8 tx_chan_width;
9e0cc6de
RR
467 u8 ht_protection;
468 u8 non_GF_STA_present;
5d08cd1d 469};
5d08cd1d 470
1ff50bda 471union iwl_qos_capabity {
5d08cd1d
CH
472 struct {
473 u8 edca_count:4; /* bit 0-3 */
474 u8 q_ack:1; /* bit 4 */
475 u8 queue_request:1; /* bit 5 */
476 u8 txop_request:1; /* bit 6 */
477 u8 reserved:1; /* bit 7 */
478 } q_AP;
479 struct {
480 u8 acvo_APSD:1; /* bit 0 */
481 u8 acvi_APSD:1; /* bit 1 */
482 u8 ac_bk_APSD:1; /* bit 2 */
483 u8 ac_be_APSD:1; /* bit 3 */
484 u8 q_ack:1; /* bit 4 */
485 u8 max_len:2; /* bit 5-6 */
486 u8 more_data_ack:1; /* bit 7 */
487 } q_STA;
488 u8 val;
489};
490
491/* QoS structures */
1ff50bda 492struct iwl_qos_info {
5d08cd1d 493 int qos_active;
1ff50bda
EG
494 union iwl_qos_capabity qos_cap;
495 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 496};
5d08cd1d
CH
497
498#define STA_PS_STATUS_WAKE 0
499#define STA_PS_STATUS_SLEEP 1
500
85d41495
KA
501
502struct iwl3945_station_entry {
503 struct iwl3945_addsta_cmd sta;
c15ff610 504 struct iwl_tid_data tid[MAX_TID_COUNT];
85d41495
KA
505 u8 used;
506 u8 ps_status;
bed420d9 507 struct iwl_hw_key keyinfo;
85d41495
KA
508};
509
6def9761 510struct iwl_station_entry {
133636de 511 struct iwl_addsta_cmd sta;
6def9761 512 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d
CH
513 u8 used;
514 u8 ps_status;
6def9761 515 struct iwl_hw_key keyinfo;
5d08cd1d
CH
516};
517
518/* one for each uCode image (inst/data, boot/init/runtime) */
519struct fw_desc {
520 void *v_addr; /* access by driver */
521 dma_addr_t p_addr; /* access by card's busmaster DMA */
522 u32 len; /* bytes */
523};
524
525/* uCode file layout */
14b3d338 526struct iwl_ucode {
c02b3acd 527 __le32 ver; /* major/minor/API/serial */
5d08cd1d
CH
528 __le32 inst_size; /* bytes of runtime instructions */
529 __le32 data_size; /* bytes of runtime data */
530 __le32 init_size; /* bytes of initialization instructions */
531 __le32 init_data_size; /* bytes of initialization data */
532 __le32 boot_size; /* bytes of bootstrap instructions */
533 u8 data[0]; /* data in same order as "size" elements */
534};
535
bb8c093b 536struct iwl4965_ibss_seq {
5d08cd1d
CH
537 u8 mac[ETH_ALEN];
538 u16 seq_num;
539 u16 frag_num;
540 unsigned long packet_time;
541 struct list_head list;
542};
543
f0832f13
EG
544struct iwl_sensitivity_ranges {
545 u16 min_nrg_cck;
546 u16 max_nrg_cck;
547
548 u16 nrg_th_cck;
549 u16 nrg_th_ofdm;
550
551 u16 auto_corr_min_ofdm;
552 u16 auto_corr_min_ofdm_mrc;
553 u16 auto_corr_min_ofdm_x1;
554 u16 auto_corr_min_ofdm_mrc_x1;
555
556 u16 auto_corr_max_ofdm;
557 u16 auto_corr_max_ofdm_mrc;
558 u16 auto_corr_max_ofdm_x1;
559 u16 auto_corr_max_ofdm_mrc_x1;
560
561 u16 auto_corr_max_cck;
562 u16 auto_corr_max_cck_mrc;
563 u16 auto_corr_min_cck;
564 u16 auto_corr_min_cck_mrc;
565};
566
099b40b7 567
b5047f78
TW
568#define KELVIN_TO_CELSIUS(x) ((x)-273)
569#define CELSIUS_TO_KELVIN(x) ((x)+273)
570
571
bc47279f 572/**
5425e490 573 * struct iwl_hw_params
bc47279f 574 * @max_txq_num: Max # Tx queues supported
f3f911d1 575 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 576 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 577 * @tfd_size: TFD size
099b40b7
RR
578 * @tx/rx_chains_num: Number of TX/RX chains
579 * @valid_tx/rx_ant: usable antennas
bc47279f 580 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 581 * @max_rxq_log: Log-base-2 of max_rxq_size
099b40b7 582 * @rx_buf_size: Rx buffer size
141c43a3 583 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
584 * @max_stations:
585 * @bcast_sta_id:
099b40b7
RR
586 * @fat_channel: is 40MHz width possible in band 2.4
587 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
588 * @sw_crypto: 0 for hw, 1 for sw
589 * @max_xxx_size: for ucode uses
590 * @ct_kill_threshold: temperature threshold
a96a27f9 591 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 592 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 593 */
5425e490 594struct iwl_hw_params {
f3f911d1
ZY
595 u8 max_txq_num;
596 u8 dma_chnl_num;
4ddbb7d0 597 u16 scd_bc_tbls_size;
a8e74e27 598 u32 tfd_size;
ec35cf2a
TW
599 u8 tx_chains_num;
600 u8 rx_chains_num;
601 u8 valid_tx_ant;
602 u8 valid_rx_ant;
5d08cd1d 603 u16 max_rxq_size;
ec35cf2a 604 u16 max_rxq_log;
9ee1ba47 605 u32 rx_buf_size;
141c43a3 606 u32 rx_wrt_ptr_reg;
9ee1ba47 607 u32 max_pkt_size;
5d08cd1d
CH
608 u8 max_stations;
609 u8 bcast_sta_id;
099b40b7 610 u8 fat_channel;
2c2f3b33 611 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
612 u32 max_inst_size;
613 u32 max_data_size;
614 u32 max_bsm_size;
615 u32 ct_kill_threshold; /* value in hw-dependent units */
be5d56ed 616 u32 calib_init_cfg;
f0832f13 617 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
618};
619
5d08cd1d 620
5d08cd1d
CH
621/******************************************************************************
622 *
a33c2f47
EG
623 * Functions implemented in core module which are forward declared here
624 * for use by iwl-[4-5].c
5d08cd1d 625 *
a33c2f47
EG
626 * NOTE: The implementation of these functions are not hardware specific
627 * which is why they are in the core module files.
5d08cd1d
CH
628 *
629 * Naming convention --
a33c2f47 630 * iwl_ <-- Is part of iwlwifi
5d08cd1d 631 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
632 * iwl4965_bg_ <-- Called from work queue context
633 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
634 *
635 ****************************************************************************/
5b9f8cd3
EG
636extern void iwl_update_chain_flags(struct iwl_priv *priv);
637extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 638extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 639extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 640extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 641extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
642static inline int iwl_queue_used(const struct iwl_queue *q, int i)
643{
644 return q->write_ptr > q->read_ptr ?
645 (i >= q->read_ptr && i < q->write_ptr) :
646 !(i < q->read_ptr && i >= q->write_ptr);
647}
648
649
650static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
651{
652 /* This is for scan command, the big buffer at end of command array */
653 if (is_huge)
654 return q->n_window; /* must be power of 2 */
655
656 /* Otherwise, use normal size buffers */
657 return index & (q->n_window - 1);
658}
659
660
4ddbb7d0
TW
661struct iwl_dma_ptr {
662 dma_addr_t dma;
663 void *addr;
b481de9c
ZY
664 size_t size;
665};
666
34c22cf9
WT
667#define HT_SHORT_GI_20MHZ (1 << 0)
668#define HT_SHORT_GI_40MHZ (1 << 1)
669
b481de9c
ZY
670#define IWL_CHANNEL_WIDTH_20MHZ 0
671#define IWL_CHANNEL_WIDTH_40MHZ 1
672
b481de9c
ZY
673#define IWL_OPERATION_MODE_AUTO 0
674#define IWL_OPERATION_MODE_HT_ONLY 1
675#define IWL_OPERATION_MODE_MIXED 2
676#define IWL_OPERATION_MODE_20MHZ 3
677
3195cdb7
TW
678#define IWL_TX_CRC_SIZE 4
679#define IWL_TX_DELIMITER_SIZE 4
b481de9c 680
b481de9c 681#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 682
b481de9c 683/* Sensitivity and chain noise calibration */
b481de9c
ZY
684#define INITIALIZATION_VALUE 0xFFFF
685#define CAL_NUM_OF_BEACONS 20
686#define MAXIMUM_ALLOWED_PATHLOSS 15
687
b481de9c
ZY
688#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
689
690#define MAX_FA_OFDM 50
691#define MIN_FA_OFDM 5
692#define MAX_FA_CCK 50
693#define MIN_FA_CCK 5
694
b481de9c
ZY
695#define AUTO_CORR_STEP_OFDM 1
696
b481de9c
ZY
697#define AUTO_CORR_STEP_CCK 3
698#define AUTO_CORR_MAX_TH_CCK 160
699
b481de9c
ZY
700#define NRG_DIFF 2
701#define NRG_STEP_CCK 2
702#define NRG_MARGIN 8
703#define MAX_NUMBER_CCK_NO_FA 100
704
705#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
706
707#define CHAIN_A 0
708#define CHAIN_B 1
709#define CHAIN_C 2
710#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
711#define ALL_BAND_FILTER 0xFF00
712#define IN_BAND_FILTER 0xFF
713#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
714
3195cdb7
TW
715#define NRG_NUM_PREV_STAT_L 20
716#define NUM_RX_CHAINS 3
717
bb8c093b 718enum iwl4965_false_alarm_state {
b481de9c
ZY
719 IWL_FA_TOO_MANY = 0,
720 IWL_FA_TOO_FEW = 1,
721 IWL_FA_GOOD_RANGE = 2,
722};
723
bb8c093b 724enum iwl4965_chain_noise_state {
b481de9c 725 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
726 IWL_CHAIN_NOISE_ACCUMULATE,
727 IWL_CHAIN_NOISE_CALIBRATED,
728 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
729};
730
bb8c093b 731enum iwl4965_calib_enabled_state {
b481de9c
ZY
732 IWL_CALIB_DISABLED = 0, /* must be 0 */
733 IWL_CALIB_ENABLED = 1,
734};
735
f69f42a6
TW
736
737/*
738 * enum iwl_calib
739 * defines the order in which results of initial calibrations
740 * should be sent to the runtime uCode
741 */
742enum iwl_calib {
743 IWL_CALIB_XTAL,
819500c5 744 IWL_CALIB_DC,
f69f42a6
TW
745 IWL_CALIB_LO,
746 IWL_CALIB_TX_IQ,
747 IWL_CALIB_TX_IQ_PERD,
201706ac 748 IWL_CALIB_BASE_BAND,
f69f42a6
TW
749 IWL_CALIB_MAX
750};
751
6e21f2c1
TW
752/* Opaque calibration results */
753struct iwl_calib_result {
754 void *buf;
755 size_t buf_len;
7c616cba
TW
756};
757
dbb983b7
RR
758enum ucode_type {
759 UCODE_NONE = 0,
760 UCODE_INIT,
761 UCODE_RT
762};
763
b481de9c 764/* Sensitivity calib data */
f0832f13 765struct iwl_sensitivity_data {
b481de9c
ZY
766 u32 auto_corr_ofdm;
767 u32 auto_corr_ofdm_mrc;
768 u32 auto_corr_ofdm_x1;
769 u32 auto_corr_ofdm_mrc_x1;
770 u32 auto_corr_cck;
771 u32 auto_corr_cck_mrc;
772
773 u32 last_bad_plcp_cnt_ofdm;
774 u32 last_fa_cnt_ofdm;
775 u32 last_bad_plcp_cnt_cck;
776 u32 last_fa_cnt_cck;
777
778 u32 nrg_curr_state;
779 u32 nrg_prev_state;
780 u32 nrg_value[10];
781 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
782 u32 nrg_silence_ref;
783 u32 nrg_energy_idx;
784 u32 nrg_silence_idx;
785 u32 nrg_th_cck;
786 s32 nrg_auto_corr_silence_diff;
787 u32 num_in_cck_no_fa;
788 u32 nrg_th_ofdm;
b481de9c
ZY
789};
790
791/* Chain noise (differential Rx gain) calib data */
f0832f13 792struct iwl_chain_noise_data {
04816448 793 u32 active_chains;
b481de9c
ZY
794 u32 chain_noise_a;
795 u32 chain_noise_b;
796 u32 chain_noise_c;
797 u32 chain_signal_a;
798 u32 chain_signal_b;
799 u32 chain_signal_c;
04816448 800 u16 beacon_count;
b481de9c
ZY
801 u8 disconn_array[NUM_RX_CHAINS];
802 u8 delta_gain_code[NUM_RX_CHAINS];
803 u8 radio_write;
04816448 804 u8 state;
b481de9c
ZY
805};
806
abceddb4
BC
807#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
808#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 809
5d08cd1d 810
5d08cd1d
CH
811enum {
812 MEASUREMENT_READY = (1 << 0),
813 MEASUREMENT_ACTIVE = (1 << 1),
814};
815
0848e297
WYG
816enum iwl_nvm_type {
817 NVM_DEVICE_TYPE_EEPROM = 0,
818 NVM_DEVICE_TYPE_OTP,
819};
820
a83b9141
WYG
821/* interrupt statistics */
822struct isr_statistics {
823 u32 hw;
824 u32 sw;
825 u32 sw_err;
826 u32 sch;
827 u32 alive;
828 u32 rfkill;
829 u32 ctkill;
830 u32 wakeup;
831 u32 rx;
832 u32 rx_handlers[REPLY_MAX];
833 u32 tx;
834 u32 unhandled;
835};
5d08cd1d 836
dfe7d458
RR
837#define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */
838
c79dd5b5 839struct iwl_priv {
5d08cd1d
CH
840
841 /* ieee device used by generic ieee processing code */
842 struct ieee80211_hw *hw;
843 struct ieee80211_channel *ieee_channels;
844 struct ieee80211_rate *ieee_rates;
82b9a121 845 struct iwl_cfg *cfg;
5d08cd1d
CH
846
847 /* temporary frame storage list */
848 struct list_head free_frames;
849 int frames_count;
850
8318d78a 851 enum ieee80211_band band;
5d08cd1d
CH
852 int alloc_rxb_skb;
853
c79dd5b5 854 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 855 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 856
8318d78a 857 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 858
80bc5393 859#if defined(CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT) || defined(CONFIG_IWL3945_SPECTRUM_MEASUREMENT)
5d08cd1d 860 /* spectrum measurement report caching */
2aa6ab86 861 struct iwl_spectrum_notification measure_report;
5d08cd1d
CH
862 u8 measurement_status;
863#endif
864 /* ucode beacon time */
865 u32 ucode_beacon_time;
866
bb8c093b 867 /* we allocate array of iwl4965_channel_info for NIC's valid channels.
5d08cd1d 868 * Access via channel # using indirect index array */
bf85ea4f 869 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
870 u8 channel_count; /* # of channels */
871
85d41495
KA
872 /* each calibration channel group in the EEPROM has a derived
873 * clip setting for each rate. 3945 only.*/
874 const struct iwl3945_clip_group clip39_groups[5];
875
5d08cd1d
CH
876 /* thermal calibration */
877 s32 temperature; /* degrees Kelvin */
878 s32 last_temperature;
879
7c616cba 880 /* init calibration results */
6e21f2c1 881 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 882
5d08cd1d
CH
883 /* Scan related variables */
884 unsigned long last_scan_jiffies;
7878a5a4 885 unsigned long next_scan_jiffies;
5d08cd1d
CH
886 unsigned long scan_start;
887 unsigned long scan_pass_start;
888 unsigned long scan_start_tsf;
805cee5b 889 void *scan;
5d08cd1d 890 int scan_bands;
1ecf9fc1 891 struct cfg80211_scan_request *scan_request;
76eff18b
TW
892 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
893 u8 mgmt_tx_ant;
5d08cd1d
CH
894
895 /* spinlock */
896 spinlock_t lock; /* protect general shared data */
897 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 898 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d
CH
899 struct mutex mutex;
900
901 /* basic pci-network driver stuff */
902 struct pci_dev *pci_dev;
903
904 /* pci hardware address support */
905 void __iomem *hw_base;
b661c819
TW
906 u32 hw_rev;
907 u32 hw_wa_rev;
908 u8 rev_id;
5d08cd1d
CH
909
910 /* uCode images, save to reload in case of failure */
c02b3acd
CR
911 u32 ucode_ver; /* version of ucode, copy of
912 iwl_ucode.ver */
5d08cd1d
CH
913 struct fw_desc ucode_code; /* runtime inst */
914 struct fw_desc ucode_data; /* runtime data original */
915 struct fw_desc ucode_data_backup; /* runtime data save/restore */
916 struct fw_desc ucode_init; /* initialization inst */
917 struct fw_desc ucode_init_data; /* initialization data */
918 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
919 enum ucode_type ucode_type;
920 u8 ucode_write_complete; /* the image write is complete */
5d08cd1d
CH
921
922
3195c1f3 923 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
924
925 /* We declare this const so it can only be
926 * changed via explicit cast within the
927 * routines that actually update the physical
928 * hardware */
c1adf9fb
GG
929 const struct iwl_rxon_cmd active_rxon;
930 struct iwl_rxon_cmd staging_rxon;
5d08cd1d 931
c1adf9fb 932 struct iwl_rxon_cmd recovery_rxon;
5d08cd1d
CH
933
934 /* 1st responses from initialize and runtime uCode images.
935 * 4965's initialize alive response contains some calibration data. */
885ba202
TW
936 struct iwl_init_alive_resp card_alive_init;
937 struct iwl_alive_resp card_alive;
5d08cd1d 938
5c8df2d5 939#ifdef CONFIG_IWLWIFI_LEDS
ab53d8af
MA
940 unsigned long last_blink_time;
941 u8 last_blink_rate;
942 u8 allow_blinking;
943 u64 led_tpt;
4a8a4322 944 struct iwl_led led[IWL_LED_TRG_MAX];
4a8a4322
AK
945 unsigned int rxtxpackets;
946#endif
5d08cd1d
CH
947 u16 active_rate;
948 u16 active_rate_basic;
949
5d08cd1d 950 u8 assoc_station_added;
5d08cd1d 951 u8 start_calib;
f0832f13
EG
952 struct iwl_sensitivity_data sensitivity_data;
953 struct iwl_chain_noise_data chain_noise_data;
5d08cd1d 954 __le16 sensitivity_tbl[HD_TABLE_SIZE];
5d08cd1d 955
9e0cc6de 956 struct iwl_ht_info current_ht_config;
5d08cd1d
CH
957 u8 last_phy_res[100];
958
5d08cd1d
CH
959 /* Rate scaling data */
960 s8 data_retry_limit;
961 u8 retry_rate;
962
963 wait_queue_head_t wait_command_queue;
964
965 int activity_timer_active;
966
967 /* Rx and Tx DMA processing queues */
a55360e4 968 struct iwl_rx_queue rxq;
16466903 969 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
5d08cd1d 970 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
971 struct iwl_dma_ptr kw; /* keep warm address */
972 struct iwl_dma_ptr scd_bc_tbls;
973
5d08cd1d
CH
974 u32 scd_base_addr; /* scheduler sram base address */
975
976 unsigned long status;
5d08cd1d 977
a96a27f9 978 int last_rx_rssi; /* From Rx packet statistics */
5d08cd1d
CH
979 int last_rx_noise; /* From beacon statistics */
980
19758bef
TW
981 /* counts mgmt, ctl, and data packets */
982 struct traffic_stats {
983 u32 cnt;
984 u64 bytes;
985 } tx_stats[3], rx_stats[3];
986
a83b9141
WYG
987 /* counts interrupts */
988 struct isr_statistics isr_stats;
989
5da4b55f 990 struct iwl_power_mgr power_data;
5d08cd1d 991
8f91aecb 992 struct iwl_notif_statistics statistics;
5d08cd1d
CH
993 unsigned long last_statistics_time;
994
995 /* context information */
5d08cd1d
CH
996 u16 rates_mask;
997
998 u32 power_mode;
5d08cd1d
CH
999 u8 bssid[ETH_ALEN];
1000 u16 rts_threshold;
1001 u8 mac_addr[ETH_ALEN];
1002
1003 /*station table variables */
1004 spinlock_t sta_lock;
1005 int num_stations;
6def9761 1006 struct iwl_station_entry stations[IWL_STATION_COUNT];
6974e363
EG
1007 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1008 u8 default_wep_key;
1009 u8 key_mapping_key;
80fb47a1 1010 unsigned long ucode_key_table;
5d08cd1d 1011
e4e72fb4
JB
1012 /* queue refcounts */
1013#define IWL_MAX_HW_QUEUES 32
1014 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1015 /* for each AC */
1016 atomic_t queue_stop_count[4];
1017
5d08cd1d 1018 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1019 u8 is_open;
5d08cd1d
CH
1020
1021 u8 mac80211_registered;
5d08cd1d 1022
5d08cd1d
CH
1023 /* Rx'd packet timing information */
1024 u32 last_beacon_time;
1025 u64 last_tsf;
1026
5d08cd1d 1027 /* eeprom */
073d3f5f 1028 u8 *eeprom;
0848e297 1029 int nvm_device_type;
073d3f5f 1030 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1031
05c914fe 1032 enum nl80211_iftype iw_mode;
5d08cd1d
CH
1033
1034 struct sk_buff *ibss_beacon;
1035
1036 /* Last Rx'd beacon timestamp */
3109ece1 1037 u64 timestamp;
5d08cd1d 1038 u16 beacon_int;
32bfd35d 1039 struct ieee80211_vif *vif;
5d08cd1d 1040
8cd812bc 1041 /*Added for 3945 */
3832ec9d
AK
1042 void *shared_virt;
1043 dma_addr_t shared_phys;
1044 /*End*/
5425e490 1045 struct iwl_hw_params hw_params;
4ddbb7d0 1046
ef850d7c
MA
1047 /* INT ICT Table */
1048 u32 *ict_tbl;
1049 dma_addr_t ict_tbl_dma;
1050 dma_addr_t aligned_ict_tbl_dma;
1051 int ict_index;
1052 void *ict_tbl_vir;
1053 u32 inta;
1054 bool use_ict;
059ff826 1055
40cefda9 1056 u32 inta_mask;
5d08cd1d
CH
1057 /* Current association information needed to configure the
1058 * hardware */
1059 u16 assoc_id;
1060 u16 assoc_capability;
5d08cd1d 1061
1ff50bda 1062 struct iwl_qos_info qos_data;
5d08cd1d
CH
1063
1064 struct workqueue_struct *workqueue;
1065
1066 struct work_struct up;
1067 struct work_struct restart;
1068 struct work_struct calibrated_work;
1069 struct work_struct scan_completed;
1070 struct work_struct rx_replenish;
5d08cd1d
CH
1071 struct work_struct abort_scan;
1072 struct work_struct update_link_led;
1073 struct work_struct auth_work;
1074 struct work_struct report_work;
1075 struct work_struct request_scan;
1076 struct work_struct beacon_update;
1077
1078 struct tasklet_struct irq_tasklet;
1079
1080 struct delayed_work init_alive_start;
1081 struct delayed_work alive_start;
5d08cd1d 1082 struct delayed_work scan_check;
4a8a4322
AK
1083
1084 /*For 3945 only*/
1085 struct delayed_work thermal_periodic;
2663516d 1086 struct delayed_work rfkill_poll;
4a8a4322 1087
630fe9b6
TW
1088 /* TX Power */
1089 s8 tx_power_user_lmt;
1090 s8 tx_power_channel_lmt;
5d08cd1d 1091
5d08cd1d 1092
d08853a3 1093#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1094 /* debugging info */
bf403db8 1095 u32 debug_level;
5d08cd1d
CH
1096 u32 framecnt_to_us;
1097 atomic_t restrict_refcnt;
712b6cf5
TW
1098#ifdef CONFIG_IWLWIFI_DEBUGFS
1099 /* debugfs */
1100 struct iwl_debugfs *dbgfs;
1101#endif /* CONFIG_IWLWIFI_DEBUGFS */
1102#endif /* CONFIG_IWLWIFI_DEBUG */
5d08cd1d
CH
1103
1104 struct work_struct txpower_work;
445c2dff
TW
1105 u32 disable_sens_cal;
1106 u32 disable_chain_noise_cal;
203566f3 1107 u32 disable_tx_power_cal;
16e727e8 1108 struct work_struct run_time_calib_work;
5d08cd1d 1109 struct timer_list statistics_periodic;
086ed117 1110 bool hw_ready;
4a8a4322
AK
1111 /*For 3945*/
1112#define IWL_DEFAULT_TX_POWER 0x0F
4a8a4322 1113
4a8a4322
AK
1114 struct iwl3945_notif_statistics statistics_39;
1115
4a8a4322 1116 u32 sta_supp_rates;
c79dd5b5 1117}; /*iwl_priv */
5d08cd1d 1118
36470749
RR
1119static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1120{
1121 set_bit(txq_id, &priv->txq_ctx_active_msk);
1122}
1123
1124static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1125{
1126 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1127}
1128
994d31f7 1129#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW
1130const char *iwl_get_tx_fail_reason(u32 status);
1131#else
1132static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
1133#endif
1134
1135
a332f8d6
TW
1136static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1137 int txq_id, int idx)
1138{
1139 if (priv->txq[txq_id].txb[idx].skb[0])
1140 return (struct ieee80211_hdr *)priv->txq[txq_id].
1141 txb[idx].skb[0]->data;
1142 return NULL;
1143}
a332f8d6
TW
1144
1145
3109ece1 1146static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1147{
1148 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1149}
1150
bf85ea4f 1151static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1152{
1153 if (ch_info == NULL)
1154 return 0;
1155 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1156}
1157
bf85ea4f 1158static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1159{
1160 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1161}
1162
bf85ea4f 1163static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1164{
8318d78a 1165 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1166}
1167
bf85ea4f 1168static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1169{
8318d78a 1170 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1171}
1172
bf85ea4f 1173static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1174{
1175 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1176}
1177
bf85ea4f 1178static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1179{
1180 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1181}
1182
be1f3ab6 1183#endif /* __iwl_dev_h__ */
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