iwlagn: don't read the PCI_REVISION_ID from iwl-agn.c
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 */
30
be1f3ab6
EG
31#ifndef __iwl_dev_h__
32#define __iwl_dev_h__
b481de9c 33
5d08cd1d
CH
34#include <linux/pci.h> /* for struct pci_device_id */
35#include <linux/kernel.h>
7194207c 36#include <linux/wait.h>
5ed540ae 37#include <linux/leds.h>
5d08cd1d
CH
38#include <net/ieee80211_radiotap.h>
39
6bc913bd 40#include "iwl-eeprom.h"
6f83eaa1 41#include "iwl-csr.h"
5d08cd1d 42#include "iwl-prph.h"
dbb6654c 43#include "iwl-fh.h"
0a6857e7 44#include "iwl-debug.h"
b744cb79 45#include "iwl-agn-hw.h"
ab53d8af 46#include "iwl-led.h"
5da4b55f 47#include "iwl-power.h"
e227ceac 48#include "iwl-agn-rs.h"
0975cc8f 49#include "iwl-agn-tt.h"
5d08cd1d 50
48d1a211
EG
51#define DRV_NAME "iwlagn"
52
672639de
WYG
53struct iwl_tx_queue;
54
099b40b7 55/* CT-KILL constants */
672639de
WYG
56#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
57#define CT_KILL_THRESHOLD 114 /* in Celsius */
58#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 59
5d08cd1d
CH
60/* Default noise level to report when noise measurement is not available.
61 * This may be because we're:
62 * 1) Not associated (4965, no beacon statistics being sent to driver)
63 * 2) Scanning (noise measurement does not apply to associated channel)
64 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
65 * Use default noise value of -127 ... this is below the range of measurable
66 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
67 * Also, -127 works better than 0 when averaging frames with/without
68 * noise info (e.g. averaging might be done in app); measured dBm values are
69 * always negative ... using a negative value as the default keeps all
70 * averages within an s8's (used in some apps) range of negative values. */
71#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
72
5d08cd1d
CH
73/*
74 * RTS threshold here is total size [2347] minus 4 FCS bytes
75 * Per spec:
76 * a value of 0 means RTS on all data/management packets
77 * a value > max MSDU size means no RTS
78 * else RTS for data/management frames where MPDU is larger
79 * than RTS value.
80 */
81#define DEFAULT_RTS_THRESHOLD 2347U
82#define MIN_RTS_THRESHOLD 0U
83#define MAX_RTS_THRESHOLD 2347U
84#define MAX_MSDU_SIZE 2304U
85#define MAX_MPDU_SIZE 2346U
51b7ef05 86#define DEFAULT_BEACON_INTERVAL 200U
5d08cd1d
CH
87#define DEFAULT_SHORT_RETRY_LIMIT 7U
88#define DEFAULT_LONG_RETRY_LIMIT 4U
89
a55360e4 90struct iwl_rx_mem_buffer {
2f301227
ZY
91 dma_addr_t page_dma;
92 struct page *page;
5d08cd1d
CH
93 struct list_head list;
94};
95
2f301227
ZY
96#define rxb_addr(r) page_address(r->page)
97
c2acea8e
JB
98/* defined below */
99struct iwl_device_cmd;
100
101struct iwl_cmd_meta {
102 /* only for SYNC commands, iff the reply skb is wanted */
103 struct iwl_host_cmd *source;
104 /*
105 * only for ASYNC commands
106 * (which is somewhat stupid -- look at iwl-sta.c for instance
107 * which duplicates a bunch of code because the callback isn't
108 * invoked for SYNC commands, if it were and its result passed
109 * through it would be simpler...)
110 */
5696aea6
JB
111 void (*callback)(struct iwl_priv *priv,
112 struct iwl_device_cmd *cmd,
2f301227 113 struct iwl_rx_packet *pkt);
c2acea8e 114
c2acea8e
JB
115 u32 flags;
116
2e724443
FT
117 DEFINE_DMA_UNMAP_ADDR(mapping);
118 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
119};
120
5d08cd1d
CH
121/*
122 * Generic queue structure
123 *
4ce7cc2b
JB
124 * Contains common data for Rx and Tx queues.
125 *
126 * Note the difference between n_bd and n_window: the hardware
127 * always assumes 256 descriptors, so n_bd is always 256 (unless
128 * there might be HW changes in the future). For the normal TX
129 * queues, n_window, which is the size of the software queue data
130 * is also 256; however, for the command queue, n_window is only
131 * 32 since we don't need so many commands pending. Since the HW
132 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
133 * the software buffers (in the variables @meta, @txb in struct
134 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
135 * in the same struct) have 256.
136 * This means that we end up with the following:
137 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
138 * SW entries: | 0 | ... | 31 |
139 * where N is a number between 0 and 7. This means that the SW
140 * data is a window overlayed over the HW queue.
5d08cd1d 141 */
443cfd45 142struct iwl_queue {
5d08cd1d
CH
143 int n_bd; /* number of BDs in this queue */
144 int write_ptr; /* 1-st empty entry (index) host_w*/
145 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 146 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
147 dma_addr_t dma_addr; /* physical addr for BD's */
148 int n_window; /* safe queue window */
149 u32 id;
150 int low_mark; /* low watermark, resume queue if free
151 * space more than this */
152 int high_mark; /* high watermark, stop queue if free
153 * space less than this */
a839cf69 154};
5d08cd1d 155
bc47279f 156/* One for each TFD */
8567c63e 157struct iwl_tx_info {
ff0d91c3 158 struct sk_buff *skb;
c90cbbbd 159 struct iwl_rxon_context *ctx;
5d08cd1d
CH
160};
161
162/**
16466903 163 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
164 * @q: generic Rx/Tx queue descriptor
165 * @bd: base of circular buffer of TFDs
c2acea8e
JB
166 * @cmd: array of command/TX buffer pointers
167 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
168 * @dma_addr_cmd: physical address of cmd/tx buffer array
169 * @txb: array of per-TFD driver data
22de94de 170 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
171 * @need_update: indicates need to update read/write index
172 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 173 *
bc47279f
BC
174 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
175 * descriptors) and required locking structures.
5d08cd1d 176 */
188cf6c7
SO
177#define TFD_TX_CMD_SLOTS 256
178#define TFD_CMD_SLOTS 32
179
16466903 180struct iwl_tx_queue {
443cfd45 181 struct iwl_queue q;
4ce7cc2b 182 struct iwl_tfd *tfds;
c2acea8e
JB
183 struct iwl_device_cmd **cmd;
184 struct iwl_cmd_meta *meta;
8567c63e 185 struct iwl_tx_info *txb;
22de94de 186 unsigned long time_stamp;
3fd07a1e
TW
187 u8 need_update;
188 u8 sched_retry;
189 u8 active;
190 u8 swq_id;
5d08cd1d
CH
191};
192
193#define IWL_NUM_SCAN_RATES (2)
194
5d08cd1d
CH
195/*
196 * One for each channel, holds all channel setup data
197 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
198 * with one another!
199 */
bf85ea4f 200struct iwl_channel_info {
073d3f5f 201 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
202 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
203 * HT40 channel */
5d08cd1d
CH
204
205 u8 channel; /* channel number */
206 u8 flags; /* flags copied from EEPROM */
207 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 208 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
209 s8 min_power; /* always 0 */
210 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
211
212 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
213 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 214 enum ieee80211_band band;
5d08cd1d 215
7aafef1c
WYG
216 /* HT40 channel info */
217 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
218 u8 ht40_flags; /* flags copied from EEPROM */
219 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
220};
221
751ca305 222#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 223#define IWL_TX_FIFO_BE 1
751ca305 224#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 225#define IWL_TX_FIFO_VO 3
751ca305
JB
226#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
227#define IWL_TX_FIFO_BE_IPAN 4
228#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
229#define IWL_TX_FIFO_VO_IPAN 5
edc1a3a0 230#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 231
01a7e084
RC
232/* Minimum number of queues. MAX_NUM is defined in hw specific files.
233 * Set the minimum to accommodate the 4 standard TX queues, 1 command
234 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
235#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 236
bd35f150 237/*
13bb9483 238 * Command queue depends on iPAN support.
bd35f150 239 */
13bb9483
JB
240#define IWL_DEFAULT_CMD_QUEUE_NUM 4
241#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 242
751ca305
JB
243/*
244 * This queue number is required for proper operation
245 * because the ucode will stop/start the scheduler as
246 * required.
247 */
248#define IWL_IPAN_MCAST_QUEUE 8
249
5d08cd1d
CH
250#define IEEE80211_DATA_LEN 2304
251#define IEEE80211_4ADDR_LEN 30
252#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
253#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
254
5d08cd1d 255
5d08cd1d
CH
256#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
257#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
258#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
259
260enum {
c587de0b
TW
261 CMD_SYNC = 0,
262 CMD_SIZE_NORMAL = 0,
263 CMD_NO_SKB = 0,
5d08cd1d 264 CMD_ASYNC = (1 << 1),
5d08cd1d 265 CMD_WANT_SKB = (1 << 2),
3598e177 266 CMD_MAPPED = (1 << 3),
5d08cd1d
CH
267};
268
c8c24872 269#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 270
bc47279f 271/**
c2acea8e 272 * struct iwl_device_cmd
bc47279f
BC
273 *
274 * For allocation of the command and tx queues, this establishes the overall
4ce7cc2b
JB
275 * size of the largest command we send to uCode, except for commands that
276 * aren't fully copied and use other TFD space.
bc47279f 277 */
c2acea8e 278struct iwl_device_cmd {
857485c0 279 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 280 union {
5d08cd1d
CH
281 u32 flags;
282 u8 val8;
283 u16 val16;
284 u32 val32;
83d527d9 285 struct iwl_tx_cmd tx;
c8c24872
WYG
286 struct iwl6000_channel_switch_cmd chswitch;
287 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
288 } __packed cmd;
289} __packed;
5d08cd1d 290
c2acea8e
JB
291#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
292
4ce7cc2b
JB
293#define IWL_MAX_CMD_TFDS 2
294
295enum iwl_hcmd_dataflag {
296 IWL_HCMD_DFL_NOCOPY = BIT(0),
297};
3257e5d4 298
857485c0 299struct iwl_host_cmd {
3fa50738 300 const void *data[IWL_MAX_CMD_TFDS];
2f301227 301 unsigned long reply_page;
5696aea6
JB
302 void (*callback)(struct iwl_priv *priv,
303 struct iwl_device_cmd *cmd,
2f301227 304 struct iwl_rx_packet *pkt);
c2acea8e 305 u32 flags;
3fa50738 306 u16 len[IWL_MAX_CMD_TFDS];
4ce7cc2b 307 u8 dataflags[IWL_MAX_CMD_TFDS];
c2acea8e 308 u8 id;
5d08cd1d
CH
309};
310
5d08cd1d
CH
311#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
312#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
313#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
314
315/**
a55360e4 316 * struct iwl_rx_queue - Rx queue
df833b1d 317 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 318 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
319 * @read: Shared index to newest available Rx buffer
320 * @write: Shared index to oldest written Rx packet
321 * @free_count: Number of pre-allocated buffers in rx_free
322 * @rx_free: list of free SKBs for use
323 * @rx_used: List of Rx buffers with no SKB
324 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
325 * @rb_stts: driver's pointer to receive buffer status
326 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 327 *
a55360e4 328 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 329 */
a55360e4 330struct iwl_rx_queue {
5d08cd1d 331 __le32 *bd;
d5b25c90 332 dma_addr_t bd_dma;
a55360e4
TW
333 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
334 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
335 u32 read;
336 u32 write;
337 u32 free_count;
4752c93c 338 u32 write_actual;
5d08cd1d
CH
339 struct list_head rx_free;
340 struct list_head rx_used;
341 int need_update;
8d86422a
WT
342 struct iwl_rb_status *rb_stts;
343 dma_addr_t rb_stts_dma;
5d08cd1d
CH
344 spinlock_t lock;
345};
346
347#define IWL_SUPPORTED_RATES_IE_LEN 8
348
5d08cd1d
CH
349#define MAX_TID_COUNT 9
350
351#define IWL_INVALID_RATE 0xFF
352#define IWL_INVALID_VALUE -1
353
bc47279f 354/**
6def9761 355 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
356 * @txq_id: Tx queue used for Tx attempt
357 * @frame_count: # frames attempted by Tx command
358 * @wait_for_ba: Expect block-ack before next Tx reply
359 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
360 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
361 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
362 * @rate_n_flags: Rate at which Tx was attempted
363 *
364 * If REPLY_TX indicates that aggregation was attempted, driver must wait
365 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
366 * until block ack arrives.
367 */
6def9761 368struct iwl_ht_agg {
5d08cd1d
CH
369 u16 txq_id;
370 u16 frame_count;
371 u16 wait_for_ba;
372 u16 start_idx;
fe01b477 373 u64 bitmap;
5d08cd1d 374 u32 rate_n_flags;
fe01b477
RR
375#define IWL_AGG_OFF 0
376#define IWL_AGG_ON 1
377#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
378#define IWL_EMPTYING_HW_QUEUE_DELBA 3
379 u8 state;
c8823ec1 380 u8 tx_fifo;
5d08cd1d 381};
fe01b477 382
5d08cd1d 383
6def9761 384struct iwl_tid_data {
f862a236 385 u16 seq_number; /* agn only */
fe01b477 386 u16 tfds_in_queue;
6def9761 387 struct iwl_ht_agg agg;
5d08cd1d
CH
388};
389
6def9761 390struct iwl_hw_key {
97359d12 391 u32 cipher;
5d08cd1d 392 int keylen;
0211ddda 393 u8 keyidx;
5d08cd1d
CH
394 u8 key[32];
395};
396
a78fe754 397union iwl_ht_rate_supp {
5d08cd1d
CH
398 u16 rates;
399 struct {
400 u8 siso_rate;
401 u8 mimo_rate;
402 };
403};
404
172c1d11
WYG
405#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
406#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
407#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
408#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
409#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
410#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
411#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
412
413/*
414 * Maximal MPDU density for TX aggregation
415 * 4 - 2us density
416 * 5 - 4us density
417 * 6 - 8us density
418 * 7 - 16us density
419 */
172c1d11 420#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 421#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
422#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
423#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 424#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
425#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
426#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 427
fad95bf5 428struct iwl_ht_config {
02bb1bea 429 bool single_chain_sufficient;
ba37a3d0 430 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 431};
5d08cd1d 432
5d08cd1d 433/* QoS structures */
1ff50bda 434struct iwl_qos_info {
5d08cd1d 435 int qos_active;
1ff50bda 436 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 437};
5d08cd1d 438
fe6b23dd
RC
439/*
440 * Structure should be accessed with sta_lock held. When station addition
441 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
442 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
443 * held.
444 */
6def9761 445struct iwl_station_entry {
133636de 446 struct iwl_addsta_cmd sta;
6def9761 447 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 448 u8 used, ctxid;
6def9761 449 struct iwl_hw_key keyinfo;
fe6b23dd 450 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
451};
452
fd1af15d 453struct iwl_station_priv_common {
238d781d 454 struct iwl_rxon_context *ctx;
fd1af15d
JB
455 u8 sta_id;
456};
457
8d9698b3
RC
458/*
459 * iwl_station_priv: Driver's private station information
460 *
461 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
462 * in the structure for use by driver. This structure is places in that
463 * space.
8d9698b3
RC
464 */
465struct iwl_station_priv {
fd1af15d 466 struct iwl_station_priv_common common;
8d9698b3 467 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
468 atomic_t pending_frames;
469 bool client;
470 bool asleep;
7b090687 471 u8 max_agg_bufsize;
8d9698b3
RC
472};
473
fd1af15d
JB
474/**
475 * struct iwl_vif_priv - driver's private per-interface information
476 *
477 * When mac80211 allocates a virtual interface, it can allocate
478 * space for us to put data into.
479 */
480struct iwl_vif_priv {
246ed355 481 struct iwl_rxon_context *ctx;
fd1af15d
JB
482 u8 ibss_bssid_sta_id;
483};
484
5d08cd1d
CH
485/* one for each uCode image (inst/data, boot/init/runtime) */
486struct fw_desc {
487 void *v_addr; /* access by driver */
488 dma_addr_t p_addr; /* access by card's busmaster DMA */
489 u32 len; /* bytes */
490};
491
dbf28e21
JB
492struct fw_img {
493 struct fw_desc code, data;
494};
495
dd7a2509 496/* v1/v2 uCode file layout */
cc0f555d
JS
497struct iwl_ucode_header {
498 __le32 ver; /* major/minor/API/serial */
499 union {
500 struct {
501 __le32 inst_size; /* bytes of runtime code */
502 __le32 data_size; /* bytes of runtime data */
503 __le32 init_size; /* bytes of init code */
504 __le32 init_data_size; /* bytes of init data */
505 __le32 boot_size; /* bytes of bootstrap code */
506 u8 data[0]; /* in same order as sizes */
507 } v1;
508 struct {
509 __le32 build; /* build number */
510 __le32 inst_size; /* bytes of runtime code */
511 __le32 data_size; /* bytes of runtime data */
512 __le32 init_size; /* bytes of init code */
513 __le32 init_data_size; /* bytes of init data */
514 __le32 boot_size; /* bytes of bootstrap code */
515 u8 data[0]; /* in same order as sizes */
516 } v2;
517 } u;
5d08cd1d
CH
518};
519
dd7a2509
JB
520/*
521 * new TLV uCode file layout
522 *
523 * The new TLV file format contains TLVs, that each specify
524 * some piece of data. To facilitate "groups", for example
525 * different instruction image with different capabilities,
526 * bundled with the same init image, an alternative mechanism
527 * is provided:
528 * When the alternative field is 0, that means that the item
529 * is always valid. When it is non-zero, then it is only
530 * valid in conjunction with items of the same alternative,
531 * in which case the driver (user) selects one alternative
532 * to use.
533 */
534
535enum iwl_ucode_tlv_type {
536 IWL_UCODE_TLV_INVALID = 0, /* unused */
537 IWL_UCODE_TLV_INST = 1,
538 IWL_UCODE_TLV_DATA = 2,
539 IWL_UCODE_TLV_INIT = 3,
540 IWL_UCODE_TLV_INIT_DATA = 4,
541 IWL_UCODE_TLV_BOOT = 5,
542 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 543 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
544 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
545 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
546 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
547 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
548 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
549 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 550 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 551 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
3997ff39
JB
552 /* 16 and 17 reserved for future use */
553 IWL_UCODE_TLV_FLAGS = 18,
554};
555
556/**
557 * enum iwl_ucode_tlv_flag - ucode API flags
558 * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
559 * was a separate TLV but moved here to save space.
d2690c0d
JB
560 * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
561 * treats good CRC threshold as a boolean
3997ff39
JB
562 * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
563 */
564enum iwl_ucode_tlv_flag {
565 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
d2690c0d 566 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
3997ff39 567 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
dd7a2509
JB
568};
569
570struct iwl_ucode_tlv {
571 __le16 type; /* see above */
572 __le16 alternative; /* see comment */
573 __le32 length; /* not including type/length fields */
574 u8 data[0];
ba2d3587 575} __packed;
dd7a2509
JB
576
577#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
578
579struct iwl_tlv_ucode_header {
580 /*
581 * The TLV style ucode header is distinguished from
582 * the v1/v2 style header by first four bytes being
583 * zero, as such is an invalid combination of
584 * major/minor/API/serial versions.
585 */
586 __le32 zero;
587 __le32 magic;
588 u8 human_readable[64];
589 __le32 ver; /* major/minor/API/serial */
590 __le32 build;
591 __le64 alternatives; /* bitmask of valid alternatives */
592 /*
593 * The data contained herein has a TLV layout,
594 * see above for the TLV header and types.
595 * Note that each TLV is padded to a length
596 * that is a multiple of 4 for alignment.
597 */
598 u8 data[0];
599};
600
f0832f13
EG
601struct iwl_sensitivity_ranges {
602 u16 min_nrg_cck;
603 u16 max_nrg_cck;
604
605 u16 nrg_th_cck;
606 u16 nrg_th_ofdm;
607
608 u16 auto_corr_min_ofdm;
609 u16 auto_corr_min_ofdm_mrc;
610 u16 auto_corr_min_ofdm_x1;
611 u16 auto_corr_min_ofdm_mrc_x1;
612
613 u16 auto_corr_max_ofdm;
614 u16 auto_corr_max_ofdm_mrc;
615 u16 auto_corr_max_ofdm_x1;
616 u16 auto_corr_max_ofdm_mrc_x1;
617
618 u16 auto_corr_max_cck;
619 u16 auto_corr_max_cck_mrc;
620 u16 auto_corr_min_cck;
621 u16 auto_corr_min_cck_mrc;
55036d66
WYG
622
623 u16 barker_corr_th_min;
624 u16 barker_corr_th_min_mrc;
625 u16 nrg_th_cca;
f0832f13
EG
626};
627
099b40b7 628
b5047f78
TW
629#define KELVIN_TO_CELSIUS(x) ((x)-273)
630#define CELSIUS_TO_KELVIN(x) ((x)+273)
631
632
bc47279f 633/**
5425e490 634 * struct iwl_hw_params
bc47279f 635 * @max_txq_num: Max # Tx queues supported
f3f911d1 636 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 637 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 638 * @tfd_size: TFD size
099b40b7
RR
639 * @tx/rx_chains_num: Number of TX/RX chains
640 * @valid_tx/rx_ant: usable antennas
bc47279f 641 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 642 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 643 * @rx_page_order: Rx buffer page order
141c43a3 644 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 645 * @max_stations:
7aafef1c 646 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
647 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
648 * @sw_crypto: 0 for hw, 1 for sw
649 * @max_xxx_size: for ucode uses
650 * @ct_kill_threshold: temperature threshold
a0ee74cf 651 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 652 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 653 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 654 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 655 */
5425e490 656struct iwl_hw_params {
f3f911d1
ZY
657 u8 max_txq_num;
658 u8 dma_chnl_num;
4ddbb7d0 659 u16 scd_bc_tbls_size;
a8e74e27 660 u32 tfd_size;
ec35cf2a
TW
661 u8 tx_chains_num;
662 u8 rx_chains_num;
663 u8 valid_tx_ant;
664 u8 valid_rx_ant;
5d08cd1d 665 u16 max_rxq_size;
ec35cf2a 666 u16 max_rxq_log;
2f301227 667 u32 rx_page_order;
141c43a3 668 u32 rx_wrt_ptr_reg;
5d08cd1d 669 u8 max_stations;
7aafef1c 670 u8 ht40_channel;
2c2f3b33 671 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
672 u32 max_inst_size;
673 u32 max_data_size;
099b40b7 674 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
675 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
676 /* for 1000, 6000 series and up */
a0ee74cf 677 u16 beacon_time_tsf_bits;
be5d56ed 678 u32 calib_init_cfg;
6d6a1afd 679 u32 calib_rt_cfg;
f0832f13 680 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
681};
682
5d08cd1d 683
5d08cd1d
CH
684/******************************************************************************
685 *
a33c2f47
EG
686 * Functions implemented in core module which are forward declared here
687 * for use by iwl-[4-5].c
5d08cd1d 688 *
a33c2f47
EG
689 * NOTE: The implementation of these functions are not hardware specific
690 * which is why they are in the core module files.
5d08cd1d
CH
691 *
692 * Naming convention --
a33c2f47 693 * iwl_ <-- Is part of iwlwifi
5d08cd1d 694 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
5d08cd1d
CH
695 *
696 ****************************************************************************/
5b9f8cd3 697extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 698extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 699extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 700extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 701extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
702static inline int iwl_queue_used(const struct iwl_queue *q, int i)
703{
c8106d76 704 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
705 (i >= q->read_ptr && i < q->write_ptr) :
706 !(i < q->read_ptr && i >= q->write_ptr);
707}
708
709
4ce7cc2b 710static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
fd4abac5 711{
fd4abac5
TW
712 return index & (q->n_window - 1);
713}
714
715
4ddbb7d0
TW
716struct iwl_dma_ptr {
717 dma_addr_t dma;
718 void *addr;
b481de9c
ZY
719 size_t size;
720};
721
b481de9c
ZY
722#define IWL_OPERATION_MODE_AUTO 0
723#define IWL_OPERATION_MODE_HT_ONLY 1
724#define IWL_OPERATION_MODE_MIXED 2
725#define IWL_OPERATION_MODE_20MHZ 3
726
3195cdb7
TW
727#define IWL_TX_CRC_SIZE 4
728#define IWL_TX_DELIMITER_SIZE 4
b481de9c 729
b481de9c 730#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 731
b481de9c 732/* Sensitivity and chain noise calibration */
b481de9c 733#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a 734#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
735#define MAXIMUM_ALLOWED_PATHLOSS 15
736
b481de9c
ZY
737#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
738
739#define MAX_FA_OFDM 50
740#define MIN_FA_OFDM 5
741#define MAX_FA_CCK 50
742#define MIN_FA_CCK 5
743
b481de9c
ZY
744#define AUTO_CORR_STEP_OFDM 1
745
b481de9c
ZY
746#define AUTO_CORR_STEP_CCK 3
747#define AUTO_CORR_MAX_TH_CCK 160
748
b481de9c
ZY
749#define NRG_DIFF 2
750#define NRG_STEP_CCK 2
751#define NRG_MARGIN 8
752#define MAX_NUMBER_CCK_NO_FA 100
753
754#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
755
756#define CHAIN_A 0
757#define CHAIN_B 1
758#define CHAIN_C 2
759#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
760#define ALL_BAND_FILTER 0xFF00
761#define IN_BAND_FILTER 0xFF
762#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
763
3195cdb7
TW
764#define NRG_NUM_PREV_STAT_L 20
765#define NUM_RX_CHAINS 3
766
3240cab3 767enum iwlagn_false_alarm_state {
b481de9c
ZY
768 IWL_FA_TOO_MANY = 0,
769 IWL_FA_TOO_FEW = 1,
770 IWL_FA_GOOD_RANGE = 2,
771};
772
3240cab3 773enum iwlagn_chain_noise_state {
b481de9c 774 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
775 IWL_CHAIN_NOISE_ACCUMULATE,
776 IWL_CHAIN_NOISE_CALIBRATED,
777 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
778};
779
f69f42a6
TW
780
781/*
782 * enum iwl_calib
783 * defines the order in which results of initial calibrations
784 * should be sent to the runtime uCode
785 */
786enum iwl_calib {
787 IWL_CALIB_XTAL,
819500c5 788 IWL_CALIB_DC,
f69f42a6
TW
789 IWL_CALIB_LO,
790 IWL_CALIB_TX_IQ,
791 IWL_CALIB_TX_IQ_PERD,
201706ac 792 IWL_CALIB_BASE_BAND,
bf53f939 793 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
794 IWL_CALIB_MAX
795};
796
6e21f2c1
TW
797/* Opaque calibration results */
798struct iwl_calib_result {
799 void *buf;
800 size_t buf_len;
7c616cba
TW
801};
802
b481de9c 803/* Sensitivity calib data */
f0832f13 804struct iwl_sensitivity_data {
b481de9c
ZY
805 u32 auto_corr_ofdm;
806 u32 auto_corr_ofdm_mrc;
807 u32 auto_corr_ofdm_x1;
808 u32 auto_corr_ofdm_mrc_x1;
809 u32 auto_corr_cck;
810 u32 auto_corr_cck_mrc;
811
812 u32 last_bad_plcp_cnt_ofdm;
813 u32 last_fa_cnt_ofdm;
814 u32 last_bad_plcp_cnt_cck;
815 u32 last_fa_cnt_cck;
816
817 u32 nrg_curr_state;
818 u32 nrg_prev_state;
819 u32 nrg_value[10];
820 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
821 u32 nrg_silence_ref;
822 u32 nrg_energy_idx;
823 u32 nrg_silence_idx;
824 u32 nrg_th_cck;
825 s32 nrg_auto_corr_silence_diff;
826 u32 num_in_cck_no_fa;
827 u32 nrg_th_ofdm;
55036d66
WYG
828
829 u16 barker_corr_th_min;
830 u16 barker_corr_th_min_mrc;
831 u16 nrg_th_cca;
b481de9c
ZY
832};
833
834/* Chain noise (differential Rx gain) calib data */
f0832f13 835struct iwl_chain_noise_data {
04816448 836 u32 active_chains;
b481de9c
ZY
837 u32 chain_noise_a;
838 u32 chain_noise_b;
839 u32 chain_noise_c;
840 u32 chain_signal_a;
841 u32 chain_signal_b;
842 u32 chain_signal_c;
04816448 843 u16 beacon_count;
b481de9c
ZY
844 u8 disconn_array[NUM_RX_CHAINS];
845 u8 delta_gain_code[NUM_RX_CHAINS];
846 u8 radio_write;
04816448 847 u8 state;
b481de9c
ZY
848};
849
abceddb4
BC
850#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
851#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 852
20594eb0
WYG
853#define IWL_TRAFFIC_ENTRIES (256)
854#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 855
5d08cd1d
CH
856enum {
857 MEASUREMENT_READY = (1 << 0),
858 MEASUREMENT_ACTIVE = (1 << 1),
859};
860
0848e297
WYG
861enum iwl_nvm_type {
862 NVM_DEVICE_TYPE_EEPROM = 0,
863 NVM_DEVICE_TYPE_OTP,
864};
865
415e4993
WYG
866/*
867 * Two types of OTP memory access modes
868 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
869 * based on physical memory addressing
870 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
871 * based on logical memory addressing
872 */
873enum iwl_access_mode {
874 IWL_OTP_ACCESS_ABSOLUTE,
875 IWL_OTP_ACCESS_RELATIVE,
876};
65b7998a
WYG
877
878/**
879 * enum iwl_pa_type - Power Amplifier type
880 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
881 * @IWL_PA_INTERNAL: use Internal only
882 */
883enum iwl_pa_type {
884 IWL_PA_SYSTEM = 0,
740e7f51 885 IWL_PA_INTERNAL = 1,
65b7998a
WYG
886};
887
a83b9141
WYG
888/* interrupt statistics */
889struct isr_statistics {
890 u32 hw;
891 u32 sw;
6e6ebf4b 892 u32 err_code;
a83b9141
WYG
893 u32 sch;
894 u32 alive;
895 u32 rfkill;
896 u32 ctkill;
897 u32 wakeup;
898 u32 rx;
899 u32 rx_handlers[REPLY_MAX];
900 u32 tx;
901 u32 unhandled;
902};
5d08cd1d 903
91835ba4
WYG
904/* reply_tx_statistics (for _agn devices) */
905struct reply_tx_error_statistics {
906 u32 pp_delay;
907 u32 pp_few_bytes;
908 u32 pp_bt_prio;
909 u32 pp_quiet_period;
910 u32 pp_calc_ttak;
911 u32 int_crossed_retry;
912 u32 short_limit;
913 u32 long_limit;
914 u32 fifo_underrun;
915 u32 drain_flow;
916 u32 rfkill_flush;
917 u32 life_expire;
918 u32 dest_ps;
919 u32 host_abort;
920 u32 bt_retry;
921 u32 sta_invalid;
922 u32 frag_drop;
923 u32 tid_disable;
924 u32 fifo_flush;
925 u32 insuff_cf_poll;
926 u32 fail_hw_drop;
927 u32 sta_color_mismatch;
928 u32 unknown;
929};
930
814665fe
WYG
931/* reply_agg_tx_statistics (for _agn devices) */
932struct reply_agg_tx_error_statistics {
933 u32 underrun;
934 u32 bt_prio;
935 u32 few_bytes;
936 u32 abort;
937 u32 last_sent_ttl;
938 u32 last_sent_try;
939 u32 last_sent_bt_kill;
940 u32 scd_query;
941 u32 bad_crc32;
942 u32 response;
943 u32 dump_tx;
944 u32 delay_tx;
945 u32 unknown;
946};
947
22fdf3c9
WYG
948/* management statistics */
949enum iwl_mgmt_stats {
950 MANAGEMENT_ASSOC_REQ = 0,
951 MANAGEMENT_ASSOC_RESP,
952 MANAGEMENT_REASSOC_REQ,
953 MANAGEMENT_REASSOC_RESP,
954 MANAGEMENT_PROBE_REQ,
955 MANAGEMENT_PROBE_RESP,
956 MANAGEMENT_BEACON,
957 MANAGEMENT_ATIM,
958 MANAGEMENT_DISASSOC,
959 MANAGEMENT_AUTH,
960 MANAGEMENT_DEAUTH,
961 MANAGEMENT_ACTION,
962 MANAGEMENT_MAX,
963};
964/* control statistics */
965enum iwl_ctrl_stats {
966 CONTROL_BACK_REQ = 0,
967 CONTROL_BACK,
968 CONTROL_PSPOLL,
969 CONTROL_RTS,
970 CONTROL_CTS,
971 CONTROL_ACK,
972 CONTROL_CFEND,
973 CONTROL_CFENDACK,
974 CONTROL_MAX,
975};
976
977struct traffic_stats {
5ed540ae 978#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
979 u32 mgmt[MANAGEMENT_MAX];
980 u32 ctrl[CONTROL_MAX];
981 u32 data_cnt;
982 u64 data_bytes;
22fdf3c9 983#endif
5ed540ae 984};
22fdf3c9 985
a9e1cb6a
WYG
986/*
987 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
988 * to perform continuous uCode event logging operation if enabled
989 */
990#define UCODE_TRACE_PERIOD (100)
991
992/*
993 * iwl_event_log: current uCode event log position
994 *
995 * @ucode_trace: enable/disable ucode continuous trace timer
996 * @num_wraps: how many times the event buffer wraps
997 * @next_entry: the entry just before the next one that uCode would fill
998 * @non_wraps_count: counter for no wrap detected when dump ucode events
999 * @wraps_once_count: counter for wrap once detected when dump ucode events
1000 * @wraps_more_count: counter for wrap more than once detected
1001 * when dump ucode events
1002 */
1003struct iwl_event_log {
1004 bool ucode_trace;
1005 u32 num_wraps;
1006 u32 next_entry;
1007 int non_wraps_count;
1008 int wraps_once_count;
1009 int wraps_more_count;
1010};
1011
2be76703
WYG
1012/*
1013 * host interrupt timeout value
1014 * used with setting interrupt coalescing timer
1015 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1016 *
1017 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1018 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1019 */
1020#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1021#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1022#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1023#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1024#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1025#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1026
3e4fb5fa
TAN
1027/*
1028 * This is the threshold value of plcp error rate per 100mSecs. It is
1029 * used to set and check for the validity of plcp_delta.
1030 */
680788ac 1031#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1032#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1033#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1034#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1035#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1036#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1037
8a472da4
WYG
1038#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1039#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1040
22de94de
SG
1041/* TX queue watchdog timeouts in mSecs */
1042#define IWL_DEF_WD_TIMEOUT (2000)
1043#define IWL_LONG_WD_TIMEOUT (10000)
1044#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1045
bee008b7
WYG
1046/* BT Antenna Coupling Threshold (dB) */
1047#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1048
491bc292
WYG
1049/* Firmware reload counter and Timestamp */
1050#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1051#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1052
1053
a93e7973
WYG
1054enum iwl_reset {
1055 IWL_RF_RESET = 0,
1056 IWL_FW_RESET,
8a472da4
WYG
1057 IWL_MAX_FORCE_RESET,
1058};
1059
1060struct iwl_force_reset {
1061 int reset_request_count;
1062 int reset_success_count;
1063 int reset_reject_count;
1064 unsigned long reset_duration;
1065 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1066};
1067
a0ee74cf 1068/* extend beacon time format bit shifting */
a0ee74cf
WYG
1069/*
1070 * for _agn devices
1071 * bits 31:22 - extended
1072 * bits 21:0 - interval
1073 */
1074#define IWLAGN_EXT_BEACON_TIME_POS 22
1075
7194207c
JB
1076/**
1077 * struct iwl_notification_wait - notification wait entry
1078 * @list: list head for global list
1079 * @fn: function called with the notification
1080 * @cmd: command ID
1081 *
1082 * This structure is not used directly, to wait for a
1083 * notification declare it on the stack, and call
1084 * iwlagn_init_notification_wait() with appropriate
1085 * parameters. Then do whatever will cause the ucode
1086 * to notify the driver, and to wait for that then
1087 * call iwlagn_wait_notification().
1088 *
1089 * Each notification is one-shot. If at some point we
1090 * need to support multi-shot notifications (which
1091 * can't be allocated on the stack) we need to modify
1092 * the code for them.
1093 */
1094struct iwl_notification_wait {
1095 struct list_head list;
1096
09f18afe
JB
1097 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt,
1098 void *data);
1099 void *fn_data;
7194207c
JB
1100
1101 u8 cmd;
e74fe233 1102 bool triggered, aborted;
7194207c
JB
1103};
1104
246ed355
JB
1105enum iwl_rxon_context_id {
1106 IWL_RXON_CTX_BSS,
ece9c4ee 1107 IWL_RXON_CTX_PAN,
246ed355
JB
1108
1109 NUM_IWL_RXON_CTX
1110};
1111
1112struct iwl_rxon_context {
8bd413e6 1113 struct ieee80211_vif *vif;
e72f368b
JB
1114
1115 const u8 *ac_to_fifo;
1116 const u8 *ac_to_queue;
1117 u8 mcast_queue;
1118
763cc3bf
JB
1119 /*
1120 * We could use the vif to indicate active, but we
1121 * also need it to be active during disabling when
1122 * we already removed the vif for type setting.
1123 */
1124 bool always_active, is_active;
1125
2295c66b
JB
1126 bool ht_need_multiple_chains;
1127
246ed355 1128 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1129
1130 u32 interface_modes, exclusive_interface_modes;
1131 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1132
246ed355
JB
1133 /*
1134 * We declare this const so it can only be
1135 * changed via explicit cast within the
1136 * routines that actually update the physical
1137 * hardware.
1138 */
1139 const struct iwl_rxon_cmd active;
1140 struct iwl_rxon_cmd staging;
1141
1142 struct iwl_rxon_time_cmd timing;
a194e324 1143
8dfdb9d5
JB
1144 struct iwl_qos_info qos_data;
1145
2995bafa 1146 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1147
1148 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1149 u8 qos_cmd;
c10afb6e
JB
1150 u8 wep_key_cmd;
1151
1152 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1153 u8 key_mapping_keys;
770e13bd
JB
1154
1155 __le32 station_flags;
7e6a5886
JB
1156
1157 struct {
1158 bool non_gf_sta_present;
1159 u8 protection;
1160 bool enabled, is_40mhz;
1161 u8 extension_chan_offset;
1162 } ht;
68b99311
GT
1163
1164 bool last_tx_rejected;
246ed355
JB
1165};
1166
266af4c7
JB
1167enum iwl_scan_type {
1168 IWL_SCAN_NORMAL,
1169 IWL_SCAN_RADIO_RESET,
1170 IWL_SCAN_OFFCH_TX,
1171};
1172
872907bb
JB
1173enum iwlagn_ucode_type {
1174 IWL_UCODE_NONE,
1175 IWL_UCODE_REGULAR,
1176 IWL_UCODE_INIT,
1177 IWL_UCODE_WOWLAN,
1178};
1179
7a4e5281
WYG
1180#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1181struct iwl_testmode_trace {
49b72100
WYG
1182 u32 buff_size;
1183 u32 total_size;
eb64dca0 1184 u32 num_chunks;
7a4e5281
WYG
1185 u8 *cpu_addr;
1186 u8 *trace_addr;
1187 dma_addr_t dma_addr;
1188 bool trace_enabled;
1189};
1190#endif
a48709c5
EG
1191
1192struct iwl_bus;
1193
1194/**
1195 * struct iwl_bus_ops - bus specific operations
d57fa99d
WYG
1196
1197 * @get_pm_support: must returns true if the bus can go to sleep
1198 * @apm_config: will be called during the config of the APM configuration
a48709c5 1199 * @set_drv_data: set the priv pointer to the bus layer
3599d39a 1200 * @get_dev: returns the device struct
19707bac 1201 * @get_hw_id: prints the hw_id in the provided buffer
084dd791
EG
1202 * @write8: write a byte to register at offset ofs
1203 * @write32: write a dword to register at offset ofs
1204 * @wread32: read a dword at register at offset ofs
a48709c5
EG
1205 */
1206struct iwl_bus_ops {
d57fa99d
WYG
1207 bool (*get_pm_support)(struct iwl_bus *bus);
1208 void (*apm_config)(struct iwl_bus *bus);
a48709c5 1209 void (*set_drv_data)(struct iwl_bus *bus, void *priv);
3599d39a 1210 struct device *(*get_dev)(const struct iwl_bus *bus);
19707bac 1211 void (*get_hw_id)(struct iwl_bus *bus, char buf[], int buf_len);
084dd791
EG
1212 void (*write8)(struct iwl_bus *bus, u32 ofs, u8 val);
1213 void (*write32)(struct iwl_bus *bus, u32 ofs, u32 val);
1214 u32 (*read32)(struct iwl_bus *bus, u32 ofs);
a48709c5
EG
1215};
1216
1217struct iwl_bus {
1218 /* pointer to bus specific struct */
1219 void *bus_specific;
1220
1221 /* Common data to all buses */
1222 struct iwl_priv *priv; /* driver's context */
3599d39a 1223 struct device *dev;
a48709c5
EG
1224 struct iwl_bus_ops *ops;
1225};
1226
c79dd5b5 1227struct iwl_priv {
5d08cd1d
CH
1228
1229 /* ieee device used by generic ieee processing code */
1230 struct ieee80211_hw *hw;
1231 struct ieee80211_channel *ieee_channels;
1232 struct ieee80211_rate *ieee_rates;
82b9a121 1233 struct iwl_cfg *cfg;
5d08cd1d 1234
8318d78a 1235 enum ieee80211_band band;
5d08cd1d 1236
4613e72d
CK
1237 void (*pre_rx_handler)(struct iwl_priv *priv,
1238 struct iwl_rx_mem_buffer *rxb);
c79dd5b5 1239 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1240 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1241
8318d78a 1242 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1243
5d08cd1d 1244 /* spectrum measurement report caching */
2aa6ab86 1245 struct iwl_spectrum_notification measure_report;
5d08cd1d 1246 u8 measurement_status;
81963d68 1247
5d08cd1d
CH
1248 /* ucode beacon time */
1249 u32 ucode_beacon_time;
a13d276f 1250 int missed_beacon_threshold;
5d08cd1d 1251
a85d7cca
JB
1252 /* track IBSS manager (last beacon) status */
1253 u32 ibss_manager;
1254
410f2bb3
SG
1255 /* jiffies when last recovery from statistics was performed */
1256 unsigned long rx_statistics_jiffies;
3e4fb5fa 1257
a93e7973 1258 /* force reset */
8a472da4 1259 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1260
491bc292
WYG
1261 /* firmware reload counter and timestamp */
1262 unsigned long reload_jiffies;
1263 int reload_count;
1264
5a2a780c 1265 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1266 * Access via channel # using indirect index array */
bf85ea4f 1267 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1268 u8 channel_count; /* # of channels */
1269
5d08cd1d
CH
1270 /* thermal calibration */
1271 s32 temperature; /* degrees Kelvin */
1272 s32 last_temperature;
1273
7c616cba 1274 /* init calibration results */
6e21f2c1 1275 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1276
5d08cd1d 1277 /* Scan related variables */
5d08cd1d 1278 unsigned long scan_start;
5d08cd1d 1279 unsigned long scan_start_tsf;
811ecc99 1280 void *scan_cmd;
00700ee0 1281 enum ieee80211_band scan_band;
1ecf9fc1 1282 struct cfg80211_scan_request *scan_request;
f84b29ec 1283 struct ieee80211_vif *scan_vif;
266af4c7 1284 enum iwl_scan_type scan_type;
76eff18b
TW
1285 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1286 u8 mgmt_tx_ant;
5d08cd1d
CH
1287
1288 /* spinlock */
1289 spinlock_t lock; /* protect general shared data */
1290 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1291 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d
CH
1292 struct mutex mutex;
1293
a48709c5 1294 /* TODO: remove this after PCI abstraction is done */
5d08cd1d
CH
1295 /* basic pci-network driver stuff */
1296 struct pci_dev *pci_dev;
1297
a48709c5
EG
1298 struct iwl_bus bus; /* bus specific data */
1299
246ed355
JB
1300 /* microcode/device supports multiple contexts */
1301 u8 valid_contexts;
1302
13bb9483
JB
1303 /* command queue number */
1304 u8 cmd_queue;
1305
c10afb6e
JB
1306 /* max number of station keys */
1307 u8 sta_key_max_num;
1308
d2690c0d
JB
1309 bool new_scan_threshold_behaviour;
1310
c6fa17ed
WYG
1311 /* EEPROM MAC addresses */
1312 struct mac_address addresses[2];
1313
5d08cd1d 1314 /* uCode images, save to reload in case of failure */
b08dfd04 1315 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1316 u32 ucode_ver; /* version of ucode, copy of
1317 iwl_ucode.ver */
dbf28e21
JB
1318 struct fw_img ucode_rt;
1319 struct fw_img ucode_init;
1320
872907bb 1321 enum iwlagn_ucode_type ucode_type;
dbb983b7 1322 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1323 char firmware_name[25];
5d08cd1d 1324
246ed355 1325 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1326
6f213ff1 1327 __le16 switch_channel;
0924e519 1328
d7d5783c
JB
1329 struct {
1330 u32 error_event_table;
1331 u32 log_event_table;
1332 } device_pointers;
5d08cd1d 1333
5d08cd1d 1334 u16 active_rate;
5d08cd1d 1335
5d08cd1d 1336 u8 start_calib;
f0832f13
EG
1337 struct iwl_sensitivity_data sensitivity_data;
1338 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1339 bool enhance_sensitivity_table;
5d08cd1d 1340 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1341 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1342
fad95bf5 1343 struct iwl_ht_config current_ht_config;
5d08cd1d 1344
5d08cd1d 1345 /* Rate scaling data */
5d08cd1d
CH
1346 u8 retry_rate;
1347
1348 wait_queue_head_t wait_command_queue;
1349
1350 int activity_timer_active;
1351
1352 /* Rx and Tx DMA processing queues */
a55360e4 1353 struct iwl_rx_queue rxq;
88804e2b 1354 struct iwl_tx_queue *txq;
5d08cd1d 1355 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1356 struct iwl_dma_ptr kw; /* keep warm address */
1357 struct iwl_dma_ptr scd_bc_tbls;
1358
5d08cd1d
CH
1359 u32 scd_base_addr; /* scheduler sram base address */
1360
1361 unsigned long status;
5d08cd1d 1362
19758bef 1363 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1364 struct traffic_stats tx_stats;
1365 struct traffic_stats rx_stats;
19758bef 1366
a83b9141
WYG
1367 /* counts interrupts */
1368 struct isr_statistics isr_stats;
1369
5da4b55f 1370 struct iwl_power_mgr power_data;
3ad3b92a 1371 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1372
9c5ac091
RC
1373 /* station table variables */
1374
1375 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1376 spinlock_t sta_lock;
1377 int num_stations;
3240cab3 1378 struct iwl_station_entry stations[IWLAGN_STATION_COUNT];
80fb47a1 1379 unsigned long ucode_key_table;
5d08cd1d 1380
e4e72fb4
JB
1381 /* queue refcounts */
1382#define IWL_MAX_HW_QUEUES 32
1383 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1384 /* for each AC */
1385 atomic_t queue_stop_count[4];
1386
5d08cd1d 1387 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1388 u8 is_open;
5d08cd1d
CH
1389
1390 u8 mac80211_registered;
5d08cd1d 1391
af6b8ee3 1392 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1393 u8 *eeprom;
0848e297 1394 int nvm_device_type;
073d3f5f 1395 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1396
05c914fe 1397 enum nl80211_iftype iw_mode;
5d08cd1d 1398
5d08cd1d 1399 /* Last Rx'd beacon timestamp */
3109ece1 1400 u64 timestamp;
5d08cd1d 1401
0da0e5bf
JB
1402 struct {
1403 __le32 flag;
1404 struct statistics_general_common common;
1405 struct statistics_rx_non_phy rx_non_phy;
1406 struct statistics_rx_phy rx_ofdm;
1407 struct statistics_rx_ht_phy rx_ofdm_ht;
1408 struct statistics_rx_phy rx_cck;
1409 struct statistics_tx tx;
1410#ifdef CONFIG_IWLWIFI_DEBUGFS
1411 struct statistics_bt_activity bt_activity;
1412 __le32 num_bt_kills, accum_num_bt_kills;
1413#endif
1414 } statistics;
1415#ifdef CONFIG_IWLWIFI_DEBUGFS
1416 struct {
1417 struct statistics_general_common common;
1418 struct statistics_rx_non_phy rx_non_phy;
1419 struct statistics_rx_phy rx_ofdm;
1420 struct statistics_rx_ht_phy rx_ofdm_ht;
1421 struct statistics_rx_phy rx_cck;
1422 struct statistics_tx tx;
1423 struct statistics_bt_activity bt_activity;
1424 } accum_stats, delta_stats, max_delta_stats;
1425#endif
1426
3240cab3
JB
1427 struct {
1428 /* INT ICT Table */
1429 __le32 *ict_tbl;
1430 void *ict_tbl_vir;
1431 dma_addr_t ict_tbl_dma;
1432 dma_addr_t aligned_ict_tbl_dma;
1433 int ict_index;
1434 u32 inta;
1435 bool use_ict;
1436 /*
1437 * reporting the number of tids has AGG on. 0 means
1438 * no AGGREGATION
1439 */
1440 u8 agg_tids_count;
1441
1442 struct iwl_rx_phy_res last_phy_res;
1443 bool last_phy_res_valid;
1444
1445 struct completion firmware_loading_complete;
1446
1447 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1448 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1449
1450 /*
1451 * chain noise reset and gain commands are the
1452 * two extra calibration commands follows the standard
1453 * phy calibration commands
1454 */
1455 u8 phy_calib_chain_noise_reset_cmd;
1456 u8 phy_calib_chain_noise_gain_cmd;
1457
3240cab3
JB
1458 /* counts reply_tx error */
1459 struct reply_tx_error_statistics reply_tx_stats;
1460 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
3240cab3
JB
1461 /* notification wait support */
1462 struct list_head notif_waits;
1463 spinlock_t notif_wait_lock;
1464 wait_queue_head_t notif_waitq;
1465
1466 /* remain-on-channel offload support */
1467 struct ieee80211_channel *hw_roc_channel;
1468 struct delayed_work hw_roc_work;
1469 enum nl80211_channel_type hw_roc_chantype;
1470 int hw_roc_duration;
1471 bool hw_roc_setup;
1472
1473 struct sk_buff *offchan_tx_skb;
1474 int offchan_tx_timeout;
1475 struct ieee80211_channel *offchan_tx_chan;
1476 } _agn;
ee525d13 1477
22bf59a0 1478 /* bt coex */
f21dd005 1479 u8 bt_enable_flag;
da5dbb97 1480 u8 bt_status;
66e863a5 1481 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1482 bool bt_ch_announce;
bee008b7
WYG
1483 bool bt_full_concurrent;
1484 bool bt_ant_couple_ok;
fbba9410
WYG
1485 __le32 kill_ack_mask;
1486 __le32 kill_cts_mask;
1487 __le16 bt_valid;
22bf59a0
WYG
1488 u16 bt_on_thresh;
1489 u16 bt_duration;
1490 u16 dynamic_frag_thresh;
bee008b7 1491 u8 bt_ci_compliance;
9e4afc21
JB
1492 struct work_struct bt_traffic_change_work;
1493
5425e490 1494 struct iwl_hw_params hw_params;
4ddbb7d0 1495
40cefda9 1496 u32 inta_mask;
5d08cd1d 1497
5d08cd1d
CH
1498 struct workqueue_struct *workqueue;
1499
5d08cd1d 1500 struct work_struct restart;
5d08cd1d
CH
1501 struct work_struct scan_completed;
1502 struct work_struct rx_replenish;
5d08cd1d 1503 struct work_struct abort_scan;
12e934dc 1504
5d08cd1d 1505 struct work_struct beacon_update;
76d04815 1506 struct iwl_rxon_context *beacon_ctx;
12e934dc 1507 struct sk_buff *beacon_skb;
4ce7cc2b 1508 void *beacon_cmd;
76d04815 1509
a28027cd
WYG
1510 struct work_struct tt_work;
1511 struct work_struct ct_enter;
1512 struct work_struct ct_exit;
88be0264 1513 struct work_struct start_internal_scan;
65550636 1514 struct work_struct tx_flush;
bee008b7 1515 struct work_struct bt_full_concurrency;
fbba9410 1516 struct work_struct bt_runtime_config;
5d08cd1d
CH
1517
1518 struct tasklet_struct irq_tasklet;
1519
5d08cd1d 1520 struct delayed_work scan_check;
4a8a4322 1521
630fe9b6
TW
1522 /* TX Power */
1523 s8 tx_power_user_lmt;
dc1b0973 1524 s8 tx_power_device_lmt;
ae16fc3c 1525 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1526 s8 tx_power_next;
5d08cd1d 1527
5d08cd1d 1528
d08853a3 1529#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1530 /* debugging info */
3d816c77
RC
1531 u32 debug_level; /* per device debugging will override global
1532 iwl_debug_level if set */
d73e4923 1533#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1534#ifdef CONFIG_IWLWIFI_DEBUGFS
1535 /* debugfs */
20594eb0
WYG
1536 u16 tx_traffic_idx;
1537 u16 rx_traffic_idx;
1538 u8 *tx_traffic;
1539 u8 *rx_traffic;
4c84a8f1
JB
1540 struct dentry *debugfs_dir;
1541 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1542 bool disable_ht40;
712b6cf5 1543#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1544
1545 struct work_struct txpower_work;
445c2dff
TW
1546 u32 disable_sens_cal;
1547 u32 disable_chain_noise_cal;
16e727e8 1548 struct work_struct run_time_calib_work;
5d08cd1d 1549 struct timer_list statistics_periodic;
a9e1cb6a 1550 struct timer_list ucode_trace;
22de94de 1551 struct timer_list watchdog;
a9e1cb6a
WYG
1552
1553 struct iwl_event_log event_log;
5ed540ae
WYG
1554
1555 struct led_classdev led;
1556 unsigned long blink_on, blink_off;
1557 bool led_registered;
7a4e5281
WYG
1558#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1559 struct iwl_testmode_trace testmode_trace;
1560#endif
6489854b
WYG
1561 u32 dbg_fixed_rate;
1562
c79dd5b5 1563}; /*iwl_priv */
5d08cd1d 1564
36470749
RR
1565static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1566{
1567 set_bit(txq_id, &priv->txq_ctx_active_msk);
1568}
1569
1570static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1571{
1572 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1573}
1574
994d31f7 1575#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1576/*
1577 * iwl_get_debug_level: Return active debug level for device
1578 *
1579 * Using sysfs it is possible to set per device debug level. This debug
1580 * level will be used if set, otherwise the global debug level which can be
1581 * set via module parameter is used.
1582 */
1583static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1584{
1585 if (priv->debug_level)
1586 return priv->debug_level;
1587 else
1588 return iwl_debug_level;
1589}
a332f8d6 1590#else
3d816c77
RC
1591static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1592{
1593 return iwl_debug_level;
1594}
a332f8d6
TW
1595#endif
1596
1597
a332f8d6
TW
1598static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1599 int txq_id, int idx)
1600{
ff0d91c3 1601 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1602 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1603 txb[idx].skb->data;
a332f8d6
TW
1604 return NULL;
1605}
a332f8d6 1606
246ed355
JB
1607static inline struct iwl_rxon_context *
1608iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1609{
1610 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1611
1612 return vif_priv->ctx;
1613}
1614
1615#define for_each_context(priv, ctx) \
1616 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1617 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1618 if (priv->valid_contexts & BIT(ctx->ctxid))
1619
054ec924 1620static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
246ed355 1621{
054ec924 1622 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
246ed355
JB
1623}
1624
054ec924
JB
1625static inline int iwl_is_associated(struct iwl_priv *priv,
1626 enum iwl_rxon_context_id ctxid)
246ed355 1627{
054ec924 1628 return iwl_is_associated_ctx(&priv->contexts[ctxid]);
246ed355 1629}
a332f8d6 1630
054ec924 1631static inline int iwl_is_any_associated(struct iwl_priv *priv)
5d08cd1d 1632{
054ec924
JB
1633 struct iwl_rxon_context *ctx;
1634 for_each_context(priv, ctx)
1635 if (iwl_is_associated_ctx(ctx))
1636 return true;
1637 return false;
5d08cd1d
CH
1638}
1639
bf85ea4f 1640static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1641{
1642 if (ch_info == NULL)
1643 return 0;
1644 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1645}
1646
bf85ea4f 1647static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1648{
1649 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1650}
1651
bf85ea4f 1652static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1653{
8318d78a 1654 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1655}
1656
bf85ea4f 1657static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1658{
8318d78a 1659 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1660}
1661
bf85ea4f 1662static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1663{
1664 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1665}
1666
bf85ea4f 1667static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1668{
1669 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1670}
1671
64a76b50
ZY
1672static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1673{
1674 __free_pages(page, priv->hw_params.rx_page_order);
64a76b50
ZY
1675}
1676
1677static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1678{
1679 free_pages(page, priv->hw_params.rx_page_order);
64a76b50 1680}
be1f3ab6 1681#endif /* __iwl_dev_h__ */
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