iwlagn: remove un-necessary "_agn"
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 */
30
be1f3ab6
EG
31#ifndef __iwl_dev_h__
32#define __iwl_dev_h__
b481de9c 33
5d08cd1d
CH
34#include <linux/pci.h> /* for struct pci_device_id */
35#include <linux/kernel.h>
7194207c 36#include <linux/wait.h>
5ed540ae 37#include <linux/leds.h>
5d08cd1d
CH
38#include <net/ieee80211_radiotap.h>
39
6bc913bd 40#include "iwl-eeprom.h"
6f83eaa1 41#include "iwl-csr.h"
5d08cd1d 42#include "iwl-prph.h"
dbb6654c 43#include "iwl-fh.h"
0a6857e7 44#include "iwl-debug.h"
b744cb79 45#include "iwl-agn-hw.h"
ab53d8af 46#include "iwl-led.h"
5da4b55f 47#include "iwl-power.h"
e227ceac 48#include "iwl-agn-rs.h"
0975cc8f 49#include "iwl-agn-tt.h"
d5934110 50#include "iwl-bus.h"
41c50542 51#include "iwl-trans.h"
5d08cd1d 52
48d1a211
EG
53#define DRV_NAME "iwlagn"
54
672639de
WYG
55struct iwl_tx_queue;
56
099b40b7 57/* CT-KILL constants */
672639de
WYG
58#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
59#define CT_KILL_THRESHOLD 114 /* in Celsius */
60#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 61
5d08cd1d
CH
62/* Default noise level to report when noise measurement is not available.
63 * This may be because we're:
64 * 1) Not associated (4965, no beacon statistics being sent to driver)
65 * 2) Scanning (noise measurement does not apply to associated channel)
66 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
67 * Use default noise value of -127 ... this is below the range of measurable
68 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
69 * Also, -127 works better than 0 when averaging frames with/without
70 * noise info (e.g. averaging might be done in app); measured dBm values are
71 * always negative ... using a negative value as the default keeps all
72 * averages within an s8's (used in some apps) range of negative values. */
73#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
74
5d08cd1d
CH
75/*
76 * RTS threshold here is total size [2347] minus 4 FCS bytes
77 * Per spec:
78 * a value of 0 means RTS on all data/management packets
79 * a value > max MSDU size means no RTS
80 * else RTS for data/management frames where MPDU is larger
81 * than RTS value.
82 */
83#define DEFAULT_RTS_THRESHOLD 2347U
84#define MIN_RTS_THRESHOLD 0U
85#define MAX_RTS_THRESHOLD 2347U
86#define MAX_MSDU_SIZE 2304U
87#define MAX_MPDU_SIZE 2346U
51b7ef05 88#define DEFAULT_BEACON_INTERVAL 200U
5d08cd1d
CH
89#define DEFAULT_SHORT_RETRY_LIMIT 7U
90#define DEFAULT_LONG_RETRY_LIMIT 4U
91
a55360e4 92struct iwl_rx_mem_buffer {
2f301227
ZY
93 dma_addr_t page_dma;
94 struct page *page;
5d08cd1d
CH
95 struct list_head list;
96};
97
2f301227
ZY
98#define rxb_addr(r) page_address(r->page)
99
c2acea8e
JB
100/* defined below */
101struct iwl_device_cmd;
102
103struct iwl_cmd_meta {
104 /* only for SYNC commands, iff the reply skb is wanted */
105 struct iwl_host_cmd *source;
106 /*
107 * only for ASYNC commands
108 * (which is somewhat stupid -- look at iwl-sta.c for instance
109 * which duplicates a bunch of code because the callback isn't
110 * invoked for SYNC commands, if it were and its result passed
111 * through it would be simpler...)
112 */
5696aea6
JB
113 void (*callback)(struct iwl_priv *priv,
114 struct iwl_device_cmd *cmd,
2f301227 115 struct iwl_rx_packet *pkt);
c2acea8e 116
c2acea8e
JB
117 u32 flags;
118
2e724443
FT
119 DEFINE_DMA_UNMAP_ADDR(mapping);
120 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
121};
122
5d08cd1d
CH
123/*
124 * Generic queue structure
125 *
4ce7cc2b
JB
126 * Contains common data for Rx and Tx queues.
127 *
128 * Note the difference between n_bd and n_window: the hardware
129 * always assumes 256 descriptors, so n_bd is always 256 (unless
130 * there might be HW changes in the future). For the normal TX
131 * queues, n_window, which is the size of the software queue data
132 * is also 256; however, for the command queue, n_window is only
133 * 32 since we don't need so many commands pending. Since the HW
134 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
135 * the software buffers (in the variables @meta, @txb in struct
136 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
137 * in the same struct) have 256.
138 * This means that we end up with the following:
139 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
140 * SW entries: | 0 | ... | 31 |
141 * where N is a number between 0 and 7. This means that the SW
142 * data is a window overlayed over the HW queue.
5d08cd1d 143 */
443cfd45 144struct iwl_queue {
5d08cd1d
CH
145 int n_bd; /* number of BDs in this queue */
146 int write_ptr; /* 1-st empty entry (index) host_w*/
147 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 148 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
149 dma_addr_t dma_addr; /* physical addr for BD's */
150 int n_window; /* safe queue window */
151 u32 id;
152 int low_mark; /* low watermark, resume queue if free
153 * space more than this */
154 int high_mark; /* high watermark, stop queue if free
155 * space less than this */
a839cf69 156};
5d08cd1d 157
bc47279f 158/* One for each TFD */
8567c63e 159struct iwl_tx_info {
ff0d91c3 160 struct sk_buff *skb;
c90cbbbd 161 struct iwl_rxon_context *ctx;
5d08cd1d
CH
162};
163
164/**
16466903 165 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
166 * @q: generic Rx/Tx queue descriptor
167 * @bd: base of circular buffer of TFDs
c2acea8e
JB
168 * @cmd: array of command/TX buffer pointers
169 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
170 * @dma_addr_cmd: physical address of cmd/tx buffer array
171 * @txb: array of per-TFD driver data
22de94de 172 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
173 * @need_update: indicates need to update read/write index
174 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 175 *
bc47279f
BC
176 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
177 * descriptors) and required locking structures.
5d08cd1d 178 */
188cf6c7
SO
179#define TFD_TX_CMD_SLOTS 256
180#define TFD_CMD_SLOTS 32
181
16466903 182struct iwl_tx_queue {
443cfd45 183 struct iwl_queue q;
4ce7cc2b 184 struct iwl_tfd *tfds;
c2acea8e
JB
185 struct iwl_device_cmd **cmd;
186 struct iwl_cmd_meta *meta;
8567c63e 187 struct iwl_tx_info *txb;
22de94de 188 unsigned long time_stamp;
3fd07a1e
TW
189 u8 need_update;
190 u8 sched_retry;
191 u8 active;
192 u8 swq_id;
5d08cd1d
CH
193};
194
195#define IWL_NUM_SCAN_RATES (2)
196
5d08cd1d
CH
197/*
198 * One for each channel, holds all channel setup data
199 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
200 * with one another!
201 */
bf85ea4f 202struct iwl_channel_info {
073d3f5f 203 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
204 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
205 * HT40 channel */
5d08cd1d
CH
206
207 u8 channel; /* channel number */
208 u8 flags; /* flags copied from EEPROM */
209 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 210 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
211 s8 min_power; /* always 0 */
212 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
213
214 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
215 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 216 enum ieee80211_band band;
5d08cd1d 217
7aafef1c
WYG
218 /* HT40 channel info */
219 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
220 u8 ht40_flags; /* flags copied from EEPROM */
221 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
222};
223
751ca305 224#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 225#define IWL_TX_FIFO_BE 1
751ca305 226#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 227#define IWL_TX_FIFO_VO 3
751ca305
JB
228#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
229#define IWL_TX_FIFO_BE_IPAN 4
230#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
231#define IWL_TX_FIFO_VO_IPAN 5
edc1a3a0 232#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 233
01a7e084
RC
234/* Minimum number of queues. MAX_NUM is defined in hw specific files.
235 * Set the minimum to accommodate the 4 standard TX queues, 1 command
236 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
237#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 238
bd35f150 239/*
13bb9483 240 * Command queue depends on iPAN support.
bd35f150 241 */
13bb9483
JB
242#define IWL_DEFAULT_CMD_QUEUE_NUM 4
243#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 244
751ca305
JB
245/*
246 * This queue number is required for proper operation
247 * because the ucode will stop/start the scheduler as
248 * required.
249 */
250#define IWL_IPAN_MCAST_QUEUE 8
251
5d08cd1d
CH
252#define IEEE80211_DATA_LEN 2304
253#define IEEE80211_4ADDR_LEN 30
254#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
255#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
256
5d08cd1d 257
5d08cd1d
CH
258#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
259#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
260#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
261
262enum {
c587de0b 263 CMD_SYNC = 0,
e419d62d
EG
264 CMD_ASYNC = BIT(0),
265 CMD_WANT_SKB = BIT(1),
c7c1115b 266 CMD_ON_DEMAND = BIT(2),
5d08cd1d
CH
267};
268
c8c24872 269#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 270
bc47279f 271/**
c2acea8e 272 * struct iwl_device_cmd
bc47279f
BC
273 *
274 * For allocation of the command and tx queues, this establishes the overall
4ce7cc2b
JB
275 * size of the largest command we send to uCode, except for commands that
276 * aren't fully copied and use other TFD space.
bc47279f 277 */
c2acea8e 278struct iwl_device_cmd {
857485c0 279 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 280 union {
5d08cd1d
CH
281 u32 flags;
282 u8 val8;
283 u16 val16;
284 u32 val32;
83d527d9 285 struct iwl_tx_cmd tx;
c8c24872
WYG
286 struct iwl6000_channel_switch_cmd chswitch;
287 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
288 } __packed cmd;
289} __packed;
5d08cd1d 290
c2acea8e
JB
291#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
292
4ce7cc2b
JB
293#define IWL_MAX_CMD_TFDS 2
294
295enum iwl_hcmd_dataflag {
296 IWL_HCMD_DFL_NOCOPY = BIT(0),
297};
3257e5d4 298
e419d62d
EG
299/**
300 * struct iwl_host_cmd - Host command to the uCode
301 * @data: array of chunks that composes the data of the host command
302 * @reply_page: pointer to the page that holds the response to the host command
303 * @callback:
304 * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC
305 * @len: array of the lenths of the chunks in data
306 * @dataflags:
307 * @id: id of the host command
308 */
857485c0 309struct iwl_host_cmd {
3fa50738 310 const void *data[IWL_MAX_CMD_TFDS];
2f301227 311 unsigned long reply_page;
5696aea6
JB
312 void (*callback)(struct iwl_priv *priv,
313 struct iwl_device_cmd *cmd,
2f301227 314 struct iwl_rx_packet *pkt);
c2acea8e 315 u32 flags;
3fa50738 316 u16 len[IWL_MAX_CMD_TFDS];
4ce7cc2b 317 u8 dataflags[IWL_MAX_CMD_TFDS];
c2acea8e 318 u8 id;
5d08cd1d
CH
319};
320
5d08cd1d
CH
321#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
322#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
323#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
324
325/**
a55360e4 326 * struct iwl_rx_queue - Rx queue
df833b1d 327 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 328 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
329 * @read: Shared index to newest available Rx buffer
330 * @write: Shared index to oldest written Rx packet
331 * @free_count: Number of pre-allocated buffers in rx_free
332 * @rx_free: list of free SKBs for use
333 * @rx_used: List of Rx buffers with no SKB
334 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
335 * @rb_stts: driver's pointer to receive buffer status
336 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 337 *
a55360e4 338 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 339 */
a55360e4 340struct iwl_rx_queue {
5d08cd1d 341 __le32 *bd;
d5b25c90 342 dma_addr_t bd_dma;
a55360e4
TW
343 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
344 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
345 u32 read;
346 u32 write;
347 u32 free_count;
4752c93c 348 u32 write_actual;
5d08cd1d
CH
349 struct list_head rx_free;
350 struct list_head rx_used;
351 int need_update;
8d86422a
WT
352 struct iwl_rb_status *rb_stts;
353 dma_addr_t rb_stts_dma;
5d08cd1d
CH
354 spinlock_t lock;
355};
356
357#define IWL_SUPPORTED_RATES_IE_LEN 8
358
5d08cd1d
CH
359#define MAX_TID_COUNT 9
360
361#define IWL_INVALID_RATE 0xFF
362#define IWL_INVALID_VALUE -1
363
bc47279f 364/**
6def9761 365 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
366 * @txq_id: Tx queue used for Tx attempt
367 * @frame_count: # frames attempted by Tx command
368 * @wait_for_ba: Expect block-ack before next Tx reply
369 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
370 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
371 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
372 * @rate_n_flags: Rate at which Tx was attempted
373 *
374 * If REPLY_TX indicates that aggregation was attempted, driver must wait
375 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
376 * until block ack arrives.
377 */
6def9761 378struct iwl_ht_agg {
5d08cd1d
CH
379 u16 txq_id;
380 u16 frame_count;
381 u16 wait_for_ba;
382 u16 start_idx;
fe01b477 383 u64 bitmap;
5d08cd1d 384 u32 rate_n_flags;
fe01b477
RR
385#define IWL_AGG_OFF 0
386#define IWL_AGG_ON 1
387#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
388#define IWL_EMPTYING_HW_QUEUE_DELBA 3
389 u8 state;
c8823ec1 390 u8 tx_fifo;
5d08cd1d 391};
fe01b477 392
5d08cd1d 393
6def9761 394struct iwl_tid_data {
f862a236 395 u16 seq_number; /* agn only */
fe01b477 396 u16 tfds_in_queue;
6def9761 397 struct iwl_ht_agg agg;
5d08cd1d
CH
398};
399
a78fe754 400union iwl_ht_rate_supp {
5d08cd1d
CH
401 u16 rates;
402 struct {
403 u8 siso_rate;
404 u8 mimo_rate;
405 };
406};
407
172c1d11
WYG
408#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
409#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
410#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
411#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
412#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
413#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
414#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
415
416/*
417 * Maximal MPDU density for TX aggregation
418 * 4 - 2us density
419 * 5 - 4us density
420 * 6 - 8us density
421 * 7 - 16us density
422 */
172c1d11 423#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 424#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
425#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
426#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 427#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
428#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
429#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 430
fad95bf5 431struct iwl_ht_config {
02bb1bea 432 bool single_chain_sufficient;
ba37a3d0 433 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 434};
5d08cd1d 435
5d08cd1d 436/* QoS structures */
1ff50bda 437struct iwl_qos_info {
5d08cd1d 438 int qos_active;
1ff50bda 439 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 440};
5d08cd1d 441
fe6b23dd
RC
442/*
443 * Structure should be accessed with sta_lock held. When station addition
444 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
445 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
446 * held.
447 */
6def9761 448struct iwl_station_entry {
133636de 449 struct iwl_addsta_cmd sta;
6def9761 450 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 451 u8 used, ctxid;
fe6b23dd 452 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
453};
454
fd1af15d 455struct iwl_station_priv_common {
238d781d 456 struct iwl_rxon_context *ctx;
fd1af15d
JB
457 u8 sta_id;
458};
459
8d9698b3
RC
460/*
461 * iwl_station_priv: Driver's private station information
462 *
463 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
464 * in the structure for use by driver. This structure is places in that
465 * space.
8d9698b3
RC
466 */
467struct iwl_station_priv {
fd1af15d 468 struct iwl_station_priv_common common;
8d9698b3 469 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
470 atomic_t pending_frames;
471 bool client;
472 bool asleep;
7b090687 473 u8 max_agg_bufsize;
8d9698b3
RC
474};
475
fd1af15d
JB
476/**
477 * struct iwl_vif_priv - driver's private per-interface information
478 *
479 * When mac80211 allocates a virtual interface, it can allocate
480 * space for us to put data into.
481 */
482struct iwl_vif_priv {
246ed355 483 struct iwl_rxon_context *ctx;
fd1af15d
JB
484 u8 ibss_bssid_sta_id;
485};
486
5d08cd1d
CH
487/* one for each uCode image (inst/data, boot/init/runtime) */
488struct fw_desc {
489 void *v_addr; /* access by driver */
490 dma_addr_t p_addr; /* access by card's busmaster DMA */
491 u32 len; /* bytes */
492};
493
dbf28e21
JB
494struct fw_img {
495 struct fw_desc code, data;
496};
497
dd7a2509 498/* v1/v2 uCode file layout */
cc0f555d
JS
499struct iwl_ucode_header {
500 __le32 ver; /* major/minor/API/serial */
501 union {
502 struct {
503 __le32 inst_size; /* bytes of runtime code */
504 __le32 data_size; /* bytes of runtime data */
505 __le32 init_size; /* bytes of init code */
506 __le32 init_data_size; /* bytes of init data */
507 __le32 boot_size; /* bytes of bootstrap code */
508 u8 data[0]; /* in same order as sizes */
509 } v1;
510 struct {
511 __le32 build; /* build number */
512 __le32 inst_size; /* bytes of runtime code */
513 __le32 data_size; /* bytes of runtime data */
514 __le32 init_size; /* bytes of init code */
515 __le32 init_data_size; /* bytes of init data */
516 __le32 boot_size; /* bytes of bootstrap code */
517 u8 data[0]; /* in same order as sizes */
518 } v2;
519 } u;
5d08cd1d
CH
520};
521
dd7a2509
JB
522/*
523 * new TLV uCode file layout
524 *
525 * The new TLV file format contains TLVs, that each specify
526 * some piece of data. To facilitate "groups", for example
527 * different instruction image with different capabilities,
528 * bundled with the same init image, an alternative mechanism
529 * is provided:
530 * When the alternative field is 0, that means that the item
531 * is always valid. When it is non-zero, then it is only
532 * valid in conjunction with items of the same alternative,
533 * in which case the driver (user) selects one alternative
534 * to use.
535 */
536
537enum iwl_ucode_tlv_type {
538 IWL_UCODE_TLV_INVALID = 0, /* unused */
539 IWL_UCODE_TLV_INST = 1,
540 IWL_UCODE_TLV_DATA = 2,
541 IWL_UCODE_TLV_INIT = 3,
542 IWL_UCODE_TLV_INIT_DATA = 4,
543 IWL_UCODE_TLV_BOOT = 5,
544 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 545 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
546 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
547 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
548 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
549 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
550 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
551 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 552 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 553 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
3997ff39
JB
554 /* 16 and 17 reserved for future use */
555 IWL_UCODE_TLV_FLAGS = 18,
556};
557
558/**
559 * enum iwl_ucode_tlv_flag - ucode API flags
560 * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
561 * was a separate TLV but moved here to save space.
d2690c0d
JB
562 * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
563 * treats good CRC threshold as a boolean
3997ff39
JB
564 * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
565 */
566enum iwl_ucode_tlv_flag {
567 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
d2690c0d 568 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
3997ff39 569 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
dd7a2509
JB
570};
571
572struct iwl_ucode_tlv {
573 __le16 type; /* see above */
574 __le16 alternative; /* see comment */
575 __le32 length; /* not including type/length fields */
576 u8 data[0];
ba2d3587 577} __packed;
dd7a2509
JB
578
579#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
580
581struct iwl_tlv_ucode_header {
582 /*
583 * The TLV style ucode header is distinguished from
584 * the v1/v2 style header by first four bytes being
585 * zero, as such is an invalid combination of
586 * major/minor/API/serial versions.
587 */
588 __le32 zero;
589 __le32 magic;
590 u8 human_readable[64];
591 __le32 ver; /* major/minor/API/serial */
592 __le32 build;
593 __le64 alternatives; /* bitmask of valid alternatives */
594 /*
595 * The data contained herein has a TLV layout,
596 * see above for the TLV header and types.
597 * Note that each TLV is padded to a length
598 * that is a multiple of 4 for alignment.
599 */
600 u8 data[0];
601};
602
f0832f13
EG
603struct iwl_sensitivity_ranges {
604 u16 min_nrg_cck;
605 u16 max_nrg_cck;
606
607 u16 nrg_th_cck;
608 u16 nrg_th_ofdm;
609
610 u16 auto_corr_min_ofdm;
611 u16 auto_corr_min_ofdm_mrc;
612 u16 auto_corr_min_ofdm_x1;
613 u16 auto_corr_min_ofdm_mrc_x1;
614
615 u16 auto_corr_max_ofdm;
616 u16 auto_corr_max_ofdm_mrc;
617 u16 auto_corr_max_ofdm_x1;
618 u16 auto_corr_max_ofdm_mrc_x1;
619
620 u16 auto_corr_max_cck;
621 u16 auto_corr_max_cck_mrc;
622 u16 auto_corr_min_cck;
623 u16 auto_corr_min_cck_mrc;
55036d66
WYG
624
625 u16 barker_corr_th_min;
626 u16 barker_corr_th_min_mrc;
627 u16 nrg_th_cca;
f0832f13
EG
628};
629
099b40b7 630
b5047f78
TW
631#define KELVIN_TO_CELSIUS(x) ((x)-273)
632#define CELSIUS_TO_KELVIN(x) ((x)+273)
633
634
bc47279f 635/**
5425e490 636 * struct iwl_hw_params
bc47279f 637 * @max_txq_num: Max # Tx queues supported
4ddbb7d0 638 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 639 * @tfd_size: TFD size
099b40b7
RR
640 * @tx/rx_chains_num: Number of TX/RX chains
641 * @valid_tx/rx_ant: usable antennas
bc47279f 642 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 643 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 644 * @rx_page_order: Rx buffer page order
141c43a3 645 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 646 * @max_stations:
7aafef1c 647 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
648 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
649 * @sw_crypto: 0 for hw, 1 for sw
650 * @max_xxx_size: for ucode uses
651 * @ct_kill_threshold: temperature threshold
a0ee74cf 652 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 653 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 654 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 655 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 656 */
5425e490 657struct iwl_hw_params {
f3f911d1 658 u8 max_txq_num;
4ddbb7d0 659 u16 scd_bc_tbls_size;
a8e74e27 660 u32 tfd_size;
ec35cf2a
TW
661 u8 tx_chains_num;
662 u8 rx_chains_num;
663 u8 valid_tx_ant;
664 u8 valid_rx_ant;
5d08cd1d 665 u16 max_rxq_size;
ec35cf2a 666 u16 max_rxq_log;
2f301227 667 u32 rx_page_order;
5d08cd1d 668 u8 max_stations;
7aafef1c 669 u8 ht40_channel;
2c2f3b33 670 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
671 u32 max_inst_size;
672 u32 max_data_size;
099b40b7 673 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
674 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
675 /* for 1000, 6000 series and up */
a0ee74cf 676 u16 beacon_time_tsf_bits;
be5d56ed 677 u32 calib_init_cfg;
6d6a1afd 678 u32 calib_rt_cfg;
f0832f13 679 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
680};
681
5d08cd1d 682
5d08cd1d
CH
683/******************************************************************************
684 *
a33c2f47
EG
685 * Functions implemented in core module which are forward declared here
686 * for use by iwl-[4-5].c
5d08cd1d 687 *
a33c2f47
EG
688 * NOTE: The implementation of these functions are not hardware specific
689 * which is why they are in the core module files.
5d08cd1d
CH
690 *
691 * Naming convention --
a33c2f47 692 * iwl_ <-- Is part of iwlwifi
5d08cd1d 693 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
5d08cd1d
CH
694 *
695 ****************************************************************************/
5b9f8cd3 696extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 697extern const u8 iwl_bcast_addr[ETH_ALEN];
443cfd45 698extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
699static inline int iwl_queue_used(const struct iwl_queue *q, int i)
700{
c8106d76 701 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
702 (i >= q->read_ptr && i < q->write_ptr) :
703 !(i < q->read_ptr && i >= q->write_ptr);
704}
705
706
4ce7cc2b 707static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
fd4abac5 708{
fd4abac5
TW
709 return index & (q->n_window - 1);
710}
711
712
4ddbb7d0
TW
713struct iwl_dma_ptr {
714 dma_addr_t dma;
715 void *addr;
b481de9c
ZY
716 size_t size;
717};
718
b481de9c
ZY
719#define IWL_OPERATION_MODE_AUTO 0
720#define IWL_OPERATION_MODE_HT_ONLY 1
721#define IWL_OPERATION_MODE_MIXED 2
722#define IWL_OPERATION_MODE_20MHZ 3
723
3195cdb7
TW
724#define IWL_TX_CRC_SIZE 4
725#define IWL_TX_DELIMITER_SIZE 4
b481de9c 726
b481de9c 727#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 728
b481de9c 729/* Sensitivity and chain noise calibration */
b481de9c 730#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a 731#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
732#define MAXIMUM_ALLOWED_PATHLOSS 15
733
b481de9c
ZY
734#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
735
736#define MAX_FA_OFDM 50
737#define MIN_FA_OFDM 5
738#define MAX_FA_CCK 50
739#define MIN_FA_CCK 5
740
b481de9c
ZY
741#define AUTO_CORR_STEP_OFDM 1
742
b481de9c
ZY
743#define AUTO_CORR_STEP_CCK 3
744#define AUTO_CORR_MAX_TH_CCK 160
745
b481de9c
ZY
746#define NRG_DIFF 2
747#define NRG_STEP_CCK 2
748#define NRG_MARGIN 8
749#define MAX_NUMBER_CCK_NO_FA 100
750
751#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
752
753#define CHAIN_A 0
754#define CHAIN_B 1
755#define CHAIN_C 2
756#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
757#define ALL_BAND_FILTER 0xFF00
758#define IN_BAND_FILTER 0xFF
759#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
760
3195cdb7
TW
761#define NRG_NUM_PREV_STAT_L 20
762#define NUM_RX_CHAINS 3
763
3240cab3 764enum iwlagn_false_alarm_state {
b481de9c
ZY
765 IWL_FA_TOO_MANY = 0,
766 IWL_FA_TOO_FEW = 1,
767 IWL_FA_GOOD_RANGE = 2,
768};
769
3240cab3 770enum iwlagn_chain_noise_state {
b481de9c 771 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
772 IWL_CHAIN_NOISE_ACCUMULATE,
773 IWL_CHAIN_NOISE_CALIBRATED,
774 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
775};
776
f69f42a6
TW
777
778/*
779 * enum iwl_calib
780 * defines the order in which results of initial calibrations
781 * should be sent to the runtime uCode
782 */
783enum iwl_calib {
784 IWL_CALIB_XTAL,
819500c5 785 IWL_CALIB_DC,
f69f42a6
TW
786 IWL_CALIB_LO,
787 IWL_CALIB_TX_IQ,
788 IWL_CALIB_TX_IQ_PERD,
201706ac 789 IWL_CALIB_BASE_BAND,
bf53f939 790 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
791 IWL_CALIB_MAX
792};
793
6e21f2c1
TW
794/* Opaque calibration results */
795struct iwl_calib_result {
796 void *buf;
797 size_t buf_len;
7c616cba
TW
798};
799
b481de9c 800/* Sensitivity calib data */
f0832f13 801struct iwl_sensitivity_data {
b481de9c
ZY
802 u32 auto_corr_ofdm;
803 u32 auto_corr_ofdm_mrc;
804 u32 auto_corr_ofdm_x1;
805 u32 auto_corr_ofdm_mrc_x1;
806 u32 auto_corr_cck;
807 u32 auto_corr_cck_mrc;
808
809 u32 last_bad_plcp_cnt_ofdm;
810 u32 last_fa_cnt_ofdm;
811 u32 last_bad_plcp_cnt_cck;
812 u32 last_fa_cnt_cck;
813
814 u32 nrg_curr_state;
815 u32 nrg_prev_state;
816 u32 nrg_value[10];
817 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
818 u32 nrg_silence_ref;
819 u32 nrg_energy_idx;
820 u32 nrg_silence_idx;
821 u32 nrg_th_cck;
822 s32 nrg_auto_corr_silence_diff;
823 u32 num_in_cck_no_fa;
824 u32 nrg_th_ofdm;
55036d66
WYG
825
826 u16 barker_corr_th_min;
827 u16 barker_corr_th_min_mrc;
828 u16 nrg_th_cca;
b481de9c
ZY
829};
830
831/* Chain noise (differential Rx gain) calib data */
f0832f13 832struct iwl_chain_noise_data {
04816448 833 u32 active_chains;
b481de9c
ZY
834 u32 chain_noise_a;
835 u32 chain_noise_b;
836 u32 chain_noise_c;
837 u32 chain_signal_a;
838 u32 chain_signal_b;
839 u32 chain_signal_c;
04816448 840 u16 beacon_count;
b481de9c
ZY
841 u8 disconn_array[NUM_RX_CHAINS];
842 u8 delta_gain_code[NUM_RX_CHAINS];
843 u8 radio_write;
04816448 844 u8 state;
b481de9c
ZY
845};
846
abceddb4
BC
847#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
848#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 849
20594eb0
WYG
850#define IWL_TRAFFIC_ENTRIES (256)
851#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 852
5d08cd1d
CH
853enum {
854 MEASUREMENT_READY = (1 << 0),
855 MEASUREMENT_ACTIVE = (1 << 1),
856};
857
0848e297
WYG
858enum iwl_nvm_type {
859 NVM_DEVICE_TYPE_EEPROM = 0,
860 NVM_DEVICE_TYPE_OTP,
861};
862
415e4993
WYG
863/*
864 * Two types of OTP memory access modes
865 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
866 * based on physical memory addressing
867 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
868 * based on logical memory addressing
869 */
870enum iwl_access_mode {
871 IWL_OTP_ACCESS_ABSOLUTE,
872 IWL_OTP_ACCESS_RELATIVE,
873};
65b7998a
WYG
874
875/**
876 * enum iwl_pa_type - Power Amplifier type
877 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
878 * @IWL_PA_INTERNAL: use Internal only
879 */
880enum iwl_pa_type {
881 IWL_PA_SYSTEM = 0,
740e7f51 882 IWL_PA_INTERNAL = 1,
65b7998a
WYG
883};
884
a83b9141
WYG
885/* interrupt statistics */
886struct isr_statistics {
887 u32 hw;
888 u32 sw;
6e6ebf4b 889 u32 err_code;
a83b9141
WYG
890 u32 sch;
891 u32 alive;
892 u32 rfkill;
893 u32 ctkill;
894 u32 wakeup;
895 u32 rx;
896 u32 rx_handlers[REPLY_MAX];
897 u32 tx;
898 u32 unhandled;
899};
5d08cd1d 900
91835ba4
WYG
901/* reply_tx_statistics (for _agn devices) */
902struct reply_tx_error_statistics {
903 u32 pp_delay;
904 u32 pp_few_bytes;
905 u32 pp_bt_prio;
906 u32 pp_quiet_period;
907 u32 pp_calc_ttak;
908 u32 int_crossed_retry;
909 u32 short_limit;
910 u32 long_limit;
911 u32 fifo_underrun;
912 u32 drain_flow;
913 u32 rfkill_flush;
914 u32 life_expire;
915 u32 dest_ps;
916 u32 host_abort;
917 u32 bt_retry;
918 u32 sta_invalid;
919 u32 frag_drop;
920 u32 tid_disable;
921 u32 fifo_flush;
922 u32 insuff_cf_poll;
923 u32 fail_hw_drop;
924 u32 sta_color_mismatch;
925 u32 unknown;
926};
927
814665fe
WYG
928/* reply_agg_tx_statistics (for _agn devices) */
929struct reply_agg_tx_error_statistics {
930 u32 underrun;
931 u32 bt_prio;
932 u32 few_bytes;
933 u32 abort;
934 u32 last_sent_ttl;
935 u32 last_sent_try;
936 u32 last_sent_bt_kill;
937 u32 scd_query;
938 u32 bad_crc32;
939 u32 response;
940 u32 dump_tx;
941 u32 delay_tx;
942 u32 unknown;
943};
944
22fdf3c9
WYG
945/* management statistics */
946enum iwl_mgmt_stats {
947 MANAGEMENT_ASSOC_REQ = 0,
948 MANAGEMENT_ASSOC_RESP,
949 MANAGEMENT_REASSOC_REQ,
950 MANAGEMENT_REASSOC_RESP,
951 MANAGEMENT_PROBE_REQ,
952 MANAGEMENT_PROBE_RESP,
953 MANAGEMENT_BEACON,
954 MANAGEMENT_ATIM,
955 MANAGEMENT_DISASSOC,
956 MANAGEMENT_AUTH,
957 MANAGEMENT_DEAUTH,
958 MANAGEMENT_ACTION,
959 MANAGEMENT_MAX,
960};
961/* control statistics */
962enum iwl_ctrl_stats {
963 CONTROL_BACK_REQ = 0,
964 CONTROL_BACK,
965 CONTROL_PSPOLL,
966 CONTROL_RTS,
967 CONTROL_CTS,
968 CONTROL_ACK,
969 CONTROL_CFEND,
970 CONTROL_CFENDACK,
971 CONTROL_MAX,
972};
973
974struct traffic_stats {
5ed540ae 975#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
976 u32 mgmt[MANAGEMENT_MAX];
977 u32 ctrl[CONTROL_MAX];
978 u32 data_cnt;
979 u64 data_bytes;
22fdf3c9 980#endif
5ed540ae 981};
22fdf3c9 982
a9e1cb6a
WYG
983/*
984 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
985 * to perform continuous uCode event logging operation if enabled
986 */
987#define UCODE_TRACE_PERIOD (100)
988
989/*
990 * iwl_event_log: current uCode event log position
991 *
992 * @ucode_trace: enable/disable ucode continuous trace timer
993 * @num_wraps: how many times the event buffer wraps
994 * @next_entry: the entry just before the next one that uCode would fill
995 * @non_wraps_count: counter for no wrap detected when dump ucode events
996 * @wraps_once_count: counter for wrap once detected when dump ucode events
997 * @wraps_more_count: counter for wrap more than once detected
998 * when dump ucode events
999 */
1000struct iwl_event_log {
1001 bool ucode_trace;
1002 u32 num_wraps;
1003 u32 next_entry;
1004 int non_wraps_count;
1005 int wraps_once_count;
1006 int wraps_more_count;
1007};
1008
2be76703
WYG
1009/*
1010 * host interrupt timeout value
1011 * used with setting interrupt coalescing timer
1012 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1013 *
1014 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1015 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1016 */
1017#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1018#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1019#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1020#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1021#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1022#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1023
3e4fb5fa
TAN
1024/*
1025 * This is the threshold value of plcp error rate per 100mSecs. It is
1026 * used to set and check for the validity of plcp_delta.
1027 */
680788ac 1028#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1029#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1030#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1031#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1032#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1033#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1034
8a472da4
WYG
1035#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1036#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1037
22de94de
SG
1038/* TX queue watchdog timeouts in mSecs */
1039#define IWL_DEF_WD_TIMEOUT (2000)
1040#define IWL_LONG_WD_TIMEOUT (10000)
1041#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1042
bee008b7
WYG
1043/* BT Antenna Coupling Threshold (dB) */
1044#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1045
491bc292
WYG
1046/* Firmware reload counter and Timestamp */
1047#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1048#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1049
1050
a93e7973
WYG
1051enum iwl_reset {
1052 IWL_RF_RESET = 0,
1053 IWL_FW_RESET,
8a472da4
WYG
1054 IWL_MAX_FORCE_RESET,
1055};
1056
1057struct iwl_force_reset {
1058 int reset_request_count;
1059 int reset_success_count;
1060 int reset_reject_count;
1061 unsigned long reset_duration;
1062 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1063};
1064
a0ee74cf 1065/* extend beacon time format bit shifting */
a0ee74cf
WYG
1066/*
1067 * for _agn devices
1068 * bits 31:22 - extended
1069 * bits 21:0 - interval
1070 */
1071#define IWLAGN_EXT_BEACON_TIME_POS 22
1072
7194207c
JB
1073/**
1074 * struct iwl_notification_wait - notification wait entry
1075 * @list: list head for global list
1076 * @fn: function called with the notification
1077 * @cmd: command ID
1078 *
1079 * This structure is not used directly, to wait for a
1080 * notification declare it on the stack, and call
1081 * iwlagn_init_notification_wait() with appropriate
1082 * parameters. Then do whatever will cause the ucode
1083 * to notify the driver, and to wait for that then
1084 * call iwlagn_wait_notification().
1085 *
1086 * Each notification is one-shot. If at some point we
1087 * need to support multi-shot notifications (which
1088 * can't be allocated on the stack) we need to modify
1089 * the code for them.
1090 */
1091struct iwl_notification_wait {
1092 struct list_head list;
1093
09f18afe
JB
1094 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt,
1095 void *data);
1096 void *fn_data;
7194207c
JB
1097
1098 u8 cmd;
e74fe233 1099 bool triggered, aborted;
7194207c
JB
1100};
1101
246ed355
JB
1102enum iwl_rxon_context_id {
1103 IWL_RXON_CTX_BSS,
ece9c4ee 1104 IWL_RXON_CTX_PAN,
246ed355
JB
1105
1106 NUM_IWL_RXON_CTX
1107};
1108
1109struct iwl_rxon_context {
8bd413e6 1110 struct ieee80211_vif *vif;
e72f368b
JB
1111
1112 const u8 *ac_to_fifo;
1113 const u8 *ac_to_queue;
1114 u8 mcast_queue;
1115
763cc3bf
JB
1116 /*
1117 * We could use the vif to indicate active, but we
1118 * also need it to be active during disabling when
1119 * we already removed the vif for type setting.
1120 */
1121 bool always_active, is_active;
1122
2295c66b
JB
1123 bool ht_need_multiple_chains;
1124
246ed355 1125 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1126
1127 u32 interface_modes, exclusive_interface_modes;
1128 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1129
246ed355
JB
1130 /*
1131 * We declare this const so it can only be
1132 * changed via explicit cast within the
1133 * routines that actually update the physical
1134 * hardware.
1135 */
1136 const struct iwl_rxon_cmd active;
1137 struct iwl_rxon_cmd staging;
1138
1139 struct iwl_rxon_time_cmd timing;
a194e324 1140
8dfdb9d5
JB
1141 struct iwl_qos_info qos_data;
1142
2995bafa 1143 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1144
1145 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1146 u8 qos_cmd;
c10afb6e
JB
1147 u8 wep_key_cmd;
1148
1149 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1150 u8 key_mapping_keys;
770e13bd
JB
1151
1152 __le32 station_flags;
7e6a5886
JB
1153
1154 struct {
1155 bool non_gf_sta_present;
1156 u8 protection;
1157 bool enabled, is_40mhz;
1158 u8 extension_chan_offset;
1159 } ht;
68b99311
GT
1160
1161 bool last_tx_rejected;
246ed355
JB
1162};
1163
266af4c7
JB
1164enum iwl_scan_type {
1165 IWL_SCAN_NORMAL,
1166 IWL_SCAN_RADIO_RESET,
1167 IWL_SCAN_OFFCH_TX,
1168};
1169
872907bb
JB
1170enum iwlagn_ucode_type {
1171 IWL_UCODE_NONE,
1172 IWL_UCODE_REGULAR,
1173 IWL_UCODE_INIT,
1174 IWL_UCODE_WOWLAN,
1175};
1176
7a4e5281
WYG
1177#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1178struct iwl_testmode_trace {
49b72100
WYG
1179 u32 buff_size;
1180 u32 total_size;
eb64dca0 1181 u32 num_chunks;
7a4e5281
WYG
1182 u8 *cpu_addr;
1183 u8 *trace_addr;
1184 dma_addr_t dma_addr;
1185 bool trace_enabled;
1186};
1187#endif
a48709c5 1188
e98a1939
WYG
1189/* uCode ownership */
1190#define IWL_OWNERSHIP_DRIVER 0
1191#define IWL_OWNERSHIP_TM 1
1192
c79dd5b5 1193struct iwl_priv {
5d08cd1d
CH
1194
1195 /* ieee device used by generic ieee processing code */
1196 struct ieee80211_hw *hw;
1197 struct ieee80211_channel *ieee_channels;
1198 struct ieee80211_rate *ieee_rates;
82b9a121 1199 struct iwl_cfg *cfg;
5d08cd1d 1200
8318d78a 1201 enum ieee80211_band band;
5d08cd1d 1202
4613e72d
CK
1203 void (*pre_rx_handler)(struct iwl_priv *priv,
1204 struct iwl_rx_mem_buffer *rxb);
c79dd5b5 1205 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1206 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1207
8318d78a 1208 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1209
5d08cd1d 1210 /* spectrum measurement report caching */
2aa6ab86 1211 struct iwl_spectrum_notification measure_report;
5d08cd1d 1212 u8 measurement_status;
81963d68 1213
5d08cd1d
CH
1214 /* ucode beacon time */
1215 u32 ucode_beacon_time;
a13d276f 1216 int missed_beacon_threshold;
5d08cd1d 1217
a85d7cca
JB
1218 /* track IBSS manager (last beacon) status */
1219 u32 ibss_manager;
1220
410f2bb3
SG
1221 /* jiffies when last recovery from statistics was performed */
1222 unsigned long rx_statistics_jiffies;
3e4fb5fa 1223
a93e7973 1224 /* force reset */
8a472da4 1225 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1226
491bc292
WYG
1227 /* firmware reload counter and timestamp */
1228 unsigned long reload_jiffies;
1229 int reload_count;
1230
5a2a780c 1231 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1232 * Access via channel # using indirect index array */
bf85ea4f 1233 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1234 u8 channel_count; /* # of channels */
1235
5d08cd1d
CH
1236 /* thermal calibration */
1237 s32 temperature; /* degrees Kelvin */
1238 s32 last_temperature;
1239
7c616cba 1240 /* init calibration results */
6e21f2c1 1241 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1242
5d08cd1d 1243 /* Scan related variables */
5d08cd1d 1244 unsigned long scan_start;
5d08cd1d 1245 unsigned long scan_start_tsf;
811ecc99 1246 void *scan_cmd;
00700ee0 1247 enum ieee80211_band scan_band;
1ecf9fc1 1248 struct cfg80211_scan_request *scan_request;
f84b29ec 1249 struct ieee80211_vif *scan_vif;
266af4c7 1250 enum iwl_scan_type scan_type;
76eff18b
TW
1251 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1252 u8 mgmt_tx_ant;
5d08cd1d
CH
1253
1254 /* spinlock */
1255 spinlock_t lock; /* protect general shared data */
1256 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1257 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d
CH
1258 struct mutex mutex;
1259
d5934110 1260 struct iwl_bus *bus; /* bus specific data */
c85eb619 1261 struct iwl_trans trans;
a48709c5 1262
246ed355
JB
1263 /* microcode/device supports multiple contexts */
1264 u8 valid_contexts;
1265
13bb9483
JB
1266 /* command queue number */
1267 u8 cmd_queue;
1268
c10afb6e
JB
1269 /* max number of station keys */
1270 u8 sta_key_max_num;
1271
d2690c0d
JB
1272 bool new_scan_threshold_behaviour;
1273
c6fa17ed
WYG
1274 /* EEPROM MAC addresses */
1275 struct mac_address addresses[2];
1276
5d08cd1d 1277 /* uCode images, save to reload in case of failure */
b08dfd04 1278 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1279 u32 ucode_ver; /* version of ucode, copy of
1280 iwl_ucode.ver */
e98a1939
WYG
1281
1282 /* uCode owner: default: IWL_OWNERSHIP_DRIVER */
1283 u8 ucode_owner;
1284
dbf28e21
JB
1285 struct fw_img ucode_rt;
1286 struct fw_img ucode_init;
1287
872907bb 1288 enum iwlagn_ucode_type ucode_type;
dbb983b7 1289 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1290 char firmware_name[25];
5d08cd1d 1291
246ed355 1292 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1293
6f213ff1 1294 __le16 switch_channel;
0924e519 1295
d7d5783c
JB
1296 struct {
1297 u32 error_event_table;
1298 u32 log_event_table;
1299 } device_pointers;
5d08cd1d 1300
5d08cd1d 1301 u16 active_rate;
5d08cd1d 1302
5d08cd1d 1303 u8 start_calib;
f0832f13
EG
1304 struct iwl_sensitivity_data sensitivity_data;
1305 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1306 bool enhance_sensitivity_table;
5d08cd1d 1307 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1308 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1309
fad95bf5 1310 struct iwl_ht_config current_ht_config;
5d08cd1d 1311
5d08cd1d 1312 /* Rate scaling data */
5d08cd1d
CH
1313 u8 retry_rate;
1314
1315 wait_queue_head_t wait_command_queue;
1316
1317 int activity_timer_active;
1318
1319 /* Rx and Tx DMA processing queues */
a55360e4 1320 struct iwl_rx_queue rxq;
88804e2b 1321 struct iwl_tx_queue *txq;
5d08cd1d 1322 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1323 struct iwl_dma_ptr kw; /* keep warm address */
1324 struct iwl_dma_ptr scd_bc_tbls;
1325
5d08cd1d
CH
1326 u32 scd_base_addr; /* scheduler sram base address */
1327
1328 unsigned long status;
5d08cd1d 1329
19758bef 1330 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1331 struct traffic_stats tx_stats;
1332 struct traffic_stats rx_stats;
19758bef 1333
a83b9141
WYG
1334 /* counts interrupts */
1335 struct isr_statistics isr_stats;
1336
5da4b55f 1337 struct iwl_power_mgr power_data;
3ad3b92a 1338 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1339
9c5ac091
RC
1340 /* station table variables */
1341
1342 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1343 spinlock_t sta_lock;
1344 int num_stations;
3240cab3 1345 struct iwl_station_entry stations[IWLAGN_STATION_COUNT];
80fb47a1 1346 unsigned long ucode_key_table;
5d08cd1d 1347
e4e72fb4
JB
1348 /* queue refcounts */
1349#define IWL_MAX_HW_QUEUES 32
1350 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1351 /* for each AC */
1352 atomic_t queue_stop_count[4];
1353
5d08cd1d 1354 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1355 u8 is_open;
5d08cd1d
CH
1356
1357 u8 mac80211_registered;
5d08cd1d 1358
af6b8ee3 1359 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1360 u8 *eeprom;
0848e297 1361 int nvm_device_type;
073d3f5f 1362 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1363
05c914fe 1364 enum nl80211_iftype iw_mode;
5d08cd1d 1365
5d08cd1d 1366 /* Last Rx'd beacon timestamp */
3109ece1 1367 u64 timestamp;
5d08cd1d 1368
0da0e5bf
JB
1369 struct {
1370 __le32 flag;
1371 struct statistics_general_common common;
1372 struct statistics_rx_non_phy rx_non_phy;
1373 struct statistics_rx_phy rx_ofdm;
1374 struct statistics_rx_ht_phy rx_ofdm_ht;
1375 struct statistics_rx_phy rx_cck;
1376 struct statistics_tx tx;
1377#ifdef CONFIG_IWLWIFI_DEBUGFS
1378 struct statistics_bt_activity bt_activity;
1379 __le32 num_bt_kills, accum_num_bt_kills;
1380#endif
1381 } statistics;
1382#ifdef CONFIG_IWLWIFI_DEBUGFS
1383 struct {
1384 struct statistics_general_common common;
1385 struct statistics_rx_non_phy rx_non_phy;
1386 struct statistics_rx_phy rx_ofdm;
1387 struct statistics_rx_ht_phy rx_ofdm_ht;
1388 struct statistics_rx_phy rx_cck;
1389 struct statistics_tx tx;
1390 struct statistics_bt_activity bt_activity;
1391 } accum_stats, delta_stats, max_delta_stats;
1392#endif
1393
898ed67b
WYG
1394 /* INT ICT Table */
1395 __le32 *ict_tbl;
1396 void *ict_tbl_vir;
1397 dma_addr_t ict_tbl_dma;
1398 dma_addr_t aligned_ict_tbl_dma;
1399 int ict_index;
1400 u32 inta;
1401 bool use_ict;
1402 /*
1403 * reporting the number of tids has AGG on. 0 means
1404 * no AGGREGATION
1405 */
1406 u8 agg_tids_count;
1407
1408 struct iwl_rx_phy_res last_phy_res;
1409 bool last_phy_res_valid;
1410
1411 struct completion firmware_loading_complete;
1412
1413 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1414 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1415
1416 /*
1417 * chain noise reset and gain commands are the
1418 * two extra calibration commands follows the standard
1419 * phy calibration commands
1420 */
1421 u8 phy_calib_chain_noise_reset_cmd;
1422 u8 phy_calib_chain_noise_gain_cmd;
1423
1424 /* counts reply_tx error */
1425 struct reply_tx_error_statistics reply_tx_stats;
1426 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
1427 /* notification wait support */
1428 struct list_head notif_waits;
1429 spinlock_t notif_wait_lock;
1430 wait_queue_head_t notif_waitq;
1431
1432 /* remain-on-channel offload support */
1433 struct ieee80211_channel *hw_roc_channel;
1434 struct delayed_work hw_roc_work;
1435 enum nl80211_channel_type hw_roc_chantype;
1436 int hw_roc_duration;
1437 bool hw_roc_setup;
1438
1439 struct sk_buff *offchan_tx_skb;
1440 int offchan_tx_timeout;
1441 struct ieee80211_channel *offchan_tx_chan;
ee525d13 1442
22bf59a0 1443 /* bt coex */
f21dd005 1444 u8 bt_enable_flag;
da5dbb97 1445 u8 bt_status;
66e863a5 1446 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1447 bool bt_ch_announce;
bee008b7
WYG
1448 bool bt_full_concurrent;
1449 bool bt_ant_couple_ok;
fbba9410
WYG
1450 __le32 kill_ack_mask;
1451 __le32 kill_cts_mask;
1452 __le16 bt_valid;
22bf59a0
WYG
1453 u16 bt_on_thresh;
1454 u16 bt_duration;
1455 u16 dynamic_frag_thresh;
bee008b7 1456 u8 bt_ci_compliance;
9e4afc21 1457 struct work_struct bt_traffic_change_work;
207ecc5e
MV
1458 bool bt_enable_pspoll;
1459 struct iwl_rxon_context *cur_rssi_ctx;
1460 bool bt_is_sco;
9e4afc21 1461
5425e490 1462 struct iwl_hw_params hw_params;
4ddbb7d0 1463
40cefda9 1464 u32 inta_mask;
5d08cd1d 1465
5d08cd1d
CH
1466 struct workqueue_struct *workqueue;
1467
5d08cd1d 1468 struct work_struct restart;
5d08cd1d
CH
1469 struct work_struct scan_completed;
1470 struct work_struct rx_replenish;
5d08cd1d 1471 struct work_struct abort_scan;
12e934dc 1472
5d08cd1d 1473 struct work_struct beacon_update;
76d04815 1474 struct iwl_rxon_context *beacon_ctx;
12e934dc 1475 struct sk_buff *beacon_skb;
4ce7cc2b 1476 void *beacon_cmd;
76d04815 1477
a28027cd
WYG
1478 struct work_struct tt_work;
1479 struct work_struct ct_enter;
1480 struct work_struct ct_exit;
88be0264 1481 struct work_struct start_internal_scan;
65550636 1482 struct work_struct tx_flush;
bee008b7 1483 struct work_struct bt_full_concurrency;
fbba9410 1484 struct work_struct bt_runtime_config;
5d08cd1d
CH
1485
1486 struct tasklet_struct irq_tasklet;
1487
5d08cd1d 1488 struct delayed_work scan_check;
4a8a4322 1489
630fe9b6
TW
1490 /* TX Power */
1491 s8 tx_power_user_lmt;
dc1b0973 1492 s8 tx_power_device_lmt;
ae16fc3c 1493 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1494 s8 tx_power_next;
5d08cd1d 1495
5d08cd1d 1496
d08853a3 1497#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1498 /* debugging info */
3d816c77
RC
1499 u32 debug_level; /* per device debugging will override global
1500 iwl_debug_level if set */
d73e4923 1501#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1502#ifdef CONFIG_IWLWIFI_DEBUGFS
1503 /* debugfs */
20594eb0
WYG
1504 u16 tx_traffic_idx;
1505 u16 rx_traffic_idx;
1506 u8 *tx_traffic;
1507 u8 *rx_traffic;
4c84a8f1
JB
1508 struct dentry *debugfs_dir;
1509 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1510 bool disable_ht40;
712b6cf5 1511#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1512
1513 struct work_struct txpower_work;
445c2dff
TW
1514 u32 disable_sens_cal;
1515 u32 disable_chain_noise_cal;
16e727e8 1516 struct work_struct run_time_calib_work;
5d08cd1d 1517 struct timer_list statistics_periodic;
a9e1cb6a 1518 struct timer_list ucode_trace;
22de94de 1519 struct timer_list watchdog;
a9e1cb6a
WYG
1520
1521 struct iwl_event_log event_log;
5ed540ae
WYG
1522
1523 struct led_classdev led;
1524 unsigned long blink_on, blink_off;
1525 bool led_registered;
7a4e5281
WYG
1526#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1527 struct iwl_testmode_trace testmode_trace;
4e308119 1528 u32 tm_fixed_rate;
c10e2c10 1529#endif
6489854b 1530
c79dd5b5 1531}; /*iwl_priv */
5d08cd1d 1532
36470749
RR
1533static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1534{
1535 set_bit(txq_id, &priv->txq_ctx_active_msk);
1536}
1537
1538static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1539{
1540 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1541}
1542
994d31f7 1543#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1544/*
1545 * iwl_get_debug_level: Return active debug level for device
1546 *
1547 * Using sysfs it is possible to set per device debug level. This debug
1548 * level will be used if set, otherwise the global debug level which can be
1549 * set via module parameter is used.
1550 */
1551static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1552{
1553 if (priv->debug_level)
1554 return priv->debug_level;
1555 else
1556 return iwl_debug_level;
1557}
a332f8d6 1558#else
3d816c77
RC
1559static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1560{
1561 return iwl_debug_level;
1562}
a332f8d6
TW
1563#endif
1564
1565
a332f8d6
TW
1566static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1567 int txq_id, int idx)
1568{
ff0d91c3 1569 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1570 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1571 txb[idx].skb->data;
a332f8d6
TW
1572 return NULL;
1573}
a332f8d6 1574
246ed355
JB
1575static inline struct iwl_rxon_context *
1576iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1577{
1578 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1579
1580 return vif_priv->ctx;
1581}
1582
1583#define for_each_context(priv, ctx) \
1584 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1585 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1586 if (priv->valid_contexts & BIT(ctx->ctxid))
1587
054ec924 1588static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
246ed355 1589{
054ec924 1590 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
246ed355
JB
1591}
1592
054ec924
JB
1593static inline int iwl_is_associated(struct iwl_priv *priv,
1594 enum iwl_rxon_context_id ctxid)
246ed355 1595{
054ec924 1596 return iwl_is_associated_ctx(&priv->contexts[ctxid]);
246ed355 1597}
a332f8d6 1598
054ec924 1599static inline int iwl_is_any_associated(struct iwl_priv *priv)
5d08cd1d 1600{
054ec924
JB
1601 struct iwl_rxon_context *ctx;
1602 for_each_context(priv, ctx)
1603 if (iwl_is_associated_ctx(ctx))
1604 return true;
1605 return false;
5d08cd1d
CH
1606}
1607
bf85ea4f 1608static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1609{
1610 if (ch_info == NULL)
1611 return 0;
1612 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1613}
1614
bf85ea4f 1615static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1616{
1617 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1618}
1619
bf85ea4f 1620static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1621{
8318d78a 1622 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1623}
1624
bf85ea4f 1625static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1626{
8318d78a 1627 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1628}
1629
bf85ea4f 1630static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1631{
1632 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1633}
1634
bf85ea4f 1635static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1636{
1637 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1638}
1639
64a76b50
ZY
1640static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1641{
1642 __free_pages(page, priv->hw_params.rx_page_order);
64a76b50
ZY
1643}
1644
1645static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1646{
1647 free_pages(page, priv->hw_params.rx_page_order);
64a76b50 1648}
be1f3ab6 1649#endif /* __iwl_dev_h__ */
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