iwlagn: use iwl_get_debug_level instead of iwl_debug_level
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 */
30
be1f3ab6
EG
31#ifndef __iwl_dev_h__
32#define __iwl_dev_h__
b481de9c 33
a6b7a407 34#include <linux/interrupt.h>
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
7194207c 37#include <linux/wait.h>
5ed540ae 38#include <linux/leds.h>
5d08cd1d
CH
39#include <net/ieee80211_radiotap.h>
40
6bc913bd 41#include "iwl-eeprom.h"
6f83eaa1 42#include "iwl-csr.h"
5d08cd1d 43#include "iwl-prph.h"
dbb6654c 44#include "iwl-fh.h"
0a6857e7 45#include "iwl-debug.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
0975cc8f 50#include "iwl-agn-tt.h"
d5934110 51#include "iwl-bus.h"
41c50542 52#include "iwl-trans.h"
5d08cd1d 53
48d1a211
EG
54#define DRV_NAME "iwlagn"
55
672639de
WYG
56struct iwl_tx_queue;
57
099b40b7 58/* CT-KILL constants */
672639de
WYG
59#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
60#define CT_KILL_THRESHOLD 114 /* in Celsius */
61#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 62
5d08cd1d
CH
63/* Default noise level to report when noise measurement is not available.
64 * This may be because we're:
65 * 1) Not associated (4965, no beacon statistics being sent to driver)
66 * 2) Scanning (noise measurement does not apply to associated channel)
67 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
68 * Use default noise value of -127 ... this is below the range of measurable
69 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
70 * Also, -127 works better than 0 when averaging frames with/without
71 * noise info (e.g. averaging might be done in app); measured dBm values are
72 * always negative ... using a negative value as the default keeps all
73 * averages within an s8's (used in some apps) range of negative values. */
74#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
75
5d08cd1d
CH
76/*
77 * RTS threshold here is total size [2347] minus 4 FCS bytes
78 * Per spec:
79 * a value of 0 means RTS on all data/management packets
80 * a value > max MSDU size means no RTS
81 * else RTS for data/management frames where MPDU is larger
82 * than RTS value.
83 */
84#define DEFAULT_RTS_THRESHOLD 2347U
85#define MIN_RTS_THRESHOLD 0U
86#define MAX_RTS_THRESHOLD 2347U
87#define MAX_MSDU_SIZE 2304U
88#define MAX_MPDU_SIZE 2346U
51b7ef05 89#define DEFAULT_BEACON_INTERVAL 200U
5d08cd1d
CH
90#define DEFAULT_SHORT_RETRY_LIMIT 7U
91#define DEFAULT_LONG_RETRY_LIMIT 4U
92
a55360e4 93struct iwl_rx_mem_buffer {
2f301227
ZY
94 dma_addr_t page_dma;
95 struct page *page;
5d08cd1d
CH
96 struct list_head list;
97};
98
2f301227
ZY
99#define rxb_addr(r) page_address(r->page)
100
c2acea8e
JB
101/* defined below */
102struct iwl_device_cmd;
103
104struct iwl_cmd_meta {
105 /* only for SYNC commands, iff the reply skb is wanted */
106 struct iwl_host_cmd *source;
107 /*
108 * only for ASYNC commands
109 * (which is somewhat stupid -- look at iwl-sta.c for instance
110 * which duplicates a bunch of code because the callback isn't
111 * invoked for SYNC commands, if it were and its result passed
112 * through it would be simpler...)
113 */
5696aea6
JB
114 void (*callback)(struct iwl_priv *priv,
115 struct iwl_device_cmd *cmd,
2f301227 116 struct iwl_rx_packet *pkt);
c2acea8e 117
c2acea8e
JB
118 u32 flags;
119
2e724443
FT
120 DEFINE_DMA_UNMAP_ADDR(mapping);
121 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
122};
123
5d08cd1d
CH
124/*
125 * Generic queue structure
126 *
4ce7cc2b
JB
127 * Contains common data for Rx and Tx queues.
128 *
129 * Note the difference between n_bd and n_window: the hardware
130 * always assumes 256 descriptors, so n_bd is always 256 (unless
131 * there might be HW changes in the future). For the normal TX
132 * queues, n_window, which is the size of the software queue data
133 * is also 256; however, for the command queue, n_window is only
134 * 32 since we don't need so many commands pending. Since the HW
135 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
136 * the software buffers (in the variables @meta, @txb in struct
137 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
138 * in the same struct) have 256.
139 * This means that we end up with the following:
140 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
141 * SW entries: | 0 | ... | 31 |
142 * where N is a number between 0 and 7. This means that the SW
143 * data is a window overlayed over the HW queue.
5d08cd1d 144 */
443cfd45 145struct iwl_queue {
5d08cd1d
CH
146 int n_bd; /* number of BDs in this queue */
147 int write_ptr; /* 1-st empty entry (index) host_w*/
148 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 149 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
150 dma_addr_t dma_addr; /* physical addr for BD's */
151 int n_window; /* safe queue window */
152 u32 id;
153 int low_mark; /* low watermark, resume queue if free
154 * space more than this */
155 int high_mark; /* high watermark, stop queue if free
156 * space less than this */
a839cf69 157};
5d08cd1d 158
bc47279f 159/* One for each TFD */
8567c63e 160struct iwl_tx_info {
ff0d91c3 161 struct sk_buff *skb;
c90cbbbd 162 struct iwl_rxon_context *ctx;
5d08cd1d
CH
163};
164
165/**
16466903 166 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
167 * @q: generic Rx/Tx queue descriptor
168 * @bd: base of circular buffer of TFDs
c2acea8e
JB
169 * @cmd: array of command/TX buffer pointers
170 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
171 * @dma_addr_cmd: physical address of cmd/tx buffer array
172 * @txb: array of per-TFD driver data
22de94de 173 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
174 * @need_update: indicates need to update read/write index
175 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 176 *
bc47279f
BC
177 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
178 * descriptors) and required locking structures.
5d08cd1d 179 */
188cf6c7
SO
180#define TFD_TX_CMD_SLOTS 256
181#define TFD_CMD_SLOTS 32
182
16466903 183struct iwl_tx_queue {
443cfd45 184 struct iwl_queue q;
4ce7cc2b 185 struct iwl_tfd *tfds;
c2acea8e
JB
186 struct iwl_device_cmd **cmd;
187 struct iwl_cmd_meta *meta;
8567c63e 188 struct iwl_tx_info *txb;
22de94de 189 unsigned long time_stamp;
3fd07a1e
TW
190 u8 need_update;
191 u8 sched_retry;
192 u8 active;
193 u8 swq_id;
5d08cd1d
CH
194};
195
196#define IWL_NUM_SCAN_RATES (2)
197
5d08cd1d
CH
198/*
199 * One for each channel, holds all channel setup data
200 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
201 * with one another!
202 */
bf85ea4f 203struct iwl_channel_info {
073d3f5f 204 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
205 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
206 * HT40 channel */
5d08cd1d
CH
207
208 u8 channel; /* channel number */
209 u8 flags; /* flags copied from EEPROM */
210 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 211 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
212 s8 min_power; /* always 0 */
213 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
214
215 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
216 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 217 enum ieee80211_band band;
5d08cd1d 218
7aafef1c
WYG
219 /* HT40 channel info */
220 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
221 u8 ht40_flags; /* flags copied from EEPROM */
222 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
223};
224
751ca305 225#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 226#define IWL_TX_FIFO_BE 1
751ca305 227#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 228#define IWL_TX_FIFO_VO 3
751ca305
JB
229#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
230#define IWL_TX_FIFO_BE_IPAN 4
231#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
232#define IWL_TX_FIFO_VO_IPAN 5
72c04ce0
JB
233/* re-uses the VO FIFO, uCode will properly flush/schedule */
234#define IWL_TX_FIFO_AUX 5
edc1a3a0 235#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 236
72c04ce0
JB
237/* AUX (TX during scan dwell) queue */
238#define IWL_AUX_QUEUE 10
239
240/*
241 * Minimum number of queues. MAX_NUM is defined in hw specific files.
242 * Set the minimum to accommodate
243 * - 4 standard TX queues
244 * - the command queue
245 * - 4 PAN TX queues
246 * - the PAN multicast queue, and
247 * - the AUX (TX during scan dwell) queue.
248 */
249#define IWL_MIN_NUM_QUEUES 11
5d08cd1d 250
bd35f150 251/*
13bb9483 252 * Command queue depends on iPAN support.
bd35f150 253 */
13bb9483
JB
254#define IWL_DEFAULT_CMD_QUEUE_NUM 4
255#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 256
751ca305
JB
257/*
258 * This queue number is required for proper operation
259 * because the ucode will stop/start the scheduler as
260 * required.
261 */
262#define IWL_IPAN_MCAST_QUEUE 8
263
5d08cd1d
CH
264#define IEEE80211_DATA_LEN 2304
265#define IEEE80211_4ADDR_LEN 30
266#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
267#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
268
5d08cd1d 269
5d08cd1d
CH
270#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
271#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
272#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
273
274enum {
c587de0b 275 CMD_SYNC = 0,
e419d62d
EG
276 CMD_ASYNC = BIT(0),
277 CMD_WANT_SKB = BIT(1),
c7c1115b 278 CMD_ON_DEMAND = BIT(2),
5d08cd1d
CH
279};
280
c8c24872 281#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 282
bc47279f 283/**
c2acea8e 284 * struct iwl_device_cmd
bc47279f
BC
285 *
286 * For allocation of the command and tx queues, this establishes the overall
4ce7cc2b
JB
287 * size of the largest command we send to uCode, except for commands that
288 * aren't fully copied and use other TFD space.
bc47279f 289 */
c2acea8e 290struct iwl_device_cmd {
857485c0 291 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 292 union {
5d08cd1d
CH
293 u32 flags;
294 u8 val8;
295 u16 val16;
296 u32 val32;
83d527d9 297 struct iwl_tx_cmd tx;
c8c24872
WYG
298 struct iwl6000_channel_switch_cmd chswitch;
299 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
300 } __packed cmd;
301} __packed;
5d08cd1d 302
c2acea8e
JB
303#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
304
4ce7cc2b
JB
305#define IWL_MAX_CMD_TFDS 2
306
307enum iwl_hcmd_dataflag {
308 IWL_HCMD_DFL_NOCOPY = BIT(0),
309};
3257e5d4 310
e419d62d
EG
311/**
312 * struct iwl_host_cmd - Host command to the uCode
313 * @data: array of chunks that composes the data of the host command
314 * @reply_page: pointer to the page that holds the response to the host command
315 * @callback:
316 * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC
317 * @len: array of the lenths of the chunks in data
318 * @dataflags:
319 * @id: id of the host command
320 */
857485c0 321struct iwl_host_cmd {
3fa50738 322 const void *data[IWL_MAX_CMD_TFDS];
2f301227 323 unsigned long reply_page;
5696aea6
JB
324 void (*callback)(struct iwl_priv *priv,
325 struct iwl_device_cmd *cmd,
2f301227 326 struct iwl_rx_packet *pkt);
c2acea8e 327 u32 flags;
3fa50738 328 u16 len[IWL_MAX_CMD_TFDS];
4ce7cc2b 329 u8 dataflags[IWL_MAX_CMD_TFDS];
c2acea8e 330 u8 id;
5d08cd1d
CH
331};
332
5d08cd1d
CH
333#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
334#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
335#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
336
337/**
a55360e4 338 * struct iwl_rx_queue - Rx queue
df833b1d 339 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 340 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
341 * @read: Shared index to newest available Rx buffer
342 * @write: Shared index to oldest written Rx packet
343 * @free_count: Number of pre-allocated buffers in rx_free
344 * @rx_free: list of free SKBs for use
345 * @rx_used: List of Rx buffers with no SKB
346 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
347 * @rb_stts: driver's pointer to receive buffer status
348 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 349 *
a55360e4 350 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 351 */
a55360e4 352struct iwl_rx_queue {
5d08cd1d 353 __le32 *bd;
d5b25c90 354 dma_addr_t bd_dma;
a55360e4
TW
355 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
356 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
357 u32 read;
358 u32 write;
359 u32 free_count;
4752c93c 360 u32 write_actual;
5d08cd1d
CH
361 struct list_head rx_free;
362 struct list_head rx_used;
363 int need_update;
8d86422a
WT
364 struct iwl_rb_status *rb_stts;
365 dma_addr_t rb_stts_dma;
5d08cd1d
CH
366 spinlock_t lock;
367};
368
369#define IWL_SUPPORTED_RATES_IE_LEN 8
370
5d08cd1d
CH
371#define MAX_TID_COUNT 9
372
373#define IWL_INVALID_RATE 0xFF
374#define IWL_INVALID_VALUE -1
375
bc47279f 376/**
6def9761 377 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
378 * @txq_id: Tx queue used for Tx attempt
379 * @frame_count: # frames attempted by Tx command
380 * @wait_for_ba: Expect block-ack before next Tx reply
381 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
382 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
383 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
384 * @rate_n_flags: Rate at which Tx was attempted
385 *
386 * If REPLY_TX indicates that aggregation was attempted, driver must wait
387 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
388 * until block ack arrives.
389 */
6def9761 390struct iwl_ht_agg {
5d08cd1d
CH
391 u16 txq_id;
392 u16 frame_count;
393 u16 wait_for_ba;
394 u16 start_idx;
fe01b477 395 u64 bitmap;
5d08cd1d 396 u32 rate_n_flags;
fe01b477
RR
397#define IWL_AGG_OFF 0
398#define IWL_AGG_ON 1
399#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
400#define IWL_EMPTYING_HW_QUEUE_DELBA 3
401 u8 state;
c8823ec1 402 u8 tx_fifo;
5d08cd1d 403};
fe01b477 404
5d08cd1d 405
6def9761 406struct iwl_tid_data {
f862a236 407 u16 seq_number; /* agn only */
fe01b477 408 u16 tfds_in_queue;
6def9761 409 struct iwl_ht_agg agg;
5d08cd1d
CH
410};
411
a78fe754 412union iwl_ht_rate_supp {
5d08cd1d
CH
413 u16 rates;
414 struct {
415 u8 siso_rate;
416 u8 mimo_rate;
417 };
418};
419
172c1d11
WYG
420#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
421#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
422#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
423#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
424#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
425#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
426#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
427
428/*
429 * Maximal MPDU density for TX aggregation
430 * 4 - 2us density
431 * 5 - 4us density
432 * 6 - 8us density
433 * 7 - 16us density
434 */
172c1d11 435#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 436#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
437#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
438#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 439#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
440#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
441#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 442
fad95bf5 443struct iwl_ht_config {
02bb1bea 444 bool single_chain_sufficient;
ba37a3d0 445 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 446};
5d08cd1d 447
5d08cd1d 448/* QoS structures */
1ff50bda 449struct iwl_qos_info {
5d08cd1d 450 int qos_active;
1ff50bda 451 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 452};
5d08cd1d 453
fe6b23dd
RC
454/*
455 * Structure should be accessed with sta_lock held. When station addition
456 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
457 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
458 * held.
459 */
6def9761 460struct iwl_station_entry {
133636de 461 struct iwl_addsta_cmd sta;
6def9761 462 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 463 u8 used, ctxid;
fe6b23dd 464 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
465};
466
fd1af15d 467struct iwl_station_priv_common {
238d781d 468 struct iwl_rxon_context *ctx;
fd1af15d
JB
469 u8 sta_id;
470};
471
8d9698b3
RC
472/*
473 * iwl_station_priv: Driver's private station information
474 *
475 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
476 * in the structure for use by driver. This structure is places in that
477 * space.
8d9698b3
RC
478 */
479struct iwl_station_priv {
fd1af15d 480 struct iwl_station_priv_common common;
8d9698b3 481 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
482 atomic_t pending_frames;
483 bool client;
484 bool asleep;
7b090687 485 u8 max_agg_bufsize;
8d9698b3
RC
486};
487
fd1af15d
JB
488/**
489 * struct iwl_vif_priv - driver's private per-interface information
490 *
491 * When mac80211 allocates a virtual interface, it can allocate
492 * space for us to put data into.
493 */
494struct iwl_vif_priv {
246ed355 495 struct iwl_rxon_context *ctx;
fd1af15d
JB
496 u8 ibss_bssid_sta_id;
497};
498
5d08cd1d
CH
499/* one for each uCode image (inst/data, boot/init/runtime) */
500struct fw_desc {
501 void *v_addr; /* access by driver */
502 dma_addr_t p_addr; /* access by card's busmaster DMA */
503 u32 len; /* bytes */
504};
505
dbf28e21
JB
506struct fw_img {
507 struct fw_desc code, data;
508};
509
dd7a2509 510/* v1/v2 uCode file layout */
cc0f555d
JS
511struct iwl_ucode_header {
512 __le32 ver; /* major/minor/API/serial */
513 union {
514 struct {
515 __le32 inst_size; /* bytes of runtime code */
516 __le32 data_size; /* bytes of runtime data */
517 __le32 init_size; /* bytes of init code */
518 __le32 init_data_size; /* bytes of init data */
519 __le32 boot_size; /* bytes of bootstrap code */
520 u8 data[0]; /* in same order as sizes */
521 } v1;
522 struct {
523 __le32 build; /* build number */
524 __le32 inst_size; /* bytes of runtime code */
525 __le32 data_size; /* bytes of runtime data */
526 __le32 init_size; /* bytes of init code */
527 __le32 init_data_size; /* bytes of init data */
528 __le32 boot_size; /* bytes of bootstrap code */
529 u8 data[0]; /* in same order as sizes */
530 } v2;
531 } u;
5d08cd1d
CH
532};
533
dd7a2509
JB
534/*
535 * new TLV uCode file layout
536 *
537 * The new TLV file format contains TLVs, that each specify
538 * some piece of data. To facilitate "groups", for example
539 * different instruction image with different capabilities,
540 * bundled with the same init image, an alternative mechanism
541 * is provided:
542 * When the alternative field is 0, that means that the item
543 * is always valid. When it is non-zero, then it is only
544 * valid in conjunction with items of the same alternative,
545 * in which case the driver (user) selects one alternative
546 * to use.
547 */
548
549enum iwl_ucode_tlv_type {
550 IWL_UCODE_TLV_INVALID = 0, /* unused */
551 IWL_UCODE_TLV_INST = 1,
552 IWL_UCODE_TLV_DATA = 2,
553 IWL_UCODE_TLV_INIT = 3,
554 IWL_UCODE_TLV_INIT_DATA = 4,
555 IWL_UCODE_TLV_BOOT = 5,
556 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 557 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
558 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
559 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
560 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
561 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
562 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
563 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 564 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 565 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
c8ac61cf
JB
566 IWL_UCODE_TLV_WOWLAN_INST = 16,
567 IWL_UCODE_TLV_WOWLAN_DATA = 17,
3997ff39
JB
568 IWL_UCODE_TLV_FLAGS = 18,
569};
570
571/**
572 * enum iwl_ucode_tlv_flag - ucode API flags
573 * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
574 * was a separate TLV but moved here to save space.
d2690c0d
JB
575 * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
576 * treats good CRC threshold as a boolean
3997ff39 577 * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
c6baf7fb 578 * @IWL_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
3997ff39
JB
579 */
580enum iwl_ucode_tlv_flag {
581 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
d2690c0d 582 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
3997ff39 583 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
c6baf7fb 584 IWL_UCODE_TLV_FLAGS_P2P = BIT(3),
dd7a2509
JB
585};
586
587struct iwl_ucode_tlv {
588 __le16 type; /* see above */
589 __le16 alternative; /* see comment */
590 __le32 length; /* not including type/length fields */
591 u8 data[0];
ba2d3587 592} __packed;
dd7a2509
JB
593
594#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
595
596struct iwl_tlv_ucode_header {
597 /*
598 * The TLV style ucode header is distinguished from
599 * the v1/v2 style header by first four bytes being
600 * zero, as such is an invalid combination of
601 * major/minor/API/serial versions.
602 */
603 __le32 zero;
604 __le32 magic;
605 u8 human_readable[64];
606 __le32 ver; /* major/minor/API/serial */
607 __le32 build;
608 __le64 alternatives; /* bitmask of valid alternatives */
609 /*
610 * The data contained herein has a TLV layout,
611 * see above for the TLV header and types.
612 * Note that each TLV is padded to a length
613 * that is a multiple of 4 for alignment.
614 */
615 u8 data[0];
616};
617
f0832f13
EG
618struct iwl_sensitivity_ranges {
619 u16 min_nrg_cck;
620 u16 max_nrg_cck;
621
622 u16 nrg_th_cck;
623 u16 nrg_th_ofdm;
624
625 u16 auto_corr_min_ofdm;
626 u16 auto_corr_min_ofdm_mrc;
627 u16 auto_corr_min_ofdm_x1;
628 u16 auto_corr_min_ofdm_mrc_x1;
629
630 u16 auto_corr_max_ofdm;
631 u16 auto_corr_max_ofdm_mrc;
632 u16 auto_corr_max_ofdm_x1;
633 u16 auto_corr_max_ofdm_mrc_x1;
634
635 u16 auto_corr_max_cck;
636 u16 auto_corr_max_cck_mrc;
637 u16 auto_corr_min_cck;
638 u16 auto_corr_min_cck_mrc;
55036d66
WYG
639
640 u16 barker_corr_th_min;
641 u16 barker_corr_th_min_mrc;
642 u16 nrg_th_cca;
f0832f13
EG
643};
644
099b40b7 645
b5047f78
TW
646#define KELVIN_TO_CELSIUS(x) ((x)-273)
647#define CELSIUS_TO_KELVIN(x) ((x)+273)
648
649
bc47279f 650/**
5425e490 651 * struct iwl_hw_params
bc47279f 652 * @max_txq_num: Max # Tx queues supported
4ddbb7d0 653 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 654 * @tfd_size: TFD size
099b40b7
RR
655 * @tx/rx_chains_num: Number of TX/RX chains
656 * @valid_tx/rx_ant: usable antennas
bc47279f 657 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 658 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 659 * @rx_page_order: Rx buffer page order
141c43a3 660 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 661 * @max_stations:
7aafef1c 662 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
663 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
664 * @sw_crypto: 0 for hw, 1 for sw
665 * @max_xxx_size: for ucode uses
666 * @ct_kill_threshold: temperature threshold
a0ee74cf 667 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 668 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 669 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 670 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 671 */
5425e490 672struct iwl_hw_params {
f3f911d1 673 u8 max_txq_num;
4ddbb7d0 674 u16 scd_bc_tbls_size;
a8e74e27 675 u32 tfd_size;
ec35cf2a
TW
676 u8 tx_chains_num;
677 u8 rx_chains_num;
678 u8 valid_tx_ant;
679 u8 valid_rx_ant;
5d08cd1d 680 u16 max_rxq_size;
ec35cf2a 681 u16 max_rxq_log;
2f301227 682 u32 rx_page_order;
5d08cd1d 683 u8 max_stations;
7aafef1c 684 u8 ht40_channel;
2c2f3b33 685 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
686 u32 max_inst_size;
687 u32 max_data_size;
099b40b7 688 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
689 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
690 /* for 1000, 6000 series and up */
a0ee74cf 691 u16 beacon_time_tsf_bits;
be5d56ed 692 u32 calib_init_cfg;
6d6a1afd 693 u32 calib_rt_cfg;
f0832f13 694 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
695};
696
5d08cd1d 697
5d08cd1d
CH
698/******************************************************************************
699 *
a33c2f47
EG
700 * Functions implemented in core module which are forward declared here
701 * for use by iwl-[4-5].c
5d08cd1d 702 *
a33c2f47
EG
703 * NOTE: The implementation of these functions are not hardware specific
704 * which is why they are in the core module files.
5d08cd1d
CH
705 *
706 * Naming convention --
a33c2f47 707 * iwl_ <-- Is part of iwlwifi
5d08cd1d 708 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
5d08cd1d
CH
709 *
710 ****************************************************************************/
5b9f8cd3 711extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 712extern const u8 iwl_bcast_addr[ETH_ALEN];
443cfd45 713extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
714static inline int iwl_queue_used(const struct iwl_queue *q, int i)
715{
c8106d76 716 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
717 (i >= q->read_ptr && i < q->write_ptr) :
718 !(i < q->read_ptr && i >= q->write_ptr);
719}
720
721
4ce7cc2b 722static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
fd4abac5 723{
fd4abac5
TW
724 return index & (q->n_window - 1);
725}
726
727
4ddbb7d0
TW
728struct iwl_dma_ptr {
729 dma_addr_t dma;
730 void *addr;
b481de9c
ZY
731 size_t size;
732};
733
b481de9c
ZY
734#define IWL_OPERATION_MODE_AUTO 0
735#define IWL_OPERATION_MODE_HT_ONLY 1
736#define IWL_OPERATION_MODE_MIXED 2
737#define IWL_OPERATION_MODE_20MHZ 3
738
3195cdb7
TW
739#define IWL_TX_CRC_SIZE 4
740#define IWL_TX_DELIMITER_SIZE 4
b481de9c 741
b481de9c 742#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 743
b481de9c 744/* Sensitivity and chain noise calibration */
b481de9c 745#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a 746#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
747#define MAXIMUM_ALLOWED_PATHLOSS 15
748
b481de9c
ZY
749#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
750
751#define MAX_FA_OFDM 50
752#define MIN_FA_OFDM 5
753#define MAX_FA_CCK 50
754#define MIN_FA_CCK 5
755
b481de9c
ZY
756#define AUTO_CORR_STEP_OFDM 1
757
b481de9c
ZY
758#define AUTO_CORR_STEP_CCK 3
759#define AUTO_CORR_MAX_TH_CCK 160
760
b481de9c
ZY
761#define NRG_DIFF 2
762#define NRG_STEP_CCK 2
763#define NRG_MARGIN 8
764#define MAX_NUMBER_CCK_NO_FA 100
765
766#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
767
768#define CHAIN_A 0
769#define CHAIN_B 1
770#define CHAIN_C 2
771#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
772#define ALL_BAND_FILTER 0xFF00
773#define IN_BAND_FILTER 0xFF
774#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
775
3195cdb7
TW
776#define NRG_NUM_PREV_STAT_L 20
777#define NUM_RX_CHAINS 3
778
3240cab3 779enum iwlagn_false_alarm_state {
b481de9c
ZY
780 IWL_FA_TOO_MANY = 0,
781 IWL_FA_TOO_FEW = 1,
782 IWL_FA_GOOD_RANGE = 2,
783};
784
3240cab3 785enum iwlagn_chain_noise_state {
b481de9c 786 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
787 IWL_CHAIN_NOISE_ACCUMULATE,
788 IWL_CHAIN_NOISE_CALIBRATED,
789 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
790};
791
f69f42a6
TW
792
793/*
794 * enum iwl_calib
795 * defines the order in which results of initial calibrations
796 * should be sent to the runtime uCode
797 */
798enum iwl_calib {
799 IWL_CALIB_XTAL,
819500c5 800 IWL_CALIB_DC,
f69f42a6
TW
801 IWL_CALIB_LO,
802 IWL_CALIB_TX_IQ,
803 IWL_CALIB_TX_IQ_PERD,
201706ac 804 IWL_CALIB_BASE_BAND,
bf53f939 805 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
806 IWL_CALIB_MAX
807};
808
6e21f2c1
TW
809/* Opaque calibration results */
810struct iwl_calib_result {
811 void *buf;
812 size_t buf_len;
7c616cba
TW
813};
814
b481de9c 815/* Sensitivity calib data */
f0832f13 816struct iwl_sensitivity_data {
b481de9c
ZY
817 u32 auto_corr_ofdm;
818 u32 auto_corr_ofdm_mrc;
819 u32 auto_corr_ofdm_x1;
820 u32 auto_corr_ofdm_mrc_x1;
821 u32 auto_corr_cck;
822 u32 auto_corr_cck_mrc;
823
824 u32 last_bad_plcp_cnt_ofdm;
825 u32 last_fa_cnt_ofdm;
826 u32 last_bad_plcp_cnt_cck;
827 u32 last_fa_cnt_cck;
828
829 u32 nrg_curr_state;
830 u32 nrg_prev_state;
831 u32 nrg_value[10];
832 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
833 u32 nrg_silence_ref;
834 u32 nrg_energy_idx;
835 u32 nrg_silence_idx;
836 u32 nrg_th_cck;
837 s32 nrg_auto_corr_silence_diff;
838 u32 num_in_cck_no_fa;
839 u32 nrg_th_ofdm;
55036d66
WYG
840
841 u16 barker_corr_th_min;
842 u16 barker_corr_th_min_mrc;
843 u16 nrg_th_cca;
b481de9c
ZY
844};
845
846/* Chain noise (differential Rx gain) calib data */
f0832f13 847struct iwl_chain_noise_data {
04816448 848 u32 active_chains;
b481de9c
ZY
849 u32 chain_noise_a;
850 u32 chain_noise_b;
851 u32 chain_noise_c;
852 u32 chain_signal_a;
853 u32 chain_signal_b;
854 u32 chain_signal_c;
04816448 855 u16 beacon_count;
b481de9c
ZY
856 u8 disconn_array[NUM_RX_CHAINS];
857 u8 delta_gain_code[NUM_RX_CHAINS];
858 u8 radio_write;
04816448 859 u8 state;
b481de9c
ZY
860};
861
abceddb4
BC
862#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
863#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 864
20594eb0
WYG
865#define IWL_TRAFFIC_ENTRIES (256)
866#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 867
5d08cd1d
CH
868enum {
869 MEASUREMENT_READY = (1 << 0),
870 MEASUREMENT_ACTIVE = (1 << 1),
871};
872
0848e297
WYG
873enum iwl_nvm_type {
874 NVM_DEVICE_TYPE_EEPROM = 0,
875 NVM_DEVICE_TYPE_OTP,
876};
877
415e4993
WYG
878/*
879 * Two types of OTP memory access modes
880 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
881 * based on physical memory addressing
882 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
883 * based on logical memory addressing
884 */
885enum iwl_access_mode {
886 IWL_OTP_ACCESS_ABSOLUTE,
887 IWL_OTP_ACCESS_RELATIVE,
888};
65b7998a
WYG
889
890/**
891 * enum iwl_pa_type - Power Amplifier type
892 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
893 * @IWL_PA_INTERNAL: use Internal only
894 */
895enum iwl_pa_type {
896 IWL_PA_SYSTEM = 0,
740e7f51 897 IWL_PA_INTERNAL = 1,
65b7998a
WYG
898};
899
a83b9141
WYG
900/* interrupt statistics */
901struct isr_statistics {
902 u32 hw;
903 u32 sw;
6e6ebf4b 904 u32 err_code;
a83b9141
WYG
905 u32 sch;
906 u32 alive;
907 u32 rfkill;
908 u32 ctkill;
909 u32 wakeup;
910 u32 rx;
911 u32 rx_handlers[REPLY_MAX];
912 u32 tx;
913 u32 unhandled;
914};
5d08cd1d 915
91835ba4
WYG
916/* reply_tx_statistics (for _agn devices) */
917struct reply_tx_error_statistics {
918 u32 pp_delay;
919 u32 pp_few_bytes;
920 u32 pp_bt_prio;
921 u32 pp_quiet_period;
922 u32 pp_calc_ttak;
923 u32 int_crossed_retry;
924 u32 short_limit;
925 u32 long_limit;
926 u32 fifo_underrun;
927 u32 drain_flow;
928 u32 rfkill_flush;
929 u32 life_expire;
930 u32 dest_ps;
931 u32 host_abort;
932 u32 bt_retry;
933 u32 sta_invalid;
934 u32 frag_drop;
935 u32 tid_disable;
936 u32 fifo_flush;
937 u32 insuff_cf_poll;
938 u32 fail_hw_drop;
939 u32 sta_color_mismatch;
940 u32 unknown;
941};
942
814665fe
WYG
943/* reply_agg_tx_statistics (for _agn devices) */
944struct reply_agg_tx_error_statistics {
945 u32 underrun;
946 u32 bt_prio;
947 u32 few_bytes;
948 u32 abort;
949 u32 last_sent_ttl;
950 u32 last_sent_try;
951 u32 last_sent_bt_kill;
952 u32 scd_query;
953 u32 bad_crc32;
954 u32 response;
955 u32 dump_tx;
956 u32 delay_tx;
957 u32 unknown;
958};
959
22fdf3c9
WYG
960/* management statistics */
961enum iwl_mgmt_stats {
962 MANAGEMENT_ASSOC_REQ = 0,
963 MANAGEMENT_ASSOC_RESP,
964 MANAGEMENT_REASSOC_REQ,
965 MANAGEMENT_REASSOC_RESP,
966 MANAGEMENT_PROBE_REQ,
967 MANAGEMENT_PROBE_RESP,
968 MANAGEMENT_BEACON,
969 MANAGEMENT_ATIM,
970 MANAGEMENT_DISASSOC,
971 MANAGEMENT_AUTH,
972 MANAGEMENT_DEAUTH,
973 MANAGEMENT_ACTION,
974 MANAGEMENT_MAX,
975};
976/* control statistics */
977enum iwl_ctrl_stats {
978 CONTROL_BACK_REQ = 0,
979 CONTROL_BACK,
980 CONTROL_PSPOLL,
981 CONTROL_RTS,
982 CONTROL_CTS,
983 CONTROL_ACK,
984 CONTROL_CFEND,
985 CONTROL_CFENDACK,
986 CONTROL_MAX,
987};
988
989struct traffic_stats {
5ed540ae 990#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
991 u32 mgmt[MANAGEMENT_MAX];
992 u32 ctrl[CONTROL_MAX];
993 u32 data_cnt;
994 u64 data_bytes;
22fdf3c9 995#endif
5ed540ae 996};
22fdf3c9 997
a9e1cb6a
WYG
998/*
999 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
1000 * to perform continuous uCode event logging operation if enabled
1001 */
1002#define UCODE_TRACE_PERIOD (100)
1003
1004/*
1005 * iwl_event_log: current uCode event log position
1006 *
1007 * @ucode_trace: enable/disable ucode continuous trace timer
1008 * @num_wraps: how many times the event buffer wraps
1009 * @next_entry: the entry just before the next one that uCode would fill
1010 * @non_wraps_count: counter for no wrap detected when dump ucode events
1011 * @wraps_once_count: counter for wrap once detected when dump ucode events
1012 * @wraps_more_count: counter for wrap more than once detected
1013 * when dump ucode events
1014 */
1015struct iwl_event_log {
1016 bool ucode_trace;
1017 u32 num_wraps;
1018 u32 next_entry;
1019 int non_wraps_count;
1020 int wraps_once_count;
1021 int wraps_more_count;
1022};
1023
2be76703
WYG
1024/*
1025 * host interrupt timeout value
1026 * used with setting interrupt coalescing timer
1027 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1028 *
1029 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1030 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1031 */
1032#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1033#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1034#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1035#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1036#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1037#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1038
3e4fb5fa
TAN
1039/*
1040 * This is the threshold value of plcp error rate per 100mSecs. It is
1041 * used to set and check for the validity of plcp_delta.
1042 */
680788ac 1043#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1044#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1045#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1046#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1047#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1048#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1049
8a472da4
WYG
1050#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1051#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1052
22de94de
SG
1053/* TX queue watchdog timeouts in mSecs */
1054#define IWL_DEF_WD_TIMEOUT (2000)
1055#define IWL_LONG_WD_TIMEOUT (10000)
1056#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1057
bee008b7
WYG
1058/* BT Antenna Coupling Threshold (dB) */
1059#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1060
491bc292
WYG
1061/* Firmware reload counter and Timestamp */
1062#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1063#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1064
1065
a93e7973
WYG
1066enum iwl_reset {
1067 IWL_RF_RESET = 0,
1068 IWL_FW_RESET,
8a472da4
WYG
1069 IWL_MAX_FORCE_RESET,
1070};
1071
1072struct iwl_force_reset {
1073 int reset_request_count;
1074 int reset_success_count;
1075 int reset_reject_count;
1076 unsigned long reset_duration;
1077 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1078};
1079
a0ee74cf 1080/* extend beacon time format bit shifting */
a0ee74cf
WYG
1081/*
1082 * for _agn devices
1083 * bits 31:22 - extended
1084 * bits 21:0 - interval
1085 */
1086#define IWLAGN_EXT_BEACON_TIME_POS 22
1087
7194207c
JB
1088/**
1089 * struct iwl_notification_wait - notification wait entry
1090 * @list: list head for global list
1091 * @fn: function called with the notification
1092 * @cmd: command ID
1093 *
1094 * This structure is not used directly, to wait for a
1095 * notification declare it on the stack, and call
1096 * iwlagn_init_notification_wait() with appropriate
1097 * parameters. Then do whatever will cause the ucode
1098 * to notify the driver, and to wait for that then
1099 * call iwlagn_wait_notification().
1100 *
1101 * Each notification is one-shot. If at some point we
1102 * need to support multi-shot notifications (which
1103 * can't be allocated on the stack) we need to modify
1104 * the code for them.
1105 */
1106struct iwl_notification_wait {
1107 struct list_head list;
1108
09f18afe
JB
1109 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt,
1110 void *data);
1111 void *fn_data;
7194207c
JB
1112
1113 u8 cmd;
e74fe233 1114 bool triggered, aborted;
7194207c
JB
1115};
1116
246ed355
JB
1117enum iwl_rxon_context_id {
1118 IWL_RXON_CTX_BSS,
ece9c4ee 1119 IWL_RXON_CTX_PAN,
246ed355
JB
1120
1121 NUM_IWL_RXON_CTX
1122};
1123
1124struct iwl_rxon_context {
8bd413e6 1125 struct ieee80211_vif *vif;
e72f368b
JB
1126
1127 const u8 *ac_to_fifo;
1128 const u8 *ac_to_queue;
1129 u8 mcast_queue;
1130
763cc3bf
JB
1131 /*
1132 * We could use the vif to indicate active, but we
1133 * also need it to be active during disabling when
1134 * we already removed the vif for type setting.
1135 */
1136 bool always_active, is_active;
1137
2295c66b
JB
1138 bool ht_need_multiple_chains;
1139
246ed355 1140 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1141
1142 u32 interface_modes, exclusive_interface_modes;
1143 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1144
246ed355
JB
1145 /*
1146 * We declare this const so it can only be
1147 * changed via explicit cast within the
1148 * routines that actually update the physical
1149 * hardware.
1150 */
1151 const struct iwl_rxon_cmd active;
1152 struct iwl_rxon_cmd staging;
1153
1154 struct iwl_rxon_time_cmd timing;
a194e324 1155
8dfdb9d5
JB
1156 struct iwl_qos_info qos_data;
1157
2995bafa 1158 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1159
1160 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1161 u8 qos_cmd;
c10afb6e
JB
1162 u8 wep_key_cmd;
1163
1164 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1165 u8 key_mapping_keys;
770e13bd
JB
1166
1167 __le32 station_flags;
7e6a5886 1168
bbb05cb5
JB
1169 int beacon_int;
1170
7e6a5886
JB
1171 struct {
1172 bool non_gf_sta_present;
1173 u8 protection;
1174 bool enabled, is_40mhz;
1175 u8 extension_chan_offset;
1176 } ht;
68b99311
GT
1177
1178 bool last_tx_rejected;
246ed355
JB
1179};
1180
266af4c7
JB
1181enum iwl_scan_type {
1182 IWL_SCAN_NORMAL,
1183 IWL_SCAN_RADIO_RESET,
c6baf7fb 1184 IWL_SCAN_ROC,
266af4c7
JB
1185};
1186
872907bb
JB
1187enum iwlagn_ucode_type {
1188 IWL_UCODE_NONE,
1189 IWL_UCODE_REGULAR,
1190 IWL_UCODE_INIT,
1191 IWL_UCODE_WOWLAN,
1192};
1193
7a4e5281
WYG
1194#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1195struct iwl_testmode_trace {
49b72100
WYG
1196 u32 buff_size;
1197 u32 total_size;
eb64dca0 1198 u32 num_chunks;
7a4e5281
WYG
1199 u8 *cpu_addr;
1200 u8 *trace_addr;
1201 dma_addr_t dma_addr;
1202 bool trace_enabled;
1203};
1204#endif
a48709c5 1205
e98a1939
WYG
1206/* uCode ownership */
1207#define IWL_OWNERSHIP_DRIVER 0
1208#define IWL_OWNERSHIP_TM 1
1209
c79dd5b5 1210struct iwl_priv {
5d08cd1d
CH
1211
1212 /* ieee device used by generic ieee processing code */
1213 struct ieee80211_hw *hw;
1214 struct ieee80211_channel *ieee_channels;
1215 struct ieee80211_rate *ieee_rates;
82b9a121 1216 struct iwl_cfg *cfg;
5d08cd1d 1217
8318d78a 1218 enum ieee80211_band band;
5d08cd1d 1219
4613e72d
CK
1220 void (*pre_rx_handler)(struct iwl_priv *priv,
1221 struct iwl_rx_mem_buffer *rxb);
c79dd5b5 1222 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1223 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1224
8318d78a 1225 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1226
5d08cd1d 1227 /* spectrum measurement report caching */
2aa6ab86 1228 struct iwl_spectrum_notification measure_report;
5d08cd1d 1229 u8 measurement_status;
81963d68 1230
5d08cd1d
CH
1231 /* ucode beacon time */
1232 u32 ucode_beacon_time;
a13d276f 1233 int missed_beacon_threshold;
5d08cd1d 1234
a85d7cca
JB
1235 /* track IBSS manager (last beacon) status */
1236 u32 ibss_manager;
1237
410f2bb3
SG
1238 /* jiffies when last recovery from statistics was performed */
1239 unsigned long rx_statistics_jiffies;
3e4fb5fa 1240
a93e7973 1241 /* force reset */
8a472da4 1242 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1243
491bc292
WYG
1244 /* firmware reload counter and timestamp */
1245 unsigned long reload_jiffies;
1246 int reload_count;
1247
5a2a780c 1248 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1249 * Access via channel # using indirect index array */
bf85ea4f 1250 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1251 u8 channel_count; /* # of channels */
1252
5d08cd1d
CH
1253 /* thermal calibration */
1254 s32 temperature; /* degrees Kelvin */
1255 s32 last_temperature;
1256
7c616cba 1257 /* init calibration results */
6e21f2c1 1258 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1259
5d08cd1d 1260 /* Scan related variables */
5d08cd1d 1261 unsigned long scan_start;
5d08cd1d 1262 unsigned long scan_start_tsf;
811ecc99 1263 void *scan_cmd;
00700ee0 1264 enum ieee80211_band scan_band;
1ecf9fc1 1265 struct cfg80211_scan_request *scan_request;
f84b29ec 1266 struct ieee80211_vif *scan_vif;
266af4c7 1267 enum iwl_scan_type scan_type;
76eff18b
TW
1268 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1269 u8 mgmt_tx_ant;
5d08cd1d
CH
1270
1271 /* spinlock */
1272 spinlock_t lock; /* protect general shared data */
1273 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1274 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d
CH
1275 struct mutex mutex;
1276
d5934110 1277 struct iwl_bus *bus; /* bus specific data */
c85eb619 1278 struct iwl_trans trans;
5d08cd1d 1279
246ed355
JB
1280 /* microcode/device supports multiple contexts */
1281 u8 valid_contexts;
1282
13bb9483
JB
1283 /* command queue number */
1284 u8 cmd_queue;
1285
c10afb6e
JB
1286 /* max number of station keys */
1287 u8 sta_key_max_num;
1288
d2690c0d
JB
1289 bool new_scan_threshold_behaviour;
1290
c6fa17ed
WYG
1291 /* EEPROM MAC addresses */
1292 struct mac_address addresses[2];
1293
5d08cd1d 1294 /* uCode images, save to reload in case of failure */
b08dfd04 1295 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1296 u32 ucode_ver; /* version of ucode, copy of
1297 iwl_ucode.ver */
e98a1939
WYG
1298
1299 /* uCode owner: default: IWL_OWNERSHIP_DRIVER */
1300 u8 ucode_owner;
1301
dbf28e21
JB
1302 struct fw_img ucode_rt;
1303 struct fw_img ucode_init;
c8ac61cf 1304 struct fw_img ucode_wowlan;
dbf28e21 1305
872907bb 1306 enum iwlagn_ucode_type ucode_type;
dbb983b7 1307 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1308 char firmware_name[25];
5d08cd1d 1309
246ed355 1310 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1311
6f213ff1 1312 __le16 switch_channel;
0924e519 1313
d7d5783c
JB
1314 struct {
1315 u32 error_event_table;
1316 u32 log_event_table;
1317 } device_pointers;
5d08cd1d 1318
5d08cd1d 1319 u16 active_rate;
5d08cd1d 1320
5d08cd1d 1321 u8 start_calib;
f0832f13
EG
1322 struct iwl_sensitivity_data sensitivity_data;
1323 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1324 bool enhance_sensitivity_table;
5d08cd1d 1325 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1326 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1327
fad95bf5 1328 struct iwl_ht_config current_ht_config;
5d08cd1d 1329
5d08cd1d 1330 /* Rate scaling data */
5d08cd1d
CH
1331 u8 retry_rate;
1332
1333 wait_queue_head_t wait_command_queue;
1334
1335 int activity_timer_active;
1336
1337 /* Rx and Tx DMA processing queues */
a55360e4 1338 struct iwl_rx_queue rxq;
88804e2b 1339 struct iwl_tx_queue *txq;
5d08cd1d 1340 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1341 struct iwl_dma_ptr kw; /* keep warm address */
1342 struct iwl_dma_ptr scd_bc_tbls;
1343
5d08cd1d
CH
1344 u32 scd_base_addr; /* scheduler sram base address */
1345
1346 unsigned long status;
5d08cd1d 1347
19758bef 1348 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1349 struct traffic_stats tx_stats;
1350 struct traffic_stats rx_stats;
19758bef 1351
a83b9141
WYG
1352 /* counts interrupts */
1353 struct isr_statistics isr_stats;
1354
5da4b55f 1355 struct iwl_power_mgr power_data;
3ad3b92a 1356 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1357
9c5ac091
RC
1358 /* station table variables */
1359
1360 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1361 spinlock_t sta_lock;
1362 int num_stations;
3240cab3 1363 struct iwl_station_entry stations[IWLAGN_STATION_COUNT];
80fb47a1 1364 unsigned long ucode_key_table;
5d08cd1d 1365
e4e72fb4
JB
1366 /* queue refcounts */
1367#define IWL_MAX_HW_QUEUES 32
1368 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1369 /* for each AC */
1370 atomic_t queue_stop_count[4];
1371
5d08cd1d 1372 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1373 u8 is_open;
5d08cd1d
CH
1374
1375 u8 mac80211_registered;
5d08cd1d 1376
c8ac61cf
JB
1377 bool wowlan;
1378
af6b8ee3 1379 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1380 u8 *eeprom;
0848e297 1381 int nvm_device_type;
073d3f5f 1382 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1383
05c914fe 1384 enum nl80211_iftype iw_mode;
5d08cd1d 1385
5d08cd1d 1386 /* Last Rx'd beacon timestamp */
3109ece1 1387 u64 timestamp;
5d08cd1d 1388
0da0e5bf
JB
1389 struct {
1390 __le32 flag;
1391 struct statistics_general_common common;
1392 struct statistics_rx_non_phy rx_non_phy;
1393 struct statistics_rx_phy rx_ofdm;
1394 struct statistics_rx_ht_phy rx_ofdm_ht;
1395 struct statistics_rx_phy rx_cck;
1396 struct statistics_tx tx;
1397#ifdef CONFIG_IWLWIFI_DEBUGFS
1398 struct statistics_bt_activity bt_activity;
1399 __le32 num_bt_kills, accum_num_bt_kills;
1400#endif
1401 } statistics;
1402#ifdef CONFIG_IWLWIFI_DEBUGFS
1403 struct {
1404 struct statistics_general_common common;
1405 struct statistics_rx_non_phy rx_non_phy;
1406 struct statistics_rx_phy rx_ofdm;
1407 struct statistics_rx_ht_phy rx_ofdm_ht;
1408 struct statistics_rx_phy rx_cck;
1409 struct statistics_tx tx;
1410 struct statistics_bt_activity bt_activity;
1411 } accum_stats, delta_stats, max_delta_stats;
1412#endif
1413
898ed67b
WYG
1414 /* INT ICT Table */
1415 __le32 *ict_tbl;
1416 void *ict_tbl_vir;
1417 dma_addr_t ict_tbl_dma;
1418 dma_addr_t aligned_ict_tbl_dma;
1419 int ict_index;
1420 u32 inta;
1421 bool use_ict;
1422 /*
1423 * reporting the number of tids has AGG on. 0 means
1424 * no AGGREGATION
1425 */
1426 u8 agg_tids_count;
1427
1428 struct iwl_rx_phy_res last_phy_res;
1429 bool last_phy_res_valid;
1430
1431 struct completion firmware_loading_complete;
1432
1433 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1434 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1435
1436 /*
1437 * chain noise reset and gain commands are the
1438 * two extra calibration commands follows the standard
1439 * phy calibration commands
1440 */
1441 u8 phy_calib_chain_noise_reset_cmd;
1442 u8 phy_calib_chain_noise_gain_cmd;
1443
1444 /* counts reply_tx error */
1445 struct reply_tx_error_statistics reply_tx_stats;
1446 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
1447 /* notification wait support */
1448 struct list_head notif_waits;
1449 spinlock_t notif_wait_lock;
1450 wait_queue_head_t notif_waitq;
1451
1452 /* remain-on-channel offload support */
1453 struct ieee80211_channel *hw_roc_channel;
c6baf7fb 1454 struct delayed_work hw_roc_disable_work;
898ed67b
WYG
1455 enum nl80211_channel_type hw_roc_chantype;
1456 int hw_roc_duration;
1457 bool hw_roc_setup;
1458
22bf59a0 1459 /* bt coex */
f21dd005 1460 u8 bt_enable_flag;
da5dbb97 1461 u8 bt_status;
66e863a5 1462 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1463 bool bt_ch_announce;
bee008b7
WYG
1464 bool bt_full_concurrent;
1465 bool bt_ant_couple_ok;
fbba9410
WYG
1466 __le32 kill_ack_mask;
1467 __le32 kill_cts_mask;
1468 __le16 bt_valid;
22bf59a0
WYG
1469 u16 bt_on_thresh;
1470 u16 bt_duration;
1471 u16 dynamic_frag_thresh;
bee008b7 1472 u8 bt_ci_compliance;
9e4afc21 1473 struct work_struct bt_traffic_change_work;
207ecc5e
MV
1474 bool bt_enable_pspoll;
1475 struct iwl_rxon_context *cur_rssi_ctx;
1476 bool bt_is_sco;
9e4afc21 1477
5425e490 1478 struct iwl_hw_params hw_params;
4ddbb7d0 1479
40cefda9 1480 u32 inta_mask;
5d08cd1d 1481
5d08cd1d
CH
1482 struct workqueue_struct *workqueue;
1483
5d08cd1d 1484 struct work_struct restart;
5d08cd1d
CH
1485 struct work_struct scan_completed;
1486 struct work_struct rx_replenish;
5d08cd1d 1487 struct work_struct abort_scan;
12e934dc 1488
5d08cd1d 1489 struct work_struct beacon_update;
76d04815 1490 struct iwl_rxon_context *beacon_ctx;
12e934dc 1491 struct sk_buff *beacon_skb;
4ce7cc2b 1492 void *beacon_cmd;
76d04815 1493
a28027cd
WYG
1494 struct work_struct tt_work;
1495 struct work_struct ct_enter;
1496 struct work_struct ct_exit;
88be0264 1497 struct work_struct start_internal_scan;
65550636 1498 struct work_struct tx_flush;
bee008b7 1499 struct work_struct bt_full_concurrency;
fbba9410 1500 struct work_struct bt_runtime_config;
5d08cd1d
CH
1501
1502 struct tasklet_struct irq_tasklet;
1503
5d08cd1d 1504 struct delayed_work scan_check;
4a8a4322 1505
630fe9b6
TW
1506 /* TX Power */
1507 s8 tx_power_user_lmt;
dc1b0973 1508 s8 tx_power_device_lmt;
ae16fc3c 1509 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1510 s8 tx_power_next;
5d08cd1d 1511
5d08cd1d 1512
d08853a3 1513#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1514 /* debugging info */
3d816c77
RC
1515 u32 debug_level; /* per device debugging will override global
1516 iwl_debug_level if set */
d73e4923 1517#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1518#ifdef CONFIG_IWLWIFI_DEBUGFS
1519 /* debugfs */
20594eb0
WYG
1520 u16 tx_traffic_idx;
1521 u16 rx_traffic_idx;
1522 u8 *tx_traffic;
1523 u8 *rx_traffic;
4c84a8f1
JB
1524 struct dentry *debugfs_dir;
1525 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1526 bool disable_ht40;
c8ac61cf 1527 void *wowlan_sram;
712b6cf5 1528#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1529
1530 struct work_struct txpower_work;
445c2dff
TW
1531 u32 disable_sens_cal;
1532 u32 disable_chain_noise_cal;
16e727e8 1533 struct work_struct run_time_calib_work;
5d08cd1d 1534 struct timer_list statistics_periodic;
a9e1cb6a 1535 struct timer_list ucode_trace;
22de94de 1536 struct timer_list watchdog;
a9e1cb6a
WYG
1537
1538 struct iwl_event_log event_log;
5ed540ae
WYG
1539
1540 struct led_classdev led;
1541 unsigned long blink_on, blink_off;
1542 bool led_registered;
7a4e5281
WYG
1543#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1544 struct iwl_testmode_trace testmode_trace;
4e308119 1545 u32 tm_fixed_rate;
c10e2c10 1546#endif
6489854b 1547
c8ac61cf
JB
1548 /* WoWLAN GTK rekey data */
1549 u8 kck[NL80211_KCK_LEN], kek[NL80211_KEK_LEN];
1550 __le64 replay_ctr;
1551 __le16 last_seq_ctl;
1552 bool have_rekey_data;
c79dd5b5 1553}; /*iwl_priv */
5d08cd1d 1554
36470749
RR
1555static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1556{
1557 set_bit(txq_id, &priv->txq_ctx_active_msk);
1558}
1559
1560static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1561{
1562 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1563}
1564
994d31f7 1565#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1566/*
1567 * iwl_get_debug_level: Return active debug level for device
1568 *
1569 * Using sysfs it is possible to set per device debug level. This debug
1570 * level will be used if set, otherwise the global debug level which can be
1571 * set via module parameter is used.
1572 */
1573static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1574{
1575 if (priv->debug_level)
1576 return priv->debug_level;
1577 else
1578 return iwl_debug_level;
1579}
a332f8d6 1580#else
3d816c77
RC
1581static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1582{
1583 return iwl_debug_level;
1584}
a332f8d6
TW
1585#endif
1586
1587
a332f8d6
TW
1588static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1589 int txq_id, int idx)
1590{
ff0d91c3 1591 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1592 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1593 txb[idx].skb->data;
a332f8d6
TW
1594 return NULL;
1595}
a332f8d6 1596
246ed355
JB
1597static inline struct iwl_rxon_context *
1598iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1599{
1600 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1601
1602 return vif_priv->ctx;
1603}
1604
1605#define for_each_context(priv, ctx) \
1606 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1607 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1608 if (priv->valid_contexts & BIT(ctx->ctxid))
1609
054ec924 1610static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
246ed355 1611{
054ec924 1612 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
246ed355
JB
1613}
1614
054ec924
JB
1615static inline int iwl_is_associated(struct iwl_priv *priv,
1616 enum iwl_rxon_context_id ctxid)
246ed355 1617{
054ec924 1618 return iwl_is_associated_ctx(&priv->contexts[ctxid]);
246ed355 1619}
a332f8d6 1620
054ec924 1621static inline int iwl_is_any_associated(struct iwl_priv *priv)
5d08cd1d 1622{
054ec924
JB
1623 struct iwl_rxon_context *ctx;
1624 for_each_context(priv, ctx)
1625 if (iwl_is_associated_ctx(ctx))
1626 return true;
1627 return false;
5d08cd1d
CH
1628}
1629
bf85ea4f 1630static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1631{
1632 if (ch_info == NULL)
1633 return 0;
1634 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1635}
1636
bf85ea4f 1637static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1638{
1639 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1640}
1641
bf85ea4f 1642static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1643{
8318d78a 1644 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1645}
1646
bf85ea4f 1647static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1648{
8318d78a 1649 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1650}
1651
bf85ea4f 1652static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1653{
1654 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1655}
1656
bf85ea4f 1657static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1658{
1659 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1660}
1661
64a76b50
ZY
1662static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1663{
1664 __free_pages(page, priv->hw_params.rx_page_order);
64a76b50
ZY
1665}
1666
1667static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1668{
1669 free_pages(page, priv->hw_params.rx_page_order);
64a76b50 1670}
be1f3ab6 1671#endif /* __iwl_dev_h__ */
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