iwl3945: Remove DRV_NAME dependenies
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
ad97edd2 39#include "iwl-rfkill.h"
6bc913bd 40#include "iwl-eeprom.h"
5d08cd1d 41#include "iwl-4965-hw.h"
6f83eaa1 42#include "iwl-csr.h"
5d08cd1d 43#include "iwl-prph.h"
0a6857e7 44#include "iwl-debug.h"
ab53d8af 45#include "iwl-led.h"
5da4b55f 46#include "iwl-power.h"
e227ceac 47#include "iwl-agn-rs.h"
5d08cd1d 48
fed9017e
RR
49/* configuration for the iwl4965 */
50extern struct iwl_cfg iwl4965_agn_cfg;
5a6a256e
TW
51extern struct iwl_cfg iwl5300_agn_cfg;
52extern struct iwl_cfg iwl5100_agn_cfg;
53extern struct iwl_cfg iwl5350_agn_cfg;
47408639
EK
54extern struct iwl_cfg iwl5100_bg_cfg;
55extern struct iwl_cfg iwl5100_abg_cfg;
7100e924 56extern struct iwl_cfg iwl5150_agn_cfg;
fed9017e 57
099b40b7
RR
58/* CT-KILL constants */
59#define CT_KILL_THRESHOLD 110 /* in Celsius */
4bf775cd 60
5d08cd1d
CH
61/* Default noise level to report when noise measurement is not available.
62 * This may be because we're:
63 * 1) Not associated (4965, no beacon statistics being sent to driver)
64 * 2) Scanning (noise measurement does not apply to associated channel)
65 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
66 * Use default noise value of -127 ... this is below the range of measurable
67 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
68 * Also, -127 works better than 0 when averaging frames with/without
69 * noise info (e.g. averaging might be done in app); measured dBm values are
70 * always negative ... using a negative value as the default keeps all
71 * averages within an s8's (used in some apps) range of negative values. */
72#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
73
5d08cd1d
CH
74/*
75 * RTS threshold here is total size [2347] minus 4 FCS bytes
76 * Per spec:
77 * a value of 0 means RTS on all data/management packets
78 * a value > max MSDU size means no RTS
79 * else RTS for data/management frames where MPDU is larger
80 * than RTS value.
81 */
82#define DEFAULT_RTS_THRESHOLD 2347U
83#define MIN_RTS_THRESHOLD 0U
84#define MAX_RTS_THRESHOLD 2347U
85#define MAX_MSDU_SIZE 2304U
86#define MAX_MPDU_SIZE 2346U
87#define DEFAULT_BEACON_INTERVAL 100U
88#define DEFAULT_SHORT_RETRY_LIMIT 7U
89#define DEFAULT_LONG_RETRY_LIMIT 4U
90
a55360e4 91struct iwl_rx_mem_buffer {
4018517a
JB
92 dma_addr_t real_dma_addr;
93 dma_addr_t aligned_dma_addr;
5d08cd1d
CH
94 struct sk_buff *skb;
95 struct list_head list;
96};
97
5d08cd1d
CH
98/*
99 * Generic queue structure
100 *
101 * Contains common data for Rx and Tx queues
102 */
443cfd45 103struct iwl_queue {
5d08cd1d
CH
104 int n_bd; /* number of BDs in this queue */
105 int write_ptr; /* 1-st empty entry (index) host_w*/
106 int read_ptr; /* last used entry (index) host_r*/
107 dma_addr_t dma_addr; /* physical addr for BD's */
108 int n_window; /* safe queue window */
109 u32 id;
110 int low_mark; /* low watermark, resume queue if free
111 * space more than this */
112 int high_mark; /* high watermark, stop queue if free
113 * space less than this */
114} __attribute__ ((packed));
115
bc47279f 116/* One for each TFD */
8567c63e 117struct iwl_tx_info {
499b1883 118 struct sk_buff *skb[IWL_NUM_OF_TBS - 1];
5d08cd1d
CH
119};
120
121/**
16466903 122 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
123 * @q: generic Rx/Tx queue descriptor
124 * @bd: base of circular buffer of TFDs
125 * @cmd: array of command/Tx buffers
126 * @dma_addr_cmd: physical address of cmd/tx buffer array
127 * @txb: array of per-TFD driver data
128 * @need_update: indicates need to update read/write index
129 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 130 *
bc47279f
BC
131 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
132 * descriptors) and required locking structures.
5d08cd1d 133 */
16466903 134struct iwl_tx_queue {
443cfd45 135 struct iwl_queue q;
499b1883 136 struct iwl_tfd *tfds;
da99c4b6 137 struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS];
8567c63e 138 struct iwl_tx_info *txb;
3fd07a1e
TW
139 u8 need_update;
140 u8 sched_retry;
141 u8 active;
142 u8 swq_id;
5d08cd1d
CH
143};
144
145#define IWL_NUM_SCAN_RATES (2)
146
bb8c093b 147struct iwl4965_channel_tgd_info {
5d08cd1d
CH
148 u8 type;
149 s8 max_power;
150};
151
bb8c093b 152struct iwl4965_channel_tgh_info {
5d08cd1d
CH
153 s64 last_radar_time;
154};
155
5d08cd1d
CH
156/*
157 * One for each channel, holds all channel setup data
158 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
159 * with one another!
160 */
bf85ea4f 161struct iwl_channel_info {
bb8c093b
CH
162 struct iwl4965_channel_tgd_info tgd;
163 struct iwl4965_channel_tgh_info tgh;
073d3f5f
TW
164 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
165 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
166 * FAT channel */
5d08cd1d
CH
167
168 u8 channel; /* channel number */
169 u8 flags; /* flags copied from EEPROM */
170 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 171 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
172 s8 min_power; /* always 0 */
173 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
174
175 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
176 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 177 enum ieee80211_band band;
5d08cd1d 178
5d08cd1d
CH
179 /* FAT channel info */
180 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
181 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
182 s8 fat_min_power; /* always 0 */
183 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */
184 u8 fat_flags; /* flags copied from EEPROM */
fcd427bb 185 u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
186};
187
5d08cd1d
CH
188
189#define IWL_TX_FIFO_AC0 0
190#define IWL_TX_FIFO_AC1 1
191#define IWL_TX_FIFO_AC2 2
192#define IWL_TX_FIFO_AC3 3
193#define IWL_TX_FIFO_HCCA_1 5
194#define IWL_TX_FIFO_HCCA_2 6
195#define IWL_TX_FIFO_NONE 7
196
197/* Minimum number of queues. MAX_NUM is defined in hw specific files */
198#define IWL_MIN_NUM_QUEUES 4
199
200/* Power management (not Tx power) structures */
201
6f4083aa
TW
202enum iwl_pwr_src {
203 IWL_PWR_SRC_VMAIN,
204 IWL_PWR_SRC_VAUX,
205};
206
5d08cd1d
CH
207#define IEEE80211_DATA_LEN 2304
208#define IEEE80211_4ADDR_LEN 30
209#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
210#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
211
fcab423d 212struct iwl_frame {
5d08cd1d
CH
213 union {
214 struct ieee80211_hdr frame;
4bf64efd 215 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
216 u8 raw[IEEE80211_FRAME_LEN];
217 u8 cmd[360];
218 } u;
219 struct list_head list;
220};
221
5d08cd1d
CH
222#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
223#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
224#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
225
226enum {
227 /* CMD_SIZE_NORMAL = 0, */
228 CMD_SIZE_HUGE = (1 << 0),
229 /* CMD_SYNC = 0, */
230 CMD_ASYNC = (1 << 1),
231 /* CMD_NO_SKB = 0, */
232 CMD_WANT_SKB = (1 << 2),
233};
234
857485c0 235struct iwl_cmd;
c79dd5b5 236struct iwl_priv;
5d08cd1d 237
857485c0
TW
238struct iwl_cmd_meta {
239 struct iwl_cmd_meta *source;
5d08cd1d
CH
240 union {
241 struct sk_buff *skb;
c79dd5b5 242 int (*callback)(struct iwl_priv *priv,
857485c0 243 struct iwl_cmd *cmd, struct sk_buff *skb);
5d08cd1d
CH
244 } __attribute__ ((packed)) u;
245
246 /* The CMD_SIZE_HUGE flag bit indicates that the command
247 * structure is stored at the end of the shared queue memory. */
248 u32 flags;
499b1883
TW
249 DECLARE_PCI_UNMAP_ADDR(mapping)
250 DECLARE_PCI_UNMAP_LEN(len)
5d08cd1d
CH
251} __attribute__ ((packed));
252
d2f18bfd 253#define IWL_CMD_MAX_PAYLOAD 320
bd68fb6f 254
bc47279f 255/**
857485c0 256 * struct iwl_cmd
bc47279f
BC
257 *
258 * For allocation of the command and tx queues, this establishes the overall
259 * size of the largest command we send to uCode, except for a scan command
260 * (which is relatively huge; space is allocated separately).
261 */
857485c0
TW
262struct iwl_cmd {
263 struct iwl_cmd_meta meta; /* driver data */
264 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 265 union {
5d08cd1d
CH
266 u32 flags;
267 u8 val8;
268 u16 val16;
269 u32 val32;
83d527d9 270 struct iwl_tx_cmd tx;
bd68fb6f 271 u8 payload[IWL_CMD_MAX_PAYLOAD];
5d08cd1d
CH
272 } __attribute__ ((packed)) cmd;
273} __attribute__ ((packed));
274
3257e5d4 275
857485c0 276struct iwl_host_cmd {
5d08cd1d
CH
277 u8 id;
278 u16 len;
857485c0 279 struct iwl_cmd_meta meta;
5d08cd1d
CH
280 const void *data;
281};
282
857485c0
TW
283#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
284 sizeof(struct iwl_cmd_meta))
5d08cd1d
CH
285
286/*
287 * RX related structures and functions
288 */
289#define RX_FREE_BUFFERS 64
290#define RX_LOW_WATERMARK 8
291
292#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
293#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
294#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
295
296/**
a55360e4 297 * struct iwl_rx_queue - Rx queue
5d08cd1d
CH
298 * @read: Shared index to newest available Rx buffer
299 * @write: Shared index to oldest written Rx packet
300 * @free_count: Number of pre-allocated buffers in rx_free
301 * @rx_free: list of free SKBs for use
302 * @rx_used: List of Rx buffers with no SKB
303 * @need_update: flag to indicate we need to update read/write index
304 *
a55360e4 305 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 306 */
a55360e4 307struct iwl_rx_queue {
5d08cd1d
CH
308 __le32 *bd;
309 dma_addr_t dma_addr;
a55360e4
TW
310 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
311 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
312 u32 read;
313 u32 write;
314 u32 free_count;
315 struct list_head rx_free;
316 struct list_head rx_used;
317 int need_update;
8d86422a
WT
318 struct iwl_rb_status *rb_stts;
319 dma_addr_t rb_stts_dma;
5d08cd1d
CH
320 spinlock_t lock;
321};
322
323#define IWL_SUPPORTED_RATES_IE_LEN 8
324
5d08cd1d
CH
325#define MAX_TID_COUNT 9
326
327#define IWL_INVALID_RATE 0xFF
328#define IWL_INVALID_VALUE -1
329
bc47279f 330/**
6def9761 331 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
332 * @txq_id: Tx queue used for Tx attempt
333 * @frame_count: # frames attempted by Tx command
334 * @wait_for_ba: Expect block-ack before next Tx reply
335 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
336 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
337 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
338 * @rate_n_flags: Rate at which Tx was attempted
339 *
340 * If REPLY_TX indicates that aggregation was attempted, driver must wait
341 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
342 * until block ack arrives.
343 */
6def9761 344struct iwl_ht_agg {
5d08cd1d
CH
345 u16 txq_id;
346 u16 frame_count;
347 u16 wait_for_ba;
348 u16 start_idx;
fe01b477 349 u64 bitmap;
5d08cd1d 350 u32 rate_n_flags;
fe01b477
RR
351#define IWL_AGG_OFF 0
352#define IWL_AGG_ON 1
353#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
354#define IWL_EMPTYING_HW_QUEUE_DELBA 3
355 u8 state;
5d08cd1d 356};
fe01b477 357
5d08cd1d 358
6def9761 359struct iwl_tid_data {
5d08cd1d 360 u16 seq_number;
fe01b477 361 u16 tfds_in_queue;
6def9761 362 struct iwl_ht_agg agg;
5d08cd1d
CH
363};
364
6def9761 365struct iwl_hw_key {
5d08cd1d
CH
366 enum ieee80211_key_alg alg;
367 int keylen;
0211ddda 368 u8 keyidx;
5d08cd1d
CH
369 u8 key[32];
370};
371
bb8c093b 372union iwl4965_ht_rate_supp {
5d08cd1d
CH
373 u16 rates;
374 struct {
375 u8 siso_rate;
376 u8 mimo_rate;
377 };
378};
379
5d08cd1d 380#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
5d08cd1d
CH
381#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
382#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
383
9e0cc6de
RR
384struct iwl_ht_info {
385 /* self configuration data */
5d08cd1d 386 u8 is_ht;
9e0cc6de 387 u8 supported_chan_width;
12837be1 388 u8 sm_ps;
9e0cc6de 389 u8 is_green_field;
bb54244b 390 u8 sgf; /* HT_SHORT_GI_* short guard interval */
5d08cd1d
CH
391 u8 max_amsdu_size;
392 u8 ampdu_factor;
393 u8 mpdu_density;
d9fe60de 394 struct ieee80211_mcs_info mcs;
9e0cc6de 395 /* BSS related data */
5d08cd1d 396 u8 extension_chan_offset;
5d08cd1d 397 u8 tx_chan_width;
9e0cc6de
RR
398 u8 ht_protection;
399 u8 non_GF_STA_present;
5d08cd1d 400};
5d08cd1d 401
1ff50bda 402union iwl_qos_capabity {
5d08cd1d
CH
403 struct {
404 u8 edca_count:4; /* bit 0-3 */
405 u8 q_ack:1; /* bit 4 */
406 u8 queue_request:1; /* bit 5 */
407 u8 txop_request:1; /* bit 6 */
408 u8 reserved:1; /* bit 7 */
409 } q_AP;
410 struct {
411 u8 acvo_APSD:1; /* bit 0 */
412 u8 acvi_APSD:1; /* bit 1 */
413 u8 ac_bk_APSD:1; /* bit 2 */
414 u8 ac_be_APSD:1; /* bit 3 */
415 u8 q_ack:1; /* bit 4 */
416 u8 max_len:2; /* bit 5-6 */
417 u8 more_data_ack:1; /* bit 7 */
418 } q_STA;
419 u8 val;
420};
421
422/* QoS structures */
1ff50bda 423struct iwl_qos_info {
5d08cd1d 424 int qos_active;
1ff50bda
EG
425 union iwl_qos_capabity qos_cap;
426 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 427};
5d08cd1d
CH
428
429#define STA_PS_STATUS_WAKE 0
430#define STA_PS_STATUS_SLEEP 1
431
6def9761 432struct iwl_station_entry {
133636de 433 struct iwl_addsta_cmd sta;
6def9761 434 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d
CH
435 u8 used;
436 u8 ps_status;
6def9761 437 struct iwl_hw_key keyinfo;
5d08cd1d
CH
438};
439
440/* one for each uCode image (inst/data, boot/init/runtime) */
441struct fw_desc {
442 void *v_addr; /* access by driver */
443 dma_addr_t p_addr; /* access by card's busmaster DMA */
444 u32 len; /* bytes */
445};
446
447/* uCode file layout */
14b3d338 448struct iwl_ucode {
c02b3acd 449 __le32 ver; /* major/minor/API/serial */
5d08cd1d
CH
450 __le32 inst_size; /* bytes of runtime instructions */
451 __le32 data_size; /* bytes of runtime data */
452 __le32 init_size; /* bytes of initialization instructions */
453 __le32 init_data_size; /* bytes of initialization data */
454 __le32 boot_size; /* bytes of bootstrap instructions */
455 u8 data[0]; /* data in same order as "size" elements */
456};
457
bb8c093b 458struct iwl4965_ibss_seq {
5d08cd1d
CH
459 u8 mac[ETH_ALEN];
460 u16 seq_num;
461 u16 frag_num;
462 unsigned long packet_time;
463 struct list_head list;
464};
465
f0832f13
EG
466struct iwl_sensitivity_ranges {
467 u16 min_nrg_cck;
468 u16 max_nrg_cck;
469
470 u16 nrg_th_cck;
471 u16 nrg_th_ofdm;
472
473 u16 auto_corr_min_ofdm;
474 u16 auto_corr_min_ofdm_mrc;
475 u16 auto_corr_min_ofdm_x1;
476 u16 auto_corr_min_ofdm_mrc_x1;
477
478 u16 auto_corr_max_ofdm;
479 u16 auto_corr_max_ofdm_mrc;
480 u16 auto_corr_max_ofdm_x1;
481 u16 auto_corr_max_ofdm_mrc_x1;
482
483 u16 auto_corr_max_cck;
484 u16 auto_corr_max_cck_mrc;
485 u16 auto_corr_min_cck;
486 u16 auto_corr_min_cck_mrc;
487};
488
099b40b7 489
b5047f78
TW
490#define KELVIN_TO_CELSIUS(x) ((x)-273)
491#define CELSIUS_TO_KELVIN(x) ((x)+273)
492
493
bc47279f 494/**
5425e490 495 * struct iwl_hw_params
bc47279f 496 * @max_txq_num: Max # Tx queues supported
f3f911d1 497 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 498 * @scd_bc_tbls_size: size of scheduler byte count tables
099b40b7
RR
499 * @tx/rx_chains_num: Number of TX/RX chains
500 * @valid_tx/rx_ant: usable antennas
bc47279f 501 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 502 * @max_rxq_log: Log-base-2 of max_rxq_size
099b40b7 503 * @rx_buf_size: Rx buffer size
bc47279f
BC
504 * @max_stations:
505 * @bcast_sta_id:
099b40b7
RR
506 * @fat_channel: is 40MHz width possible in band 2.4
507 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
508 * @sw_crypto: 0 for hw, 1 for sw
509 * @max_xxx_size: for ucode uses
510 * @ct_kill_threshold: temperature threshold
a96a27f9 511 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 512 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 513 */
5425e490 514struct iwl_hw_params {
f3f911d1
ZY
515 u8 max_txq_num;
516 u8 dma_chnl_num;
4ddbb7d0 517 u16 scd_bc_tbls_size;
ec35cf2a
TW
518 u8 tx_chains_num;
519 u8 rx_chains_num;
520 u8 valid_tx_ant;
521 u8 valid_rx_ant;
5d08cd1d 522 u16 max_rxq_size;
ec35cf2a 523 u16 max_rxq_log;
9ee1ba47
RR
524 u32 rx_buf_size;
525 u32 max_pkt_size;
5d08cd1d
CH
526 u8 max_stations;
527 u8 bcast_sta_id;
099b40b7
RR
528 u8 fat_channel;
529 u8 sw_crypto;
530 u32 max_inst_size;
531 u32 max_data_size;
532 u32 max_bsm_size;
533 u32 ct_kill_threshold; /* value in hw-dependent units */
be5d56ed 534 u32 calib_init_cfg;
f0832f13 535 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
536};
537
5d08cd1d 538
5d08cd1d
CH
539/******************************************************************************
540 *
a33c2f47
EG
541 * Functions implemented in core module which are forward declared here
542 * for use by iwl-[4-5].c
5d08cd1d 543 *
a33c2f47
EG
544 * NOTE: The implementation of these functions are not hardware specific
545 * which is why they are in the core module files.
5d08cd1d
CH
546 *
547 * Naming convention --
a33c2f47 548 * iwl_ <-- Is part of iwlwifi
5d08cd1d 549 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
550 * iwl4965_bg_ <-- Called from work queue context
551 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
552 *
553 ****************************************************************************/
5b9f8cd3
EG
554extern void iwl_update_chain_flags(struct iwl_priv *priv);
555extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 556extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 557extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 558extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 559extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
560static inline int iwl_queue_used(const struct iwl_queue *q, int i)
561{
562 return q->write_ptr > q->read_ptr ?
563 (i >= q->read_ptr && i < q->write_ptr) :
564 !(i < q->read_ptr && i >= q->write_ptr);
565}
566
567
568static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
569{
570 /* This is for scan command, the big buffer at end of command array */
571 if (is_huge)
572 return q->n_window; /* must be power of 2 */
573
574 /* Otherwise, use normal size buffers */
575 return index & (q->n_window - 1);
576}
577
578
4ddbb7d0
TW
579struct iwl_dma_ptr {
580 dma_addr_t dma;
581 void *addr;
b481de9c
ZY
582 size_t size;
583};
584
34c22cf9
WT
585#define HT_SHORT_GI_20MHZ (1 << 0)
586#define HT_SHORT_GI_40MHZ (1 << 1)
587
b481de9c
ZY
588#define IWL_CHANNEL_WIDTH_20MHZ 0
589#define IWL_CHANNEL_WIDTH_40MHZ 1
590
b481de9c
ZY
591#define IWL_OPERATION_MODE_AUTO 0
592#define IWL_OPERATION_MODE_HT_ONLY 1
593#define IWL_OPERATION_MODE_MIXED 2
594#define IWL_OPERATION_MODE_20MHZ 3
595
3195cdb7
TW
596#define IWL_TX_CRC_SIZE 4
597#define IWL_TX_DELIMITER_SIZE 4
b481de9c 598
b481de9c 599#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 600
b481de9c 601/* Sensitivity and chain noise calibration */
b481de9c
ZY
602#define INITIALIZATION_VALUE 0xFFFF
603#define CAL_NUM_OF_BEACONS 20
604#define MAXIMUM_ALLOWED_PATHLOSS 15
605
b481de9c
ZY
606#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
607
608#define MAX_FA_OFDM 50
609#define MIN_FA_OFDM 5
610#define MAX_FA_CCK 50
611#define MIN_FA_CCK 5
612
b481de9c
ZY
613#define AUTO_CORR_STEP_OFDM 1
614
b481de9c
ZY
615#define AUTO_CORR_STEP_CCK 3
616#define AUTO_CORR_MAX_TH_CCK 160
617
b481de9c
ZY
618#define NRG_DIFF 2
619#define NRG_STEP_CCK 2
620#define NRG_MARGIN 8
621#define MAX_NUMBER_CCK_NO_FA 100
622
623#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
624
625#define CHAIN_A 0
626#define CHAIN_B 1
627#define CHAIN_C 2
628#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
629#define ALL_BAND_FILTER 0xFF00
630#define IN_BAND_FILTER 0xFF
631#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
632
3195cdb7
TW
633#define NRG_NUM_PREV_STAT_L 20
634#define NUM_RX_CHAINS 3
635
bb8c093b 636enum iwl4965_false_alarm_state {
b481de9c
ZY
637 IWL_FA_TOO_MANY = 0,
638 IWL_FA_TOO_FEW = 1,
639 IWL_FA_GOOD_RANGE = 2,
640};
641
bb8c093b 642enum iwl4965_chain_noise_state {
b481de9c 643 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
644 IWL_CHAIN_NOISE_ACCUMULATE,
645 IWL_CHAIN_NOISE_CALIBRATED,
646 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
647};
648
bb8c093b 649enum iwl4965_calib_enabled_state {
b481de9c
ZY
650 IWL_CALIB_DISABLED = 0, /* must be 0 */
651 IWL_CALIB_ENABLED = 1,
652};
653
f69f42a6
TW
654
655/*
656 * enum iwl_calib
657 * defines the order in which results of initial calibrations
658 * should be sent to the runtime uCode
659 */
660enum iwl_calib {
661 IWL_CALIB_XTAL,
819500c5 662 IWL_CALIB_DC,
f69f42a6
TW
663 IWL_CALIB_LO,
664 IWL_CALIB_TX_IQ,
665 IWL_CALIB_TX_IQ_PERD,
201706ac 666 IWL_CALIB_BASE_BAND,
f69f42a6
TW
667 IWL_CALIB_MAX
668};
669
6e21f2c1
TW
670/* Opaque calibration results */
671struct iwl_calib_result {
672 void *buf;
673 size_t buf_len;
7c616cba
TW
674};
675
dbb983b7
RR
676enum ucode_type {
677 UCODE_NONE = 0,
678 UCODE_INIT,
679 UCODE_RT
680};
681
b481de9c 682/* Sensitivity calib data */
f0832f13 683struct iwl_sensitivity_data {
b481de9c
ZY
684 u32 auto_corr_ofdm;
685 u32 auto_corr_ofdm_mrc;
686 u32 auto_corr_ofdm_x1;
687 u32 auto_corr_ofdm_mrc_x1;
688 u32 auto_corr_cck;
689 u32 auto_corr_cck_mrc;
690
691 u32 last_bad_plcp_cnt_ofdm;
692 u32 last_fa_cnt_ofdm;
693 u32 last_bad_plcp_cnt_cck;
694 u32 last_fa_cnt_cck;
695
696 u32 nrg_curr_state;
697 u32 nrg_prev_state;
698 u32 nrg_value[10];
699 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
700 u32 nrg_silence_ref;
701 u32 nrg_energy_idx;
702 u32 nrg_silence_idx;
703 u32 nrg_th_cck;
704 s32 nrg_auto_corr_silence_diff;
705 u32 num_in_cck_no_fa;
706 u32 nrg_th_ofdm;
b481de9c
ZY
707};
708
709/* Chain noise (differential Rx gain) calib data */
f0832f13 710struct iwl_chain_noise_data {
04816448 711 u32 active_chains;
b481de9c
ZY
712 u32 chain_noise_a;
713 u32 chain_noise_b;
714 u32 chain_noise_c;
715 u32 chain_signal_a;
716 u32 chain_signal_b;
717 u32 chain_signal_c;
04816448 718 u16 beacon_count;
b481de9c
ZY
719 u8 disconn_array[NUM_RX_CHAINS];
720 u8 delta_gain_code[NUM_RX_CHAINS];
721 u8 radio_write;
04816448 722 u8 state;
b481de9c
ZY
723};
724
abceddb4
BC
725#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
726#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 727
5d08cd1d 728
5d08cd1d
CH
729enum {
730 MEASUREMENT_READY = (1 << 0),
731 MEASUREMENT_ACTIVE = (1 << 1),
732};
733
5d08cd1d 734
dfe7d458
RR
735#define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */
736
c79dd5b5 737struct iwl_priv {
5d08cd1d
CH
738
739 /* ieee device used by generic ieee processing code */
740 struct ieee80211_hw *hw;
741 struct ieee80211_channel *ieee_channels;
742 struct ieee80211_rate *ieee_rates;
82b9a121 743 struct iwl_cfg *cfg;
5d08cd1d
CH
744
745 /* temporary frame storage list */
746 struct list_head free_frames;
747 int frames_count;
748
8318d78a 749 enum ieee80211_band band;
5d08cd1d
CH
750 int alloc_rxb_skb;
751
c79dd5b5 752 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 753 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 754
8318d78a 755 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 756
4fc22b21 757#ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT
5d08cd1d 758 /* spectrum measurement report caching */
2aa6ab86 759 struct iwl_spectrum_notification measure_report;
5d08cd1d
CH
760 u8 measurement_status;
761#endif
762 /* ucode beacon time */
763 u32 ucode_beacon_time;
764
bb8c093b 765 /* we allocate array of iwl4965_channel_info for NIC's valid channels.
5d08cd1d 766 * Access via channel # using indirect index array */
bf85ea4f 767 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
768 u8 channel_count; /* # of channels */
769
5d08cd1d
CH
770 /* thermal calibration */
771 s32 temperature; /* degrees Kelvin */
772 s32 last_temperature;
773
7c616cba 774 /* init calibration results */
6e21f2c1 775 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 776
5d08cd1d
CH
777 /* Scan related variables */
778 unsigned long last_scan_jiffies;
7878a5a4 779 unsigned long next_scan_jiffies;
5d08cd1d
CH
780 unsigned long scan_start;
781 unsigned long scan_pass_start;
782 unsigned long scan_start_tsf;
76eff18b 783 struct iwl_scan_cmd *scan;
5d08cd1d
CH
784 int scan_bands;
785 int one_direct_scan;
786 u8 direct_ssid_len;
787 u8 direct_ssid[IW_ESSID_MAX_SIZE];
76eff18b
TW
788 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
789 u8 mgmt_tx_ant;
5d08cd1d
CH
790
791 /* spinlock */
792 spinlock_t lock; /* protect general shared data */
793 spinlock_t hcmd_lock; /* protect hcmd */
794 struct mutex mutex;
795
796 /* basic pci-network driver stuff */
797 struct pci_dev *pci_dev;
798
799 /* pci hardware address support */
800 void __iomem *hw_base;
b661c819
TW
801 u32 hw_rev;
802 u32 hw_wa_rev;
803 u8 rev_id;
5d08cd1d
CH
804
805 /* uCode images, save to reload in case of failure */
c02b3acd
CR
806 u32 ucode_ver; /* version of ucode, copy of
807 iwl_ucode.ver */
5d08cd1d
CH
808 struct fw_desc ucode_code; /* runtime inst */
809 struct fw_desc ucode_data; /* runtime data original */
810 struct fw_desc ucode_data_backup; /* runtime data save/restore */
811 struct fw_desc ucode_init; /* initialization inst */
812 struct fw_desc ucode_init_data; /* initialization data */
813 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
814 enum ucode_type ucode_type;
815 u8 ucode_write_complete; /* the image write is complete */
5d08cd1d
CH
816
817
3195c1f3 818 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
819
820 /* We declare this const so it can only be
821 * changed via explicit cast within the
822 * routines that actually update the physical
823 * hardware */
c1adf9fb
GG
824 const struct iwl_rxon_cmd active_rxon;
825 struct iwl_rxon_cmd staging_rxon;
5d08cd1d
CH
826
827 int error_recovering;
c1adf9fb 828 struct iwl_rxon_cmd recovery_rxon;
5d08cd1d
CH
829
830 /* 1st responses from initialize and runtime uCode images.
831 * 4965's initialize alive response contains some calibration data. */
885ba202
TW
832 struct iwl_init_alive_resp card_alive_init;
833 struct iwl_alive_resp card_alive;
eadd3c4b 834#ifdef CONFIG_IWLWIFI_RFKILL
80fcc9e2 835 struct rfkill *rfkill;
ad97edd2 836#endif
5d08cd1d 837
36316126 838#ifdef CONFIG_IWLWIFI_LEDS
0eee6127 839 struct iwl_led led[IWL_LED_TRG_MAX];
ab53d8af
MA
840 unsigned long last_blink_time;
841 u8 last_blink_rate;
842 u8 allow_blinking;
843 u64 led_tpt;
5d08cd1d
CH
844#endif
845
846 u16 active_rate;
847 u16 active_rate_basic;
848
5d08cd1d 849 u8 assoc_station_added;
5d08cd1d 850 u8 start_calib;
f0832f13
EG
851 struct iwl_sensitivity_data sensitivity_data;
852 struct iwl_chain_noise_data chain_noise_data;
5d08cd1d 853 __le16 sensitivity_tbl[HD_TABLE_SIZE];
5d08cd1d 854
9e0cc6de 855 struct iwl_ht_info current_ht_config;
5d08cd1d
CH
856 u8 last_phy_res[100];
857
5d08cd1d
CH
858 /* Rate scaling data */
859 s8 data_retry_limit;
860 u8 retry_rate;
861
862 wait_queue_head_t wait_command_queue;
863
864 int activity_timer_active;
865
866 /* Rx and Tx DMA processing queues */
a55360e4 867 struct iwl_rx_queue rxq;
16466903 868 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
5d08cd1d 869 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
870 struct iwl_dma_ptr kw; /* keep warm address */
871 struct iwl_dma_ptr scd_bc_tbls;
872
5d08cd1d
CH
873 u32 scd_base_addr; /* scheduler sram base address */
874
875 unsigned long status;
5d08cd1d 876
a96a27f9 877 int last_rx_rssi; /* From Rx packet statistics */
5d08cd1d
CH
878 int last_rx_noise; /* From beacon statistics */
879
19758bef
TW
880 /* counts mgmt, ctl, and data packets */
881 struct traffic_stats {
882 u32 cnt;
883 u64 bytes;
884 } tx_stats[3], rx_stats[3];
885
5da4b55f 886 struct iwl_power_mgr power_data;
5d08cd1d 887
8f91aecb 888 struct iwl_notif_statistics statistics;
5d08cd1d
CH
889 unsigned long last_statistics_time;
890
891 /* context information */
5d08cd1d
CH
892 u16 rates_mask;
893
894 u32 power_mode;
895 u32 antenna;
896 u8 bssid[ETH_ALEN];
897 u16 rts_threshold;
898 u8 mac_addr[ETH_ALEN];
899
900 /*station table variables */
901 spinlock_t sta_lock;
902 int num_stations;
6def9761 903 struct iwl_station_entry stations[IWL_STATION_COUNT];
6974e363
EG
904 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
905 u8 default_wep_key;
906 u8 key_mapping_key;
80fb47a1 907 unsigned long ucode_key_table;
5d08cd1d
CH
908
909 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 910 u8 is_open;
5d08cd1d
CH
911
912 u8 mac80211_registered;
5d08cd1d 913
5d08cd1d
CH
914 /* Rx'd packet timing information */
915 u32 last_beacon_time;
916 u64 last_tsf;
917
5d08cd1d 918 /* eeprom */
073d3f5f
TW
919 u8 *eeprom;
920 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 921
05c914fe 922 enum nl80211_iftype iw_mode;
5d08cd1d
CH
923
924 struct sk_buff *ibss_beacon;
925
926 /* Last Rx'd beacon timestamp */
3109ece1 927 u64 timestamp;
5d08cd1d 928 u16 beacon_int;
32bfd35d 929 struct ieee80211_vif *vif;
5d08cd1d 930
5425e490 931 struct iwl_hw_params hw_params;
4ddbb7d0 932
059ff826 933
5d08cd1d
CH
934 /* Current association information needed to configure the
935 * hardware */
936 u16 assoc_id;
937 u16 assoc_capability;
5d08cd1d 938
1ff50bda 939 struct iwl_qos_info qos_data;
5d08cd1d
CH
940
941 struct workqueue_struct *workqueue;
942
943 struct work_struct up;
944 struct work_struct restart;
945 struct work_struct calibrated_work;
946 struct work_struct scan_completed;
947 struct work_struct rx_replenish;
948 struct work_struct rf_kill;
949 struct work_struct abort_scan;
950 struct work_struct update_link_led;
951 struct work_struct auth_work;
952 struct work_struct report_work;
953 struct work_struct request_scan;
954 struct work_struct beacon_update;
955
956 struct tasklet_struct irq_tasklet;
957
c90a74ba 958 struct delayed_work set_power_save;
5d08cd1d
CH
959 struct delayed_work init_alive_start;
960 struct delayed_work alive_start;
5d08cd1d 961 struct delayed_work scan_check;
630fe9b6
TW
962 /* TX Power */
963 s8 tx_power_user_lmt;
964 s8 tx_power_channel_lmt;
5d08cd1d 965
5d08cd1d 966
0a6857e7 967#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 968 /* debugging info */
bf403db8 969 u32 debug_level;
5d08cd1d
CH
970 u32 framecnt_to_us;
971 atomic_t restrict_refcnt;
712b6cf5
TW
972#ifdef CONFIG_IWLWIFI_DEBUGFS
973 /* debugfs */
974 struct iwl_debugfs *dbgfs;
975#endif /* CONFIG_IWLWIFI_DEBUGFS */
976#endif /* CONFIG_IWLWIFI_DEBUG */
5d08cd1d
CH
977
978 struct work_struct txpower_work;
445c2dff
TW
979 u32 disable_sens_cal;
980 u32 disable_chain_noise_cal;
203566f3 981 u32 disable_tx_power_cal;
16e727e8 982 struct work_struct run_time_calib_work;
5d08cd1d 983 struct timer_list statistics_periodic;
c79dd5b5 984}; /*iwl_priv */
5d08cd1d 985
36470749
RR
986static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
987{
988 set_bit(txq_id, &priv->txq_ctx_active_msk);
989}
990
991static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
992{
993 clear_bit(txq_id, &priv->txq_ctx_active_msk);
994}
995
994d31f7 996#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW
997const char *iwl_get_tx_fail_reason(u32 status);
998#else
999static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
1000#endif
1001
1002
a332f8d6
TW
1003static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1004 int txq_id, int idx)
1005{
1006 if (priv->txq[txq_id].txb[idx].skb[0])
1007 return (struct ieee80211_hdr *)priv->txq[txq_id].
1008 txb[idx].skb[0]->data;
1009 return NULL;
1010}
a332f8d6
TW
1011
1012
3109ece1 1013static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1014{
1015 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1016}
1017
bf85ea4f 1018static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1019{
1020 if (ch_info == NULL)
1021 return 0;
1022 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1023}
1024
bf85ea4f 1025static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1026{
1027 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1028}
1029
bf85ea4f 1030static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1031{
8318d78a 1032 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1033}
1034
bf85ea4f 1035static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1036{
8318d78a 1037 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1038}
1039
bf85ea4f 1040static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1041{
1042 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1043}
1044
bf85ea4f 1045static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1046{
1047 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1048}
1049
be1f3ab6 1050#endif /* __iwl_dev_h__ */
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