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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
fcd427bb | 26 | /* |
3e0d4cb1 | 27 | * Please use this file (iwl-dev.h) for driver implementation definitions. |
5a36ba0e | 28 | * Please use iwl-commands.h for uCode API definitions. |
fcd427bb BC |
29 | * Please use iwl-4965-hw.h for hardware-related definitions. |
30 | */ | |
31 | ||
be1f3ab6 EG |
32 | #ifndef __iwl_dev_h__ |
33 | #define __iwl_dev_h__ | |
b481de9c | 34 | |
5d08cd1d CH |
35 | #include <linux/pci.h> /* for struct pci_device_id */ |
36 | #include <linux/kernel.h> | |
37 | #include <net/ieee80211_radiotap.h> | |
38 | ||
6bc913bd | 39 | #include "iwl-eeprom.h" |
6f83eaa1 | 40 | #include "iwl-csr.h" |
5d08cd1d | 41 | #include "iwl-prph.h" |
dbb6654c | 42 | #include "iwl-fh.h" |
0a6857e7 | 43 | #include "iwl-debug.h" |
dbb6654c WT |
44 | #include "iwl-4965-hw.h" |
45 | #include "iwl-3945-hw.h" | |
46 | #include "iwl-3945-led.h" | |
ab53d8af | 47 | #include "iwl-led.h" |
5da4b55f | 48 | #include "iwl-power.h" |
e227ceac | 49 | #include "iwl-agn-rs.h" |
5d08cd1d | 50 | |
fed9017e RR |
51 | /* configuration for the iwl4965 */ |
52 | extern struct iwl_cfg iwl4965_agn_cfg; | |
5a6a256e TW |
53 | extern struct iwl_cfg iwl5300_agn_cfg; |
54 | extern struct iwl_cfg iwl5100_agn_cfg; | |
55 | extern struct iwl_cfg iwl5350_agn_cfg; | |
47408639 EK |
56 | extern struct iwl_cfg iwl5100_bg_cfg; |
57 | extern struct iwl_cfg iwl5100_abg_cfg; | |
7100e924 | 58 | extern struct iwl_cfg iwl5150_agn_cfg; |
e1228374 JS |
59 | extern struct iwl_cfg iwl6000_2ag_cfg; |
60 | extern struct iwl_cfg iwl6000_2agn_cfg; | |
61 | extern struct iwl_cfg iwl6000_3agn_cfg; | |
62 | extern struct iwl_cfg iwl6050_2agn_cfg; | |
63 | extern struct iwl_cfg iwl6050_3agn_cfg; | |
77dcb6a9 | 64 | extern struct iwl_cfg iwl1000_bgn_cfg; |
fed9017e | 65 | |
672639de WYG |
66 | struct iwl_tx_queue; |
67 | ||
cec2d3f3 JS |
68 | /* shared structures from iwl-5000.c */ |
69 | extern struct iwl_mod_params iwl50_mod_params; | |
70 | extern struct iwl_ops iwl5000_ops; | |
cc0f555d | 71 | extern struct iwl_ucode_ops iwl5000_ucode; |
e8c00dcb JS |
72 | extern struct iwl_lib_ops iwl5000_lib; |
73 | extern struct iwl_hcmd_ops iwl5000_hcmd; | |
74 | extern struct iwl_hcmd_utils_ops iwl5000_hcmd_utils; | |
75 | ||
76 | /* shared functions from iwl-5000.c */ | |
77 | extern u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len); | |
78 | extern u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, | |
79 | u8 *data); | |
80 | extern void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, | |
81 | __le32 *tx_flags); | |
82 | extern int iwl5000_calc_rssi(struct iwl_priv *priv, | |
83 | struct iwl_rx_phy_res *rx_resp); | |
672639de WYG |
84 | extern int iwl5000_apm_init(struct iwl_priv *priv); |
85 | extern void iwl5000_apm_stop(struct iwl_priv *priv); | |
86 | extern int iwl5000_apm_reset(struct iwl_priv *priv); | |
87 | extern void iwl5000_nic_config(struct iwl_priv *priv); | |
88 | extern u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv); | |
89 | extern const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, | |
90 | size_t offset); | |
91 | extern void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
92 | struct iwl_tx_queue *txq, | |
93 | u16 byte_cnt); | |
94 | extern void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, | |
95 | struct iwl_tx_queue *txq); | |
96 | extern int iwl5000_load_ucode(struct iwl_priv *priv); | |
97 | extern void iwl5000_init_alive_start(struct iwl_priv *priv); | |
98 | extern int iwl5000_alive_notify(struct iwl_priv *priv); | |
99 | extern int iwl5000_hw_set_hw_params(struct iwl_priv *priv); | |
100 | extern int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |
101 | int tx_fifo, int sta_id, int tid, u16 ssn_idx); | |
102 | extern int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |
103 | u16 ssn_idx, u8 tx_fifo); | |
104 | extern void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask); | |
105 | extern void iwl5000_setup_deferred_work(struct iwl_priv *priv); | |
106 | extern void iwl5000_rx_handler_setup(struct iwl_priv *priv); | |
107 | extern int iwl5000_hw_valid_rtc_data_addr(u32 addr); | |
108 | extern int iwl5000_send_tx_power(struct iwl_priv *priv); | |
109 | extern void iwl5000_temperature(struct iwl_priv *priv); | |
cec2d3f3 | 110 | |
099b40b7 | 111 | /* CT-KILL constants */ |
672639de WYG |
112 | #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ |
113 | #define CT_KILL_THRESHOLD 114 /* in Celsius */ | |
114 | #define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ | |
4bf775cd | 115 | |
5d08cd1d CH |
116 | /* Default noise level to report when noise measurement is not available. |
117 | * This may be because we're: | |
118 | * 1) Not associated (4965, no beacon statistics being sent to driver) | |
119 | * 2) Scanning (noise measurement does not apply to associated channel) | |
120 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
121 | * Use default noise value of -127 ... this is below the range of measurable | |
122 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
123 | * Also, -127 works better than 0 when averaging frames with/without | |
124 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
125 | * always negative ... using a negative value as the default keeps all | |
126 | * averages within an s8's (used in some apps) range of negative values. */ | |
127 | #define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
128 | ||
5d08cd1d CH |
129 | /* |
130 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
131 | * Per spec: | |
132 | * a value of 0 means RTS on all data/management packets | |
133 | * a value > max MSDU size means no RTS | |
134 | * else RTS for data/management frames where MPDU is larger | |
135 | * than RTS value. | |
136 | */ | |
137 | #define DEFAULT_RTS_THRESHOLD 2347U | |
138 | #define MIN_RTS_THRESHOLD 0U | |
139 | #define MAX_RTS_THRESHOLD 2347U | |
140 | #define MAX_MSDU_SIZE 2304U | |
141 | #define MAX_MPDU_SIZE 2346U | |
142 | #define DEFAULT_BEACON_INTERVAL 100U | |
143 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
144 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
145 | ||
a55360e4 | 146 | struct iwl_rx_mem_buffer { |
4018517a JB |
147 | dma_addr_t real_dma_addr; |
148 | dma_addr_t aligned_dma_addr; | |
5d08cd1d CH |
149 | struct sk_buff *skb; |
150 | struct list_head list; | |
151 | }; | |
152 | ||
5d08cd1d CH |
153 | /* |
154 | * Generic queue structure | |
155 | * | |
156 | * Contains common data for Rx and Tx queues | |
157 | */ | |
443cfd45 | 158 | struct iwl_queue { |
5d08cd1d CH |
159 | int n_bd; /* number of BDs in this queue */ |
160 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
161 | int read_ptr; /* last used entry (index) host_r*/ | |
162 | dma_addr_t dma_addr; /* physical addr for BD's */ | |
163 | int n_window; /* safe queue window */ | |
164 | u32 id; | |
165 | int low_mark; /* low watermark, resume queue if free | |
166 | * space more than this */ | |
167 | int high_mark; /* high watermark, stop queue if free | |
168 | * space less than this */ | |
169 | } __attribute__ ((packed)); | |
170 | ||
bc47279f | 171 | /* One for each TFD */ |
8567c63e | 172 | struct iwl_tx_info { |
499b1883 | 173 | struct sk_buff *skb[IWL_NUM_OF_TBS - 1]; |
5d08cd1d CH |
174 | }; |
175 | ||
176 | /** | |
16466903 | 177 | * struct iwl_tx_queue - Tx Queue for DMA |
bc47279f BC |
178 | * @q: generic Rx/Tx queue descriptor |
179 | * @bd: base of circular buffer of TFDs | |
180 | * @cmd: array of command/Tx buffers | |
181 | * @dma_addr_cmd: physical address of cmd/tx buffer array | |
182 | * @txb: array of per-TFD driver data | |
183 | * @need_update: indicates need to update read/write index | |
184 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
5d08cd1d | 185 | * |
bc47279f BC |
186 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame |
187 | * descriptors) and required locking structures. | |
5d08cd1d | 188 | */ |
188cf6c7 SO |
189 | #define TFD_TX_CMD_SLOTS 256 |
190 | #define TFD_CMD_SLOTS 32 | |
191 | ||
16466903 | 192 | struct iwl_tx_queue { |
443cfd45 | 193 | struct iwl_queue q; |
59606ffa | 194 | void *tfds; |
da99c4b6 | 195 | struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS]; |
8567c63e | 196 | struct iwl_tx_info *txb; |
3fd07a1e TW |
197 | u8 need_update; |
198 | u8 sched_retry; | |
199 | u8 active; | |
200 | u8 swq_id; | |
5d08cd1d CH |
201 | }; |
202 | ||
203 | #define IWL_NUM_SCAN_RATES (2) | |
204 | ||
bb8c093b | 205 | struct iwl4965_channel_tgd_info { |
5d08cd1d CH |
206 | u8 type; |
207 | s8 max_power; | |
208 | }; | |
209 | ||
bb8c093b | 210 | struct iwl4965_channel_tgh_info { |
5d08cd1d CH |
211 | s64 last_radar_time; |
212 | }; | |
213 | ||
d20b3c65 SO |
214 | #define IWL4965_MAX_RATE (33) |
215 | ||
85d41495 KA |
216 | struct iwl3945_clip_group { |
217 | /* maximum power level to prevent clipping for each rate, derived by | |
218 | * us from this band's saturation power in EEPROM */ | |
219 | const s8 clip_powers[IWL_MAX_RATES]; | |
220 | }; | |
221 | ||
d20b3c65 SO |
222 | /* current Tx power values to use, one for each rate for each channel. |
223 | * requested power is limited by: | |
224 | * -- regulatory EEPROM limits for this channel | |
225 | * -- hardware capabilities (clip-powers) | |
226 | * -- spectrum management | |
227 | * -- user preference (e.g. iwconfig) | |
228 | * when requested power is set, base power index must also be set. */ | |
229 | struct iwl3945_channel_power_info { | |
230 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
231 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
232 | s8 base_power_index; /* gain index for power at factory temp. */ | |
233 | s8 requested_power; /* power (dBm) requested for this chnl/rate */ | |
234 | }; | |
235 | ||
236 | /* current scan Tx power values to use, one for each scan rate for each | |
237 | * channel. */ | |
238 | struct iwl3945_scan_power_info { | |
239 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
240 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
241 | s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ | |
242 | }; | |
243 | ||
5d08cd1d CH |
244 | /* |
245 | * One for each channel, holds all channel setup data | |
246 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
247 | * with one another! | |
248 | */ | |
bf85ea4f | 249 | struct iwl_channel_info { |
bb8c093b CH |
250 | struct iwl4965_channel_tgd_info tgd; |
251 | struct iwl4965_channel_tgh_info tgh; | |
073d3f5f TW |
252 | struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */ |
253 | struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for | |
254 | * FAT channel */ | |
5d08cd1d CH |
255 | |
256 | u8 channel; /* channel number */ | |
257 | u8 flags; /* flags copied from EEPROM */ | |
258 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
fcd427bb | 259 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ |
5d08cd1d CH |
260 | s8 min_power; /* always 0 */ |
261 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
262 | ||
263 | u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */ | |
264 | u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ | |
8318d78a | 265 | enum ieee80211_band band; |
5d08cd1d | 266 | |
5d08cd1d CH |
267 | /* FAT channel info */ |
268 | s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
269 | s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */ | |
270 | s8 fat_min_power; /* always 0 */ | |
271 | s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */ | |
272 | u8 fat_flags; /* flags copied from EEPROM */ | |
fcd427bb | 273 | u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */ |
d20b3c65 SO |
274 | |
275 | /* Radio/DSP gain settings for each "normal" data Tx rate. | |
276 | * These include, in addition to RF and DSP gain, a few fields for | |
277 | * remembering/modifying gain settings (indexes). */ | |
278 | struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE]; | |
279 | ||
280 | /* Radio/DSP gain settings for each scan rate, for directed scans. */ | |
281 | struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES]; | |
5d08cd1d CH |
282 | }; |
283 | ||
5d08cd1d CH |
284 | #define IWL_TX_FIFO_AC0 0 |
285 | #define IWL_TX_FIFO_AC1 1 | |
286 | #define IWL_TX_FIFO_AC2 2 | |
287 | #define IWL_TX_FIFO_AC3 3 | |
288 | #define IWL_TX_FIFO_HCCA_1 5 | |
289 | #define IWL_TX_FIFO_HCCA_2 6 | |
290 | #define IWL_TX_FIFO_NONE 7 | |
291 | ||
01a7e084 RC |
292 | /* Minimum number of queues. MAX_NUM is defined in hw specific files. |
293 | * Set the minimum to accommodate the 4 standard TX queues, 1 command | |
294 | * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ | |
295 | #define IWL_MIN_NUM_QUEUES 10 | |
5d08cd1d CH |
296 | |
297 | /* Power management (not Tx power) structures */ | |
298 | ||
6f4083aa TW |
299 | enum iwl_pwr_src { |
300 | IWL_PWR_SRC_VMAIN, | |
301 | IWL_PWR_SRC_VAUX, | |
302 | }; | |
303 | ||
5d08cd1d CH |
304 | #define IEEE80211_DATA_LEN 2304 |
305 | #define IEEE80211_4ADDR_LEN 30 | |
306 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
307 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
308 | ||
fcab423d | 309 | struct iwl_frame { |
5d08cd1d CH |
310 | union { |
311 | struct ieee80211_hdr frame; | |
4bf64efd | 312 | struct iwl_tx_beacon_cmd beacon; |
5d08cd1d CH |
313 | u8 raw[IEEE80211_FRAME_LEN]; |
314 | u8 cmd[360]; | |
315 | } u; | |
316 | struct list_head list; | |
317 | }; | |
318 | ||
5d08cd1d CH |
319 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
320 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
321 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
322 | ||
323 | enum { | |
c587de0b TW |
324 | CMD_SYNC = 0, |
325 | CMD_SIZE_NORMAL = 0, | |
326 | CMD_NO_SKB = 0, | |
5d08cd1d | 327 | CMD_SIZE_HUGE = (1 << 0), |
5d08cd1d | 328 | CMD_ASYNC = (1 << 1), |
5d08cd1d CH |
329 | CMD_WANT_SKB = (1 << 2), |
330 | }; | |
331 | ||
857485c0 | 332 | struct iwl_cmd; |
c79dd5b5 | 333 | struct iwl_priv; |
5d08cd1d | 334 | |
857485c0 TW |
335 | struct iwl_cmd_meta { |
336 | struct iwl_cmd_meta *source; | |
5d08cd1d CH |
337 | union { |
338 | struct sk_buff *skb; | |
c79dd5b5 | 339 | int (*callback)(struct iwl_priv *priv, |
857485c0 | 340 | struct iwl_cmd *cmd, struct sk_buff *skb); |
5d08cd1d CH |
341 | } __attribute__ ((packed)) u; |
342 | ||
343 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
344 | * structure is stored at the end of the shared queue memory. */ | |
345 | u32 flags; | |
499b1883 TW |
346 | DECLARE_PCI_UNMAP_ADDR(mapping) |
347 | DECLARE_PCI_UNMAP_LEN(len) | |
5d08cd1d CH |
348 | } __attribute__ ((packed)); |
349 | ||
d2f18bfd | 350 | #define IWL_CMD_MAX_PAYLOAD 320 |
bd68fb6f | 351 | |
bc47279f | 352 | /** |
857485c0 | 353 | * struct iwl_cmd |
bc47279f BC |
354 | * |
355 | * For allocation of the command and tx queues, this establishes the overall | |
356 | * size of the largest command we send to uCode, except for a scan command | |
357 | * (which is relatively huge; space is allocated separately). | |
358 | */ | |
857485c0 TW |
359 | struct iwl_cmd { |
360 | struct iwl_cmd_meta meta; /* driver data */ | |
361 | struct iwl_cmd_header hdr; /* uCode API */ | |
5d08cd1d | 362 | union { |
5d08cd1d CH |
363 | u32 flags; |
364 | u8 val8; | |
365 | u16 val16; | |
366 | u32 val32; | |
83d527d9 | 367 | struct iwl_tx_cmd tx; |
bd68fb6f | 368 | u8 payload[IWL_CMD_MAX_PAYLOAD]; |
5d08cd1d CH |
369 | } __attribute__ ((packed)) cmd; |
370 | } __attribute__ ((packed)); | |
371 | ||
3257e5d4 | 372 | |
857485c0 | 373 | struct iwl_host_cmd { |
5d08cd1d CH |
374 | u8 id; |
375 | u16 len; | |
857485c0 | 376 | struct iwl_cmd_meta meta; |
5d08cd1d CH |
377 | const void *data; |
378 | }; | |
379 | ||
857485c0 TW |
380 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \ |
381 | sizeof(struct iwl_cmd_meta)) | |
5d08cd1d CH |
382 | |
383 | /* | |
384 | * RX related structures and functions | |
385 | */ | |
386 | #define RX_FREE_BUFFERS 64 | |
387 | #define RX_LOW_WATERMARK 8 | |
388 | ||
389 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 | |
390 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
391 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
392 | ||
393 | /** | |
a55360e4 | 394 | * struct iwl_rx_queue - Rx queue |
df833b1d RC |
395 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) |
396 | * @dma_addr: bus address of buffer of receive buffer descriptors (rbd) | |
5d08cd1d CH |
397 | * @read: Shared index to newest available Rx buffer |
398 | * @write: Shared index to oldest written Rx packet | |
399 | * @free_count: Number of pre-allocated buffers in rx_free | |
400 | * @rx_free: list of free SKBs for use | |
401 | * @rx_used: List of Rx buffers with no SKB | |
402 | * @need_update: flag to indicate we need to update read/write index | |
df833b1d RC |
403 | * @rb_stts: driver's pointer to receive buffer status |
404 | * @rb_stts_dma: bus address of receive buffer status | |
5d08cd1d | 405 | * |
a55360e4 | 406 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers |
5d08cd1d | 407 | */ |
a55360e4 | 408 | struct iwl_rx_queue { |
5d08cd1d CH |
409 | __le32 *bd; |
410 | dma_addr_t dma_addr; | |
a55360e4 TW |
411 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; |
412 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
5d08cd1d CH |
413 | u32 read; |
414 | u32 write; | |
415 | u32 free_count; | |
4752c93c | 416 | u32 write_actual; |
5d08cd1d CH |
417 | struct list_head rx_free; |
418 | struct list_head rx_used; | |
419 | int need_update; | |
8d86422a WT |
420 | struct iwl_rb_status *rb_stts; |
421 | dma_addr_t rb_stts_dma; | |
5d08cd1d CH |
422 | spinlock_t lock; |
423 | }; | |
424 | ||
425 | #define IWL_SUPPORTED_RATES_IE_LEN 8 | |
426 | ||
5d08cd1d CH |
427 | #define MAX_TID_COUNT 9 |
428 | ||
429 | #define IWL_INVALID_RATE 0xFF | |
430 | #define IWL_INVALID_VALUE -1 | |
431 | ||
bc47279f | 432 | /** |
6def9761 | 433 | * struct iwl_ht_agg -- aggregation status while waiting for block-ack |
bc47279f BC |
434 | * @txq_id: Tx queue used for Tx attempt |
435 | * @frame_count: # frames attempted by Tx command | |
436 | * @wait_for_ba: Expect block-ack before next Tx reply | |
437 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window | |
438 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window | |
439 | * @bitmap1: High order, one bit for each frame pending ACK in Tx window | |
440 | * @rate_n_flags: Rate at which Tx was attempted | |
441 | * | |
442 | * If REPLY_TX indicates that aggregation was attempted, driver must wait | |
443 | * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info | |
444 | * until block ack arrives. | |
445 | */ | |
6def9761 | 446 | struct iwl_ht_agg { |
5d08cd1d CH |
447 | u16 txq_id; |
448 | u16 frame_count; | |
449 | u16 wait_for_ba; | |
450 | u16 start_idx; | |
fe01b477 | 451 | u64 bitmap; |
5d08cd1d | 452 | u32 rate_n_flags; |
fe01b477 RR |
453 | #define IWL_AGG_OFF 0 |
454 | #define IWL_AGG_ON 1 | |
455 | #define IWL_EMPTYING_HW_QUEUE_ADDBA 2 | |
456 | #define IWL_EMPTYING_HW_QUEUE_DELBA 3 | |
457 | u8 state; | |
5d08cd1d | 458 | }; |
fe01b477 | 459 | |
5d08cd1d | 460 | |
6def9761 | 461 | struct iwl_tid_data { |
5d08cd1d | 462 | u16 seq_number; |
fe01b477 | 463 | u16 tfds_in_queue; |
6def9761 | 464 | struct iwl_ht_agg agg; |
5d08cd1d CH |
465 | }; |
466 | ||
6def9761 | 467 | struct iwl_hw_key { |
5d08cd1d CH |
468 | enum ieee80211_key_alg alg; |
469 | int keylen; | |
0211ddda | 470 | u8 keyidx; |
5d08cd1d CH |
471 | u8 key[32]; |
472 | }; | |
473 | ||
a78fe754 | 474 | union iwl_ht_rate_supp { |
5d08cd1d CH |
475 | u16 rates; |
476 | struct { | |
477 | u8 siso_rate; | |
478 | u8 mimo_rate; | |
479 | }; | |
480 | }; | |
481 | ||
5d08cd1d | 482 | #define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3) |
5d08cd1d CH |
483 | #define CFG_HT_MPDU_DENSITY_2USEC (0x5) |
484 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC | |
485 | ||
9e0cc6de RR |
486 | struct iwl_ht_info { |
487 | /* self configuration data */ | |
5d08cd1d | 488 | u8 is_ht; |
9e0cc6de | 489 | u8 supported_chan_width; |
12837be1 | 490 | u8 sm_ps; |
9e0cc6de | 491 | u8 is_green_field; |
bb54244b | 492 | u8 sgf; /* HT_SHORT_GI_* short guard interval */ |
5d08cd1d CH |
493 | u8 max_amsdu_size; |
494 | u8 ampdu_factor; | |
495 | u8 mpdu_density; | |
d9fe60de | 496 | struct ieee80211_mcs_info mcs; |
9e0cc6de | 497 | /* BSS related data */ |
5d08cd1d | 498 | u8 extension_chan_offset; |
5d08cd1d | 499 | u8 tx_chan_width; |
9e0cc6de RR |
500 | u8 ht_protection; |
501 | u8 non_GF_STA_present; | |
5d08cd1d | 502 | }; |
5d08cd1d | 503 | |
1ff50bda | 504 | union iwl_qos_capabity { |
5d08cd1d CH |
505 | struct { |
506 | u8 edca_count:4; /* bit 0-3 */ | |
507 | u8 q_ack:1; /* bit 4 */ | |
508 | u8 queue_request:1; /* bit 5 */ | |
509 | u8 txop_request:1; /* bit 6 */ | |
510 | u8 reserved:1; /* bit 7 */ | |
511 | } q_AP; | |
512 | struct { | |
513 | u8 acvo_APSD:1; /* bit 0 */ | |
514 | u8 acvi_APSD:1; /* bit 1 */ | |
515 | u8 ac_bk_APSD:1; /* bit 2 */ | |
516 | u8 ac_be_APSD:1; /* bit 3 */ | |
517 | u8 q_ack:1; /* bit 4 */ | |
518 | u8 max_len:2; /* bit 5-6 */ | |
519 | u8 more_data_ack:1; /* bit 7 */ | |
520 | } q_STA; | |
521 | u8 val; | |
522 | }; | |
523 | ||
524 | /* QoS structures */ | |
1ff50bda | 525 | struct iwl_qos_info { |
5d08cd1d | 526 | int qos_active; |
1ff50bda EG |
527 | union iwl_qos_capabity qos_cap; |
528 | struct iwl_qosparam_cmd def_qos_parm; | |
5d08cd1d | 529 | }; |
5d08cd1d CH |
530 | |
531 | #define STA_PS_STATUS_WAKE 0 | |
532 | #define STA_PS_STATUS_SLEEP 1 | |
533 | ||
85d41495 KA |
534 | |
535 | struct iwl3945_station_entry { | |
536 | struct iwl3945_addsta_cmd sta; | |
c15ff610 | 537 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
85d41495 KA |
538 | u8 used; |
539 | u8 ps_status; | |
bed420d9 | 540 | struct iwl_hw_key keyinfo; |
85d41495 KA |
541 | }; |
542 | ||
6def9761 | 543 | struct iwl_station_entry { |
133636de | 544 | struct iwl_addsta_cmd sta; |
6def9761 | 545 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
5d08cd1d CH |
546 | u8 used; |
547 | u8 ps_status; | |
6def9761 | 548 | struct iwl_hw_key keyinfo; |
5d08cd1d CH |
549 | }; |
550 | ||
551 | /* one for each uCode image (inst/data, boot/init/runtime) */ | |
552 | struct fw_desc { | |
553 | void *v_addr; /* access by driver */ | |
554 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
555 | u32 len; /* bytes */ | |
556 | }; | |
557 | ||
558 | /* uCode file layout */ | |
cc0f555d JS |
559 | struct iwl_ucode_header { |
560 | __le32 ver; /* major/minor/API/serial */ | |
561 | union { | |
562 | struct { | |
563 | __le32 inst_size; /* bytes of runtime code */ | |
564 | __le32 data_size; /* bytes of runtime data */ | |
565 | __le32 init_size; /* bytes of init code */ | |
566 | __le32 init_data_size; /* bytes of init data */ | |
567 | __le32 boot_size; /* bytes of bootstrap code */ | |
568 | u8 data[0]; /* in same order as sizes */ | |
569 | } v1; | |
570 | struct { | |
571 | __le32 build; /* build number */ | |
572 | __le32 inst_size; /* bytes of runtime code */ | |
573 | __le32 data_size; /* bytes of runtime data */ | |
574 | __le32 init_size; /* bytes of init code */ | |
575 | __le32 init_data_size; /* bytes of init data */ | |
576 | __le32 boot_size; /* bytes of bootstrap code */ | |
577 | u8 data[0]; /* in same order as sizes */ | |
578 | } v2; | |
579 | } u; | |
5d08cd1d | 580 | }; |
cc0f555d | 581 | #define UCODE_HEADER_SIZE(ver) ((ver) == 1 ? 24 : 28) |
5d08cd1d | 582 | |
bb8c093b | 583 | struct iwl4965_ibss_seq { |
5d08cd1d CH |
584 | u8 mac[ETH_ALEN]; |
585 | u16 seq_num; | |
586 | u16 frag_num; | |
587 | unsigned long packet_time; | |
588 | struct list_head list; | |
589 | }; | |
590 | ||
f0832f13 EG |
591 | struct iwl_sensitivity_ranges { |
592 | u16 min_nrg_cck; | |
593 | u16 max_nrg_cck; | |
594 | ||
595 | u16 nrg_th_cck; | |
596 | u16 nrg_th_ofdm; | |
597 | ||
598 | u16 auto_corr_min_ofdm; | |
599 | u16 auto_corr_min_ofdm_mrc; | |
600 | u16 auto_corr_min_ofdm_x1; | |
601 | u16 auto_corr_min_ofdm_mrc_x1; | |
602 | ||
603 | u16 auto_corr_max_ofdm; | |
604 | u16 auto_corr_max_ofdm_mrc; | |
605 | u16 auto_corr_max_ofdm_x1; | |
606 | u16 auto_corr_max_ofdm_mrc_x1; | |
607 | ||
608 | u16 auto_corr_max_cck; | |
609 | u16 auto_corr_max_cck_mrc; | |
610 | u16 auto_corr_min_cck; | |
611 | u16 auto_corr_min_cck_mrc; | |
612 | }; | |
613 | ||
099b40b7 | 614 | |
b5047f78 TW |
615 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
616 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
617 | ||
618 | ||
bc47279f | 619 | /** |
5425e490 | 620 | * struct iwl_hw_params |
bc47279f | 621 | * @max_txq_num: Max # Tx queues supported |
f3f911d1 | 622 | * @dma_chnl_num: Number of Tx DMA/FIFO channels |
4ddbb7d0 | 623 | * @scd_bc_tbls_size: size of scheduler byte count tables |
a8e74e27 | 624 | * @tfd_size: TFD size |
099b40b7 RR |
625 | * @tx/rx_chains_num: Number of TX/RX chains |
626 | * @valid_tx/rx_ant: usable antennas | |
bc47279f | 627 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) |
bc47279f | 628 | * @max_rxq_log: Log-base-2 of max_rxq_size |
099b40b7 | 629 | * @rx_buf_size: Rx buffer size |
141c43a3 | 630 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR |
bc47279f BC |
631 | * @max_stations: |
632 | * @bcast_sta_id: | |
099b40b7 RR |
633 | * @fat_channel: is 40MHz width possible in band 2.4 |
634 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) | |
635 | * @sw_crypto: 0 for hw, 1 for sw | |
636 | * @max_xxx_size: for ucode uses | |
637 | * @ct_kill_threshold: temperature threshold | |
a96a27f9 | 638 | * @calib_init_cfg: setup initial calibrations for the hw |
f0832f13 | 639 | * @struct iwl_sensitivity_ranges: range of sensitivity values |
bc47279f | 640 | */ |
5425e490 | 641 | struct iwl_hw_params { |
f3f911d1 ZY |
642 | u8 max_txq_num; |
643 | u8 dma_chnl_num; | |
4ddbb7d0 | 644 | u16 scd_bc_tbls_size; |
a8e74e27 | 645 | u32 tfd_size; |
ec35cf2a TW |
646 | u8 tx_chains_num; |
647 | u8 rx_chains_num; | |
648 | u8 valid_tx_ant; | |
649 | u8 valid_rx_ant; | |
5d08cd1d | 650 | u16 max_rxq_size; |
ec35cf2a | 651 | u16 max_rxq_log; |
9ee1ba47 | 652 | u32 rx_buf_size; |
141c43a3 | 653 | u32 rx_wrt_ptr_reg; |
9ee1ba47 | 654 | u32 max_pkt_size; |
5d08cd1d CH |
655 | u8 max_stations; |
656 | u8 bcast_sta_id; | |
099b40b7 | 657 | u8 fat_channel; |
2c2f3b33 | 658 | u8 max_beacon_itrvl; /* in 1024 ms */ |
099b40b7 RR |
659 | u32 max_inst_size; |
660 | u32 max_data_size; | |
661 | u32 max_bsm_size; | |
662 | u32 ct_kill_threshold; /* value in hw-dependent units */ | |
672639de WYG |
663 | u32 ct_kill_exit_threshold; /* value in hw-dependent units */ |
664 | /* for 1000, 6000 series and up */ | |
be5d56ed | 665 | u32 calib_init_cfg; |
f0832f13 | 666 | const struct iwl_sensitivity_ranges *sens; |
5d08cd1d CH |
667 | }; |
668 | ||
5d08cd1d | 669 | |
5d08cd1d CH |
670 | /****************************************************************************** |
671 | * | |
a33c2f47 EG |
672 | * Functions implemented in core module which are forward declared here |
673 | * for use by iwl-[4-5].c | |
5d08cd1d | 674 | * |
a33c2f47 EG |
675 | * NOTE: The implementation of these functions are not hardware specific |
676 | * which is why they are in the core module files. | |
5d08cd1d CH |
677 | * |
678 | * Naming convention -- | |
a33c2f47 | 679 | * iwl_ <-- Is part of iwlwifi |
5d08cd1d | 680 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) |
bb8c093b CH |
681 | * iwl4965_bg_ <-- Called from work queue context |
682 | * iwl4965_mac_ <-- mac80211 callback | |
5d08cd1d CH |
683 | * |
684 | ****************************************************************************/ | |
5b9f8cd3 EG |
685 | extern void iwl_update_chain_flags(struct iwl_priv *priv); |
686 | extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src); | |
a33c2f47 | 687 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
b3bbacb7 | 688 | extern int iwl_rxq_stop(struct iwl_priv *priv); |
da1bc453 | 689 | extern void iwl_txq_ctx_stop(struct iwl_priv *priv); |
443cfd45 | 690 | extern int iwl_queue_space(const struct iwl_queue *q); |
fd4abac5 TW |
691 | static inline int iwl_queue_used(const struct iwl_queue *q, int i) |
692 | { | |
693 | return q->write_ptr > q->read_ptr ? | |
694 | (i >= q->read_ptr && i < q->write_ptr) : | |
695 | !(i < q->read_ptr && i >= q->write_ptr); | |
696 | } | |
697 | ||
698 | ||
699 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge) | |
700 | { | |
701 | /* This is for scan command, the big buffer at end of command array */ | |
702 | if (is_huge) | |
703 | return q->n_window; /* must be power of 2 */ | |
704 | ||
705 | /* Otherwise, use normal size buffers */ | |
706 | return index & (q->n_window - 1); | |
707 | } | |
708 | ||
709 | ||
4ddbb7d0 TW |
710 | struct iwl_dma_ptr { |
711 | dma_addr_t dma; | |
712 | void *addr; | |
b481de9c ZY |
713 | size_t size; |
714 | }; | |
715 | ||
34c22cf9 WT |
716 | #define HT_SHORT_GI_20MHZ (1 << 0) |
717 | #define HT_SHORT_GI_40MHZ (1 << 1) | |
718 | ||
b481de9c ZY |
719 | #define IWL_CHANNEL_WIDTH_20MHZ 0 |
720 | #define IWL_CHANNEL_WIDTH_40MHZ 1 | |
721 | ||
b481de9c ZY |
722 | #define IWL_OPERATION_MODE_AUTO 0 |
723 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
724 | #define IWL_OPERATION_MODE_MIXED 2 | |
725 | #define IWL_OPERATION_MODE_20MHZ 3 | |
726 | ||
3195cdb7 TW |
727 | #define IWL_TX_CRC_SIZE 4 |
728 | #define IWL_TX_DELIMITER_SIZE 4 | |
b481de9c | 729 | |
b481de9c | 730 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
b481de9c | 731 | |
b481de9c | 732 | /* Sensitivity and chain noise calibration */ |
b481de9c ZY |
733 | #define INITIALIZATION_VALUE 0xFFFF |
734 | #define CAL_NUM_OF_BEACONS 20 | |
735 | #define MAXIMUM_ALLOWED_PATHLOSS 15 | |
736 | ||
b481de9c ZY |
737 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 |
738 | ||
739 | #define MAX_FA_OFDM 50 | |
740 | #define MIN_FA_OFDM 5 | |
741 | #define MAX_FA_CCK 50 | |
742 | #define MIN_FA_CCK 5 | |
743 | ||
b481de9c ZY |
744 | #define AUTO_CORR_STEP_OFDM 1 |
745 | ||
b481de9c ZY |
746 | #define AUTO_CORR_STEP_CCK 3 |
747 | #define AUTO_CORR_MAX_TH_CCK 160 | |
748 | ||
b481de9c ZY |
749 | #define NRG_DIFF 2 |
750 | #define NRG_STEP_CCK 2 | |
751 | #define NRG_MARGIN 8 | |
752 | #define MAX_NUMBER_CCK_NO_FA 100 | |
753 | ||
754 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
755 | ||
756 | #define CHAIN_A 0 | |
757 | #define CHAIN_B 1 | |
758 | #define CHAIN_C 2 | |
759 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
760 | #define ALL_BAND_FILTER 0xFF00 | |
761 | #define IN_BAND_FILTER 0xFF | |
762 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
763 | ||
3195cdb7 TW |
764 | #define NRG_NUM_PREV_STAT_L 20 |
765 | #define NUM_RX_CHAINS 3 | |
766 | ||
bb8c093b | 767 | enum iwl4965_false_alarm_state { |
b481de9c ZY |
768 | IWL_FA_TOO_MANY = 0, |
769 | IWL_FA_TOO_FEW = 1, | |
770 | IWL_FA_GOOD_RANGE = 2, | |
771 | }; | |
772 | ||
bb8c093b | 773 | enum iwl4965_chain_noise_state { |
b481de9c | 774 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
04816448 GE |
775 | IWL_CHAIN_NOISE_ACCUMULATE, |
776 | IWL_CHAIN_NOISE_CALIBRATED, | |
777 | IWL_CHAIN_NOISE_DONE, | |
b481de9c ZY |
778 | }; |
779 | ||
bb8c093b | 780 | enum iwl4965_calib_enabled_state { |
b481de9c ZY |
781 | IWL_CALIB_DISABLED = 0, /* must be 0 */ |
782 | IWL_CALIB_ENABLED = 1, | |
783 | }; | |
784 | ||
f69f42a6 TW |
785 | |
786 | /* | |
787 | * enum iwl_calib | |
788 | * defines the order in which results of initial calibrations | |
789 | * should be sent to the runtime uCode | |
790 | */ | |
791 | enum iwl_calib { | |
792 | IWL_CALIB_XTAL, | |
819500c5 | 793 | IWL_CALIB_DC, |
f69f42a6 TW |
794 | IWL_CALIB_LO, |
795 | IWL_CALIB_TX_IQ, | |
796 | IWL_CALIB_TX_IQ_PERD, | |
201706ac | 797 | IWL_CALIB_BASE_BAND, |
f69f42a6 TW |
798 | IWL_CALIB_MAX |
799 | }; | |
800 | ||
6e21f2c1 TW |
801 | /* Opaque calibration results */ |
802 | struct iwl_calib_result { | |
803 | void *buf; | |
804 | size_t buf_len; | |
7c616cba TW |
805 | }; |
806 | ||
34a66de6 WYG |
807 | #define UCODE_ALIVE_TIMEOUT (5 * HZ) |
808 | ||
dbb983b7 RR |
809 | enum ucode_type { |
810 | UCODE_NONE = 0, | |
811 | UCODE_INIT, | |
812 | UCODE_RT | |
813 | }; | |
814 | ||
b481de9c | 815 | /* Sensitivity calib data */ |
f0832f13 | 816 | struct iwl_sensitivity_data { |
b481de9c ZY |
817 | u32 auto_corr_ofdm; |
818 | u32 auto_corr_ofdm_mrc; | |
819 | u32 auto_corr_ofdm_x1; | |
820 | u32 auto_corr_ofdm_mrc_x1; | |
821 | u32 auto_corr_cck; | |
822 | u32 auto_corr_cck_mrc; | |
823 | ||
824 | u32 last_bad_plcp_cnt_ofdm; | |
825 | u32 last_fa_cnt_ofdm; | |
826 | u32 last_bad_plcp_cnt_cck; | |
827 | u32 last_fa_cnt_cck; | |
828 | ||
829 | u32 nrg_curr_state; | |
830 | u32 nrg_prev_state; | |
831 | u32 nrg_value[10]; | |
832 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
833 | u32 nrg_silence_ref; | |
834 | u32 nrg_energy_idx; | |
835 | u32 nrg_silence_idx; | |
836 | u32 nrg_th_cck; | |
837 | s32 nrg_auto_corr_silence_diff; | |
838 | u32 num_in_cck_no_fa; | |
839 | u32 nrg_th_ofdm; | |
b481de9c ZY |
840 | }; |
841 | ||
842 | /* Chain noise (differential Rx gain) calib data */ | |
f0832f13 | 843 | struct iwl_chain_noise_data { |
04816448 | 844 | u32 active_chains; |
b481de9c ZY |
845 | u32 chain_noise_a; |
846 | u32 chain_noise_b; | |
847 | u32 chain_noise_c; | |
848 | u32 chain_signal_a; | |
849 | u32 chain_signal_b; | |
850 | u32 chain_signal_c; | |
04816448 | 851 | u16 beacon_count; |
b481de9c ZY |
852 | u8 disconn_array[NUM_RX_CHAINS]; |
853 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
854 | u8 radio_write; | |
04816448 | 855 | u8 state; |
b481de9c ZY |
856 | }; |
857 | ||
abceddb4 BC |
858 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
859 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
b481de9c | 860 | |
5d08cd1d | 861 | |
5d08cd1d CH |
862 | enum { |
863 | MEASUREMENT_READY = (1 << 0), | |
864 | MEASUREMENT_ACTIVE = (1 << 1), | |
865 | }; | |
866 | ||
0848e297 WYG |
867 | enum iwl_nvm_type { |
868 | NVM_DEVICE_TYPE_EEPROM = 0, | |
869 | NVM_DEVICE_TYPE_OTP, | |
870 | }; | |
871 | ||
a83b9141 WYG |
872 | /* interrupt statistics */ |
873 | struct isr_statistics { | |
874 | u32 hw; | |
875 | u32 sw; | |
876 | u32 sw_err; | |
877 | u32 sch; | |
878 | u32 alive; | |
879 | u32 rfkill; | |
880 | u32 ctkill; | |
881 | u32 wakeup; | |
882 | u32 rx; | |
883 | u32 rx_handlers[REPLY_MAX]; | |
884 | u32 tx; | |
885 | u32 unhandled; | |
886 | }; | |
5d08cd1d | 887 | |
dfe7d458 RR |
888 | #define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */ |
889 | ||
c79dd5b5 | 890 | struct iwl_priv { |
5d08cd1d CH |
891 | |
892 | /* ieee device used by generic ieee processing code */ | |
893 | struct ieee80211_hw *hw; | |
894 | struct ieee80211_channel *ieee_channels; | |
895 | struct ieee80211_rate *ieee_rates; | |
82b9a121 | 896 | struct iwl_cfg *cfg; |
5d08cd1d CH |
897 | |
898 | /* temporary frame storage list */ | |
899 | struct list_head free_frames; | |
900 | int frames_count; | |
901 | ||
8318d78a | 902 | enum ieee80211_band band; |
5d08cd1d CH |
903 | int alloc_rxb_skb; |
904 | ||
c79dd5b5 | 905 | void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, |
a55360e4 | 906 | struct iwl_rx_mem_buffer *rxb); |
5d08cd1d | 907 | |
8318d78a | 908 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
5d08cd1d | 909 | |
80bc5393 | 910 | #if defined(CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT) || defined(CONFIG_IWL3945_SPECTRUM_MEASUREMENT) |
5d08cd1d | 911 | /* spectrum measurement report caching */ |
2aa6ab86 | 912 | struct iwl_spectrum_notification measure_report; |
5d08cd1d CH |
913 | u8 measurement_status; |
914 | #endif | |
915 | /* ucode beacon time */ | |
916 | u32 ucode_beacon_time; | |
917 | ||
bb8c093b | 918 | /* we allocate array of iwl4965_channel_info for NIC's valid channels. |
5d08cd1d | 919 | * Access via channel # using indirect index array */ |
bf85ea4f | 920 | struct iwl_channel_info *channel_info; /* channel info array */ |
5d08cd1d CH |
921 | u8 channel_count; /* # of channels */ |
922 | ||
85d41495 KA |
923 | /* each calibration channel group in the EEPROM has a derived |
924 | * clip setting for each rate. 3945 only.*/ | |
925 | const struct iwl3945_clip_group clip39_groups[5]; | |
926 | ||
5d08cd1d CH |
927 | /* thermal calibration */ |
928 | s32 temperature; /* degrees Kelvin */ | |
929 | s32 last_temperature; | |
930 | ||
7c616cba | 931 | /* init calibration results */ |
6e21f2c1 | 932 | struct iwl_calib_result calib_results[IWL_CALIB_MAX]; |
7c616cba | 933 | |
5d08cd1d CH |
934 | /* Scan related variables */ |
935 | unsigned long last_scan_jiffies; | |
7878a5a4 | 936 | unsigned long next_scan_jiffies; |
5d08cd1d CH |
937 | unsigned long scan_start; |
938 | unsigned long scan_pass_start; | |
939 | unsigned long scan_start_tsf; | |
805cee5b | 940 | void *scan; |
5d08cd1d | 941 | int scan_bands; |
1ecf9fc1 | 942 | struct cfg80211_scan_request *scan_request; |
76eff18b TW |
943 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; |
944 | u8 mgmt_tx_ant; | |
5d08cd1d CH |
945 | |
946 | /* spinlock */ | |
947 | spinlock_t lock; /* protect general shared data */ | |
948 | spinlock_t hcmd_lock; /* protect hcmd */ | |
a8b50a0a | 949 | spinlock_t reg_lock; /* protect hw register access */ |
5d08cd1d CH |
950 | struct mutex mutex; |
951 | ||
952 | /* basic pci-network driver stuff */ | |
953 | struct pci_dev *pci_dev; | |
954 | ||
955 | /* pci hardware address support */ | |
956 | void __iomem *hw_base; | |
b661c819 TW |
957 | u32 hw_rev; |
958 | u32 hw_wa_rev; | |
959 | u8 rev_id; | |
5d08cd1d CH |
960 | |
961 | /* uCode images, save to reload in case of failure */ | |
c02b3acd CR |
962 | u32 ucode_ver; /* version of ucode, copy of |
963 | iwl_ucode.ver */ | |
5d08cd1d CH |
964 | struct fw_desc ucode_code; /* runtime inst */ |
965 | struct fw_desc ucode_data; /* runtime data original */ | |
966 | struct fw_desc ucode_data_backup; /* runtime data save/restore */ | |
967 | struct fw_desc ucode_init; /* initialization inst */ | |
968 | struct fw_desc ucode_init_data; /* initialization data */ | |
969 | struct fw_desc ucode_boot; /* bootstrap inst */ | |
dbb983b7 RR |
970 | enum ucode_type ucode_type; |
971 | u8 ucode_write_complete; /* the image write is complete */ | |
5d08cd1d CH |
972 | |
973 | ||
3195c1f3 | 974 | struct iwl_rxon_time_cmd rxon_timing; |
5d08cd1d CH |
975 | |
976 | /* We declare this const so it can only be | |
977 | * changed via explicit cast within the | |
978 | * routines that actually update the physical | |
979 | * hardware */ | |
c1adf9fb GG |
980 | const struct iwl_rxon_cmd active_rxon; |
981 | struct iwl_rxon_cmd staging_rxon; | |
5d08cd1d | 982 | |
c1adf9fb | 983 | struct iwl_rxon_cmd recovery_rxon; |
5d08cd1d CH |
984 | |
985 | /* 1st responses from initialize and runtime uCode images. | |
986 | * 4965's initialize alive response contains some calibration data. */ | |
885ba202 TW |
987 | struct iwl_init_alive_resp card_alive_init; |
988 | struct iwl_alive_resp card_alive; | |
5d08cd1d | 989 | |
5c8df2d5 | 990 | #ifdef CONFIG_IWLWIFI_LEDS |
ab53d8af MA |
991 | unsigned long last_blink_time; |
992 | u8 last_blink_rate; | |
993 | u8 allow_blinking; | |
994 | u64 led_tpt; | |
4a8a4322 | 995 | struct iwl_led led[IWL_LED_TRG_MAX]; |
4a8a4322 AK |
996 | unsigned int rxtxpackets; |
997 | #endif | |
5d08cd1d CH |
998 | u16 active_rate; |
999 | u16 active_rate_basic; | |
1000 | ||
5d08cd1d | 1001 | u8 assoc_station_added; |
5d08cd1d | 1002 | u8 start_calib; |
f0832f13 EG |
1003 | struct iwl_sensitivity_data sensitivity_data; |
1004 | struct iwl_chain_noise_data chain_noise_data; | |
5d08cd1d | 1005 | __le16 sensitivity_tbl[HD_TABLE_SIZE]; |
5d08cd1d | 1006 | |
9e0cc6de | 1007 | struct iwl_ht_info current_ht_config; |
5d08cd1d CH |
1008 | u8 last_phy_res[100]; |
1009 | ||
5d08cd1d CH |
1010 | /* Rate scaling data */ |
1011 | s8 data_retry_limit; | |
1012 | u8 retry_rate; | |
1013 | ||
1014 | wait_queue_head_t wait_command_queue; | |
1015 | ||
1016 | int activity_timer_active; | |
1017 | ||
1018 | /* Rx and Tx DMA processing queues */ | |
a55360e4 | 1019 | struct iwl_rx_queue rxq; |
16466903 | 1020 | struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES]; |
5d08cd1d | 1021 | unsigned long txq_ctx_active_msk; |
4ddbb7d0 TW |
1022 | struct iwl_dma_ptr kw; /* keep warm address */ |
1023 | struct iwl_dma_ptr scd_bc_tbls; | |
1024 | ||
5d08cd1d CH |
1025 | u32 scd_base_addr; /* scheduler sram base address */ |
1026 | ||
1027 | unsigned long status; | |
5d08cd1d | 1028 | |
a96a27f9 | 1029 | int last_rx_rssi; /* From Rx packet statistics */ |
5d08cd1d CH |
1030 | int last_rx_noise; /* From beacon statistics */ |
1031 | ||
19758bef TW |
1032 | /* counts mgmt, ctl, and data packets */ |
1033 | struct traffic_stats { | |
1034 | u32 cnt; | |
1035 | u64 bytes; | |
1036 | } tx_stats[3], rx_stats[3]; | |
1037 | ||
a83b9141 WYG |
1038 | /* counts interrupts */ |
1039 | struct isr_statistics isr_stats; | |
1040 | ||
5da4b55f | 1041 | struct iwl_power_mgr power_data; |
5d08cd1d | 1042 | |
8f91aecb | 1043 | struct iwl_notif_statistics statistics; |
5d08cd1d CH |
1044 | unsigned long last_statistics_time; |
1045 | ||
1046 | /* context information */ | |
5d08cd1d CH |
1047 | u16 rates_mask; |
1048 | ||
1049 | u32 power_mode; | |
5d08cd1d CH |
1050 | u8 bssid[ETH_ALEN]; |
1051 | u16 rts_threshold; | |
1052 | u8 mac_addr[ETH_ALEN]; | |
1053 | ||
1054 | /*station table variables */ | |
1055 | spinlock_t sta_lock; | |
1056 | int num_stations; | |
6def9761 | 1057 | struct iwl_station_entry stations[IWL_STATION_COUNT]; |
6974e363 EG |
1058 | struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; |
1059 | u8 default_wep_key; | |
1060 | u8 key_mapping_key; | |
80fb47a1 | 1061 | unsigned long ucode_key_table; |
5d08cd1d | 1062 | |
e4e72fb4 JB |
1063 | /* queue refcounts */ |
1064 | #define IWL_MAX_HW_QUEUES 32 | |
1065 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; | |
1066 | /* for each AC */ | |
1067 | atomic_t queue_stop_count[4]; | |
1068 | ||
5d08cd1d | 1069 | /* Indication if ieee80211_ops->open has been called */ |
69dc5d9d | 1070 | u8 is_open; |
5d08cd1d CH |
1071 | |
1072 | u8 mac80211_registered; | |
5d08cd1d | 1073 | |
5d08cd1d CH |
1074 | /* Rx'd packet timing information */ |
1075 | u32 last_beacon_time; | |
1076 | u64 last_tsf; | |
1077 | ||
5d08cd1d | 1078 | /* eeprom */ |
073d3f5f | 1079 | u8 *eeprom; |
0848e297 | 1080 | int nvm_device_type; |
073d3f5f | 1081 | struct iwl_eeprom_calib_info *calib_info; |
5d08cd1d | 1082 | |
05c914fe | 1083 | enum nl80211_iftype iw_mode; |
5d08cd1d CH |
1084 | |
1085 | struct sk_buff *ibss_beacon; | |
1086 | ||
1087 | /* Last Rx'd beacon timestamp */ | |
3109ece1 | 1088 | u64 timestamp; |
5d08cd1d | 1089 | u16 beacon_int; |
32bfd35d | 1090 | struct ieee80211_vif *vif; |
5d08cd1d | 1091 | |
8cd812bc | 1092 | /*Added for 3945 */ |
3832ec9d AK |
1093 | void *shared_virt; |
1094 | dma_addr_t shared_phys; | |
1095 | /*End*/ | |
5425e490 | 1096 | struct iwl_hw_params hw_params; |
4ddbb7d0 | 1097 | |
ef850d7c MA |
1098 | /* INT ICT Table */ |
1099 | u32 *ict_tbl; | |
1100 | dma_addr_t ict_tbl_dma; | |
1101 | dma_addr_t aligned_ict_tbl_dma; | |
1102 | int ict_index; | |
1103 | void *ict_tbl_vir; | |
1104 | u32 inta; | |
1105 | bool use_ict; | |
059ff826 | 1106 | |
40cefda9 | 1107 | u32 inta_mask; |
5d08cd1d CH |
1108 | /* Current association information needed to configure the |
1109 | * hardware */ | |
1110 | u16 assoc_id; | |
1111 | u16 assoc_capability; | |
5d08cd1d | 1112 | |
1ff50bda | 1113 | struct iwl_qos_info qos_data; |
5d08cd1d CH |
1114 | |
1115 | struct workqueue_struct *workqueue; | |
1116 | ||
1117 | struct work_struct up; | |
1118 | struct work_struct restart; | |
1119 | struct work_struct calibrated_work; | |
1120 | struct work_struct scan_completed; | |
1121 | struct work_struct rx_replenish; | |
5d08cd1d CH |
1122 | struct work_struct abort_scan; |
1123 | struct work_struct update_link_led; | |
1124 | struct work_struct auth_work; | |
1125 | struct work_struct report_work; | |
1126 | struct work_struct request_scan; | |
1127 | struct work_struct beacon_update; | |
1128 | ||
1129 | struct tasklet_struct irq_tasklet; | |
1130 | ||
1131 | struct delayed_work init_alive_start; | |
1132 | struct delayed_work alive_start; | |
5d08cd1d | 1133 | struct delayed_work scan_check; |
4a8a4322 AK |
1134 | |
1135 | /*For 3945 only*/ | |
1136 | struct delayed_work thermal_periodic; | |
2663516d | 1137 | struct delayed_work rfkill_poll; |
4a8a4322 | 1138 | |
630fe9b6 TW |
1139 | /* TX Power */ |
1140 | s8 tx_power_user_lmt; | |
1141 | s8 tx_power_channel_lmt; | |
5d08cd1d | 1142 | |
5d08cd1d | 1143 | |
d08853a3 | 1144 | #ifdef CONFIG_IWLWIFI_DEBUG |
5d08cd1d CH |
1145 | /* debugging info */ |
1146 | u32 framecnt_to_us; | |
1147 | atomic_t restrict_refcnt; | |
712b6cf5 TW |
1148 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1149 | /* debugfs */ | |
1150 | struct iwl_debugfs *dbgfs; | |
1151 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ | |
1152 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
5d08cd1d CH |
1153 | |
1154 | struct work_struct txpower_work; | |
445c2dff TW |
1155 | u32 disable_sens_cal; |
1156 | u32 disable_chain_noise_cal; | |
203566f3 | 1157 | u32 disable_tx_power_cal; |
16e727e8 | 1158 | struct work_struct run_time_calib_work; |
5d08cd1d | 1159 | struct timer_list statistics_periodic; |
086ed117 | 1160 | bool hw_ready; |
4a8a4322 AK |
1161 | /*For 3945*/ |
1162 | #define IWL_DEFAULT_TX_POWER 0x0F | |
4a8a4322 | 1163 | |
4a8a4322 AK |
1164 | struct iwl3945_notif_statistics statistics_39; |
1165 | ||
4a8a4322 | 1166 | u32 sta_supp_rates; |
c79dd5b5 | 1167 | }; /*iwl_priv */ |
5d08cd1d | 1168 | |
36470749 RR |
1169 | static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) |
1170 | { | |
1171 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1172 | } | |
1173 | ||
1174 | static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id) | |
1175 | { | |
1176 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1177 | } | |
1178 | ||
994d31f7 | 1179 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1180 | const char *iwl_get_tx_fail_reason(u32 status); |
1181 | #else | |
1182 | static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; } | |
1183 | #endif | |
1184 | ||
1185 | ||
a332f8d6 TW |
1186 | static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv, |
1187 | int txq_id, int idx) | |
1188 | { | |
1189 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
1190 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
1191 | txb[idx].skb[0]->data; | |
1192 | return NULL; | |
1193 | } | |
a332f8d6 TW |
1194 | |
1195 | ||
3109ece1 | 1196 | static inline int iwl_is_associated(struct iwl_priv *priv) |
5d08cd1d CH |
1197 | { |
1198 | return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; | |
1199 | } | |
1200 | ||
bf85ea4f | 1201 | static inline int is_channel_valid(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1202 | { |
1203 | if (ch_info == NULL) | |
1204 | return 0; | |
1205 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1206 | } | |
1207 | ||
bf85ea4f | 1208 | static inline int is_channel_radar(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1209 | { |
1210 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1211 | } | |
1212 | ||
bf85ea4f | 1213 | static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1214 | { |
8318d78a | 1215 | return ch_info->band == IEEE80211_BAND_5GHZ; |
5d08cd1d CH |
1216 | } |
1217 | ||
bf85ea4f | 1218 | static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1219 | { |
8318d78a | 1220 | return ch_info->band == IEEE80211_BAND_2GHZ; |
5d08cd1d CH |
1221 | } |
1222 | ||
bf85ea4f | 1223 | static inline int is_channel_passive(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1224 | { |
1225 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1226 | } | |
1227 | ||
bf85ea4f | 1228 | static inline int is_channel_ibss(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1229 | { |
1230 | return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; | |
1231 | } | |
1232 | ||
be1f3ab6 | 1233 | #endif /* __iwl_dev_h__ */ |