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26a7ca9a JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. |
26a7ca9a JB |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
26a7ca9a JB |
26 | * |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
51368bf7 | 33 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
26a7ca9a JB |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | *****************************************************************************/ | |
62 | #include <linux/types.h> | |
63 | #include <linux/slab.h> | |
64 | #include <linux/export.h> | |
48e29340 | 65 | #include "iwl-drv.h" |
26a7ca9a JB |
66 | #include "iwl-modparams.h" |
67 | #include "iwl-eeprom-parse.h" | |
68 | ||
69 | /* EEPROM offset definitions */ | |
70 | ||
71 | /* indirect access definitions */ | |
72 | #define ADDRESS_MSK 0x0000FFFF | |
73 | #define INDIRECT_TYPE_MSK 0x000F0000 | |
74 | #define INDIRECT_HOST 0x00010000 | |
75 | #define INDIRECT_GENERAL 0x00020000 | |
76 | #define INDIRECT_REGULATORY 0x00030000 | |
77 | #define INDIRECT_CALIBRATION 0x00040000 | |
78 | #define INDIRECT_PROCESS_ADJST 0x00050000 | |
79 | #define INDIRECT_OTHERS 0x00060000 | |
80 | #define INDIRECT_TXP_LIMIT 0x00070000 | |
81 | #define INDIRECT_TXP_LIMIT_SIZE 0x00080000 | |
82 | #define INDIRECT_ADDRESS 0x00100000 | |
83 | ||
84 | /* corresponding link offsets in EEPROM */ | |
85 | #define EEPROM_LINK_HOST (2*0x64) | |
86 | #define EEPROM_LINK_GENERAL (2*0x65) | |
87 | #define EEPROM_LINK_REGULATORY (2*0x66) | |
88 | #define EEPROM_LINK_CALIBRATION (2*0x67) | |
89 | #define EEPROM_LINK_PROCESS_ADJST (2*0x68) | |
90 | #define EEPROM_LINK_OTHERS (2*0x69) | |
91 | #define EEPROM_LINK_TXP_LIMIT (2*0x6a) | |
92 | #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b) | |
93 | ||
94 | /* General */ | |
95 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ | |
96 | #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */ | |
97 | #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ | |
98 | #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ | |
99 | #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ | |
100 | #define EEPROM_VERSION (2*0x44) /* 2 bytes */ | |
101 | #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ | |
102 | #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ | |
103 | #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ | |
104 | #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ | |
105 | ||
106 | /* calibration */ | |
107 | struct iwl_eeprom_calib_hdr { | |
108 | u8 version; | |
109 | u8 pa_type; | |
110 | __le16 voltage; | |
111 | } __packed; | |
112 | ||
113 | #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION) | |
114 | #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL) | |
115 | ||
116 | /* temperature */ | |
117 | #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL) | |
118 | #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL) | |
119 | ||
b7998c8b EL |
120 | /* SKU Capabilities (actual values from EEPROM definition) */ |
121 | enum eeprom_sku_bits { | |
122 | EEPROM_SKU_CAP_BAND_24GHZ = BIT(4), | |
123 | EEPROM_SKU_CAP_BAND_52GHZ = BIT(5), | |
124 | EEPROM_SKU_CAP_11N_ENABLE = BIT(6), | |
125 | EEPROM_SKU_CAP_AMT_ENABLE = BIT(7), | |
126 | EEPROM_SKU_CAP_IPAN_ENABLE = BIT(8) | |
127 | }; | |
128 | ||
129 | /* radio config bits (actual values from EEPROM definition) */ | |
130 | #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ | |
131 | #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ | |
132 | #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ | |
133 | #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ | |
134 | #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ | |
135 | #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ | |
136 | ||
137 | ||
26a7ca9a JB |
138 | /* |
139 | * EEPROM bands | |
140 | * These are the channel numbers from each band in the order | |
141 | * that they are stored in the EEPROM band information. Note | |
142 | * that EEPROM bands aren't the same as mac80211 bands, and | |
143 | * there are even special "ht40 bands" in the EEPROM. | |
144 | */ | |
145 | static const u8 iwl_eeprom_band_1[14] = { /* 2.4 GHz */ | |
146 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
147 | }; | |
148 | ||
149 | static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */ | |
150 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 | |
151 | }; | |
152 | ||
153 | static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */ | |
154 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
155 | }; | |
156 | ||
157 | static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */ | |
158 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
159 | }; | |
160 | ||
161 | static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */ | |
162 | 145, 149, 153, 157, 161, 165 | |
163 | }; | |
164 | ||
165 | static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */ | |
166 | 1, 2, 3, 4, 5, 6, 7 | |
167 | }; | |
168 | ||
169 | static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */ | |
170 | 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 | |
171 | }; | |
172 | ||
173 | #define IWL_NUM_CHANNELS (ARRAY_SIZE(iwl_eeprom_band_1) + \ | |
174 | ARRAY_SIZE(iwl_eeprom_band_2) + \ | |
175 | ARRAY_SIZE(iwl_eeprom_band_3) + \ | |
176 | ARRAY_SIZE(iwl_eeprom_band_4) + \ | |
177 | ARRAY_SIZE(iwl_eeprom_band_5)) | |
178 | ||
179 | /* rate data (static) */ | |
180 | static struct ieee80211_rate iwl_cfg80211_rates[] = { | |
181 | { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, | |
182 | { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, | |
183 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
184 | { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, | |
185 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
186 | { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, | |
187 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
188 | { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, | |
189 | { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, | |
190 | { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, | |
191 | { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, | |
192 | { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, | |
193 | { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, | |
194 | { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, | |
195 | { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, | |
196 | }; | |
197 | #define RATES_24_OFFS 0 | |
198 | #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) | |
199 | #define RATES_52_OFFS 4 | |
200 | #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) | |
201 | ||
202 | /* EEPROM reading functions */ | |
203 | ||
204 | static u16 iwl_eeprom_query16(const u8 *eeprom, size_t eeprom_size, int offset) | |
205 | { | |
206 | if (WARN_ON(offset + sizeof(u16) > eeprom_size)) | |
207 | return 0; | |
208 | return le16_to_cpup((__le16 *)(eeprom + offset)); | |
209 | } | |
210 | ||
211 | static u32 eeprom_indirect_address(const u8 *eeprom, size_t eeprom_size, | |
212 | u32 address) | |
213 | { | |
214 | u16 offset = 0; | |
215 | ||
216 | if ((address & INDIRECT_ADDRESS) == 0) | |
217 | return address; | |
218 | ||
219 | switch (address & INDIRECT_TYPE_MSK) { | |
220 | case INDIRECT_HOST: | |
221 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
222 | EEPROM_LINK_HOST); | |
223 | break; | |
224 | case INDIRECT_GENERAL: | |
225 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
226 | EEPROM_LINK_GENERAL); | |
227 | break; | |
228 | case INDIRECT_REGULATORY: | |
229 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
230 | EEPROM_LINK_REGULATORY); | |
231 | break; | |
232 | case INDIRECT_TXP_LIMIT: | |
233 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
234 | EEPROM_LINK_TXP_LIMIT); | |
235 | break; | |
236 | case INDIRECT_TXP_LIMIT_SIZE: | |
237 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
238 | EEPROM_LINK_TXP_LIMIT_SIZE); | |
239 | break; | |
240 | case INDIRECT_CALIBRATION: | |
241 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
242 | EEPROM_LINK_CALIBRATION); | |
243 | break; | |
244 | case INDIRECT_PROCESS_ADJST: | |
245 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
246 | EEPROM_LINK_PROCESS_ADJST); | |
247 | break; | |
248 | case INDIRECT_OTHERS: | |
249 | offset = iwl_eeprom_query16(eeprom, eeprom_size, | |
250 | EEPROM_LINK_OTHERS); | |
251 | break; | |
252 | default: | |
253 | WARN_ON(1); | |
254 | break; | |
255 | } | |
256 | ||
257 | /* translate the offset from words to byte */ | |
258 | return (address & ADDRESS_MSK) + (offset << 1); | |
259 | } | |
260 | ||
261 | static const u8 *iwl_eeprom_query_addr(const u8 *eeprom, size_t eeprom_size, | |
262 | u32 offset) | |
263 | { | |
264 | u32 address = eeprom_indirect_address(eeprom, eeprom_size, offset); | |
265 | ||
266 | if (WARN_ON(address >= eeprom_size)) | |
267 | return NULL; | |
268 | ||
269 | return &eeprom[address]; | |
270 | } | |
271 | ||
272 | static int iwl_eeprom_read_calib(const u8 *eeprom, size_t eeprom_size, | |
b7998c8b | 273 | struct iwl_nvm_data *data) |
26a7ca9a JB |
274 | { |
275 | struct iwl_eeprom_calib_hdr *hdr; | |
276 | ||
277 | hdr = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, | |
278 | EEPROM_CALIB_ALL); | |
279 | if (!hdr) | |
280 | return -ENODATA; | |
281 | data->calib_version = hdr->version; | |
282 | data->calib_voltage = hdr->voltage; | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | /** | |
288 | * enum iwl_eeprom_channel_flags - channel flags in EEPROM | |
289 | * @EEPROM_CHANNEL_VALID: channel is usable for this SKU/geo | |
290 | * @EEPROM_CHANNEL_IBSS: usable as an IBSS channel | |
291 | * @EEPROM_CHANNEL_ACTIVE: active scanning allowed | |
292 | * @EEPROM_CHANNEL_RADAR: radar detection required | |
293 | * @EEPROM_CHANNEL_WIDE: 20 MHz channel okay (?) | |
294 | * @EEPROM_CHANNEL_DFS: dynamic freq selection candidate | |
295 | */ | |
296 | enum iwl_eeprom_channel_flags { | |
297 | EEPROM_CHANNEL_VALID = BIT(0), | |
298 | EEPROM_CHANNEL_IBSS = BIT(1), | |
299 | EEPROM_CHANNEL_ACTIVE = BIT(3), | |
300 | EEPROM_CHANNEL_RADAR = BIT(4), | |
301 | EEPROM_CHANNEL_WIDE = BIT(5), | |
302 | EEPROM_CHANNEL_DFS = BIT(7), | |
303 | }; | |
304 | ||
305 | /** | |
306 | * struct iwl_eeprom_channel - EEPROM channel data | |
307 | * @flags: %EEPROM_CHANNEL_* flags | |
308 | * @max_power_avg: max power (in dBm) on this channel, at most 31 dBm | |
309 | */ | |
310 | struct iwl_eeprom_channel { | |
311 | u8 flags; | |
312 | s8 max_power_avg; | |
313 | } __packed; | |
314 | ||
315 | ||
316 | enum iwl_eeprom_enhanced_txpwr_flags { | |
317 | IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0), | |
318 | IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1), | |
319 | IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2), | |
320 | IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3), | |
321 | IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4), | |
322 | IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5), | |
323 | IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6), | |
324 | IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7), | |
325 | }; | |
326 | ||
327 | /** | |
328 | * iwl_eeprom_enhanced_txpwr structure | |
329 | * @flags: entry flags | |
330 | * @channel: channel number | |
331 | * @chain_a_max_pwr: chain a max power in 1/2 dBm | |
332 | * @chain_b_max_pwr: chain b max power in 1/2 dBm | |
333 | * @chain_c_max_pwr: chain c max power in 1/2 dBm | |
334 | * @delta_20_in_40: 20-in-40 deltas (hi/lo) | |
335 | * @mimo2_max_pwr: mimo2 max power in 1/2 dBm | |
336 | * @mimo3_max_pwr: mimo3 max power in 1/2 dBm | |
337 | * | |
338 | * This structure presents the enhanced regulatory tx power limit layout | |
339 | * in an EEPROM image. | |
340 | */ | |
341 | struct iwl_eeprom_enhanced_txpwr { | |
342 | u8 flags; | |
343 | u8 channel; | |
344 | s8 chain_a_max; | |
345 | s8 chain_b_max; | |
346 | s8 chain_c_max; | |
347 | u8 delta_20_in_40; | |
348 | s8 mimo2_max; | |
349 | s8 mimo3_max; | |
350 | } __packed; | |
351 | ||
b7998c8b | 352 | static s8 iwl_get_max_txpwr_half_dbm(const struct iwl_nvm_data *data, |
26a7ca9a JB |
353 | struct iwl_eeprom_enhanced_txpwr *txp) |
354 | { | |
355 | s8 result = 0; /* (.5 dBm) */ | |
356 | ||
357 | /* Take the highest tx power from any valid chains */ | |
358 | if (data->valid_tx_ant & ANT_A && txp->chain_a_max > result) | |
359 | result = txp->chain_a_max; | |
360 | ||
361 | if (data->valid_tx_ant & ANT_B && txp->chain_b_max > result) | |
362 | result = txp->chain_b_max; | |
363 | ||
364 | if (data->valid_tx_ant & ANT_C && txp->chain_c_max > result) | |
365 | result = txp->chain_c_max; | |
366 | ||
367 | if ((data->valid_tx_ant == ANT_AB || | |
368 | data->valid_tx_ant == ANT_BC || | |
369 | data->valid_tx_ant == ANT_AC) && txp->mimo2_max > result) | |
370 | result = txp->mimo2_max; | |
371 | ||
372 | if (data->valid_tx_ant == ANT_ABC && txp->mimo3_max > result) | |
373 | result = txp->mimo3_max; | |
374 | ||
375 | return result; | |
376 | } | |
377 | ||
378 | #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT) | |
379 | #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr) | |
380 | #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE) | |
381 | ||
382 | #define TXP_CHECK_AND_PRINT(x) \ | |
383 | ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) ? # x " " : "") | |
384 | ||
385 | static void | |
b7998c8b | 386 | iwl_eeprom_enh_txp_read_element(struct iwl_nvm_data *data, |
26a7ca9a JB |
387 | struct iwl_eeprom_enhanced_txpwr *txp, |
388 | int n_channels, s8 max_txpower_avg) | |
389 | { | |
390 | int ch_idx; | |
391 | enum ieee80211_band band; | |
392 | ||
393 | band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ? | |
394 | IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ; | |
395 | ||
396 | for (ch_idx = 0; ch_idx < n_channels; ch_idx++) { | |
397 | struct ieee80211_channel *chan = &data->channels[ch_idx]; | |
398 | ||
399 | /* update matching channel or from common data only */ | |
400 | if (txp->channel != 0 && chan->hw_value != txp->channel) | |
401 | continue; | |
402 | ||
403 | /* update matching band only */ | |
404 | if (band != chan->band) | |
405 | continue; | |
406 | ||
407 | if (chan->max_power < max_txpower_avg && | |
408 | !(txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ)) | |
409 | chan->max_power = max_txpower_avg; | |
410 | } | |
411 | } | |
412 | ||
413 | static void iwl_eeprom_enhanced_txpower(struct device *dev, | |
b7998c8b | 414 | struct iwl_nvm_data *data, |
26a7ca9a JB |
415 | const u8 *eeprom, size_t eeprom_size, |
416 | int n_channels) | |
417 | { | |
418 | struct iwl_eeprom_enhanced_txpwr *txp_array, *txp; | |
419 | int idx, entries; | |
420 | __le16 *txp_len; | |
421 | s8 max_txp_avg_halfdbm; | |
422 | ||
423 | BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8); | |
424 | ||
425 | /* the length is in 16-bit words, but we want entries */ | |
426 | txp_len = (__le16 *)iwl_eeprom_query_addr(eeprom, eeprom_size, | |
427 | EEPROM_TXP_SZ_OFFS); | |
428 | entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN; | |
429 | ||
430 | txp_array = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, | |
431 | EEPROM_TXP_OFFS); | |
432 | ||
433 | for (idx = 0; idx < entries; idx++) { | |
434 | txp = &txp_array[idx]; | |
435 | /* skip invalid entries */ | |
436 | if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID)) | |
437 | continue; | |
438 | ||
439 | IWL_DEBUG_EEPROM(dev, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n", | |
440 | (txp->channel && (txp->flags & | |
441 | IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ? | |
442 | "Common " : (txp->channel) ? | |
443 | "Channel" : "Common", | |
444 | (txp->channel), | |
445 | TXP_CHECK_AND_PRINT(VALID), | |
446 | TXP_CHECK_AND_PRINT(BAND_52G), | |
447 | TXP_CHECK_AND_PRINT(OFDM), | |
448 | TXP_CHECK_AND_PRINT(40MHZ), | |
449 | TXP_CHECK_AND_PRINT(HT_AP), | |
450 | TXP_CHECK_AND_PRINT(RES1), | |
451 | TXP_CHECK_AND_PRINT(RES2), | |
452 | TXP_CHECK_AND_PRINT(COMMON_TYPE), | |
453 | txp->flags); | |
454 | IWL_DEBUG_EEPROM(dev, | |
455 | "\t\t chain_A: 0x%02x chain_B: 0X%02x chain_C: 0X%02x\n", | |
456 | txp->chain_a_max, txp->chain_b_max, | |
457 | txp->chain_c_max); | |
458 | IWL_DEBUG_EEPROM(dev, | |
459 | "\t\t MIMO2: 0x%02x MIMO3: 0x%02x High 20_on_40: 0x%02x Low 20_on_40: 0x%02x\n", | |
460 | txp->mimo2_max, txp->mimo3_max, | |
461 | ((txp->delta_20_in_40 & 0xf0) >> 4), | |
462 | (txp->delta_20_in_40 & 0x0f)); | |
463 | ||
464 | max_txp_avg_halfdbm = iwl_get_max_txpwr_half_dbm(data, txp); | |
465 | ||
466 | iwl_eeprom_enh_txp_read_element(data, txp, n_channels, | |
467 | DIV_ROUND_UP(max_txp_avg_halfdbm, 2)); | |
468 | ||
469 | if (max_txp_avg_halfdbm > data->max_tx_pwr_half_dbm) | |
470 | data->max_tx_pwr_half_dbm = max_txp_avg_halfdbm; | |
471 | } | |
472 | } | |
473 | ||
474 | static void iwl_init_band_reference(const struct iwl_cfg *cfg, | |
475 | const u8 *eeprom, size_t eeprom_size, | |
476 | int eeprom_band, int *eeprom_ch_count, | |
477 | const struct iwl_eeprom_channel **ch_info, | |
478 | const u8 **eeprom_ch_array) | |
479 | { | |
480 | u32 offset = cfg->eeprom_params->regulatory_bands[eeprom_band - 1]; | |
481 | ||
482 | offset |= INDIRECT_ADDRESS | INDIRECT_REGULATORY; | |
483 | ||
484 | *ch_info = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, offset); | |
485 | ||
486 | switch (eeprom_band) { | |
487 | case 1: /* 2.4GHz band */ | |
488 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1); | |
489 | *eeprom_ch_array = iwl_eeprom_band_1; | |
490 | break; | |
491 | case 2: /* 4.9GHz band */ | |
492 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2); | |
493 | *eeprom_ch_array = iwl_eeprom_band_2; | |
494 | break; | |
495 | case 3: /* 5.2GHz band */ | |
496 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3); | |
497 | *eeprom_ch_array = iwl_eeprom_band_3; | |
498 | break; | |
499 | case 4: /* 5.5GHz band */ | |
500 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4); | |
501 | *eeprom_ch_array = iwl_eeprom_band_4; | |
502 | break; | |
503 | case 5: /* 5.7GHz band */ | |
504 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5); | |
505 | *eeprom_ch_array = iwl_eeprom_band_5; | |
506 | break; | |
507 | case 6: /* 2.4GHz ht40 channels */ | |
508 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6); | |
509 | *eeprom_ch_array = iwl_eeprom_band_6; | |
510 | break; | |
511 | case 7: /* 5 GHz ht40 channels */ | |
512 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7); | |
513 | *eeprom_ch_array = iwl_eeprom_band_7; | |
514 | break; | |
515 | default: | |
516 | *eeprom_ch_count = 0; | |
517 | *eeprom_ch_array = NULL; | |
518 | WARN_ON(1); | |
519 | } | |
520 | } | |
521 | ||
522 | #define CHECK_AND_PRINT(x) \ | |
523 | ((eeprom_ch->flags & EEPROM_CHANNEL_##x) ? # x " " : "") | |
524 | ||
525 | static void iwl_mod_ht40_chan_info(struct device *dev, | |
b7998c8b | 526 | struct iwl_nvm_data *data, int n_channels, |
26a7ca9a JB |
527 | enum ieee80211_band band, u16 channel, |
528 | const struct iwl_eeprom_channel *eeprom_ch, | |
529 | u8 clear_ht40_extension_channel) | |
530 | { | |
531 | struct ieee80211_channel *chan = NULL; | |
532 | int i; | |
533 | ||
534 | for (i = 0; i < n_channels; i++) { | |
535 | if (data->channels[i].band != band) | |
536 | continue; | |
537 | if (data->channels[i].hw_value != channel) | |
538 | continue; | |
539 | chan = &data->channels[i]; | |
540 | break; | |
541 | } | |
542 | ||
543 | if (!chan) | |
544 | return; | |
545 | ||
546 | IWL_DEBUG_EEPROM(dev, | |
547 | "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", | |
548 | channel, | |
549 | band == IEEE80211_BAND_5GHZ ? "5.2" : "2.4", | |
550 | CHECK_AND_PRINT(IBSS), | |
551 | CHECK_AND_PRINT(ACTIVE), | |
552 | CHECK_AND_PRINT(RADAR), | |
553 | CHECK_AND_PRINT(WIDE), | |
554 | CHECK_AND_PRINT(DFS), | |
555 | eeprom_ch->flags, | |
556 | eeprom_ch->max_power_avg, | |
557 | ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) && | |
558 | !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" | |
559 | : "not "); | |
560 | ||
561 | if (eeprom_ch->flags & EEPROM_CHANNEL_VALID) | |
562 | chan->flags &= ~clear_ht40_extension_channel; | |
563 | } | |
564 | ||
565 | #define CHECK_AND_PRINT_I(x) \ | |
566 | ((eeprom_ch_info[ch_idx].flags & EEPROM_CHANNEL_##x) ? # x " " : "") | |
567 | ||
568 | static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, | |
b7998c8b | 569 | struct iwl_nvm_data *data, |
26a7ca9a JB |
570 | const u8 *eeprom, size_t eeprom_size) |
571 | { | |
572 | int band, ch_idx; | |
573 | const struct iwl_eeprom_channel *eeprom_ch_info; | |
574 | const u8 *eeprom_ch_array; | |
575 | int eeprom_ch_count; | |
576 | int n_channels = 0; | |
577 | ||
578 | /* | |
579 | * Loop through the 5 EEPROM bands and add them to the parse list | |
580 | */ | |
581 | for (band = 1; band <= 5; band++) { | |
582 | struct ieee80211_channel *channel; | |
583 | ||
584 | iwl_init_band_reference(cfg, eeprom, eeprom_size, band, | |
585 | &eeprom_ch_count, &eeprom_ch_info, | |
586 | &eeprom_ch_array); | |
587 | ||
588 | /* Loop through each band adding each of the channels */ | |
589 | for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { | |
590 | const struct iwl_eeprom_channel *eeprom_ch; | |
591 | ||
592 | eeprom_ch = &eeprom_ch_info[ch_idx]; | |
593 | ||
594 | if (!(eeprom_ch->flags & EEPROM_CHANNEL_VALID)) { | |
595 | IWL_DEBUG_EEPROM(dev, | |
596 | "Ch. %d Flags %x [%sGHz] - No traffic\n", | |
597 | eeprom_ch_array[ch_idx], | |
598 | eeprom_ch_info[ch_idx].flags, | |
599 | (band != 1) ? "5.2" : "2.4"); | |
600 | continue; | |
601 | } | |
602 | ||
603 | channel = &data->channels[n_channels]; | |
604 | n_channels++; | |
605 | ||
606 | channel->hw_value = eeprom_ch_array[ch_idx]; | |
607 | channel->band = (band == 1) ? IEEE80211_BAND_2GHZ | |
608 | : IEEE80211_BAND_5GHZ; | |
609 | channel->center_freq = | |
610 | ieee80211_channel_to_frequency( | |
611 | channel->hw_value, channel->band); | |
612 | ||
613 | /* set no-HT40, will enable as appropriate later */ | |
614 | channel->flags = IEEE80211_CHAN_NO_HT40; | |
615 | ||
616 | if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS)) | |
8fe02e16 | 617 | channel->flags |= IEEE80211_CHAN_NO_IR; |
26a7ca9a JB |
618 | |
619 | if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
8fe02e16 | 620 | channel->flags |= IEEE80211_CHAN_NO_IR; |
26a7ca9a JB |
621 | |
622 | if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR) | |
623 | channel->flags |= IEEE80211_CHAN_RADAR; | |
624 | ||
625 | /* Initialize regulatory-based run-time data */ | |
626 | channel->max_power = | |
627 | eeprom_ch_info[ch_idx].max_power_avg; | |
628 | IWL_DEBUG_EEPROM(dev, | |
629 | "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", | |
630 | channel->hw_value, | |
631 | (band != 1) ? "5.2" : "2.4", | |
632 | CHECK_AND_PRINT_I(VALID), | |
633 | CHECK_AND_PRINT_I(IBSS), | |
634 | CHECK_AND_PRINT_I(ACTIVE), | |
635 | CHECK_AND_PRINT_I(RADAR), | |
636 | CHECK_AND_PRINT_I(WIDE), | |
637 | CHECK_AND_PRINT_I(DFS), | |
638 | eeprom_ch_info[ch_idx].flags, | |
639 | eeprom_ch_info[ch_idx].max_power_avg, | |
640 | ((eeprom_ch_info[ch_idx].flags & | |
641 | EEPROM_CHANNEL_IBSS) && | |
642 | !(eeprom_ch_info[ch_idx].flags & | |
643 | EEPROM_CHANNEL_RADAR)) | |
644 | ? "" : "not "); | |
645 | } | |
646 | } | |
647 | ||
648 | if (cfg->eeprom_params->enhanced_txpower) { | |
649 | /* | |
650 | * for newer device (6000 series and up) | |
651 | * EEPROM contain enhanced tx power information | |
652 | * driver need to process addition information | |
653 | * to determine the max channel tx power limits | |
654 | */ | |
655 | iwl_eeprom_enhanced_txpower(dev, data, eeprom, eeprom_size, | |
656 | n_channels); | |
657 | } else { | |
658 | /* All others use data from channel map */ | |
659 | int i; | |
660 | ||
661 | data->max_tx_pwr_half_dbm = -128; | |
662 | ||
663 | for (i = 0; i < n_channels; i++) | |
664 | data->max_tx_pwr_half_dbm = | |
665 | max_t(s8, data->max_tx_pwr_half_dbm, | |
666 | data->channels[i].max_power * 2); | |
667 | } | |
668 | ||
669 | /* Check if we do have HT40 channels */ | |
670 | if (cfg->eeprom_params->regulatory_bands[5] == | |
671 | EEPROM_REGULATORY_BAND_NO_HT40 && | |
672 | cfg->eeprom_params->regulatory_bands[6] == | |
673 | EEPROM_REGULATORY_BAND_NO_HT40) | |
674 | return n_channels; | |
675 | ||
676 | /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */ | |
677 | for (band = 6; band <= 7; band++) { | |
678 | enum ieee80211_band ieeeband; | |
679 | ||
680 | iwl_init_band_reference(cfg, eeprom, eeprom_size, band, | |
681 | &eeprom_ch_count, &eeprom_ch_info, | |
682 | &eeprom_ch_array); | |
683 | ||
684 | /* EEPROM band 6 is 2.4, band 7 is 5 GHz */ | |
685 | ieeeband = (band == 6) ? IEEE80211_BAND_2GHZ | |
686 | : IEEE80211_BAND_5GHZ; | |
687 | ||
688 | /* Loop through each band adding each of the channels */ | |
689 | for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { | |
690 | /* Set up driver's info for lower half */ | |
691 | iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband, | |
692 | eeprom_ch_array[ch_idx], | |
693 | &eeprom_ch_info[ch_idx], | |
694 | IEEE80211_CHAN_NO_HT40PLUS); | |
695 | ||
696 | /* Set up driver's info for upper half */ | |
697 | iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband, | |
698 | eeprom_ch_array[ch_idx] + 4, | |
699 | &eeprom_ch_info[ch_idx], | |
700 | IEEE80211_CHAN_NO_HT40MINUS); | |
701 | } | |
702 | } | |
703 | ||
704 | return n_channels; | |
705 | } | |
706 | ||
b1e1adfa JB |
707 | int iwl_init_sband_channels(struct iwl_nvm_data *data, |
708 | struct ieee80211_supported_band *sband, | |
709 | int n_channels, enum ieee80211_band band) | |
26a7ca9a JB |
710 | { |
711 | struct ieee80211_channel *chan = &data->channels[0]; | |
712 | int n = 0, idx = 0; | |
713 | ||
714 | while (chan->band != band && idx < n_channels) | |
715 | chan = &data->channels[++idx]; | |
716 | ||
717 | sband->channels = &data->channels[idx]; | |
718 | ||
719 | while (chan->band == band && idx < n_channels) { | |
720 | chan = &data->channels[++idx]; | |
721 | n++; | |
722 | } | |
723 | ||
724 | sband->n_channels = n; | |
725 | ||
726 | return n; | |
727 | } | |
728 | ||
729 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ | |
730 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
731 | ||
b1e1adfa JB |
732 | void iwl_init_ht_hw_capab(const struct iwl_cfg *cfg, |
733 | struct iwl_nvm_data *data, | |
734 | struct ieee80211_sta_ht_cap *ht_info, | |
9ce4fa72 EG |
735 | enum ieee80211_band band, |
736 | u8 tx_chains, u8 rx_chains) | |
26a7ca9a JB |
737 | { |
738 | int max_bit_rate = 0; | |
26a7ca9a | 739 | |
9ce4fa72 | 740 | tx_chains = hweight8(tx_chains); |
26a7ca9a JB |
741 | if (cfg->rx_with_siso_diversity) |
742 | rx_chains = 1; | |
743 | else | |
9ce4fa72 | 744 | rx_chains = hweight8(rx_chains); |
26a7ca9a | 745 | |
b7998c8b | 746 | if (!(data->sku_cap_11n_enable) || !cfg->ht_params) { |
26a7ca9a JB |
747 | ht_info->ht_supported = false; |
748 | return; | |
749 | } | |
750 | ||
751 | ht_info->ht_supported = true; | |
f7546c76 | 752 | ht_info->cap = IEEE80211_HT_CAP_DSSSCCK40; |
26a7ca9a | 753 | |
183d281d ES |
754 | if (cfg->ht_params->stbc) { |
755 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
756 | ||
757 | if (tx_chains > 1) | |
758 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
759 | } | |
760 | ||
26a7ca9a JB |
761 | if (iwlwifi_mod_params.amsdu_size_8K) |
762 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; | |
763 | ||
764 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; | |
765 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_4; | |
766 | ||
767 | ht_info->mcs.rx_mask[0] = 0xFF; | |
768 | if (rx_chains >= 2) | |
769 | ht_info->mcs.rx_mask[1] = 0xFF; | |
770 | if (rx_chains >= 3) | |
771 | ht_info->mcs.rx_mask[2] = 0xFF; | |
772 | ||
773 | if (cfg->ht_params->ht_greenfield_support) | |
774 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; | |
775 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
776 | ||
777 | max_bit_rate = MAX_BIT_RATE_20_MHZ; | |
778 | ||
779 | if (cfg->ht_params->ht40_bands & BIT(band)) { | |
780 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; | |
781 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
26a7ca9a JB |
782 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
783 | } | |
784 | ||
785 | /* Highest supported Rx data rate */ | |
786 | max_bit_rate *= rx_chains; | |
787 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); | |
788 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
789 | ||
790 | /* Tx MCS capabilities */ | |
791 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
792 | if (tx_chains != rx_chains) { | |
793 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
794 | ht_info->mcs.tx_params |= ((tx_chains - 1) << | |
795 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
796 | } | |
797 | } | |
798 | ||
799 | static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg, | |
b7998c8b | 800 | struct iwl_nvm_data *data, |
26a7ca9a JB |
801 | const u8 *eeprom, size_t eeprom_size) |
802 | { | |
803 | int n_channels = iwl_init_channel_map(dev, cfg, data, | |
804 | eeprom, eeprom_size); | |
805 | int n_used = 0; | |
806 | struct ieee80211_supported_band *sband; | |
807 | ||
808 | sband = &data->bands[IEEE80211_BAND_2GHZ]; | |
809 | sband->band = IEEE80211_BAND_2GHZ; | |
810 | sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; | |
811 | sband->n_bitrates = N_RATES_24; | |
812 | n_used += iwl_init_sband_channels(data, sband, n_channels, | |
813 | IEEE80211_BAND_2GHZ); | |
9ce4fa72 EG |
814 | iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ, |
815 | data->valid_tx_ant, data->valid_rx_ant); | |
26a7ca9a JB |
816 | |
817 | sband = &data->bands[IEEE80211_BAND_5GHZ]; | |
818 | sband->band = IEEE80211_BAND_5GHZ; | |
819 | sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; | |
820 | sband->n_bitrates = N_RATES_52; | |
821 | n_used += iwl_init_sband_channels(data, sband, n_channels, | |
822 | IEEE80211_BAND_5GHZ); | |
9ce4fa72 EG |
823 | iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ, |
824 | data->valid_tx_ant, data->valid_rx_ant); | |
26a7ca9a JB |
825 | |
826 | if (n_channels != n_used) | |
827 | IWL_ERR_DEV(dev, "EEPROM: used only %d of %d channels\n", | |
828 | n_used, n_channels); | |
829 | } | |
830 | ||
831 | /* EEPROM data functions */ | |
832 | ||
b7998c8b | 833 | struct iwl_nvm_data * |
26a7ca9a JB |
834 | iwl_parse_eeprom_data(struct device *dev, const struct iwl_cfg *cfg, |
835 | const u8 *eeprom, size_t eeprom_size) | |
836 | { | |
b7998c8b | 837 | struct iwl_nvm_data *data; |
26a7ca9a | 838 | const void *tmp; |
b7998c8b | 839 | u16 radio_cfg, sku; |
26a7ca9a JB |
840 | |
841 | if (WARN_ON(!cfg || !cfg->eeprom_params)) | |
842 | return NULL; | |
843 | ||
844 | data = kzalloc(sizeof(*data) + | |
845 | sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS, | |
846 | GFP_KERNEL); | |
847 | if (!data) | |
848 | return NULL; | |
849 | ||
850 | /* get MAC address(es) */ | |
851 | tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_MAC_ADDRESS); | |
852 | if (!tmp) | |
853 | goto err_free; | |
854 | memcpy(data->hw_addr, tmp, ETH_ALEN); | |
855 | data->n_hw_addrs = iwl_eeprom_query16(eeprom, eeprom_size, | |
856 | EEPROM_NUM_MAC_ADDRESS); | |
857 | ||
858 | if (iwl_eeprom_read_calib(eeprom, eeprom_size, data)) | |
859 | goto err_free; | |
860 | ||
861 | tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_XTAL); | |
862 | if (!tmp) | |
863 | goto err_free; | |
864 | memcpy(data->xtal_calib, tmp, sizeof(data->xtal_calib)); | |
865 | ||
866 | tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, | |
867 | EEPROM_RAW_TEMPERATURE); | |
868 | if (!tmp) | |
869 | goto err_free; | |
870 | data->raw_temperature = *(__le16 *)tmp; | |
871 | ||
872 | tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, | |
873 | EEPROM_KELVIN_TEMPERATURE); | |
874 | if (!tmp) | |
875 | goto err_free; | |
876 | data->kelvin_temperature = *(__le16 *)tmp; | |
877 | data->kelvin_voltage = *((__le16 *)tmp + 1); | |
878 | ||
b7998c8b | 879 | radio_cfg = iwl_eeprom_query16(eeprom, eeprom_size, |
26a7ca9a | 880 | EEPROM_RADIO_CONFIG); |
b7998c8b EL |
881 | data->radio_cfg_dash = EEPROM_RF_CFG_DASH_MSK(radio_cfg); |
882 | data->radio_cfg_pnum = EEPROM_RF_CFG_PNUM_MSK(radio_cfg); | |
883 | data->radio_cfg_step = EEPROM_RF_CFG_STEP_MSK(radio_cfg); | |
884 | data->radio_cfg_type = EEPROM_RF_CFG_TYPE_MSK(radio_cfg); | |
885 | data->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg); | |
886 | data->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg); | |
887 | ||
888 | sku = iwl_eeprom_query16(eeprom, eeprom_size, | |
889 | EEPROM_SKU_CAP); | |
890 | data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE; | |
891 | data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE; | |
892 | data->sku_cap_band_24GHz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ; | |
893 | data->sku_cap_band_52GHz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ; | |
894 | data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE; | |
63d76dc0 | 895 | if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) |
b7998c8b | 896 | data->sku_cap_11n_enable = false; |
26a7ca9a | 897 | |
b7998c8b EL |
898 | data->nvm_version = iwl_eeprom_query16(eeprom, eeprom_size, |
899 | EEPROM_VERSION); | |
26a7ca9a JB |
900 | |
901 | /* check overrides (some devices have wrong EEPROM) */ | |
902 | if (cfg->valid_tx_ant) | |
903 | data->valid_tx_ant = cfg->valid_tx_ant; | |
904 | if (cfg->valid_rx_ant) | |
905 | data->valid_rx_ant = cfg->valid_rx_ant; | |
906 | ||
907 | if (!data->valid_tx_ant || !data->valid_rx_ant) { | |
908 | IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n", | |
909 | data->valid_tx_ant, data->valid_rx_ant); | |
910 | goto err_free; | |
911 | } | |
912 | ||
913 | iwl_init_sbands(dev, cfg, data, eeprom, eeprom_size); | |
914 | ||
915 | return data; | |
916 | err_free: | |
917 | kfree(data); | |
918 | return NULL; | |
919 | } | |
48e29340 | 920 | IWL_EXPORT_SYMBOL(iwl_parse_eeprom_data); |
26a7ca9a JB |
921 | |
922 | /* helper functions */ | |
b7998c8b | 923 | int iwl_nvm_check_version(struct iwl_nvm_data *data, |
26a7ca9a JB |
924 | struct iwl_trans *trans) |
925 | { | |
b7998c8b EL |
926 | if (data->nvm_version >= trans->cfg->nvm_ver || |
927 | data->calib_version >= trans->cfg->nvm_calib_ver) { | |
d01031b2 | 928 | IWL_DEBUG_INFO(trans, "device EEPROM VER=0x%x, CALIB=0x%x\n", |
b7998c8b | 929 | data->nvm_version, data->calib_version); |
26a7ca9a JB |
930 | return 0; |
931 | } | |
932 | ||
933 | IWL_ERR(trans, | |
934 | "Unsupported (too old) EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n", | |
b7998c8b EL |
935 | data->nvm_version, trans->cfg->nvm_ver, |
936 | data->calib_version, trans->cfg->nvm_calib_ver); | |
26a7ca9a JB |
937 | return -EINVAL; |
938 | } | |
48e29340 | 939 | IWL_EXPORT_SYMBOL(iwl_nvm_check_version); |