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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-eeprom.c
CommitLineData
34cf6ff6
AK		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
4e318262 8 * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
34cf6ff6
AK		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
759ef89f 28 * Intel Linux Wireless <ilw@linux.intel.com>
34cf6ff6
AK		 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
4e318262 33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34cf6ff6
AK		 34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62
63
64#include <linux/kernel.h>
65#include <linux/module.h>
5a0e3ad6 66#include <linux/slab.h>
34cf6ff6
AK		 67#include <linux/init.h>
68
69#include <net/mac80211.h>
70
5a36ba0e 71#include "iwl-commands.h"
3e0d4cb1 72#include "iwl-dev.h"
34cf6ff6 73#include "iwl-core.h"
0a6857e7 74#include "iwl-debug.h"
701cb099 75#include "iwl-agn.h"
34cf6ff6 76#include "iwl-eeprom.h"
3395f6e9 77#include "iwl-io.h"
eae63b85 78#include "iwl-prph.h"
34cf6ff6 79
bf85ea4f
AK		 80/************************** EEPROM BANDS ****************************
81 *
82 * The iwl_eeprom_band definitions below provide the mapping from the
83 * EEPROM contents to the specific channel number supported for each
84 * band.
85 *
86 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
87 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
88 * The specific geography and calibration information for that channel
89 * is contained in the eeprom map itself.
90 *
91 * During init, we copy the eeprom information and channel map
92 * information into priv->channel_info_24/52 and priv->channel_map_24/52
93 *
94 * channel_map_24/52 provides the index in the channel_info array for a
95 * given channel. We have to have two separate maps as there is channel
96 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
97 * band_2
98 *
99 * A value of 0xff stored in the channel_map indicates that the channel
100 * is not supported by the hardware at all.
101 *
102 * A value of 0xfe in the channel_map indicates that the channel is not
103 * valid for Tx with the current hardware. This means that
104 * while the system can tune and receive on a given channel, it may not
105 * be able to associate or transmit any frames on that
106 * channel. There is no corresponding channel information for that
107 * entry.
108 *
109 *********************************************************************/
110
111/* 2.4 GHz */
112const u8 iwl_eeprom_band_1[14] = {
113 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
114};
115
116/* 5.2 GHz bands */
117static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
118 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
119};
120
121static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
122 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
123};
124
125static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
126 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
127};
128
129static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
130 145, 149, 153, 157, 161, 165
131};
132
7aafef1c 133static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */
bf85ea4f
AK		 134 1, 2, 3, 4, 5, 6, 7
135};
136
7aafef1c 137static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
bf85ea4f
AK		 138 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
139};
140
34cf6ff6
AK		 141/******************************************************************************
142 *
701cb099 143 * generic NVM functions
34cf6ff6
AK		 144 *
145******************************************************************************/
146
16b80b71
DF		 147/*
148 * The device's EEPROM semaphore prevents conflicts between driver and uCode
149 * when accessing the EEPROM; each access is a series of pulses to/from the
150 * EEPROM chip, not a single event, so even reads could conflict if they
151 * weren't arbitrated by the semaphore.
152 */
90304749
EG		 153
154#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
155#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
156
ca77d534 157static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
16b80b71
DF		 158{
159 u16 count;
160 int ret;
161
162 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
163 /* Request semaphore */
ca77d534 164 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
16b80b71
DF		 165 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
166
167 /* See if we got it */
ca77d534 168 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
16b80b71
DF		 169 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
170 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
171 EEPROM_SEM_TIMEOUT);
172 if (ret >= 0) {
ca77d534 173 IWL_DEBUG_EEPROM(trans,
16b80b71
DF		 174 "Acquired semaphore after %d tries.\n",
175 count+1);
176 return ret;
177 }
178 }
179
180 return ret;
181}
182
ca77d534 183static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
16b80b71 184{
ca77d534 185 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
16b80b71
DF		 186 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
187
188}
189
11483b5c 190static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
34cf6ff6 191{
11483b5c 192 u32 gp = iwl_read32(trans(priv), CSR_EEPROM_GP) &
1042db2a 193 CSR_EEPROM_GP_VALID_MSK;
f41bb897
WYG		 194 int ret = 0;
195
11483b5c 196 IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp);
f41bb897
WYG		 197 switch (gp) {
198 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
11483b5c
JB		 199 if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
200 IWL_ERR(priv, "EEPROM with bad signature: 0x%08x\n",
f41bb897
WYG		 201 gp);
202 ret = -ENOENT;
203 }
204 break;
205 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
206 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
11483b5c
JB		 207 if (priv->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
208 IWL_ERR(priv, "OTP with bad signature: 0x%08x\n", gp);
f41bb897
WYG		 209 ret = -ENOENT;
210 }
211 break;
212 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
213 default:
11483b5c 214 IWL_ERR(priv, "bad EEPROM/OTP signature, type=%s, "
f41bb897 215 "EEPROM_GP=0x%08x\n",
11483b5c 216 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
f41bb897
WYG		 217 ? "OTP" : "EEPROM", gp);
218 ret = -ENOENT;
219 break;
34cf6ff6 220 }
f41bb897 221 return ret;
34cf6ff6 222}
34cf6ff6 223
11483b5c 224u16 iwl_eeprom_query16(struct iwl_priv *priv, size_t offset)
701cb099 225{
11483b5c 226 if (!priv->eeprom)
701cb099 227 return 0;
11483b5c 228 return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
701cb099
WYG		 229}
230
231int iwl_eeprom_check_version(struct iwl_priv *priv)
232{
233 u16 eeprom_ver;
234 u16 calib_ver;
235
11483b5c
JB		 236 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
237 calib_ver = iwl_eeprom_calib_version(priv);
701cb099 238
38622419
DF		 239 if (eeprom_ver < cfg(priv)->eeprom_ver ||
240 calib_ver < cfg(priv)->eeprom_calib_ver)
701cb099
WYG		 241 goto err;
242
243 IWL_INFO(priv, "device EEPROM VER=0x%x, CALIB=0x%x\n",
244 eeprom_ver, calib_ver);
245
246 return 0;
247err:
248 IWL_ERR(priv, "Unsupported (too old) EEPROM VER=0x%x < 0x%x "
249 "CALIB=0x%x < 0x%x\n",
38622419
DF		 250 eeprom_ver, cfg(priv)->eeprom_ver,
251 calib_ver, cfg(priv)->eeprom_calib_ver);
701cb099
WYG		 252 return -EINVAL;
253
254}
255
54708d8d 256int iwl_eeprom_init_hw_params(struct iwl_priv *priv)
701cb099
WYG		 257{
258 u16 radio_cfg;
259
11483b5c 260 priv->hw_params.sku = iwl_eeprom_query16(priv, EEPROM_SKU_CAP);
9e295116 261 if (priv->hw_params.sku & EEPROM_SKU_CAP_11N_ENABLE &&
54708d8d
JB		 262 !cfg(priv)->ht_params) {
263 IWL_ERR(priv, "Invalid 11n configuration\n");
264 return -EINVAL;
701cb099 265 }
54708d8d 266
9e295116 267 if (!priv->hw_params.sku) {
701cb099
WYG		 268 IWL_ERR(priv, "Invalid device sku\n");
269 return -EINVAL;
270 }
271
9e295116 272 IWL_INFO(priv, "Device SKU: 0x%X\n", priv->hw_params.sku);
701cb099 273
11483b5c 274 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
7e79a393 275
9e295116
JB		 276 priv->hw_params.valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
277 priv->hw_params.valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg);
7e79a393
JB		 278
279 /* check overrides (some devices have wrong EEPROM) */
280 if (cfg(priv)->valid_tx_ant)
9e295116 281 priv->hw_params.valid_tx_ant = cfg(priv)->valid_tx_ant;
7e79a393 282 if (cfg(priv)->valid_rx_ant)
9e295116 283 priv->hw_params.valid_rx_ant = cfg(priv)->valid_rx_ant;
7e79a393 284
9e295116 285 if (!priv->hw_params.valid_tx_ant || !priv->hw_params.valid_rx_ant) {
7e79a393 286 IWL_ERR(priv, "Invalid chain (0x%X, 0x%X)\n",
9e295116
JB		 287 priv->hw_params.valid_tx_ant,
288 priv->hw_params.valid_rx_ant);
7e79a393 289 return -EINVAL;
701cb099 290 }
7e79a393
JB		 291
292 IWL_INFO(priv, "Valid Tx ant: 0x%X, Valid Rx ant: 0x%X\n",
9e295116 293 priv->hw_params.valid_tx_ant, priv->hw_params.valid_rx_ant);
7e79a393 294
701cb099
WYG		 295 return 0;
296}
297
11483b5c 298u16 iwl_eeprom_calib_version(struct iwl_priv *priv)
701cb099 299{
11483b5c
JB		 300 struct iwl_eeprom_calib_hdr *hdr;
301
302 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
303 EEPROM_CALIB_ALL);
304 return hdr->version;
305}
306
307static u32 eeprom_indirect_address(struct iwl_priv *priv, u32 address)
308{
309 u16 offset = 0;
310
311 if ((address & INDIRECT_ADDRESS) == 0)
312 return address;
313
314 switch (address & INDIRECT_TYPE_MSK) {
315 case INDIRECT_HOST:
316 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
317 break;
318 case INDIRECT_GENERAL:
319 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
320 break;
321 case INDIRECT_REGULATORY:
322 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
323 break;
324 case INDIRECT_TXP_LIMIT:
325 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
326 break;
327 case INDIRECT_TXP_LIMIT_SIZE:
328 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
329 break;
330 case INDIRECT_CALIBRATION:
331 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
332 break;
333 case INDIRECT_PROCESS_ADJST:
334 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
335 break;
336 case INDIRECT_OTHERS:
337 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
338 break;
339 default:
340 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
341 address & INDIRECT_TYPE_MSK);
342 break;
343 }
344
345 /* translate the offset from words to byte */
346 return (address & ADDRESS_MSK) + (offset << 1);
347}
348
349const u8 *iwl_eeprom_query_addr(struct iwl_priv *priv, size_t offset)
350{
351 u32 address = eeprom_indirect_address(priv, offset);
352 BUG_ON(address >= cfg(priv)->base_params->eeprom_size);
353 return &priv->eeprom[address];
354}
355
356void iwl_eeprom_get_mac(struct iwl_priv *priv, u8 *mac)
357{
358 const u8 *addr = iwl_eeprom_query_addr(priv,
701cb099
WYG		 359 EEPROM_MAC_ADDRESS);
360 memcpy(mac, addr, ETH_ALEN);
361}
362
363/******************************************************************************
364 *
365 * OTP related functions
366 *
367******************************************************************************/
368
ca77d534
EG		 369static void iwl_set_otp_access(struct iwl_trans *trans,
370 enum iwl_access_mode mode)
415e4993 371{
ca77d534 372 iwl_read32(trans, CSR_OTP_GP_REG);
415e4993 373
415e4993 374 if (mode == IWL_OTP_ACCESS_ABSOLUTE)
ca77d534 375 iwl_clear_bit(trans, CSR_OTP_GP_REG,
70817b5e 376 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
415e4993 377 else
ca77d534 378 iwl_set_bit(trans, CSR_OTP_GP_REG,
70817b5e 379 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
415e4993
WYG		 380}
381
ca77d534 382static int iwl_get_nvm_type(struct iwl_trans *trans, u32 hw_rev)
0848e297
WYG		 383{
384 u32 otpgp;
385 int nvm_type;
386
387 /* OTP only valid for CP/PP and after */
e98a1302 388 switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
b23a0524 389 case CSR_HW_REV_TYPE_NONE:
ca77d534 390 IWL_ERR(trans, "Unknown hardware type\n");
b23a0524 391 return -ENOENT;
0848e297
WYG		 392 case CSR_HW_REV_TYPE_5300:
393 case CSR_HW_REV_TYPE_5350:
394 case CSR_HW_REV_TYPE_5100:
395 case CSR_HW_REV_TYPE_5150:
396 nvm_type = NVM_DEVICE_TYPE_EEPROM;
397 break;
398 default:
ca77d534 399 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
0848e297
WYG		 400 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
401 nvm_type = NVM_DEVICE_TYPE_OTP;
402 else
403 nvm_type = NVM_DEVICE_TYPE_EEPROM;
404 break;
405 }
406 return nvm_type;
407}
408
ca77d534 409static int iwl_init_otp_access(struct iwl_trans *trans)
0848e297
WYG		 410{
411 int ret;
412
413 /* Enable 40MHz radio clock */
ca77d534
EG		 414 iwl_write32(trans, CSR_GP_CNTRL,
415 iwl_read32(trans, CSR_GP_CNTRL) |
02a7fa00 416 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
0848e297
WYG		 417
418 /* wait for clock to be ready */
ca77d534 419 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
02a7fa00
JB		 420 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
421 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
422 25000);
0848e297 423 if (ret < 0)
ca77d534 424 IWL_ERR(trans, "Time out access OTP\n");
0848e297 425 else {
ca77d534 426 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
d77b034f
RC		 427 APMG_PS_CTRL_VAL_RESET_REQ);
428 udelay(5);
ca77d534 429 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
d77b034f 430 APMG_PS_CTRL_VAL_RESET_REQ);
32004ee4
WYG		 431
432 /*
433 * CSR auto clock gate disable bit -
434 * this is only applicable for HW with OTP shadow RAM
435 */
ca77d534
EG		 436 if (cfg(trans)->base_params->shadow_ram_support)
437 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
32004ee4 438 CSR_RESET_LINK_PWR_MGMT_DISABLED);
0848e297
WYG		 439 }
440 return ret;
441}
442
ca77d534
EG		 443static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
444 __le16 *eeprom_data)
415e4993
WYG		 445{
446 int ret = 0;
447 u32 r;
448 u32 otpgp;
449
ca77d534 450 iwl_write32(trans, CSR_EEPROM_REG,
02a7fa00 451 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
ca77d534 452 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
02a7fa00
JB		 453 CSR_EEPROM_REG_READ_VALID_MSK,
454 CSR_EEPROM_REG_READ_VALID_MSK,
455 IWL_EEPROM_ACCESS_TIMEOUT);
415e4993 456 if (ret < 0) {
ca77d534 457 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
415e4993
WYG		 458 return ret;
459 }
ca77d534 460 r = iwl_read32(trans, CSR_EEPROM_REG);
415e4993 461 /* check for ECC errors: */
ca77d534 462 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
415e4993
WYG		 463 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
464 /* stop in this case */
465 /* set the uncorrectable OTP ECC bit for acknowledgement */
ca77d534 466 iwl_set_bit(trans, CSR_OTP_GP_REG,
415e4993 467 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
ca77d534 468 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
415e4993
WYG		 469 return -EINVAL;
470 }
471 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
472 /* continue in this case */
473 /* set the correctable OTP ECC bit for acknowledgement */
ca77d534 474 iwl_set_bit(trans, CSR_OTP_GP_REG,
415e4993 475 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
ca77d534 476 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
415e4993 477 }
af6b8ee3 478 *eeprom_data = cpu_to_le16(r >> 16);
415e4993
WYG		 479 return 0;
480}
481
482/*
483 * iwl_is_otp_empty: check for empty OTP
484 */
ca77d534 485static bool iwl_is_otp_empty(struct iwl_trans *trans)
415e4993 486{
af6b8ee3
JB		 487 u16 next_link_addr = 0;
488 __le16 link_value;
415e4993
WYG		 489 bool is_empty = false;
490
491 /* locate the beginning of OTP link list */
ca77d534 492 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
415e4993 493 if (!link_value) {
ca77d534 494 IWL_ERR(trans, "OTP is empty\n");
415e4993
WYG		 495 is_empty = true;
496 }
497 } else {
ca77d534 498 IWL_ERR(trans, "Unable to read first block of OTP list.\n");
415e4993
WYG		 499 is_empty = true;
500 }
501
502 return is_empty;
503}
504
505
506/*
507 * iwl_find_otp_image: find EEPROM image in OTP
508 * finding the OTP block that contains the EEPROM image.
509 * the last valid block on the link list (the block _before_ the last block)
510 * is the block we should read and used to configure the device.
511 * If all the available OTP blocks are full, the last block will be the block
512 * we should read and used to configure the device.
513 * only perform this operation if shadow RAM is disabled
514 */
ca77d534 515static int iwl_find_otp_image(struct iwl_trans *trans,
415e4993
WYG		 516 u16 *validblockaddr)
517{
af6b8ee3
JB		 518 u16 next_link_addr = 0, valid_addr;
519 __le16 link_value = 0;
415e4993
WYG		 520 int usedblocks = 0;
521
522 /* set addressing mode to absolute to traverse the link list */
ca77d534 523 iwl_set_otp_access(trans, IWL_OTP_ACCESS_ABSOLUTE);
415e4993
WYG		 524
525 /* checking for empty OTP or error */
ca77d534 526 if (iwl_is_otp_empty(trans))
415e4993
WYG		 527 return -EINVAL;
528
529 /*
530 * start traverse link list
531 * until reach the max number of OTP blocks
532 * different devices have different number of OTP blocks
533 */
534 do {
535 /* save current valid block address
536 * check for more block on the link list
537 */
538 valid_addr = next_link_addr;
af6b8ee3 539 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
ca77d534 540 IWL_DEBUG_EEPROM(trans, "OTP blocks %d addr 0x%x\n",
415e4993 541 usedblocks, next_link_addr);
ca77d534 542 if (iwl_read_otp_word(trans, next_link_addr, &link_value))
415e4993
WYG		 543 return -EINVAL;
544 if (!link_value) {
545 /*
2facba76 546 * reach the end of link list, return success and
415e4993
WYG		 547 * set address point to the starting address
548 * of the image
549 */
2facba76
JS		 550 *validblockaddr = valid_addr;
551 /* skip first 2 bytes (link list pointer) */
552 *validblockaddr += 2;
553 return 0;
415e4993
WYG		 554 }
555 /* more in the link list, continue */
556 usedblocks++;
ca77d534 557 } while (usedblocks <= cfg(trans)->base_params->max_ll_items);
2facba76
JS		 558
559 /* OTP has no valid blocks */
ca77d534 560 IWL_DEBUG_EEPROM(trans, "OTP has no valid blocks\n");
2facba76 561 return -EINVAL;
415e4993
WYG		 562}
563
701cb099
WYG		 564/******************************************************************************
565 *
566 * Tx Power related functions
567 *
568******************************************************************************/
569/**
570 * iwl_get_max_txpower_avg - get the highest tx power from all chains.
571 * find the highest tx power from all chains for the channel
572 */
706c4ff6 573static s8 iwl_get_max_txpower_avg(const struct iwl_cfg *cfg,
701cb099
WYG		 574 struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
575 int element, s8 *max_txpower_in_half_dbm)
3be63ff0 576{
701cb099
WYG		 577 s8 max_txpower_avg = 0; /* (dBm) */
578
579 /* Take the highest tx power from any valid chains */
1431b216 580 if ((cfg->valid_tx_ant & ANT_A) &&
701cb099
WYG		 581 (enhanced_txpower[element].chain_a_max > max_txpower_avg))
582 max_txpower_avg = enhanced_txpower[element].chain_a_max;
1431b216 583 if ((cfg->valid_tx_ant & ANT_B) &&
701cb099
WYG		 584 (enhanced_txpower[element].chain_b_max > max_txpower_avg))
585 max_txpower_avg = enhanced_txpower[element].chain_b_max;
1431b216 586 if ((cfg->valid_tx_ant & ANT_C) &&
701cb099
WYG		 587 (enhanced_txpower[element].chain_c_max > max_txpower_avg))
588 max_txpower_avg = enhanced_txpower[element].chain_c_max;
1431b216
DF		 589 if (((cfg->valid_tx_ant == ANT_AB) |
590 (cfg->valid_tx_ant == ANT_BC) |
591 (cfg->valid_tx_ant == ANT_AC)) &&
701cb099
WYG		 592 (enhanced_txpower[element].mimo2_max > max_txpower_avg))
593 max_txpower_avg = enhanced_txpower[element].mimo2_max;
1431b216 594 if ((cfg->valid_tx_ant == ANT_ABC) &&
701cb099
WYG		 595 (enhanced_txpower[element].mimo3_max > max_txpower_avg))
596 max_txpower_avg = enhanced_txpower[element].mimo3_max;
597
598 /*
599 * max. tx power in EEPROM is in 1/2 dBm format
600 * convert from 1/2 dBm to dBm (round-up convert)
601 * but we also do not want to loss 1/2 dBm resolution which
602 * will impact performance
603 */
604 *max_txpower_in_half_dbm = max_txpower_avg;
605 return (max_txpower_avg & 0x01) + (max_txpower_avg >> 1);
606}
607
608static void
609iwl_eeprom_enh_txp_read_element(struct iwl_priv *priv,
610 struct iwl_eeprom_enhanced_txpwr *txp,
611 s8 max_txpower_avg)
612{
613 int ch_idx;
614 bool is_ht40 = txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ;
615 enum ieee80211_band band;
616
617 band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ?
618 IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
619
620 for (ch_idx = 0; ch_idx < priv->channel_count; ch_idx++) {
621 struct iwl_channel_info *ch_info = &priv->channel_info[ch_idx];
622
623 /* update matching channel or from common data only */
624 if (txp->channel != 0 && ch_info->channel != txp->channel)
625 continue;
626
627 /* update matching band only */
628 if (band != ch_info->band)
629 continue;
630
631 if (ch_info->max_power_avg < max_txpower_avg && !is_ht40) {
632 ch_info->max_power_avg = max_txpower_avg;
633 ch_info->curr_txpow = max_txpower_avg;
634 ch_info->scan_power = max_txpower_avg;
635 }
636
637 if (is_ht40 && ch_info->ht40_max_power_avg < max_txpower_avg)
638 ch_info->ht40_max_power_avg = max_txpower_avg;
639 }
640}
641
642#define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
643#define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
644#define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
645
646#define TXP_CHECK_AND_PRINT(x) ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) \
647 ? # x " " : "")
648
51dc51d1 649static void iwl_eeprom_enhanced_txpower(struct iwl_priv *priv)
701cb099
WYG		 650{
651 struct iwl_eeprom_enhanced_txpwr *txp_array, *txp;
652 int idx, entries;
653 __le16 *txp_len;
654 s8 max_txp_avg, max_txp_avg_halfdbm;
655
656 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
657
658 /* the length is in 16-bit words, but we want entries */
11483b5c 659 txp_len = (__le16 *) iwl_eeprom_query_addr(priv, EEPROM_TXP_SZ_OFFS);
701cb099
WYG		 660 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
661
11483b5c 662 txp_array = (void *) iwl_eeprom_query_addr(priv, EEPROM_TXP_OFFS);
701cb099
WYG		 663
664 for (idx = 0; idx < entries; idx++) {
665 txp = &txp_array[idx];
666 /* skip invalid entries */
667 if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID))
668 continue;
669
670 IWL_DEBUG_EEPROM(priv, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
671 (txp->channel && (txp->flags &
672 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ?
673 "Common " : (txp->channel) ?
674 "Channel" : "Common",
675 (txp->channel),
676 TXP_CHECK_AND_PRINT(VALID),
677 TXP_CHECK_AND_PRINT(BAND_52G),
678 TXP_CHECK_AND_PRINT(OFDM),
679 TXP_CHECK_AND_PRINT(40MHZ),
680 TXP_CHECK_AND_PRINT(HT_AP),
681 TXP_CHECK_AND_PRINT(RES1),
682 TXP_CHECK_AND_PRINT(RES2),
683 TXP_CHECK_AND_PRINT(COMMON_TYPE),
684 txp->flags);
685 IWL_DEBUG_EEPROM(priv, "\t\t chain_A: 0x%02x "
686 "chain_B: 0X%02x chain_C: 0X%02x\n",
687 txp->chain_a_max, txp->chain_b_max,
688 txp->chain_c_max);
689 IWL_DEBUG_EEPROM(priv, "\t\t MIMO2: 0x%02x "
690 "MIMO3: 0x%02x High 20_on_40: 0x%02x "
691 "Low 20_on_40: 0x%02x\n",
692 txp->mimo2_max, txp->mimo3_max,
693 ((txp->delta_20_in_40 & 0xf0) >> 4),
694 (txp->delta_20_in_40 & 0x0f));
695
38622419 696 max_txp_avg = iwl_get_max_txpower_avg(cfg(priv), txp_array, idx,
701cb099
WYG		 697 &max_txp_avg_halfdbm);
698
699 /*
700 * Update the user limit values values to the highest
701 * power supported by any channel
702 */
703 if (max_txp_avg > priv->tx_power_user_lmt)
704 priv->tx_power_user_lmt = max_txp_avg;
705 if (max_txp_avg_halfdbm > priv->tx_power_lmt_in_half_dbm)
706 priv->tx_power_lmt_in_half_dbm = max_txp_avg_halfdbm;
707
708 iwl_eeprom_enh_txp_read_element(priv, txp, max_txp_avg);
709 }
3be63ff0 710}
3be63ff0 711
34cf6ff6
AK		 712/**
713 * iwl_eeprom_init - read EEPROM contents
714 *
11483b5c 715 * Load the EEPROM contents from adapter into priv->eeprom
34cf6ff6
AK		 716 *
717 * NOTE: This routine uses the non-debug IO access functions.
718 */
11483b5c 719int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
34cf6ff6 720{
af6b8ee3 721 __le16 *e;
11483b5c 722 u32 gp = iwl_read32(trans(priv), CSR_EEPROM_GP);
0848e297 723 int sz;
34cf6ff6 724 int ret;
34cf6ff6 725 u16 addr;
415e4993
WYG		 726 u16 validblockaddr = 0;
727 u16 cache_addr = 0;
0848e297 728
11483b5c
JB		 729 priv->nvm_device_type = iwl_get_nvm_type(trans(priv), hw_rev);
730 if (priv->nvm_device_type == -ENOENT)
b23a0524 731 return -ENOENT;
073d3f5f 732 /* allocate eeprom */
11483b5c
JB		 733 sz = cfg(priv)->base_params->eeprom_size;
734 IWL_DEBUG_EEPROM(priv, "NVM size = %d\n", sz);
735 priv->eeprom = kzalloc(sz, GFP_KERNEL);
736 if (!priv->eeprom) {
073d3f5f
TW		 737 ret = -ENOMEM;
738 goto alloc_err;
739 }
11483b5c 740 e = (__le16 *)priv->eeprom;
34cf6ff6 741
11483b5c 742 ret = iwl_eeprom_verify_signature(priv);
073d3f5f 743 if (ret < 0) {
11483b5c 744 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
073d3f5f
TW		 745 ret = -ENOENT;
746 goto err;
34cf6ff6
AK		 747 }
748
749 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
11483b5c 750 ret = iwl_eeprom_acquire_semaphore(trans(priv));
34cf6ff6 751 if (ret < 0) {
11483b5c 752 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
073d3f5f
TW		 753 ret = -ENOENT;
754 goto err;
34cf6ff6 755 }
88521364 756
11483b5c 757 if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
88521364 758
11483b5c 759 ret = iwl_init_otp_access(trans(priv));
0848e297 760 if (ret) {
11483b5c 761 IWL_ERR(priv, "Failed to initialize OTP access.\n");
0848e297 762 ret = -ENOENT;
415e4993 763 goto done;
0848e297 764 }
11483b5c
JB		 765 iwl_write32(trans(priv), CSR_EEPROM_GP,
766 iwl_read32(trans(priv), CSR_EEPROM_GP) &
02a7fa00 767 ~CSR_EEPROM_GP_IF_OWNER_MSK);
415e4993 768
11483b5c 769 iwl_set_bit(trans(priv), CSR_OTP_GP_REG,
0848e297
WYG		 770 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
771 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
415e4993 772 /* traversing the linked list if no shadow ram supported */
11483b5c
JB		 773 if (!cfg(priv)->base_params->shadow_ram_support) {
774 if (iwl_find_otp_image(trans(priv), &validblockaddr)) {
415e4993 775 ret = -ENOENT;
0848e297
WYG		 776 goto done;
777 }
415e4993
WYG		 778 }
779 for (addr = validblockaddr; addr < validblockaddr + sz;
780 addr += sizeof(u16)) {
af6b8ee3 781 __le16 eeprom_data;
415e4993 782
11483b5c
JB		 783 ret = iwl_read_otp_word(trans(priv), addr,
784 &eeprom_data);
415e4993 785 if (ret)
0848e297 786 goto done;
415e4993
WYG		 787 e[cache_addr / 2] = eeprom_data;
788 cache_addr += sizeof(u16);
0848e297
WYG		 789 }
790 } else {
791 /* eeprom is an array of 16bit values */
792 for (addr = 0; addr < sz; addr += sizeof(u16)) {
793 u32 r;
794
11483b5c 795 iwl_write32(trans(priv), CSR_EEPROM_REG,
02a7fa00 796 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0848e297 797
11483b5c 798 ret = iwl_poll_bit(trans(priv), CSR_EEPROM_REG,
1739d332 799 CSR_EEPROM_REG_READ_VALID_MSK,
0848e297
WYG		 800 CSR_EEPROM_REG_READ_VALID_MSK,
801 IWL_EEPROM_ACCESS_TIMEOUT);
802 if (ret < 0) {
11483b5c 803 IWL_ERR(priv,
ca77d534 804 "Time out reading EEPROM[%d]\n", addr);
0848e297
WYG		 805 goto done;
806 }
11483b5c 807 r = iwl_read32(trans(priv), CSR_EEPROM_REG);
af6b8ee3 808 e[addr / 2] = cpu_to_le16(r >> 16);
34cf6ff6 809 }
34cf6ff6 810 }
d1358f62 811
11483b5c
JB		 812 IWL_DEBUG_EEPROM(priv, "NVM Type: %s, version: 0x%x\n",
813 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
d1358f62 814 ? "OTP" : "EEPROM",
11483b5c 815 iwl_eeprom_query16(priv, EEPROM_VERSION));
d1358f62 816
34cf6ff6 817 ret = 0;
34cf6ff6 818done:
11483b5c 819 iwl_eeprom_release_semaphore(trans(priv));
d1358f62 820
073d3f5f
TW		 821err:
822 if (ret)
11483b5c 823 iwl_eeprom_free(priv);
073d3f5f 824alloc_err:
34cf6ff6
AK		 825 return ret;
826}
34cf6ff6 827
11483b5c 828void iwl_eeprom_free(struct iwl_priv *priv)
073d3f5f 829{
11483b5c
JB		 830 kfree(priv->eeprom);
831 priv->eeprom = NULL;
073d3f5f 832}
073d3f5f 833
11483b5c 834static void iwl_init_band_reference(struct iwl_priv *priv,
073d3f5f
TW		 835 int eep_band, int *eeprom_ch_count,
836 const struct iwl_eeprom_channel **eeprom_ch_info,
837 const u8 **eeprom_ch_index)
bf85ea4f 838{
e9676695 839 u32 offset = priv->lib->
073d3f5f
TW		 840 eeprom_ops.regulatory_bands[eep_band - 1];
841 switch (eep_band) {
bf85ea4f
AK		 842 case 1: /* 2.4GHz band */
843 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
073d3f5f 844 *eeprom_ch_info = (struct iwl_eeprom_channel *)
11483b5c 845 iwl_eeprom_query_addr(priv, offset);
bf85ea4f
AK		 846 *eeprom_ch_index = iwl_eeprom_band_1;
847 break;
848 case 2: /* 4.9GHz band */
849 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
073d3f5f 850 *eeprom_ch_info = (struct iwl_eeprom_channel *)
11483b5c 851 iwl_eeprom_query_addr(priv, offset);
bf85ea4f
AK		 852 *eeprom_ch_index = iwl_eeprom_band_2;
853 break;
854 case 3: /* 5.2GHz band */
855 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
073d3f5f 856 *eeprom_ch_info = (struct iwl_eeprom_channel *)
11483b5c 857 iwl_eeprom_query_addr(priv, offset);
bf85ea4f
AK		 858 *eeprom_ch_index = iwl_eeprom_band_3;
859 break;
860 case 4: /* 5.5GHz band */
861 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
073d3f5f 862 *eeprom_ch_info = (struct iwl_eeprom_channel *)
11483b5c 863 iwl_eeprom_query_addr(priv, offset);
bf85ea4f
AK		 864 *eeprom_ch_index = iwl_eeprom_band_4;
865 break;
866 case 5: /* 5.7GHz band */
867 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
073d3f5f 868 *eeprom_ch_info = (struct iwl_eeprom_channel *)
11483b5c 869 iwl_eeprom_query_addr(priv, offset);
bf85ea4f
AK		 870 *eeprom_ch_index = iwl_eeprom_band_5;
871 break;
7aafef1c 872 case 6: /* 2.4GHz ht40 channels */
bf85ea4f 873 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
073d3f5f 874 *eeprom_ch_info = (struct iwl_eeprom_channel *)
11483b5c 875 iwl_eeprom_query_addr(priv, offset);
bf85ea4f
AK		 876 *eeprom_ch_index = iwl_eeprom_band_6;
877 break;
7aafef1c 878 case 7: /* 5 GHz ht40 channels */
bf85ea4f 879 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
073d3f5f 880 *eeprom_ch_info = (struct iwl_eeprom_channel *)
11483b5c 881 iwl_eeprom_query_addr(priv, offset);
bf85ea4f
AK		 882 *eeprom_ch_index = iwl_eeprom_band_7;
883 break;
884 default:
885 BUG();
886 return;
887 }
888}
889
890#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
891 ? # x " " : "")
bf85ea4f 892/**
3b24716f 893 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
bf85ea4f
AK		 894 *
895 * Does not set up a command, or touch hardware.
896 */
3b24716f 897static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
bf85ea4f 898 enum ieee80211_band band, u16 channel,
073d3f5f 899 const struct iwl_eeprom_channel *eeprom_ch,
3b24716f 900 u8 clear_ht40_extension_channel)
bf85ea4f
AK		 901{
902 struct iwl_channel_info *ch_info;
903
904 ch_info = (struct iwl_channel_info *)
8622e705 905 iwl_get_channel_info(priv, band, channel);
bf85ea4f
AK		 906
907 if (!is_channel_valid(ch_info))
908 return -1;
909
d058ff8b 910 IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
630fe9b6 911 " Ad-Hoc %ssupported\n",
bf85ea4f
AK		 912 ch_info->channel,
913 is_channel_a_band(ch_info) ?
914 "5.2" : "2.4",
915 CHECK_AND_PRINT(IBSS),
916 CHECK_AND_PRINT(ACTIVE),
917 CHECK_AND_PRINT(RADAR),
918 CHECK_AND_PRINT(WIDE),
bf85ea4f
AK		 919 CHECK_AND_PRINT(DFS),
920 eeprom_ch->flags,
921 eeprom_ch->max_power_avg,
922 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
923 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
924 "" : "not ");
925
7aafef1c
WYG		 926 ch_info->ht40_eeprom = *eeprom_ch;
927 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
7aafef1c 928 ch_info->ht40_flags = eeprom_ch->flags;
6c3069b1
RC		 929 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
930 ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
bf85ea4f
AK		 931
932 return 0;
933}
934
935#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
936 ? # x " " : "")
937
938/**
939 * iwl_init_channel_map - Set up driver's info for all possible channels
940 */
941int iwl_init_channel_map(struct iwl_priv *priv)
942{
943 int eeprom_ch_count = 0;
944 const u8 *eeprom_ch_index = NULL;
073d3f5f 945 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
bf85ea4f
AK		 946 int band, ch;
947 struct iwl_channel_info *ch_info;
948
949 if (priv->channel_count) {
d058ff8b 950 IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n");
bf85ea4f
AK		 951 return 0;
952 }
953
d058ff8b 954 IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n");
bf85ea4f
AK		 955
956 priv->channel_count =
957 ARRAY_SIZE(iwl_eeprom_band_1) +
958 ARRAY_SIZE(iwl_eeprom_band_2) +
959 ARRAY_SIZE(iwl_eeprom_band_3) +
960 ARRAY_SIZE(iwl_eeprom_band_4) +
961 ARRAY_SIZE(iwl_eeprom_band_5);
962
d058ff8b
WYG		 963 IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n",
964 priv->channel_count);
bf85ea4f 965
7f90dce1
EG		 966 priv->channel_info = kcalloc(priv->channel_count,
967 sizeof(struct iwl_channel_info),
968 GFP_KERNEL);
bf85ea4f 969 if (!priv->channel_info) {
15b1687c 970 IWL_ERR(priv, "Could not allocate channel_info\n");
bf85ea4f
AK		 971 priv->channel_count = 0;
972 return -ENOMEM;
973 }
974
975 ch_info = priv->channel_info;
976
977 /* Loop through the 5 EEPROM bands adding them in order to the
978 * channel map we maintain (that contains additional information than
979 * what just in the EEPROM) */
980 for (band = 1; band <= 5; band++) {
981
982 iwl_init_band_reference(priv, band, &eeprom_ch_count,
983 &eeprom_ch_info, &eeprom_ch_index);
984
985 /* Loop through each band adding each of the channels */
986 for (ch = 0; ch < eeprom_ch_count; ch++) {
987 ch_info->channel = eeprom_ch_index[ch];
988 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
989 IEEE80211_BAND_5GHZ;
990
991 /* permanently store EEPROM's channel regulatory flags
992 * and max power in channel info database. */
993 ch_info->eeprom = eeprom_ch_info[ch];
994
995 /* Copy the run-time flags so they are there even on
996 * invalid channels */
997 ch_info->flags = eeprom_ch_info[ch].flags;
7aafef1c 998 /* First write that ht40 is not enabled, and then enable
963f5517 999 * one by one */
7aafef1c 1000 ch_info->ht40_extension_channel =
3b24716f 1001 IEEE80211_CHAN_NO_HT40;
bf85ea4f
AK		 1002
1003 if (!(is_channel_valid(ch_info))) {
d058ff8b
WYG		 1004 IWL_DEBUG_EEPROM(priv,
1005 "Ch. %d Flags %x [%sGHz] - "
bf85ea4f
AK		 1006 "No traffic\n",
1007 ch_info->channel,
1008 ch_info->flags,
1009 is_channel_a_band(ch_info) ?
1010 "5.2" : "2.4");
1011 ch_info++;
1012 continue;
1013 }
1014
1015 /* Initialize regulatory-based run-time data */
1016 ch_info->max_power_avg = ch_info->curr_txpow =
1017 eeprom_ch_info[ch].max_power_avg;
1018 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
1019 ch_info->min_power = 0;
1020
d058ff8b
WYG		 1021 IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] "
1022 "%s%s%s%s%s%s(0x%02x %ddBm):"
630fe9b6 1023 " Ad-Hoc %ssupported\n",
bf85ea4f
AK		 1024 ch_info->channel,
1025 is_channel_a_band(ch_info) ?
1026 "5.2" : "2.4",
1027 CHECK_AND_PRINT_I(VALID),
1028 CHECK_AND_PRINT_I(IBSS),
1029 CHECK_AND_PRINT_I(ACTIVE),
1030 CHECK_AND_PRINT_I(RADAR),
1031 CHECK_AND_PRINT_I(WIDE),
bf85ea4f
AK		 1032 CHECK_AND_PRINT_I(DFS),
1033 eeprom_ch_info[ch].flags,
1034 eeprom_ch_info[ch].max_power_avg,
1035 ((eeprom_ch_info[ch].
1036 flags & EEPROM_CHANNEL_IBSS)
1037 && !(eeprom_ch_info[ch].
1038 flags & EEPROM_CHANNEL_RADAR))
1039 ? "" : "not ");
1040
bf85ea4f
AK		 1041 ch_info++;
1042 }
1043 }
1044
7aafef1c 1045 /* Check if we do have HT40 channels */
e9676695 1046 if (priv->lib->eeprom_ops.regulatory_bands[5] ==
7aafef1c 1047 EEPROM_REGULATORY_BAND_NO_HT40 &&
e9676695 1048 priv->lib->eeprom_ops.regulatory_bands[6] ==
7aafef1c 1049 EEPROM_REGULATORY_BAND_NO_HT40)
e6148917
SO		 1050 return 0;
1051
7aafef1c 1052 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
bf85ea4f
AK		 1053 for (band = 6; band <= 7; band++) {
1054 enum ieee80211_band ieeeband;
bf85ea4f
AK		 1055
1056 iwl_init_band_reference(priv, band, &eeprom_ch_count,
1057 &eeprom_ch_info, &eeprom_ch_index);
1058
1059 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1060 ieeeband =
1061 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1062
1063 /* Loop through each band adding each of the channels */
1064 for (ch = 0; ch < eeprom_ch_count; ch++) {
bf85ea4f 1065 /* Set up driver's info for lower half */
3b24716f 1066 iwl_mod_ht40_chan_info(priv, ieeeband,
da6833cb 1067 eeprom_ch_index[ch],
3b24716f
ZY		 1068 &eeprom_ch_info[ch],
1069 IEEE80211_CHAN_NO_HT40PLUS);
bf85ea4f
AK		 1070
1071 /* Set up driver's info for upper half */
3b24716f
ZY		 1072 iwl_mod_ht40_chan_info(priv, ieeeband,
1073 eeprom_ch_index[ch] + 4,
1074 &eeprom_ch_info[ch],
1075 IEEE80211_CHAN_NO_HT40MINUS);
bf85ea4f
AK		 1076 }
1077 }
1078
ab9fd1bf
WYG		 1079 /* for newer device (6000 series and up)
1080 * EEPROM contain enhanced tx power information
1081 * driver need to process addition information
1082 * to determine the max channel tx power limits
1083 */
e9676695 1084 if (priv->lib->eeprom_ops.enhanced_txpower)
51dc51d1 1085 iwl_eeprom_enhanced_txpower(priv);
ab9fd1bf 1086
bf85ea4f
AK		 1087 return 0;
1088}
bf85ea4f
AK		 1089
1090/*
da6833cb 1091 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
bf85ea4f
AK		 1092 */
1093void iwl_free_channel_map(struct iwl_priv *priv)
1094{
1095 kfree(priv->channel_info);
1096 priv->channel_count = 0;
1097}
bf85ea4f
AK		 1098
1099/**
1100 * iwl_get_channel_info - Find driver's private channel info
1101 *
1102 * Based on band and channel number.
1103 */
82a66bbb
TW		 1104const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
1105 enum ieee80211_band band, u16 channel)
bf85ea4f
AK		 1106{
1107 int i;
1108
1109 switch (band) {
1110 case IEEE80211_BAND_5GHZ:
1111 for (i = 14; i < priv->channel_count; i++) {
1112 if (priv->channel_info[i].channel == channel)
1113 return &priv->channel_info[i];
1114 }
1115 break;
1116 case IEEE80211_BAND_2GHZ:
1117 if (channel >= 1 && channel <= 14)
1118 return &priv->channel_info[channel - 1];
1119 break;
1120 default:
1121 BUG();
1122 }
1123
1124 return NULL;
1125}
86cb3b4e
WYG		 1126
1127void iwl_rf_config(struct iwl_priv *priv)
1128{
1129 u16 radio_cfg;
1130
11483b5c 1131 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
86cb3b4e
WYG		 1132
1133 /* write radio config values to register */
1134 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
1042db2a 1135 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
86cb3b4e
WYG		 1136 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
1137 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
1138 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
1139 IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
1140 EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
1141 EEPROM_RF_CFG_STEP_MSK(radio_cfg),
1142 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
1143 } else
1144 WARN_ON(1);
1145
1146 /* set CSR_HW_CONFIG_REG for uCode use */
1042db2a 1147 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
86cb3b4e
WYG		 1148 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
1149 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
1150}
Linux kernel - Deliverables
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