[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-eeprom.h

/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *****************************************************************************/

#ifndef __iwl_eeprom_h__
#define __iwl_eeprom_h__

#include <net/mac80211.h>

struct iwl_priv;
struct iwl_shared;

/*
 * EEPROM access time values:
 *
 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
 */
#define IWL_EEPROM_ACCESS_TIMEOUT	5000 /* uSec */

#define IWL_EEPROM_SEM_TIMEOUT 		10   /* microseconds */
#define IWL_EEPROM_SEM_RETRY_LIMIT	1000 /* number of attempts (not time) */


/*
 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
 *
 * IBSS and/or AP operation is allowed *only* on those channels with
 * (VALID && IBSS && ACTIVE && !RADAR).  This restriction is in place because
 * RADAR detection is not supported by the 4965 driver, but is a
 * requirement for establishing a new network for legal operation on channels
 * requiring RADAR detection or restricting ACTIVE scanning.
 *
 * NOTE:  "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
 *        It only indicates that 20 MHz channel use is supported; HT40 channel
 *        usage is indicated by a separate set of regulatory flags for each
 *        HT40 channel pair.
 *
 * NOTE:  Using a channel inappropriately will result in a uCode error!
 */
#define IWL_NUM_TX_CALIB_GROUPS 5
enum {
	EEPROM_CHANNEL_VALID = (1 << 0),	/* usable for this SKU/geo */
	EEPROM_CHANNEL_IBSS = (1 << 1),		/* usable as an IBSS channel */
	/* Bit 2 Reserved */
	EEPROM_CHANNEL_ACTIVE = (1 << 3),	/* active scanning allowed */
	EEPROM_CHANNEL_RADAR = (1 << 4),	/* radar detection required */
	EEPROM_CHANNEL_WIDE = (1 << 5),		/* 20 MHz channel okay */
	/* Bit 6 Reserved (was Narrow Channel) */
	EEPROM_CHANNEL_DFS = (1 << 7),	/* dynamic freq selection candidate */
};

/* SKU Capabilities */
#define EEPROM_SKU_CAP_BAND_24GHZ			(1 << 4)
#define EEPROM_SKU_CAP_BAND_52GHZ			(1 << 5)
#define EEPROM_SKU_CAP_11N_ENABLE	                (1 << 6)
#define EEPROM_SKU_CAP_AMT_ENABLE			(1 << 7)
#define EEPROM_SKU_CAP_IPAN_ENABLE	                (1 << 8)

/* *regulatory* channel data format in eeprom, one for each channel.
 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
struct iwl_eeprom_channel {
	u8 flags;		/* EEPROM_CHANNEL_* flags copied from EEPROM */
	s8 max_power_avg;	/* max power (dBm) on this chnl, limit 31 */
} __packed;

enum iwl_eeprom_enhanced_txpwr_flags {
	IWL_EEPROM_ENH_TXP_FL_VALID		= BIT(0),
	IWL_EEPROM_ENH_TXP_FL_BAND_52G		= BIT(1),
	IWL_EEPROM_ENH_TXP_FL_OFDM		= BIT(2),
	IWL_EEPROM_ENH_TXP_FL_40MHZ		= BIT(3),
	IWL_EEPROM_ENH_TXP_FL_HT_AP		= BIT(4),
	IWL_EEPROM_ENH_TXP_FL_RES1		= BIT(5),
	IWL_EEPROM_ENH_TXP_FL_RES2		= BIT(6),
	IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE	= BIT(7),
};

/**
 * iwl_eeprom_enhanced_txpwr structure
 *    This structure presents the enhanced regulatory tx power limit layout
 *    in eeprom image
 *    Enhanced regulatory tx power portion of eeprom image can be broken down
 *    into individual structures; each one is 8 bytes in size and contain the
 *    following information
 * @flags: entry flags
 * @channel: channel number
 * @chain_a_max_pwr: chain a max power in 1/2 dBm
 * @chain_b_max_pwr: chain b max power in 1/2 dBm
 * @chain_c_max_pwr: chain c max power in 1/2 dBm
 * @delta_20_in_40: 20-in-40 deltas (hi/lo)
 * @mimo2_max_pwr: mimo2 max power in 1/2 dBm
 * @mimo3_max_pwr: mimo3 max power in 1/2 dBm
 *
 */
struct iwl_eeprom_enhanced_txpwr {
	u8 flags;
	u8 channel;
	s8 chain_a_max;
	s8 chain_b_max;
	s8 chain_c_max;
	u8 delta_20_in_40;
	s8 mimo2_max;
	s8 mimo3_max;
} __packed;

/* calibration */
struct iwl_eeprom_calib_hdr {
	u8 version;
	u8 pa_type;
	__le16 voltage;
} __packed;

#define EEPROM_CALIB_ALL	(INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
#define EEPROM_XTAL		((2*0x128) | EEPROM_CALIB_ALL)

/* temperature */
#define EEPROM_KELVIN_TEMPERATURE	((2*0x12A) | EEPROM_CALIB_ALL)
#define EEPROM_RAW_TEMPERATURE		((2*0x12B) | EEPROM_CALIB_ALL)


/* agn links */
#define EEPROM_LINK_HOST             (2*0x64)
#define EEPROM_LINK_GENERAL          (2*0x65)
#define EEPROM_LINK_REGULATORY       (2*0x66)
#define EEPROM_LINK_CALIBRATION      (2*0x67)
#define EEPROM_LINK_PROCESS_ADJST    (2*0x68)
#define EEPROM_LINK_OTHERS           (2*0x69)
#define EEPROM_LINK_TXP_LIMIT        (2*0x6a)
#define EEPROM_LINK_TXP_LIMIT_SIZE   (2*0x6b)

/* agn regulatory - indirect access */
#define EEPROM_REG_BAND_1_CHANNELS       ((0x08)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 28 bytes */
#define EEPROM_REG_BAND_2_CHANNELS       ((0x26)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 26 bytes */
#define EEPROM_REG_BAND_3_CHANNELS       ((0x42)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 24 bytes */
#define EEPROM_REG_BAND_4_CHANNELS       ((0x5C)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 22 bytes */
#define EEPROM_REG_BAND_5_CHANNELS       ((0x74)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 12 bytes */
#define EEPROM_REG_BAND_24_HT40_CHANNELS  ((0x82)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 14  bytes */
#define EEPROM_REG_BAND_52_HT40_CHANNELS  ((0x92)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 22  bytes */

/* 6000 regulatory - indirect access */
#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS  ((0x80)\
		| INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 14  bytes */

/* 5000 Specific */
#define EEPROM_5000_TX_POWER_VERSION    (4)
#define EEPROM_5000_EEPROM_VERSION	(0x11A)

/* 5050 Specific */
#define EEPROM_5050_TX_POWER_VERSION    (4)
#define EEPROM_5050_EEPROM_VERSION	(0x21E)

/* 1000 Specific */
#define EEPROM_1000_TX_POWER_VERSION    (4)
#define EEPROM_1000_EEPROM_VERSION	(0x15C)

/* 6x00 Specific */
#define EEPROM_6000_TX_POWER_VERSION    (4)
#define EEPROM_6000_EEPROM_VERSION	(0x423)

/* 6x50 Specific */
#define EEPROM_6050_TX_POWER_VERSION    (4)
#define EEPROM_6050_EEPROM_VERSION	(0x532)

/* 6150 Specific */
#define EEPROM_6150_TX_POWER_VERSION    (6)
#define EEPROM_6150_EEPROM_VERSION	(0x553)

/* 6x05 Specific */
#define EEPROM_6005_TX_POWER_VERSION    (6)
#define EEPROM_6005_EEPROM_VERSION	(0x709)

/* 6x30 Specific */
#define EEPROM_6030_TX_POWER_VERSION    (6)
#define EEPROM_6030_EEPROM_VERSION	(0x709)

/* 2x00 Specific */
#define EEPROM_2000_TX_POWER_VERSION    (6)
#define EEPROM_2000_EEPROM_VERSION	(0x805)

/* 6x35 Specific */
#define EEPROM_6035_TX_POWER_VERSION    (6)
#define EEPROM_6035_EEPROM_VERSION	(0x753)


/* OTP */
/* lower blocks contain EEPROM image and calibration data */
#define OTP_LOW_IMAGE_SIZE		(2 * 512 * sizeof(u16)) /* 2 KB */
/* high blocks contain PAPD data */
#define OTP_HIGH_IMAGE_SIZE_6x00        (6 * 512 * sizeof(u16)) /* 6 KB */
#define OTP_HIGH_IMAGE_SIZE_1000        (0x200 * sizeof(u16)) /* 1024 bytes */
#define OTP_MAX_LL_ITEMS_1000		(3)	/* OTP blocks for 1000 */
#define OTP_MAX_LL_ITEMS_6x00		(4)	/* OTP blocks for 6x00 */
#define OTP_MAX_LL_ITEMS_6x50		(7)	/* OTP blocks for 6x50 */
#define OTP_MAX_LL_ITEMS_2x00		(4)	/* OTP blocks for 2x00 */

/* 2.4 GHz */
extern const u8 iwl_eeprom_band_1[14];

#define ADDRESS_MSK                 0x0000FFFF
#define INDIRECT_TYPE_MSK           0x000F0000
#define INDIRECT_HOST               0x00010000
#define INDIRECT_GENERAL            0x00020000
#define INDIRECT_REGULATORY         0x00030000
#define INDIRECT_CALIBRATION        0x00040000
#define INDIRECT_PROCESS_ADJST      0x00050000
#define INDIRECT_OTHERS             0x00060000
#define INDIRECT_TXP_LIMIT          0x00070000
#define INDIRECT_TXP_LIMIT_SIZE     0x00080000
#define INDIRECT_ADDRESS            0x00100000

/* General */
#define EEPROM_DEVICE_ID                    (2*0x08)	/* 2 bytes */
#define EEPROM_SUBSYSTEM_ID		    (2*0x0A)	/* 2 bytes */
#define EEPROM_MAC_ADDRESS                  (2*0x15)	/* 6  bytes */
#define EEPROM_BOARD_REVISION               (2*0x35)	/* 2  bytes */
#define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)	/* 9  bytes */
#define EEPROM_VERSION                      (2*0x44)	/* 2  bytes */
#define EEPROM_SKU_CAP                      (2*0x45)	/* 2  bytes */
#define EEPROM_OEM_MODE                     (2*0x46)	/* 2  bytes */
#define EEPROM_RADIO_CONFIG                 (2*0x48)	/* 2  bytes */
#define EEPROM_NUM_MAC_ADDRESS              (2*0x4C)	/* 2  bytes */

/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
#define EEPROM_RF_CFG_TYPE_MSK(x)   (x & 0x3)         /* bits 0-1   */
#define EEPROM_RF_CFG_STEP_MSK(x)   ((x >> 2)  & 0x3) /* bits 2-3   */
#define EEPROM_RF_CFG_DASH_MSK(x)   ((x >> 4)  & 0x3) /* bits 4-5   */
#define EEPROM_RF_CFG_PNUM_MSK(x)   ((x >> 6)  & 0x3) /* bits 6-7   */
#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8)  & 0xF) /* bits 8-11  */
#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */

#define EEPROM_RF_CONFIG_TYPE_MAX	0x3

#define EEPROM_REGULATORY_BAND_NO_HT40			(0)

struct iwl_eeprom_ops {
	const u32 regulatory_bands[7];
	void (*update_enhanced_txpower) (struct iwl_priv *priv);
};


int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev);
void iwl_eeprom_free(struct iwl_shared *shrd);
int  iwl_eeprom_check_version(struct iwl_priv *priv);
int  iwl_eeprom_check_sku(struct iwl_priv *priv);
const u8 *iwl_eeprom_query_addr(const struct iwl_shared *shrd, size_t offset);
u16 iwl_eeprom_query16(const struct iwl_shared *shrd, size_t offset);
int iwl_init_channel_map(struct iwl_priv *priv);
void iwl_free_channel_map(struct iwl_priv *priv);
const struct iwl_channel_info *iwl_get_channel_info(
		const struct iwl_priv *priv,
		enum ieee80211_band band, u16 channel);
void iwl_rf_config(struct iwl_priv *priv);

#endif  /* __iwl_eeprom_h__ */
Commit	Line	Data
34cf6ff6 AK	1	/******************************************************************************
	2	*
	3	* This file is provided under a dual BSD/GPLv2 license. When using or
	4	* redistributing this file, you may do so under either license.
	5	*
	6	* GPL LICENSE SUMMARY
	7	*
901069c7	8	* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
34cf6ff6 AK	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of version 2 of the GNU General Public License as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	22	* USA
	23	*
	24	* The full GNU General Public License is included in this distribution
	25	* in the file called LICENSE.GPL.
	26	*
	27	* Contact Information:
759ef89f	28	* Intel Linux Wireless <ilw@linux.intel.com>
34cf6ff6 AK	29	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	30	*
	31	* BSD LICENSE
	32	*
901069c7	33	* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34cf6ff6 AK	34	* All rights reserved.
	35	*
	36	* Redistribution and use in source and binary forms, with or without
	37	* modification, are permitted provided that the following conditions
	38	* are met:
	39	*
	40	* * Redistributions of source code must retain the above copyright
	41	* notice, this list of conditions and the following disclaimer.
	42	* * Redistributions in binary form must reproduce the above copyright
	43	* notice, this list of conditions and the following disclaimer in
	44	* the documentation and/or other materials provided with the
	45	* distribution.
	46	* * Neither the name Intel Corporation nor the names of its
	47	* contributors may be used to endorse or promote products derived
	48	* from this software without specific prior written permission.
	49	*
	50	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	51	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	52	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	53	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	54	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	55	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	56	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	57	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	58	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	59	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	60	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	61	*****************************************************************************/
	62
	63	#ifndef __iwl_eeprom_h__
	64	#define __iwl_eeprom_h__
	65
be1a71a1 JB	66	#include <net/mac80211.h>
be1a71a1 JB	67
c79dd5b5	68	struct iwl_priv;
ab36eab2	69	struct iwl_shared;
34cf6ff6 AK	70
	71	/*
	72	* EEPROM access time values:
	73	*
3d5717ad	74	* Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
34cf6ff6 AK	75	* Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
	76	* When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
	77	* Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
	78	*/
	79	#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
34cf6ff6	80
3d5717ad	81	#define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
34cf6ff6 AK	82	#define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
	83
	84
	85	/*
	86	* Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
	87	*
	88	* IBSS and/or AP operation is allowed only on those channels with
	89	* (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
	90	* RADAR detection is not supported by the 4965 driver, but is a
	91	* requirement for establishing a new network for legal operation on channels
	92	* requiring RADAR detection or restricting ACTIVE scanning.
	93	*
7aafef1c WYG	94	* NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
7aafef1c WYG	95	* It only indicates that 20 MHz channel use is supported; HT40 channel
34cf6ff6	96	* usage is indicated by a separate set of regulatory flags for each
7aafef1c	97	* HT40 channel pair.
34cf6ff6 AK	98	*
	99	* NOTE: Using a channel inappropriately will result in a uCode error!
	100	*/
	101	#define IWL_NUM_TX_CALIB_GROUPS 5
	102	enum {
	103	EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
	104	EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
	105	/* Bit 2 Reserved */
	106	EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
	107	EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
	108	EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
fe7c4040	109	/* Bit 6 Reserved (was Narrow Channel) */
34cf6ff6 AK	110	EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
	111	};
	112
	113	/* SKU Capabilities */
05269297 WYG	114	#define EEPROM_SKU_CAP_BAND_24GHZ (1 << 4)
05269297 WYG	115	#define EEPROM_SKU_CAP_BAND_52GHZ (1 << 5)
21a5b3c6	116	#define EEPROM_SKU_CAP_11N_ENABLE (1 << 6)
05269297	117	#define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7)
21a5b3c6 WYG	118	#define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8)
21a5b3c6 WYG	119
34cf6ff6	120	/* regulatory channel data format in eeprom, one for each channel.
7aafef1c	121	* There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
073d3f5f	122	struct iwl_eeprom_channel {
34cf6ff6 AK	123	u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
34cf6ff6 AK	124	s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
ba2d3587	125	} __packed;
34cf6ff6	126
8d6748ca JB	127	enum iwl_eeprom_enhanced_txpwr_flags {
	128	IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
	129	IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1),
	130	IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
	131	IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3),
	132	IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4),
	133	IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5),
	134	IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6),
	135	IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7),
	136	};
	137
ab9fd1bf WYG	138	/**
	139	* iwl_eeprom_enhanced_txpwr structure
	140	* This structure presents the enhanced regulatory tx power limit layout
	141	* in eeprom image
	142	* Enhanced regulatory tx power portion of eeprom image can be broken down
	143	* into individual structures; each one is 8 bytes in size and contain the
	144	* following information
e7362a00 JB	145	* @flags: entry flags
e7362a00 JB	146	* @channel: channel number
ab9fd1bf WYG	147	* @chain_a_max_pwr: chain a max power in 1/2 dBm
	148	* @chain_b_max_pwr: chain b max power in 1/2 dBm
	149	* @chain_c_max_pwr: chain c max power in 1/2 dBm
e7362a00	150	* @delta_20_in_40: 20-in-40 deltas (hi/lo)
ab9fd1bf WYG	151	* @mimo2_max_pwr: mimo2 max power in 1/2 dBm
	152	* @mimo3_max_pwr: mimo3 max power in 1/2 dBm
	153	*
	154	*/
	155	struct iwl_eeprom_enhanced_txpwr {
e7362a00 JB	156	u8 flags;
e7362a00 JB	157	u8 channel;
ab9fd1bf WYG	158	s8 chain_a_max;
	159	s8 chain_b_max;
	160	s8 chain_c_max;
e7362a00	161	u8 delta_20_in_40;
ab9fd1bf WYG	162	s8 mimo2_max;
ab9fd1bf WYG	163	s8 mimo3_max;
ba2d3587	164	} __packed;
ab9fd1bf	165
8d8854d9	166	/* calibration */
7d8f2d50 WYG	167	struct iwl_eeprom_calib_hdr {
	168	u8 version;
	169	u8 pa_type;
	170	__le16 voltage;
	171	} __packed;
	172
7944f8e4 WYG	173	#define EEPROM_CALIB_ALL (INDIRECT_ADDRESS \| INDIRECT_CALIBRATION)
	174	#define EEPROM_XTAL ((2*0x128) \| EEPROM_CALIB_ALL)
	175
8d8854d9	176	/* temperature */
c6f30347 WYG	177	#define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) \| EEPROM_CALIB_ALL)
	178	#define EEPROM_RAW_TEMPERATURE ((2*0x12B) \| EEPROM_CALIB_ALL)
	179
7944f8e4 WYG	180
	181	/* agn links */
	182	#define EEPROM_LINK_HOST (2*0x64)
	183	#define EEPROM_LINK_GENERAL (2*0x65)
	184	#define EEPROM_LINK_REGULATORY (2*0x66)
	185	#define EEPROM_LINK_CALIBRATION (2*0x67)
	186	#define EEPROM_LINK_PROCESS_ADJST (2*0x68)
	187	#define EEPROM_LINK_OTHERS (2*0x69)
8d6748ca JB	188	#define EEPROM_LINK_TXP_LIMIT (2*0x6a)
8d6748ca JB	189	#define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
7944f8e4 WYG	190
7944f8e4 WYG	191	/* agn regulatory - indirect access */
e04ed0a5	192	#define EEPROM_REG_BAND_1_CHANNELS ((0x08)\
25ae3986	193	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 28 bytes */
e04ed0a5	194	#define EEPROM_REG_BAND_2_CHANNELS ((0x26)\
25ae3986	195	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 26 bytes */
e04ed0a5	196	#define EEPROM_REG_BAND_3_CHANNELS ((0x42)\
25ae3986	197	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 24 bytes */
e04ed0a5	198	#define EEPROM_REG_BAND_4_CHANNELS ((0x5C)\
25ae3986	199	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 22 bytes */
e04ed0a5	200	#define EEPROM_REG_BAND_5_CHANNELS ((0x74)\
25ae3986	201	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 12 bytes */
e04ed0a5	202	#define EEPROM_REG_BAND_24_HT40_CHANNELS ((0x82)\
25ae3986	203	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 14 bytes */
e04ed0a5	204	#define EEPROM_REG_BAND_52_HT40_CHANNELS ((0x92)\
25ae3986 TW	205	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 22 bytes */
25ae3986 TW	206
f2fa1b01 SZ	207	/* 6000 regulatory - indirect access */
	208	#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\
	209	\| INDIRECT_ADDRESS \| INDIRECT_REGULATORY) /* 14 bytes */
	210
109a0ac5 WYG	211	/* 5000 Specific */
	212	#define EEPROM_5000_TX_POWER_VERSION (4)
	213	#define EEPROM_5000_EEPROM_VERSION (0x11A)
	214
0ef2ca67 TW	215	/* 5050 Specific */
	216	#define EEPROM_5050_TX_POWER_VERSION (4)
	217	#define EEPROM_5050_EEPROM_VERSION (0x21E)
25ae3986	218
1f4b9665	219	/* 1000 Specific */
00e70590	220	#define EEPROM_1000_TX_POWER_VERSION (4)
72f0ebd9	221	#define EEPROM_1000_EEPROM_VERSION (0x15C)
1f4b9665	222
32b7e244	223	/* 6x00 Specific */
00e70590	224	#define EEPROM_6000_TX_POWER_VERSION (4)
3d7dc7e8	225	#define EEPROM_6000_EEPROM_VERSION (0x423)
1f4b9665	226
32b7e244	227	/* 6x50 Specific */
00e70590	228	#define EEPROM_6050_TX_POWER_VERSION (4)
32b7e244 WYG	229	#define EEPROM_6050_EEPROM_VERSION (0x532)
32b7e244 WYG	230
1956e1ad WYG	231	/* 6150 Specific */
	232	#define EEPROM_6150_TX_POWER_VERSION (6)
	233	#define EEPROM_6150_EEPROM_VERSION (0x553)
03264339	234
1956e1ad WYG	235	/* 6x05 Specific */
	236	#define EEPROM_6005_TX_POWER_VERSION (6)
	237	#define EEPROM_6005_EEPROM_VERSION (0x709)
	238
	239	/* 6x30 Specific */
	240	#define EEPROM_6030_TX_POWER_VERSION (6)
	241	#define EEPROM_6030_EEPROM_VERSION (0x709)
4b3e8062	242
fa57980e WYG	243	/* 2x00 Specific */
	244	#define EEPROM_2000_TX_POWER_VERSION (6)
	245	#define EEPROM_2000_EEPROM_VERSION (0x805)
	246
	247	/* 6x35 Specific */
	248	#define EEPROM_6035_TX_POWER_VERSION (6)
	249	#define EEPROM_6035_EEPROM_VERSION (0x753)
	250
	251
0848e297	252	/* OTP */
415e4993 WYG	253	/* lower blocks contain EEPROM image and calibration data */
	254	#define OTP_LOW_IMAGE_SIZE (2 * 512 * sizeof(u16)) /* 2 KB */
	255	/* high blocks contain PAPD data */
	256	#define OTP_HIGH_IMAGE_SIZE_6x00 (6 * 512 * sizeof(u16)) /* 6 KB */
	257	#define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */
	258	#define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
	259	#define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
	260	#define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
fa57980e	261	#define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
0848e297	262
bf85ea4f AK	263	/* 2.4 GHz */
bf85ea4f AK	264	extern const u8 iwl_eeprom_band_1[14];
34cf6ff6	265
073d3f5f TW	266	#define ADDRESS_MSK 0x0000FFFF
	267	#define INDIRECT_TYPE_MSK 0x000F0000
	268	#define INDIRECT_HOST 0x00010000
	269	#define INDIRECT_GENERAL 0x00020000
	270	#define INDIRECT_REGULATORY 0x00030000
	271	#define INDIRECT_CALIBRATION 0x00040000
	272	#define INDIRECT_PROCESS_ADJST 0x00050000
	273	#define INDIRECT_OTHERS 0x00060000
8d6748ca JB	274	#define INDIRECT_TXP_LIMIT 0x00070000
8d6748ca JB	275	#define INDIRECT_TXP_LIMIT_SIZE 0x00080000
073d3f5f TW	276	#define INDIRECT_ADDRESS 0x00100000
	277
	278	/* General */
	279	#define EEPROM_DEVICE_ID (20x08) / 2 bytes */
e1910cb3	280	#define EEPROM_SUBSYSTEM_ID (20x0A) / 2 bytes */
073d3f5f TW	281	#define EEPROM_MAC_ADDRESS (20x15) / 6 bytes */
	282	#define EEPROM_BOARD_REVISION (20x35) / 2 bytes */
	283	#define EEPROM_BOARD_PBA_NUMBER (20x3B+1) / 9 bytes */
	284	#define EEPROM_VERSION (20x44) / 2 bytes */
21a5b3c6	285	#define EEPROM_SKU_CAP (20x45) / 2 bytes */
073d3f5f	286	#define EEPROM_OEM_MODE (20x46) / 2 bytes */
694cc56d	287	#define EEPROM_RADIO_CONFIG (20x48) / 2 bytes */
c6fa17ed	288	#define EEPROM_NUM_MAC_ADDRESS (20x4C) / 2 bytes */
34cf6ff6	289
694cc56d TW	290	/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
	291	#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
	292	#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
	293	#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
	294	#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
	295	#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
	296	#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
	297
9371d4ed	298	#define EEPROM_RF_CONFIG_TYPE_MAX 0x3
694cc56d	299
7aafef1c	300	#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
a89d03c4	301
34cf6ff6	302	struct iwl_eeprom_ops {
073d3f5f	303	const u32 regulatory_bands[7];
ab9fd1bf	304	void (update_enhanced_txpower) (struct iwl_priv priv);
34cf6ff6 AK	305	};
	306
	307
e98a1302	308	int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev);
ab36eab2	309	void iwl_eeprom_free(struct iwl_shared *shrd);
8614f360	310	int iwl_eeprom_check_version(struct iwl_priv *priv);
21a5b3c6	311	int iwl_eeprom_check_sku(struct iwl_priv *priv);
ab36eab2 DF	312	const u8 iwl_eeprom_query_addr(const struct iwl_shared shrd, size_t offset);
ab36eab2 DF	313	u16 iwl_eeprom_query16(const struct iwl_shared *shrd, size_t offset);
bf85ea4f AK	314	int iwl_init_channel_map(struct iwl_priv *priv);
bf85ea4f AK	315	void iwl_free_channel_map(struct iwl_priv *priv);
8622e705	316	const struct iwl_channel_info *iwl_get_channel_info(
bf85ea4f AK	317	const struct iwl_priv *priv,
bf85ea4f AK	318	enum ieee80211_band band, u16 channel);
86cb3b4e	319	void iwl_rf_config(struct iwl_priv *priv);
bf85ea4f	320
34cf6ff6	321	#endif /* __iwl_eeprom_h__ */