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edf38334 DF |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. |
96c285da | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
edf38334 DF |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
edf38334 DF |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
96c285da | 35 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
edf38334 DF |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | *****************************************************************************/ | |
64 | ||
3995deaf JB |
65 | #ifndef __iwl_fw_file_h__ |
66 | #define __iwl_fw_file_h__ | |
edf38334 | 67 | |
b1c23d9e | 68 | #include <linux/netdevice.h> |
d2709ad7 | 69 | #include <linux/nl80211.h> |
b1c23d9e | 70 | |
edf38334 DF |
71 | /* v1/v2 uCode file layout */ |
72 | struct iwl_ucode_header { | |
73 | __le32 ver; /* major/minor/API/serial */ | |
74 | union { | |
75 | struct { | |
76 | __le32 inst_size; /* bytes of runtime code */ | |
77 | __le32 data_size; /* bytes of runtime data */ | |
78 | __le32 init_size; /* bytes of init code */ | |
79 | __le32 init_data_size; /* bytes of init data */ | |
80 | __le32 boot_size; /* bytes of bootstrap code */ | |
81 | u8 data[0]; /* in same order as sizes */ | |
82 | } v1; | |
83 | struct { | |
84 | __le32 build; /* build number */ | |
85 | __le32 inst_size; /* bytes of runtime code */ | |
86 | __le32 data_size; /* bytes of runtime data */ | |
87 | __le32 init_size; /* bytes of init code */ | |
88 | __le32 init_data_size; /* bytes of init data */ | |
89 | __le32 boot_size; /* bytes of bootstrap code */ | |
90 | u8 data[0]; /* in same order as sizes */ | |
91 | } v2; | |
92 | } u; | |
93 | }; | |
94 | ||
95 | /* | |
96 | * new TLV uCode file layout | |
97 | * | |
98 | * The new TLV file format contains TLVs, that each specify | |
0479c19d | 99 | * some piece of data. |
edf38334 DF |
100 | */ |
101 | ||
102 | enum iwl_ucode_tlv_type { | |
103 | IWL_UCODE_TLV_INVALID = 0, /* unused */ | |
104 | IWL_UCODE_TLV_INST = 1, | |
105 | IWL_UCODE_TLV_DATA = 2, | |
106 | IWL_UCODE_TLV_INIT = 3, | |
107 | IWL_UCODE_TLV_INIT_DATA = 4, | |
108 | IWL_UCODE_TLV_BOOT = 5, | |
109 | IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */ | |
110 | IWL_UCODE_TLV_PAN = 7, | |
111 | IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8, | |
112 | IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, | |
113 | IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10, | |
114 | IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11, | |
115 | IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12, | |
116 | IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13, | |
117 | IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14, | |
118 | IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, | |
119 | IWL_UCODE_TLV_WOWLAN_INST = 16, | |
120 | IWL_UCODE_TLV_WOWLAN_DATA = 17, | |
121 | IWL_UCODE_TLV_FLAGS = 18, | |
ed8c8365 DS |
122 | IWL_UCODE_TLV_SEC_RT = 19, |
123 | IWL_UCODE_TLV_SEC_INIT = 20, | |
124 | IWL_UCODE_TLV_SEC_WOWLAN = 21, | |
125 | IWL_UCODE_TLV_DEF_CALIB = 22, | |
126 | IWL_UCODE_TLV_PHY_SKU = 23, | |
e2d6f4e7 EH |
127 | IWL_UCODE_TLV_SECURE_SEC_RT = 24, |
128 | IWL_UCODE_TLV_SECURE_SEC_INIT = 25, | |
129 | IWL_UCODE_TLV_SECURE_SEC_WOWLAN = 26, | |
130 | IWL_UCODE_TLV_NUM_OF_CPU = 27, | |
e36e5433 | 131 | IWL_UCODE_TLV_CSCHEME = 28, |
a2978b11 EH |
132 | IWL_UCODE_TLV_API_CHANGES_SET = 29, |
133 | IWL_UCODE_TLV_ENABLED_CAPABILITIES = 30, | |
762533ba | 134 | IWL_UCODE_TLV_N_SCAN_CHANNELS = 31, |
61df750c | 135 | IWL_UCODE_TLV_SEC_RT_USNIFFER = 34, |
b4821767 | 136 | IWL_UCODE_TLV_SDIO_ADMA_ADDR = 35, |
7e1223b5 | 137 | IWL_UCODE_TLV_FW_VERSION = 36, |
490fefeb LK |
138 | IWL_UCODE_TLV_FW_DBG_DEST = 38, |
139 | IWL_UCODE_TLV_FW_DBG_CONF = 39, | |
d2709ad7 | 140 | IWL_UCODE_TLV_FW_DBG_TRIGGER = 40, |
edf38334 DF |
141 | }; |
142 | ||
edf38334 | 143 | struct iwl_ucode_tlv { |
0479c19d | 144 | __le32 type; /* see above */ |
edf38334 DF |
145 | __le32 length; /* not including type/length fields */ |
146 | u8 data[0]; | |
147 | }; | |
148 | ||
06ddbf5a EG |
149 | #define IWL_TLV_UCODE_MAGIC 0x0a4c5749 |
150 | #define FW_VER_HUMAN_READABLE_SZ 64 | |
edf38334 DF |
151 | |
152 | struct iwl_tlv_ucode_header { | |
153 | /* | |
154 | * The TLV style ucode header is distinguished from | |
155 | * the v1/v2 style header by first four bytes being | |
156 | * zero, as such is an invalid combination of | |
157 | * major/minor/API/serial versions. | |
158 | */ | |
159 | __le32 zero; | |
160 | __le32 magic; | |
06ddbf5a | 161 | u8 human_readable[FW_VER_HUMAN_READABLE_SZ]; |
7e1223b5 EG |
162 | /* major/minor/API/serial or major in new format */ |
163 | __le32 ver; | |
edf38334 | 164 | __le32 build; |
0479c19d | 165 | __le64 ignore; |
edf38334 DF |
166 | /* |
167 | * The data contained herein has a TLV layout, | |
168 | * see above for the TLV header and types. | |
169 | * Note that each TLV is padded to a length | |
170 | * that is a multiple of 4 for alignment. | |
171 | */ | |
172 | u8 data[0]; | |
173 | }; | |
174 | ||
a2978b11 EH |
175 | /* |
176 | * ucode TLVs | |
177 | * | |
178 | * ability to get extension for: flags & capabilities from ucode binaries files | |
179 | */ | |
180 | struct iwl_ucode_api { | |
181 | __le32 api_index; | |
182 | __le32 api_flags; | |
183 | } __packed; | |
184 | ||
185 | struct iwl_ucode_capa { | |
186 | __le32 api_index; | |
187 | __le32 api_capa; | |
188 | } __packed; | |
189 | ||
a52703b2 JB |
190 | /** |
191 | * enum iwl_ucode_tlv_flag - ucode API flags | |
192 | * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously | |
193 | * was a separate TLV but moved here to save space. | |
0d365ae5 | 194 | * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behavior on hidden SSID, |
a52703b2 JB |
195 | * treats good CRC threshold as a boolean |
196 | * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). | |
197 | * @IWL_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. | |
198 | * @IWL_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS | |
199 | * @IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT: This uCode image supports uAPSD | |
200 | * @IWL_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan | |
201 | * offload profile config command. | |
202 | * @IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six | |
203 | * (rather than two) IPv6 addresses | |
204 | * @IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element | |
205 | * from the probe request template. | |
206 | * @IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) | |
207 | * @IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) | |
208 | * @IWL_UCODE_TLV_FLAGS_P2P_PM: P2P client supports PM as a stand alone MAC | |
209 | * @IWL_UCODE_TLV_FLAGS_P2P_BSS_PS_DCM: support power save on BSS station and | |
210 | * P2P client interfaces simultaneously if they are in different bindings. | |
211 | * @IWL_UCODE_TLV_FLAGS_P2P_BSS_PS_SCM: support power save on BSS station and | |
212 | * P2P client interfaces simultaneously if they are in same bindings. | |
213 | * @IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD | |
214 | * @IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save | |
215 | * @IWL_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. | |
216 | * @IWL_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients | |
217 | * @IWL_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. | |
218 | */ | |
219 | enum iwl_ucode_tlv_flag { | |
220 | IWL_UCODE_TLV_FLAGS_PAN = BIT(0), | |
221 | IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1), | |
222 | IWL_UCODE_TLV_FLAGS_MFP = BIT(2), | |
223 | IWL_UCODE_TLV_FLAGS_P2P = BIT(3), | |
224 | IWL_UCODE_TLV_FLAGS_DW_BC_TABLE = BIT(4), | |
225 | IWL_UCODE_TLV_FLAGS_SHORT_BL = BIT(7), | |
226 | IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = BIT(10), | |
227 | IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID = BIT(12), | |
228 | IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = BIT(15), | |
229 | IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = BIT(16), | |
230 | IWL_UCODE_TLV_FLAGS_P2P_PM = BIT(21), | |
231 | IWL_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = BIT(22), | |
232 | IWL_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = BIT(23), | |
233 | IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT = BIT(24), | |
234 | IWL_UCODE_TLV_FLAGS_EBS_SUPPORT = BIT(25), | |
235 | IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD = BIT(26), | |
236 | IWL_UCODE_TLV_FLAGS_BCAST_FILTERING = BIT(29), | |
237 | IWL_UCODE_TLV_FLAGS_GO_UAPSD = BIT(30), | |
238 | }; | |
239 | ||
859d914c JB |
240 | typedef unsigned int __bitwise__ iwl_ucode_tlv_api_t; |
241 | ||
a52703b2 JB |
242 | /** |
243 | * enum iwl_ucode_tlv_api - ucode api | |
a52703b2 | 244 | * @IWL_UCODE_TLV_API_BT_COEX_SPLIT: new API for BT Coex |
a52703b2 JB |
245 | * @IWL_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time |
246 | * longer than the passive one, which is essential for fragmented scan. | |
8ba2d7a1 | 247 | * @IWL_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. |
84bfffa9 | 248 | * IWL_UCODE_TLV_API_HDC_PHASE_0: ucode supports finer configuration of LTR |
d44c3fe6 | 249 | * @IWL_UCODE_TLV_API_TX_POWER_DEV: new API for tx power. |
ab02165c | 250 | * @IWL_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header |
0294d9ee EG |
251 | * @IWL_UCODE_TLV_API_SCD_CFG: This firmware can configure the scheduler |
252 | * through the dedicated host command. | |
1f9c418f | 253 | * @IWL_UCODE_TLV_API_SINGLE_SCAN_EBS: EBS is supported for single scans too. |
57d7b6a4 | 254 | * @IWL_UCODE_TLV_API_ASYNC_DTM: Async temperature notifications are supported. |
c5d679a5 | 255 | * @IWL_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params |
777c9b6b | 256 | * @IWL_UCODE_TLV_API_STATS_V10: uCode supports/uses statistics API version 10 |
7e1223b5 | 257 | * @IWL_UCODE_TLV_API_NEW_VERSION: new versioning format |
d7afbfc4 AS |
258 | * @IWL_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority |
259 | * instead of 3. | |
a52703b2 JB |
260 | */ |
261 | enum iwl_ucode_tlv_api { | |
859d914c JB |
262 | IWL_UCODE_TLV_API_BT_COEX_SPLIT = (__force iwl_ucode_tlv_api_t)3, |
263 | IWL_UCODE_TLV_API_FRAGMENTED_SCAN = (__force iwl_ucode_tlv_api_t)8, | |
264 | IWL_UCODE_TLV_API_WIFI_MCC_UPDATE = (__force iwl_ucode_tlv_api_t)9, | |
265 | IWL_UCODE_TLV_API_HDC_PHASE_0 = (__force iwl_ucode_tlv_api_t)10, | |
266 | IWL_UCODE_TLV_API_TX_POWER_DEV = (__force iwl_ucode_tlv_api_t)11, | |
ab02165c | 267 | IWL_UCODE_TLV_API_WIDE_CMD_HDR = (__force iwl_ucode_tlv_api_t)14, |
859d914c JB |
268 | IWL_UCODE_TLV_API_SCD_CFG = (__force iwl_ucode_tlv_api_t)15, |
269 | IWL_UCODE_TLV_API_SINGLE_SCAN_EBS = (__force iwl_ucode_tlv_api_t)16, | |
270 | IWL_UCODE_TLV_API_ASYNC_DTM = (__force iwl_ucode_tlv_api_t)17, | |
271 | IWL_UCODE_TLV_API_LQ_SS_PARAMS = (__force iwl_ucode_tlv_api_t)18, | |
272 | IWL_UCODE_TLV_API_STATS_V10 = (__force iwl_ucode_tlv_api_t)19, | |
273 | IWL_UCODE_TLV_API_NEW_VERSION = (__force iwl_ucode_tlv_api_t)20, | |
274 | IWL_UCODE_TLV_API_EXT_SCAN_PRIORITY = (__force iwl_ucode_tlv_api_t)24, | |
a52703b2 JB |
275 | }; |
276 | ||
859d914c JB |
277 | typedef unsigned int __bitwise__ iwl_ucode_tlv_capa_t; |
278 | ||
a52703b2 JB |
279 | /** |
280 | * enum iwl_ucode_tlv_capa - ucode capabilities | |
281 | * @IWL_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 | |
282 | * @IWL_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory | |
283 | * @IWL_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. | |
3d44eebf | 284 | * @IWL_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer |
ce792918 | 285 | * @IWL_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) |
a52703b2 JB |
286 | * @IWL_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality |
287 | * @IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current | |
288 | * tx power value into TPC Report action frame and Link Measurement Report | |
289 | * action frame | |
290 | * @IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current | |
291 | * channel in DS parameter set element in probe requests. | |
292 | * @IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in | |
293 | * probe requests. | |
294 | * @IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests | |
295 | * @IWL_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), | |
296 | * which also implies support for the scheduler configuration command | |
297 | * @IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching | |
298 | * @IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command | |
0becb377 | 299 | * @IWL_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command |
93190fb0 | 300 | * @IWL_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload |
91a8bcde | 301 | * @IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics |
0522588d | 302 | * @IWL_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running |
4d165d12 AN |
303 | * @IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different |
304 | * sources for the MCC. This TLV bit is a future replacement to | |
305 | * IWL_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR | |
306 | * is supported. | |
70e90992 | 307 | * @IWL_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC |
a52703b2 JB |
308 | */ |
309 | enum iwl_ucode_tlv_capa { | |
859d914c JB |
310 | IWL_UCODE_TLV_CAPA_D0I3_SUPPORT = (__force iwl_ucode_tlv_capa_t)0, |
311 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT = (__force iwl_ucode_tlv_capa_t)1, | |
312 | IWL_UCODE_TLV_CAPA_UMAC_SCAN = (__force iwl_ucode_tlv_capa_t)2, | |
313 | IWL_UCODE_TLV_CAPA_BEAMFORMER = (__force iwl_ucode_tlv_capa_t)3, | |
ce792918 | 314 | IWL_UCODE_TLV_CAPA_TOF_SUPPORT = (__force iwl_ucode_tlv_capa_t)5, |
859d914c JB |
315 | IWL_UCODE_TLV_CAPA_TDLS_SUPPORT = (__force iwl_ucode_tlv_capa_t)6, |
316 | IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = (__force iwl_ucode_tlv_capa_t)8, | |
317 | IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = (__force iwl_ucode_tlv_capa_t)9, | |
318 | IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = (__force iwl_ucode_tlv_capa_t)10, | |
319 | IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = (__force iwl_ucode_tlv_capa_t)11, | |
320 | IWL_UCODE_TLV_CAPA_DQA_SUPPORT = (__force iwl_ucode_tlv_capa_t)12, | |
321 | IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = (__force iwl_ucode_tlv_capa_t)13, | |
322 | IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = (__force iwl_ucode_tlv_capa_t)18, | |
0becb377 | 323 | IWL_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = (__force iwl_ucode_tlv_capa_t)19, |
93190fb0 | 324 | IWL_UCODE_TLV_CAPA_CSUM_SUPPORT = (__force iwl_ucode_tlv_capa_t)21, |
859d914c JB |
325 | IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS = (__force iwl_ucode_tlv_capa_t)22, |
326 | IWL_UCODE_TLV_CAPA_BT_COEX_PLCR = (__force iwl_ucode_tlv_capa_t)28, | |
327 | IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC = (__force iwl_ucode_tlv_capa_t)29, | |
328 | IWL_UCODE_TLV_CAPA_BT_COEX_RRC = (__force iwl_ucode_tlv_capa_t)30, | |
a52703b2 JB |
329 | }; |
330 | ||
331 | /* The default calibrate table size if not specified by firmware file */ | |
332 | #define IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 | |
333 | #define IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 | |
334 | #define IWL_MAX_PHY_CALIBRATE_TBL_SIZE 253 | |
335 | ||
336 | /* The default max probe length if not specified by the firmware file */ | |
337 | #define IWL_DEFAULT_MAX_PROBE_LENGTH 200 | |
338 | ||
859d914c JB |
339 | #define IWL_API_MAX_BITS 64 |
340 | #define IWL_CAPABILITIES_MAX_BITS 64 | |
341 | ||
a52703b2 JB |
342 | /* |
343 | * For 16.0 uCode and above, there is no differentiation between sections, | |
344 | * just an offset to the HW address. | |
345 | */ | |
346 | #define IWL_UCODE_SECTION_MAX 12 | |
a52703b2 JB |
347 | #define CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC |
348 | ||
349 | /* uCode version contains 4 values: Major/Minor/API/Serial */ | |
350 | #define IWL_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) | |
351 | #define IWL_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) | |
352 | #define IWL_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) | |
353 | #define IWL_UCODE_SERIAL(ver) ((ver) & 0x000000FF) | |
354 | ||
355 | /* | |
356 | * Calibration control struct. | |
357 | * Sent as part of the phy configuration command. | |
358 | * @flow_trigger: bitmap for which calibrations to perform according to | |
359 | * flow triggers. | |
360 | * @event_trigger: bitmap for which calibrations to perform according to | |
361 | * event triggers. | |
362 | */ | |
363 | struct iwl_tlv_calib_ctrl { | |
364 | __le32 flow_trigger; | |
365 | __le32 event_trigger; | |
366 | } __packed; | |
367 | ||
368 | enum iwl_fw_phy_cfg { | |
369 | FW_PHY_CFG_RADIO_TYPE_POS = 0, | |
370 | FW_PHY_CFG_RADIO_TYPE = 0x3 << FW_PHY_CFG_RADIO_TYPE_POS, | |
371 | FW_PHY_CFG_RADIO_STEP_POS = 2, | |
372 | FW_PHY_CFG_RADIO_STEP = 0x3 << FW_PHY_CFG_RADIO_STEP_POS, | |
373 | FW_PHY_CFG_RADIO_DASH_POS = 4, | |
374 | FW_PHY_CFG_RADIO_DASH = 0x3 << FW_PHY_CFG_RADIO_DASH_POS, | |
375 | FW_PHY_CFG_TX_CHAIN_POS = 16, | |
376 | FW_PHY_CFG_TX_CHAIN = 0xf << FW_PHY_CFG_TX_CHAIN_POS, | |
377 | FW_PHY_CFG_RX_CHAIN_POS = 20, | |
378 | FW_PHY_CFG_RX_CHAIN = 0xf << FW_PHY_CFG_RX_CHAIN_POS, | |
379 | }; | |
380 | ||
381 | #define IWL_UCODE_MAX_CS 1 | |
382 | ||
383 | /** | |
384 | * struct iwl_fw_cipher_scheme - a cipher scheme supported by FW. | |
385 | * @cipher: a cipher suite selector | |
386 | * @flags: cipher scheme flags (currently reserved for a future use) | |
387 | * @hdr_len: a size of MPDU security header | |
388 | * @pn_len: a size of PN | |
389 | * @pn_off: an offset of pn from the beginning of the security header | |
390 | * @key_idx_off: an offset of key index byte in the security header | |
391 | * @key_idx_mask: a bit mask of key_idx bits | |
392 | * @key_idx_shift: bit shift needed to get key_idx | |
393 | * @mic_len: mic length in bytes | |
394 | * @hw_cipher: a HW cipher index used in host commands | |
395 | */ | |
396 | struct iwl_fw_cipher_scheme { | |
397 | __le32 cipher; | |
398 | u8 flags; | |
399 | u8 hdr_len; | |
400 | u8 pn_len; | |
401 | u8 pn_off; | |
402 | u8 key_idx_off; | |
403 | u8 key_idx_mask; | |
404 | u8 key_idx_shift; | |
405 | u8 mic_len; | |
406 | u8 hw_cipher; | |
407 | } __packed; | |
408 | ||
490fefeb LK |
409 | enum iwl_fw_dbg_reg_operator { |
410 | CSR_ASSIGN, | |
411 | CSR_SETBIT, | |
412 | CSR_CLEARBIT, | |
413 | ||
414 | PRPH_ASSIGN, | |
415 | PRPH_SETBIT, | |
416 | PRPH_CLEARBIT, | |
869f3b15 HD |
417 | |
418 | INDIRECT_ASSIGN, | |
419 | INDIRECT_SETBIT, | |
420 | INDIRECT_CLEARBIT, | |
421 | ||
422 | PRPH_BLOCKBIT, | |
490fefeb LK |
423 | }; |
424 | ||
425 | /** | |
426 | * struct iwl_fw_dbg_reg_op - an operation on a register | |
427 | * | |
428 | * @op: %enum iwl_fw_dbg_reg_operator | |
429 | * @addr: offset of the register | |
430 | * @val: value | |
431 | */ | |
432 | struct iwl_fw_dbg_reg_op { | |
433 | u8 op; | |
434 | u8 reserved[3]; | |
435 | __le32 addr; | |
436 | __le32 val; | |
437 | } __packed; | |
438 | ||
439 | /** | |
440 | * enum iwl_fw_dbg_monitor_mode - available monitor recording modes | |
441 | * | |
442 | * @SMEM_MODE: monitor stores the data in SMEM | |
443 | * @EXTERNAL_MODE: monitor stores the data in allocated DRAM | |
444 | * @MARBH_MODE: monitor stores the data in MARBH buffer | |
6a8ac59c | 445 | * @MIPI_MODE: monitor outputs the data through the MIPI interface |
490fefeb LK |
446 | */ |
447 | enum iwl_fw_dbg_monitor_mode { | |
448 | SMEM_MODE = 0, | |
449 | EXTERNAL_MODE = 1, | |
450 | MARBH_MODE = 2, | |
6a8ac59c | 451 | MIPI_MODE = 3, |
490fefeb LK |
452 | }; |
453 | ||
454 | /** | |
455 | * struct iwl_fw_dbg_dest_tlv - configures the destination of the debug data | |
456 | * | |
457 | * @version: version of the TLV - currently 0 | |
458 | * @monitor_mode: %enum iwl_fw_dbg_monitor_mode | |
96c285da | 459 | * @size_power: buffer size will be 2^(size_power + 11) |
490fefeb LK |
460 | * @base_reg: addr of the base addr register (PRPH) |
461 | * @end_reg: addr of the end addr register (PRPH) | |
462 | * @write_ptr_reg: the addr of the reg of the write pointer | |
463 | * @wrap_count: the addr of the reg of the wrap_count | |
464 | * @base_shift: shift right of the base addr reg | |
465 | * @end_shift: shift right of the end addr reg | |
466 | * @reg_ops: array of registers operations | |
467 | * | |
468 | * This parses IWL_UCODE_TLV_FW_DBG_DEST | |
469 | */ | |
470 | struct iwl_fw_dbg_dest_tlv { | |
471 | u8 version; | |
472 | u8 monitor_mode; | |
96c285da EG |
473 | u8 size_power; |
474 | u8 reserved; | |
490fefeb LK |
475 | __le32 base_reg; |
476 | __le32 end_reg; | |
477 | __le32 write_ptr_reg; | |
478 | __le32 wrap_count; | |
479 | u8 base_shift; | |
480 | u8 end_shift; | |
481 | struct iwl_fw_dbg_reg_op reg_ops[0]; | |
482 | } __packed; | |
483 | ||
484 | struct iwl_fw_dbg_conf_hcmd { | |
485 | u8 id; | |
486 | u8 reserved; | |
487 | __le16 len; | |
488 | u8 data[0]; | |
489 | } __packed; | |
490 | ||
491 | /** | |
d2709ad7 | 492 | * enum iwl_fw_dbg_trigger_mode - triggers functionalities |
490fefeb | 493 | * |
d2709ad7 EG |
494 | * @IWL_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism |
495 | * @IWL_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data | |
490fefeb | 496 | */ |
d2709ad7 EG |
497 | enum iwl_fw_dbg_trigger_mode { |
498 | IWL_FW_DBG_TRIGGER_START = BIT(0), | |
499 | IWL_FW_DBG_TRIGGER_STOP = BIT(1), | |
500 | }; | |
490fefeb LK |
501 | |
502 | /** | |
d2709ad7 EG |
503 | * enum iwl_fw_dbg_trigger_vif_type - define the VIF type for a trigger |
504 | * @IWL_FW_DBG_CONF_VIF_ANY: any vif type | |
505 | * @IWL_FW_DBG_CONF_VIF_IBSS: IBSS mode | |
506 | * @IWL_FW_DBG_CONF_VIF_STATION: BSS mode | |
507 | * @IWL_FW_DBG_CONF_VIF_AP: AP mode | |
508 | * @IWL_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode | |
509 | * @IWL_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode | |
510 | * @IWL_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device | |
490fefeb | 511 | */ |
d2709ad7 EG |
512 | enum iwl_fw_dbg_trigger_vif_type { |
513 | IWL_FW_DBG_CONF_VIF_ANY = NL80211_IFTYPE_UNSPECIFIED, | |
514 | IWL_FW_DBG_CONF_VIF_IBSS = NL80211_IFTYPE_ADHOC, | |
515 | IWL_FW_DBG_CONF_VIF_STATION = NL80211_IFTYPE_STATION, | |
516 | IWL_FW_DBG_CONF_VIF_AP = NL80211_IFTYPE_AP, | |
517 | IWL_FW_DBG_CONF_VIF_P2P_CLIENT = NL80211_IFTYPE_P2P_CLIENT, | |
518 | IWL_FW_DBG_CONF_VIF_P2P_GO = NL80211_IFTYPE_P2P_GO, | |
519 | IWL_FW_DBG_CONF_VIF_P2P_DEVICE = NL80211_IFTYPE_P2P_DEVICE, | |
490fefeb LK |
520 | }; |
521 | ||
522 | /** | |
d2709ad7 EG |
523 | * struct iwl_fw_dbg_trigger_tlv - a TLV that describes the trigger |
524 | * @id: %enum iwl_fw_dbg_trigger | |
525 | * @vif_type: %enum iwl_fw_dbg_trigger_vif_type | |
526 | * @stop_conf_ids: bitmap of configurations this trigger relates to. | |
527 | * if the mode is %IWL_FW_DBG_TRIGGER_STOP, then if the bit corresponding | |
528 | * to the currently running configuration is set, the data should be | |
529 | * collected. | |
530 | * @stop_delay: how many milliseconds to wait before collecting the data | |
531 | * after the STOP trigger fires. | |
532 | * @mode: %enum iwl_fw_dbg_trigger_mode - can be stop / start of both | |
533 | * @start_conf_id: if mode is %IWL_FW_DBG_TRIGGER_START, this defines what | |
534 | * configuration should be applied when the triggers kicks in. | |
535 | * @occurrences: number of occurrences. 0 means the trigger will never fire. | |
536 | */ | |
537 | struct iwl_fw_dbg_trigger_tlv { | |
538 | __le32 id; | |
539 | __le32 vif_type; | |
540 | __le32 stop_conf_ids; | |
541 | __le32 stop_delay; | |
542 | u8 mode; | |
543 | u8 start_conf_id; | |
544 | __le16 occurrences; | |
545 | __le32 reserved[2]; | |
546 | ||
547 | u8 data[0]; | |
548 | } __packed; | |
549 | ||
550 | #define FW_DBG_START_FROM_ALIVE 0 | |
551 | #define FW_DBG_CONF_MAX 32 | |
552 | #define FW_DBG_INVALID 0xff | |
553 | ||
9d761fd8 EG |
554 | /** |
555 | * struct iwl_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons | |
556 | * @stop_consec_missed_bcon: stop recording if threshold is crossed. | |
557 | * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed. | |
558 | * @start_consec_missed_bcon: start recording if threshold is crossed. | |
559 | * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed. | |
560 | * @reserved1: reserved | |
561 | * @reserved2: reserved | |
562 | */ | |
563 | struct iwl_fw_dbg_trigger_missed_bcon { | |
564 | __le32 stop_consec_missed_bcon; | |
565 | __le32 stop_consec_missed_bcon_since_rx; | |
566 | __le32 reserved2[2]; | |
567 | __le32 start_consec_missed_bcon; | |
568 | __le32 start_consec_missed_bcon_since_rx; | |
569 | __le32 reserved1[2]; | |
570 | } __packed; | |
571 | ||
917f39bb EG |
572 | /** |
573 | * struct iwl_fw_dbg_trigger_cmd - configures trigger for messages from FW. | |
574 | * cmds: the list of commands to trigger the collection on | |
575 | */ | |
576 | struct iwl_fw_dbg_trigger_cmd { | |
577 | struct cmd { | |
578 | u8 cmd_id; | |
579 | u8 group_id; | |
580 | } __packed cmds[16]; | |
581 | } __packed; | |
582 | ||
5a756c20 EG |
583 | /** |
584 | * iwl_fw_dbg_trigger_stats - configures trigger for statistics | |
585 | * @stop_offset: the offset of the value to be monitored | |
586 | * @stop_threshold: the threshold above which to collect | |
587 | * @start_offset: the offset of the value to be monitored | |
588 | * @start_threshold: the threshold above which to start recording | |
589 | */ | |
590 | struct iwl_fw_dbg_trigger_stats { | |
591 | __le32 stop_offset; | |
592 | __le32 stop_threshold; | |
593 | __le32 start_offset; | |
594 | __le32 start_threshold; | |
595 | } __packed; | |
596 | ||
3ec50b5e EG |
597 | /** |
598 | * struct iwl_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI | |
599 | * @rssi: RSSI value to trigger at | |
600 | */ | |
601 | struct iwl_fw_dbg_trigger_low_rssi { | |
602 | __le32 rssi; | |
603 | } __packed; | |
604 | ||
d42f5350 EG |
605 | /** |
606 | * struct iwl_fw_dbg_trigger_mlme - configures trigger for mlme events | |
607 | * @stop_auth_denied: number of denied authentication to collect | |
608 | * @stop_auth_timeout: number of authentication timeout to collect | |
609 | * @stop_rx_deauth: number of Rx deauth before to collect | |
610 | * @stop_tx_deauth: number of Tx deauth before to collect | |
611 | * @stop_assoc_denied: number of denied association to collect | |
612 | * @stop_assoc_timeout: number of association timeout to collect | |
31755207 | 613 | * @stop_connection_loss: number of connection loss to collect |
d42f5350 EG |
614 | * @start_auth_denied: number of denied authentication to start recording |
615 | * @start_auth_timeout: number of authentication timeout to start recording | |
616 | * @start_rx_deauth: number of Rx deauth to start recording | |
617 | * @start_tx_deauth: number of Tx deauth to start recording | |
618 | * @start_assoc_denied: number of denied association to start recording | |
619 | * @start_assoc_timeout: number of association timeout to start recording | |
31755207 | 620 | * @start_connection_loss: number of connection loss to start recording |
d42f5350 EG |
621 | */ |
622 | struct iwl_fw_dbg_trigger_mlme { | |
623 | u8 stop_auth_denied; | |
624 | u8 stop_auth_timeout; | |
625 | u8 stop_rx_deauth; | |
626 | u8 stop_tx_deauth; | |
627 | ||
628 | u8 stop_assoc_denied; | |
629 | u8 stop_assoc_timeout; | |
31755207 EG |
630 | u8 stop_connection_loss; |
631 | u8 reserved; | |
d42f5350 EG |
632 | |
633 | u8 start_auth_denied; | |
634 | u8 start_auth_timeout; | |
635 | u8 start_rx_deauth; | |
636 | u8 start_tx_deauth; | |
637 | ||
638 | u8 start_assoc_denied; | |
639 | u8 start_assoc_timeout; | |
31755207 EG |
640 | u8 start_connection_loss; |
641 | u8 reserved2; | |
d42f5350 EG |
642 | } __packed; |
643 | ||
5d42e7b2 EG |
644 | /** |
645 | * struct iwl_fw_dbg_trigger_txq_timer - configures the Tx queue's timer | |
646 | * @command_queue: timeout for the command queue in ms | |
647 | * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms | |
648 | * @softap: timeout for the queues of a softAP in ms | |
649 | * @p2p_go: timeout for the queues of a P2P GO in ms | |
650 | * @p2p_client: timeout for the queues of a P2P client in ms | |
651 | * @p2p_device: timeout for the queues of a P2P device in ms | |
652 | * @ibss: timeout for the queues of an IBSS in ms | |
653 | * @tdls: timeout for the queues of a TDLS station in ms | |
654 | */ | |
655 | struct iwl_fw_dbg_trigger_txq_timer { | |
656 | __le32 command_queue; | |
657 | __le32 bss; | |
658 | __le32 softap; | |
659 | __le32 p2p_go; | |
660 | __le32 p2p_client; | |
661 | __le32 p2p_device; | |
662 | __le32 ibss; | |
663 | __le32 tdls; | |
664 | __le32 reserved[4]; | |
665 | } __packed; | |
666 | ||
874c174e EG |
667 | /** |
668 | * struct iwl_fw_dbg_trigger_time_event - configures a time event trigger | |
669 | * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a | |
670 | * trigger each time a time event notification that relates to time event | |
671 | * id with one of the actions in the bitmap is received and | |
672 | * BIT(notif->status) is set in status_bitmap. | |
673 | * | |
674 | */ | |
675 | struct iwl_fw_dbg_trigger_time_event { | |
676 | struct { | |
677 | __le32 id; | |
678 | __le32 action_bitmap; | |
679 | __le32 status_bitmap; | |
680 | } __packed time_events[16]; | |
681 | } __packed; | |
682 | ||
4203263d EG |
683 | /** |
684 | * struct iwl_fw_dbg_trigger_ba - configures BlockAck related trigger | |
685 | * rx_ba_start: tid bitmap to configure on what tid the trigger should occur | |
686 | * when an Rx BlockAck session is started. | |
687 | * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur | |
688 | * when an Rx BlockAck session is stopped. | |
689 | * tx_ba_start: tid bitmap to configure on what tid the trigger should occur | |
690 | * when a Tx BlockAck session is started. | |
691 | * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur | |
692 | * when a Tx BlockAck session is stopped. | |
693 | * rx_bar: tid bitmap to configure on what tid the trigger should occur | |
694 | * when a BAR is received (for a Tx BlockAck session). | |
695 | * tx_bar: tid bitmap to configure on what tid the trigger should occur | |
696 | * when a BAR is send (for an Rx BlocAck session). | |
697 | * frame_timeout: tid bitmap to configure on what tid the trigger should occur | |
698 | * when a frame times out in the reodering buffer. | |
699 | */ | |
700 | struct iwl_fw_dbg_trigger_ba { | |
701 | __le16 rx_ba_start; | |
702 | __le16 rx_ba_stop; | |
703 | __le16 tx_ba_start; | |
704 | __le16 tx_ba_stop; | |
705 | __le16 rx_bar; | |
706 | __le16 tx_bar; | |
707 | __le16 frame_timeout; | |
708 | } __packed; | |
709 | ||
d2709ad7 EG |
710 | /** |
711 | * struct iwl_fw_dbg_conf_tlv - a TLV that describes a debug configuration. | |
712 | * @id: conf id | |
490fefeb LK |
713 | * @usniffer: should the uSniffer image be used |
714 | * @num_of_hcmds: how many HCMDs to send are present here | |
715 | * @hcmd: a variable length host command to be sent to apply the configuration. | |
716 | * If there is more than one HCMD to send, they will appear one after the | |
717 | * other and be sent in the order that they appear in. | |
d2709ad7 EG |
718 | * This parses IWL_UCODE_TLV_FW_DBG_CONF. The user can add up-to |
719 | * %FW_DBG_CONF_MAX configuration per run. | |
490fefeb LK |
720 | */ |
721 | struct iwl_fw_dbg_conf_tlv { | |
722 | u8 id; | |
723 | u8 usniffer; | |
724 | u8 reserved; | |
725 | u8 num_of_hcmds; | |
726 | struct iwl_fw_dbg_conf_hcmd hcmd; | |
490fefeb LK |
727 | } __packed; |
728 | ||
3995deaf | 729 | #endif /* __iwl_fw_file_h__ */ |