Commit | Line | Data |
---|---|---|
b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #ifndef __iwl_helpers_h__ | |
31 | #define __iwl_helpers_h__ | |
32 | ||
33 | #include <linux/ctype.h> | |
a1175124 JB |
34 | #include <net/mac80211.h> |
35 | ||
36 | #include "iwl-io.h" | |
b481de9c | 37 | |
da1bc453 TW |
38 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
39 | ||
b481de9c | 40 | |
b481de9c ZY |
41 | static inline struct ieee80211_conf *ieee80211_get_hw_conf( |
42 | struct ieee80211_hw *hw) | |
43 | { | |
44 | return &hw->conf; | |
45 | } | |
46 | ||
b481de9c ZY |
47 | static inline unsigned long elapsed_jiffies(unsigned long start, |
48 | unsigned long end) | |
49 | { | |
9e7d1a44 | 50 | if (end >= start) |
b481de9c ZY |
51 | return end - start; |
52 | ||
9e7d1a44 | 53 | return end + (MAX_JIFFY_OFFSET - start) + 1; |
b481de9c ZY |
54 | } |
55 | ||
c54b679d TW |
56 | /** |
57 | * iwl_queue_inc_wrap - increment queue index, wrap back to beginning | |
58 | * @index -- current index | |
59 | * @n_bd -- total number of entries in queue (must be power of 2) | |
60 | */ | |
61 | static inline int iwl_queue_inc_wrap(int index, int n_bd) | |
62 | { | |
63 | return ++index & (n_bd - 1); | |
64 | } | |
65 | ||
66 | /** | |
67 | * iwl_queue_dec_wrap - decrement queue index, wrap back to end | |
68 | * @index -- current index | |
69 | * @n_bd -- total number of entries in queue (must be power of 2) | |
70 | */ | |
71 | static inline int iwl_queue_dec_wrap(int index, int n_bd) | |
72 | { | |
73 | return --index & (n_bd - 1); | |
74 | } | |
75 | ||
98c92211 TW |
76 | /* TODO: Move fw_desc functions to iwl-pci.ko */ |
77 | static inline void iwl_free_fw_desc(struct pci_dev *pci_dev, | |
78 | struct fw_desc *desc) | |
79 | { | |
80 | if (desc->v_addr) | |
f36d04ab SG |
81 | dma_free_coherent(&pci_dev->dev, desc->len, |
82 | desc->v_addr, desc->p_addr); | |
98c92211 TW |
83 | desc->v_addr = NULL; |
84 | desc->len = 0; | |
85 | } | |
86 | ||
87 | static inline int iwl_alloc_fw_desc(struct pci_dev *pci_dev, | |
88 | struct fw_desc *desc) | |
89 | { | |
c9696b2b JB |
90 | if (!desc->len) { |
91 | desc->v_addr = NULL; | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
f36d04ab SG |
95 | desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len, |
96 | &desc->p_addr, GFP_KERNEL); | |
98c92211 TW |
97 | return (desc->v_addr != NULL) ? 0 : -ENOMEM; |
98 | } | |
99 | ||
e4e72fb4 JB |
100 | /* |
101 | * we have 8 bits used like this: | |
102 | * | |
103 | * 7 6 5 4 3 2 1 0 | |
104 | * | | | | | | | | | |
105 | * | | | | | | +-+-------- AC queue (0-3) | |
106 | * | | | | | | | |
107 | * | +-+-+-+-+------------ HW A-MPDU queue | |
108 | * | | |
109 | * +---------------------- indicates agg queue | |
110 | */ | |
111 | static inline u8 iwl_virtual_agg_queue_num(u8 ac, u8 hwq) | |
112 | { | |
113 | BUG_ON(ac > 3); /* only have 2 bits */ | |
114 | BUG_ON(hwq > 31); /* only have 5 bits */ | |
115 | ||
116 | return 0x80 | (hwq << 2) | ac; | |
117 | } | |
118 | ||
549a04e0 JB |
119 | static inline void iwl_wake_queue(struct iwl_priv *priv, |
120 | struct iwl_tx_queue *txq) | |
e4e72fb4 | 121 | { |
549a04e0 | 122 | u8 queue = txq->swq_id; |
e4e72fb4 JB |
123 | u8 ac = queue; |
124 | u8 hwq = queue; | |
125 | ||
126 | if (queue & 0x80) { | |
127 | ac = queue & 3; | |
128 | hwq = (queue >> 2) & 0x1f; | |
129 | } | |
130 | ||
131 | if (test_and_clear_bit(hwq, priv->queue_stopped)) | |
132 | if (atomic_dec_return(&priv->queue_stop_count[ac]) <= 0) | |
133 | ieee80211_wake_queue(priv->hw, ac); | |
134 | } | |
135 | ||
549a04e0 JB |
136 | static inline void iwl_stop_queue(struct iwl_priv *priv, |
137 | struct iwl_tx_queue *txq) | |
e4e72fb4 | 138 | { |
549a04e0 | 139 | u8 queue = txq->swq_id; |
e4e72fb4 JB |
140 | u8 ac = queue; |
141 | u8 hwq = queue; | |
142 | ||
143 | if (queue & 0x80) { | |
144 | ac = queue & 3; | |
145 | hwq = (queue >> 2) & 0x1f; | |
146 | } | |
147 | ||
148 | if (!test_and_set_bit(hwq, priv->queue_stopped)) | |
149 | if (atomic_inc_return(&priv->queue_stop_count[ac]) > 0) | |
150 | ieee80211_stop_queue(priv->hw, ac); | |
151 | } | |
152 | ||
153 | #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue | |
154 | #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue | |
155 | ||
30a12a8f WYG |
156 | static inline void iwl_disable_interrupts(struct iwl_priv *priv) |
157 | { | |
158 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
159 | ||
160 | /* disable interrupts from uCode/NIC to host */ | |
161 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
162 | ||
163 | /* acknowledge/clear/reset any interrupts still pending | |
164 | * from uCode or flow handler (Rx/Tx DMA) */ | |
165 | iwl_write32(priv, CSR_INT, 0xffffffff); | |
166 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
167 | IWL_DEBUG_ISR(priv, "Disabled interrupts\n"); | |
168 | } | |
169 | ||
170 | static inline void iwl_enable_interrupts(struct iwl_priv *priv) | |
171 | { | |
172 | IWL_DEBUG_ISR(priv, "Enabling interrupts\n"); | |
173 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
174 | iwl_write32(priv, CSR_INT_MASK, priv->inta_mask); | |
175 | } | |
176 | ||
a0ee74cf WYG |
177 | /** |
178 | * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time | |
179 | * @priv -- pointer to iwl_priv data structure | |
180 | * @tsf_bits -- number of bits need to shift for masking) | |
181 | */ | |
182 | static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv, | |
183 | u16 tsf_bits) | |
184 | { | |
185 | return (1 << tsf_bits) - 1; | |
186 | } | |
187 | ||
188 | /** | |
189 | * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time | |
190 | * @priv -- pointer to iwl_priv data structure | |
191 | * @tsf_bits -- number of bits need to shift for masking) | |
192 | */ | |
193 | static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv, | |
194 | u16 tsf_bits) | |
195 | { | |
196 | return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; | |
197 | } | |
198 | ||
b481de9c | 199 | #endif /* __iwl_helpers_h__ */ |