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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #ifndef __iwl_helpers_h__ | |
31 | #define __iwl_helpers_h__ | |
32 | ||
33 | #include <linux/ctype.h> | |
a1175124 JB |
34 | #include <net/mac80211.h> |
35 | ||
36 | #include "iwl-io.h" | |
b481de9c | 37 | |
da1bc453 TW |
38 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
39 | ||
b481de9c | 40 | |
b481de9c ZY |
41 | static inline struct ieee80211_conf *ieee80211_get_hw_conf( |
42 | struct ieee80211_hw *hw) | |
43 | { | |
44 | return &hw->conf; | |
45 | } | |
46 | ||
c54b679d TW |
47 | /** |
48 | * iwl_queue_inc_wrap - increment queue index, wrap back to beginning | |
49 | * @index -- current index | |
50 | * @n_bd -- total number of entries in queue (must be power of 2) | |
51 | */ | |
52 | static inline int iwl_queue_inc_wrap(int index, int n_bd) | |
53 | { | |
54 | return ++index & (n_bd - 1); | |
55 | } | |
56 | ||
57 | /** | |
58 | * iwl_queue_dec_wrap - decrement queue index, wrap back to end | |
59 | * @index -- current index | |
60 | * @n_bd -- total number of entries in queue (must be power of 2) | |
61 | */ | |
62 | static inline int iwl_queue_dec_wrap(int index, int n_bd) | |
63 | { | |
64 | return --index & (n_bd - 1); | |
65 | } | |
66 | ||
e4e72fb4 JB |
67 | /* |
68 | * we have 8 bits used like this: | |
69 | * | |
70 | * 7 6 5 4 3 2 1 0 | |
71 | * | | | | | | | | | |
72 | * | | | | | | +-+-------- AC queue (0-3) | |
73 | * | | | | | | | |
ea9b307f | 74 | * | +-+-+-+-+------------ HW queue ID |
e4e72fb4 | 75 | * | |
ea9b307f | 76 | * +---------------------- unused |
e4e72fb4 | 77 | */ |
ea9b307f | 78 | static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq) |
e4e72fb4 JB |
79 | { |
80 | BUG_ON(ac > 3); /* only have 2 bits */ | |
ea9b307f | 81 | BUG_ON(hwq > 31); /* only use 5 bits */ |
e4e72fb4 | 82 | |
ea9b307f | 83 | txq->swq_id = (hwq << 2) | ac; |
e4e72fb4 JB |
84 | } |
85 | ||
549a04e0 JB |
86 | static inline void iwl_wake_queue(struct iwl_priv *priv, |
87 | struct iwl_tx_queue *txq) | |
e4e72fb4 | 88 | { |
549a04e0 | 89 | u8 queue = txq->swq_id; |
ea9b307f JB |
90 | u8 ac = queue & 3; |
91 | u8 hwq = (queue >> 2) & 0x1f; | |
e4e72fb4 JB |
92 | |
93 | if (test_and_clear_bit(hwq, priv->queue_stopped)) | |
94 | if (atomic_dec_return(&priv->queue_stop_count[ac]) <= 0) | |
95 | ieee80211_wake_queue(priv->hw, ac); | |
96 | } | |
97 | ||
549a04e0 JB |
98 | static inline void iwl_stop_queue(struct iwl_priv *priv, |
99 | struct iwl_tx_queue *txq) | |
e4e72fb4 | 100 | { |
549a04e0 | 101 | u8 queue = txq->swq_id; |
ea9b307f JB |
102 | u8 ac = queue & 3; |
103 | u8 hwq = (queue >> 2) & 0x1f; | |
e4e72fb4 JB |
104 | |
105 | if (!test_and_set_bit(hwq, priv->queue_stopped)) | |
106 | if (atomic_inc_return(&priv->queue_stop_count[ac]) > 0) | |
107 | ieee80211_stop_queue(priv->hw, ac); | |
108 | } | |
109 | ||
68b99311 GT |
110 | static inline void iwl_wake_any_queue(struct iwl_priv *priv, |
111 | struct iwl_rxon_context *ctx) | |
112 | { | |
113 | u8 ac; | |
114 | ||
115 | for (ac = 0; ac < AC_NUM; ac++) { | |
116 | IWL_DEBUG_INFO(priv, "Queue Status: Q[%d] %s\n", | |
117 | ac, (atomic_read(&priv->queue_stop_count[ac]) > 0) | |
118 | ? "stopped" : "awake"); | |
119 | iwl_wake_queue(priv, &priv->txq[ctx->ac_to_queue[ac]]); | |
120 | } | |
121 | } | |
122 | ||
47751b0f KV |
123 | #ifdef ieee80211_stop_queue |
124 | #undef ieee80211_stop_queue | |
125 | #endif | |
126 | ||
e4e72fb4 | 127 | #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue |
47751b0f KV |
128 | |
129 | #ifdef ieee80211_wake_queue | |
130 | #undef ieee80211_wake_queue | |
131 | #endif | |
132 | ||
e4e72fb4 JB |
133 | #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue |
134 | ||
30a12a8f WYG |
135 | static inline void iwl_disable_interrupts(struct iwl_priv *priv) |
136 | { | |
63013ae3 | 137 | clear_bit(STATUS_INT_ENABLED, &priv->shrd->status); |
30a12a8f WYG |
138 | |
139 | /* disable interrupts from uCode/NIC to host */ | |
140 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
141 | ||
142 | /* acknowledge/clear/reset any interrupts still pending | |
143 | * from uCode or flow handler (Rx/Tx DMA) */ | |
144 | iwl_write32(priv, CSR_INT, 0xffffffff); | |
145 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
146 | IWL_DEBUG_ISR(priv, "Disabled interrupts\n"); | |
147 | } | |
148 | ||
554d1d02 SG |
149 | static inline void iwl_enable_rfkill_int(struct iwl_priv *priv) |
150 | { | |
151 | IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n"); | |
152 | iwl_write32(priv, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); | |
153 | } | |
154 | ||
30a12a8f WYG |
155 | static inline void iwl_enable_interrupts(struct iwl_priv *priv) |
156 | { | |
157 | IWL_DEBUG_ISR(priv, "Enabling interrupts\n"); | |
63013ae3 | 158 | set_bit(STATUS_INT_ENABLED, &priv->shrd->status); |
30a12a8f WYG |
159 | iwl_write32(priv, CSR_INT_MASK, priv->inta_mask); |
160 | } | |
161 | ||
a0ee74cf WYG |
162 | /** |
163 | * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time | |
164 | * @priv -- pointer to iwl_priv data structure | |
165 | * @tsf_bits -- number of bits need to shift for masking) | |
166 | */ | |
167 | static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv, | |
168 | u16 tsf_bits) | |
169 | { | |
170 | return (1 << tsf_bits) - 1; | |
171 | } | |
172 | ||
173 | /** | |
174 | * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time | |
175 | * @priv -- pointer to iwl_priv data structure | |
176 | * @tsf_bits -- number of bits need to shift for masking) | |
177 | */ | |
178 | static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv, | |
179 | u16 tsf_bits) | |
180 | { | |
181 | return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; | |
182 | } | |
183 | ||
b481de9c | 184 | #endif /* __iwl_helpers_h__ */ |