[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-io.c

/******************************************************************************
 *
 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

#include "iwl-io.h"

#define IWL_POLL_INTERVAL 10	/* microseconds */

static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
	iwl_write32(priv, reg, iwl_read32(priv, reg) | mask);
}

static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
	iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask);
}

void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	__iwl_set_bit(priv, reg, mask);
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	__iwl_clear_bit(priv, reg, mask);
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
		 u32 bits, u32 mask, int timeout)
{
	int t = 0;

	do {
		if ((iwl_read32(priv, addr) & mask) == (bits & mask))
			return t;
		udelay(IWL_POLL_INTERVAL);
		t += IWL_POLL_INTERVAL;
	} while (t < timeout);

	return -ETIMEDOUT;
}

int iwl_grab_nic_access_silent(struct iwl_priv *priv)
{
	int ret;

	lockdep_assert_held(&priv->reg_lock);

	/* this bit wakes up the NIC */
	__iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);

	/*
	 * These bits say the device is running, and should keep running for
	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	 * but they do not indicate that embedded SRAM is restored yet;
	 * 3945 and 4965 have volatile SRAM, and must save/restore contents
	 * to/from host DRAM when sleeping/waking for power-saving.
	 * Each direction takes approximately 1/4 millisecond; with this
	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	 * series of register accesses are expected (e.g. reading Event Log),
	 * to keep device from sleeping.
	 *
	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	 * SRAM is okay/restored.  We don't check that here because this call
	 * is just for hardware register access; but GP1 MAC_SLEEP check is a
	 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	 *
	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
	 * and do not save/restore SRAM when power cycling.
	 */
	ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
			   (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
			    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	if (ret < 0) {
		iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
		return -EIO;
	}

	return 0;
}

int iwl_grab_nic_access(struct iwl_priv *priv)
{
	int ret = iwl_grab_nic_access_silent(priv);
	if (ret) {
		u32 val = iwl_read32(priv, CSR_GP_CNTRL);
		IWL_ERR(priv,
			"MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
	}

	return ret;
}

void iwl_release_nic_access(struct iwl_priv *priv)
{
	lockdep_assert_held(&priv->reg_lock);
	__iwl_clear_bit(priv, CSR_GP_CNTRL,
			CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
}

u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
{
	u32 value;
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	iwl_grab_nic_access(priv);
	value = iwl_read32(priv, reg);
	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->reg_lock, flags);

	return value;
}

void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	if (!iwl_grab_nic_access(priv)) {
		iwl_write32(priv, reg, value);
		iwl_release_nic_access(priv);
	}
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
			int timeout)
{
	int t = 0;

	do {
		if ((iwl_read_direct32(priv, addr) & mask) == mask)
			return t;
		udelay(IWL_POLL_INTERVAL);
		t += IWL_POLL_INTERVAL;
	} while (t < timeout);

	return -ETIMEDOUT;
}

static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg)
{
	iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
	rmb();
	return iwl_read32(priv, HBUS_TARG_PRPH_RDAT);
}

static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
{
	iwl_write32(priv, HBUS_TARG_PRPH_WADDR,
		    ((addr & 0x0000FFFF) | (3 << 24)));
	wmb();
	iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val);
}

u32 iwl_read_prph(struct iwl_priv *priv, u32 reg)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&priv->reg_lock, flags);
	iwl_grab_nic_access(priv);
	val = __iwl_read_prph(priv, reg);
	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->reg_lock, flags);
	return val;
}

void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	if (!iwl_grab_nic_access(priv)) {
		__iwl_write_prph(priv, addr, val);
		iwl_release_nic_access(priv);
	}
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	iwl_grab_nic_access(priv);
	__iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) | mask);
	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
			    u32 bits, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	iwl_grab_nic_access(priv);
	__iwl_write_prph(priv, reg,
			 (__iwl_read_prph(priv, reg) & mask) | bits);
	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&priv->reg_lock, flags);
	iwl_grab_nic_access(priv);
	val = __iwl_read_prph(priv, reg);
	__iwl_write_prph(priv, reg, (val & ~mask));
	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr,
			      void *buf, int words)
{
	unsigned long flags;
	int offs;
	u32 *vals = buf;

	spin_lock_irqsave(&priv->reg_lock, flags);
	iwl_grab_nic_access(priv);

	iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr);
	rmb();

	for (offs = 0; offs < words; offs++)
		vals[offs] = iwl_read32(priv, HBUS_TARG_MEM_RDAT);

	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}

u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
{
	u32 value;

	_iwl_read_targ_mem_words(priv, addr, &value, 1);

	return value;
}

void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->reg_lock, flags);
	if (!iwl_grab_nic_access(priv)) {
		iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr);
		wmb();
		iwl_write32(priv, HBUS_TARG_MEM_WDAT, val);
		iwl_release_nic_access(priv);
	}
	spin_unlock_irqrestore(&priv->reg_lock, flags);
}
Commit	Line	Data
02a7fa00 JB	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
	4	*
	5	* Portions of this file are derived from the ipw3945 project.
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of version 2 of the GNU General Public License as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	19	*
	20	* The full GNU General Public License is included in this distribution in the
	21	* file called LICENSE.
	22	*
	23	* Contact Information:
	24	* Intel Linux Wireless <ilw@linux.intel.com>
	25	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26	*
	27	*****************************************************************************/
	28
	29	#include "iwl-io.h"
	30
	31	#define IWL_POLL_INTERVAL 10 /* microseconds */
	32
	33	static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
	34	{
	35	iwl_write32(priv, reg, iwl_read32(priv, reg) \| mask);
	36	}
	37
	38	static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
	39	{
	40	iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask);
	41	}
	42
	43	void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
	44	{
	45	unsigned long flags;
	46
	47	spin_lock_irqsave(&priv->reg_lock, flags);
	48	__iwl_set_bit(priv, reg, mask);
	49	spin_unlock_irqrestore(&priv->reg_lock, flags);
	50	}
	51
	52	void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
	53	{
	54	unsigned long flags;
	55
	56	spin_lock_irqsave(&priv->reg_lock, flags);
	57	__iwl_clear_bit(priv, reg, mask);
	58	spin_unlock_irqrestore(&priv->reg_lock, flags);
	59	}
	60
	61	int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
	62	u32 bits, u32 mask, int timeout)
	63	{
	64	int t = 0;
65
66	do {
67	if ((iwl_read32(priv, addr) & mask) == (bits & mask))
68	return t;
69	udelay(IWL_POLL_INTERVAL);
70	t += IWL_POLL_INTERVAL;
71	} while (t < timeout);
72
73	return -ETIMEDOUT;
74	}
75
4119904f	76	int iwl_grab_nic_access_silent(struct iwl_priv *priv)
02a7fa00 JB	77	{
02a7fa00 JB	78	int ret;
02a7fa00 JB	79
	80	lockdep_assert_held(&priv->reg_lock);
	81
	82	/* this bit wakes up the NIC */
	83	__iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	84
	85	/*
	86	* These bits say the device is running, and should keep running for
	87	* at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	88	* but they do not indicate that embedded SRAM is restored yet;
	89	* 3945 and 4965 have volatile SRAM, and must save/restore contents
	90	* to/from host DRAM when sleeping/waking for power-saving.
	91	* Each direction takes approximately 1/4 millisecond; with this
	92	* overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	93	* series of register accesses are expected (e.g. reading Event Log),
	94	* to keep device from sleeping.
	95	*
	96	* CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	97	* SRAM is okay/restored. We don't check that here because this call
	98	* is just for hardware register access; but GP1 MAC_SLEEP check is a
	99	* good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	100	*
	101	* 5000 series and later (including 1000 series) have non-volatile SRAM,
	102	* and do not save/restore SRAM when power cycling.
	103	*/
	104	ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
	105	CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
	106	(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY \|
	107	CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	108	if (ret < 0) {
02a7fa00 JB	109	iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
	110	return -EIO;
	111	}
	112
	113	return 0;
	114	}
	115
4119904f JB	116	int iwl_grab_nic_access(struct iwl_priv *priv)
	117	{
	118	int ret = iwl_grab_nic_access_silent(priv);
	119	if (ret) {
	120	u32 val = iwl_read32(priv, CSR_GP_CNTRL);
	121	IWL_ERR(priv,
	122	"MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
	123	}
	124
	125	return ret;
	126	}
	127
02a7fa00 JB	128	void iwl_release_nic_access(struct iwl_priv *priv)
	129	{
	130	lockdep_assert_held(&priv->reg_lock);
	131	__iwl_clear_bit(priv, CSR_GP_CNTRL,
	132	CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	133	}
	134
	135	u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
	136	{
	137	u32 value;
	138	unsigned long flags;
	139
	140	spin_lock_irqsave(&priv->reg_lock, flags);
	141	iwl_grab_nic_access(priv);
	142	value = iwl_read32(priv, reg);
	143	iwl_release_nic_access(priv);
	144	spin_unlock_irqrestore(&priv->reg_lock, flags);
	145
	146	return value;
	147	}
	148
	149	void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value)
	150	{
	151	unsigned long flags;
	152
	153	spin_lock_irqsave(&priv->reg_lock, flags);
	154	if (!iwl_grab_nic_access(priv)) {
	155	iwl_write32(priv, reg, value);
	156	iwl_release_nic_access(priv);
	157	}
	158	spin_unlock_irqrestore(&priv->reg_lock, flags);
	159	}
	160
	161	int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
	162	int timeout)
	163	{
	164	int t = 0;
	165
	166	do {
	167	if ((iwl_read_direct32(priv, addr) & mask) == mask)
	168	return t;
	169	udelay(IWL_POLL_INTERVAL);
	170	t += IWL_POLL_INTERVAL;
	171	} while (t < timeout);
	172
	173	return -ETIMEDOUT;
	174	}
	175
	176	static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg)
	177	{
	178	iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg \| (3 << 24));
	179	rmb();
	180	return iwl_read32(priv, HBUS_TARG_PRPH_RDAT);
	181	}
	182
	183	static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
	184	{
	185	iwl_write32(priv, HBUS_TARG_PRPH_WADDR,
	186	((addr & 0x0000FFFF) \| (3 << 24)));
	187	wmb();
	188	iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val);
	189	}
	190
	191	u32 iwl_read_prph(struct iwl_priv *priv, u32 reg)
192	{
193	unsigned long flags;
194	u32 val;
195
196	spin_lock_irqsave(&priv->reg_lock, flags);
197	iwl_grab_nic_access(priv);
198	val = __iwl_read_prph(priv, reg);
199	iwl_release_nic_access(priv);
200	spin_unlock_irqrestore(&priv->reg_lock, flags);
201	return val;
202	}
203
204	void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
205	{
206	unsigned long flags;
207
208	spin_lock_irqsave(&priv->reg_lock, flags);
209	if (!iwl_grab_nic_access(priv)) {
210	__iwl_write_prph(priv, addr, val);
211	iwl_release_nic_access(priv);
212	}
213	spin_unlock_irqrestore(&priv->reg_lock, flags);
214	}
215
216	void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
217	{
218	unsigned long flags;
219
220	spin_lock_irqsave(&priv->reg_lock, flags);
221	iwl_grab_nic_access(priv);
222	__iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) \| mask);
223	iwl_release_nic_access(priv);
224	spin_unlock_irqrestore(&priv->reg_lock, flags);
225	}
226
227	void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
228	u32 bits, u32 mask)
229	{
230	unsigned long flags;
231
232	spin_lock_irqsave(&priv->reg_lock, flags);
233	iwl_grab_nic_access(priv);
234	__iwl_write_prph(priv, reg,
235	(__iwl_read_prph(priv, reg) & mask) \| bits);
236	iwl_release_nic_access(priv);
237	spin_unlock_irqrestore(&priv->reg_lock, flags);
238	}
239
240	void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
241	{
242	unsigned long flags;
243	u32 val;
244
245	spin_lock_irqsave(&priv->reg_lock, flags);
246	iwl_grab_nic_access(priv);
247	val = __iwl_read_prph(priv, reg);
248	__iwl_write_prph(priv, reg, (val & ~mask));
249	iwl_release_nic_access(priv);
250	spin_unlock_irqrestore(&priv->reg_lock, flags);
251	}
252
e46f6538 JB	253	void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr,
e46f6538 JB	254	void *buf, int words)
02a7fa00 JB	255	{
02a7fa00 JB	256	unsigned long flags;
e46f6538 JB	257	int offs;
e46f6538 JB	258	u32 *vals = buf;
02a7fa00 JB	259
	260	spin_lock_irqsave(&priv->reg_lock, flags);
	261	iwl_grab_nic_access(priv);
	262
	263	iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr);
	264	rmb();
e46f6538 JB	265
	266	for (offs = 0; offs < words; offs++)
	267	vals[offs] = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
02a7fa00 JB	268
	269	iwl_release_nic_access(priv);
	270	spin_unlock_irqrestore(&priv->reg_lock, flags);
e46f6538 JB	271	}
	272
	273	u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
	274	{
	275	u32 value;
	276
	277	_iwl_read_targ_mem_words(priv, addr, &value, 1);
	278
02a7fa00 JB	279	return value;
	280	}
	281
	282	void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
	283	{
	284	unsigned long flags;
	285
	286	spin_lock_irqsave(&priv->reg_lock, flags);
	287	if (!iwl_grab_nic_access(priv)) {
	288	iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr);
	289	wmb();
	290	iwl_write32(priv, HBUS_TARG_MEM_WDAT, val);
	291	iwl_release_nic_access(priv);
	292	}
	293	spin_unlock_irqrestore(&priv->reg_lock, flags);
	294	}