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b1e1adfa JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. |
b1e1adfa JB |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
b1e1adfa JB |
26 | * |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
51368bf7 | 33 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
b1e1adfa JB |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | *****************************************************************************/ | |
62 | #include <linux/types.h> | |
63 | #include <linux/slab.h> | |
64 | #include <linux/export.h> | |
9f32e017 | 65 | #include <linux/etherdevice.h> |
1e0b393a | 66 | #include <linux/pci.h> |
48e29340 | 67 | #include "iwl-drv.h" |
b1e1adfa JB |
68 | #include "iwl-modparams.h" |
69 | #include "iwl-nvm-parse.h" | |
70 | ||
71 | /* NVM offsets (in words) definitions */ | |
72 | enum wkp_nvm_offsets { | |
73 | /* NVM HW-Section offset (in words) definitions */ | |
74 | HW_ADDR = 0x15, | |
75 | ||
77db0a3c | 76 | /* NVM SW-Section offset (in words) definitions */ |
b1e1adfa JB |
77 | NVM_SW_SECTION = 0x1C0, |
78 | NVM_VERSION = 0, | |
79 | RADIO_CFG = 1, | |
80 | SKU = 2, | |
81 | N_HW_ADDRS = 3, | |
82 | NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, | |
83 | ||
77db0a3c | 84 | /* NVM calibration section offset (in words) definitions */ |
b1e1adfa JB |
85 | NVM_CALIB_SECTION = 0x2B8, |
86 | XTAL_CALIB = 0x316 - NVM_CALIB_SECTION | |
87 | }; | |
88 | ||
77db0a3c EH |
89 | enum family_8000_nvm_offsets { |
90 | /* NVM HW-Section offset (in words) definitions */ | |
1e0b393a EH |
91 | HW_ADDR0_WFPM_FAMILY_8000 = 0x12, |
92 | HW_ADDR1_WFPM_FAMILY_8000 = 0x16, | |
93 | HW_ADDR0_PCIE_FAMILY_8000 = 0x8A, | |
94 | HW_ADDR1_PCIE_FAMILY_8000 = 0x8E, | |
77db0a3c EH |
95 | MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1, |
96 | ||
97 | /* NVM SW-Section offset (in words) definitions */ | |
98 | NVM_SW_SECTION_FAMILY_8000 = 0x1C0, | |
99 | NVM_VERSION_FAMILY_8000 = 0, | |
100 | RADIO_CFG_FAMILY_8000 = 2, | |
101 | SKU_FAMILY_8000 = 4, | |
102 | N_HW_ADDRS_FAMILY_8000 = 5, | |
103 | ||
104 | /* NVM REGULATORY -Section offset (in words) definitions */ | |
105 | NVM_CHANNELS_FAMILY_8000 = 0, | |
106 | ||
107 | /* NVM calibration section offset (in words) definitions */ | |
108 | NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8, | |
109 | XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000 | |
110 | }; | |
111 | ||
b1e1adfa JB |
112 | /* SKU Capabilities (actual values from NVM definition) */ |
113 | enum nvm_sku_bits { | |
114 | NVM_SKU_CAP_BAND_24GHZ = BIT(0), | |
115 | NVM_SKU_CAP_BAND_52GHZ = BIT(1), | |
116 | NVM_SKU_CAP_11N_ENABLE = BIT(2), | |
bfc824b0 | 117 | NVM_SKU_CAP_11AC_ENABLE = BIT(3), |
b1e1adfa JB |
118 | }; |
119 | ||
b1e1adfa JB |
120 | /* |
121 | * These are the channel numbers in the order that they are stored in the NVM | |
122 | */ | |
123 | static const u8 iwl_nvm_channels[] = { | |
124 | /* 2.4 GHz */ | |
125 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
126 | /* 5 GHz */ | |
127 | 36, 40, 44 , 48, 52, 56, 60, 64, | |
128 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, | |
129 | 149, 153, 157, 161, 165 | |
130 | }; | |
131 | ||
77db0a3c EH |
132 | static const u8 iwl_nvm_channels_family_8000[] = { |
133 | /* 2.4 GHz */ | |
9b1c9a66 | 134 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, |
77db0a3c EH |
135 | /* 5 GHz */ |
136 | 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, | |
137 | 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, | |
138 | 149, 153, 157, 161, 165, 169, 173, 177, 181 | |
139 | }; | |
140 | ||
749f1fe1 | 141 | #define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) |
77db0a3c | 142 | #define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000) |
749f1fe1 | 143 | #define NUM_2GHZ_CHANNELS 14 |
9b1c9a66 | 144 | #define NUM_2GHZ_CHANNELS_FAMILY_8000 14 |
749f1fe1 EH |
145 | #define FIRST_2GHZ_HT_MINUS 5 |
146 | #define LAST_2GHZ_HT_PLUS 9 | |
147 | #define LAST_5GHZ_HT 161 | |
b1e1adfa | 148 | |
88f2fd73 | 149 | #define DEFAULT_MAX_TX_POWER 16 |
b1e1adfa JB |
150 | |
151 | /* rate data (static) */ | |
152 | static struct ieee80211_rate iwl_cfg80211_rates[] = { | |
153 | { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, | |
154 | { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, | |
155 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
156 | { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, | |
157 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
158 | { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, | |
159 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
160 | { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, | |
161 | { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, | |
162 | { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, | |
163 | { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, | |
164 | { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, | |
165 | { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, | |
166 | { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, | |
167 | { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, | |
168 | }; | |
169 | #define RATES_24_OFFS 0 | |
170 | #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) | |
171 | #define RATES_52_OFFS 4 | |
172 | #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) | |
173 | ||
174 | /** | |
175 | * enum iwl_nvm_channel_flags - channel flags in NVM | |
176 | * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo | |
177 | * @NVM_CHANNEL_IBSS: usable as an IBSS channel | |
178 | * @NVM_CHANNEL_ACTIVE: active scanning allowed | |
179 | * @NVM_CHANNEL_RADAR: radar detection required | |
9ee6dace DS |
180 | * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed |
181 | * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS | |
182 | * on same channel on 2.4 or same UNII band on 5.2 | |
b1e1adfa JB |
183 | * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?) |
184 | * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) | |
33158fef EL |
185 | * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) |
186 | * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) | |
b1e1adfa JB |
187 | */ |
188 | enum iwl_nvm_channel_flags { | |
189 | NVM_CHANNEL_VALID = BIT(0), | |
190 | NVM_CHANNEL_IBSS = BIT(1), | |
191 | NVM_CHANNEL_ACTIVE = BIT(3), | |
192 | NVM_CHANNEL_RADAR = BIT(4), | |
9ee6dace DS |
193 | NVM_CHANNEL_INDOOR_ONLY = BIT(5), |
194 | NVM_CHANNEL_GO_CONCURRENT = BIT(6), | |
b1e1adfa JB |
195 | NVM_CHANNEL_WIDE = BIT(8), |
196 | NVM_CHANNEL_40MHZ = BIT(9), | |
33158fef EL |
197 | NVM_CHANNEL_80MHZ = BIT(10), |
198 | NVM_CHANNEL_160MHZ = BIT(11), | |
b1e1adfa JB |
199 | }; |
200 | ||
201 | #define CHECK_AND_PRINT_I(x) \ | |
202 | ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "") | |
203 | ||
204 | static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, | |
205 | struct iwl_nvm_data *data, | |
206 | const __le16 * const nvm_ch_flags) | |
207 | { | |
208 | int ch_idx; | |
209 | int n_channels = 0; | |
210 | struct ieee80211_channel *channel; | |
211 | u16 ch_flags; | |
212 | bool is_5ghz; | |
749f1fe1 | 213 | int num_of_ch, num_2ghz_channels; |
77db0a3c EH |
214 | const u8 *nvm_chan; |
215 | ||
216 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { | |
217 | num_of_ch = IWL_NUM_CHANNELS; | |
218 | nvm_chan = &iwl_nvm_channels[0]; | |
749f1fe1 | 219 | num_2ghz_channels = NUM_2GHZ_CHANNELS; |
77db0a3c EH |
220 | } else { |
221 | num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000; | |
222 | nvm_chan = &iwl_nvm_channels_family_8000[0]; | |
749f1fe1 | 223 | num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000; |
77db0a3c | 224 | } |
b1e1adfa | 225 | |
77db0a3c | 226 | for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { |
b1e1adfa | 227 | ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx); |
c5128654 | 228 | |
749f1fe1 | 229 | if (ch_idx >= num_2ghz_channels && |
c5128654 EG |
230 | !data->sku_cap_band_52GHz_enable) |
231 | ch_flags &= ~NVM_CHANNEL_VALID; | |
232 | ||
b1e1adfa JB |
233 | if (!(ch_flags & NVM_CHANNEL_VALID)) { |
234 | IWL_DEBUG_EEPROM(dev, | |
235 | "Ch. %d Flags %x [%sGHz] - No traffic\n", | |
77db0a3c | 236 | nvm_chan[ch_idx], |
b1e1adfa | 237 | ch_flags, |
749f1fe1 | 238 | (ch_idx >= num_2ghz_channels) ? |
b1e1adfa JB |
239 | "5.2" : "2.4"); |
240 | continue; | |
241 | } | |
242 | ||
243 | channel = &data->channels[n_channels]; | |
244 | n_channels++; | |
245 | ||
77db0a3c | 246 | channel->hw_value = nvm_chan[ch_idx]; |
749f1fe1 | 247 | channel->band = (ch_idx < num_2ghz_channels) ? |
b1e1adfa JB |
248 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; |
249 | channel->center_freq = | |
250 | ieee80211_channel_to_frequency( | |
251 | channel->hw_value, channel->band); | |
252 | ||
253 | /* TODO: Need to be dependent to the NVM */ | |
254 | channel->flags = IEEE80211_CHAN_NO_HT40; | |
749f1fe1 | 255 | if (ch_idx < num_2ghz_channels && |
b1e1adfa | 256 | (ch_flags & NVM_CHANNEL_40MHZ)) { |
77db0a3c | 257 | if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) |
b1e1adfa | 258 | channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS; |
77db0a3c | 259 | if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) |
b1e1adfa | 260 | channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS; |
77db0a3c | 261 | } else if (nvm_chan[ch_idx] <= LAST_5GHZ_HT && |
b1e1adfa | 262 | (ch_flags & NVM_CHANNEL_40MHZ)) { |
749f1fe1 | 263 | if ((ch_idx - num_2ghz_channels) % 2 == 0) |
b1e1adfa JB |
264 | channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS; |
265 | else | |
266 | channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS; | |
267 | } | |
33158fef EL |
268 | if (!(ch_flags & NVM_CHANNEL_80MHZ)) |
269 | channel->flags |= IEEE80211_CHAN_NO_80MHZ; | |
270 | if (!(ch_flags & NVM_CHANNEL_160MHZ)) | |
271 | channel->flags |= IEEE80211_CHAN_NO_160MHZ; | |
b1e1adfa JB |
272 | |
273 | if (!(ch_flags & NVM_CHANNEL_IBSS)) | |
8fe02e16 | 274 | channel->flags |= IEEE80211_CHAN_NO_IR; |
b1e1adfa JB |
275 | |
276 | if (!(ch_flags & NVM_CHANNEL_ACTIVE)) | |
8fe02e16 | 277 | channel->flags |= IEEE80211_CHAN_NO_IR; |
b1e1adfa JB |
278 | |
279 | if (ch_flags & NVM_CHANNEL_RADAR) | |
280 | channel->flags |= IEEE80211_CHAN_RADAR; | |
281 | ||
9ee6dace DS |
282 | if (ch_flags & NVM_CHANNEL_INDOOR_ONLY) |
283 | channel->flags |= IEEE80211_CHAN_INDOOR_ONLY; | |
284 | ||
285 | /* Set the GO concurrent flag only in case that NO_IR is set. | |
286 | * Otherwise it is meaningless | |
287 | */ | |
288 | if ((ch_flags & NVM_CHANNEL_GO_CONCURRENT) && | |
289 | (channel->flags & IEEE80211_CHAN_NO_IR)) | |
290 | channel->flags |= IEEE80211_CHAN_GO_CONCURRENT; | |
291 | ||
b1e1adfa JB |
292 | /* Initialize regulatory-based run-time data */ |
293 | ||
88f2fd73 MG |
294 | /* |
295 | * Default value - highest tx power value. max_power | |
296 | * is not used in mvm, and is used for backwards compatibility | |
297 | */ | |
298 | channel->max_power = DEFAULT_MAX_TX_POWER; | |
b1e1adfa JB |
299 | is_5ghz = channel->band == IEEE80211_BAND_5GHZ; |
300 | IWL_DEBUG_EEPROM(dev, | |
9ee6dace | 301 | "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", |
b1e1adfa JB |
302 | channel->hw_value, |
303 | is_5ghz ? "5.2" : "2.4", | |
304 | CHECK_AND_PRINT_I(VALID), | |
305 | CHECK_AND_PRINT_I(IBSS), | |
306 | CHECK_AND_PRINT_I(ACTIVE), | |
307 | CHECK_AND_PRINT_I(RADAR), | |
308 | CHECK_AND_PRINT_I(WIDE), | |
9ee6dace DS |
309 | CHECK_AND_PRINT_I(INDOOR_ONLY), |
310 | CHECK_AND_PRINT_I(GO_CONCURRENT), | |
b1e1adfa JB |
311 | ch_flags, |
312 | channel->max_power, | |
313 | ((ch_flags & NVM_CHANNEL_IBSS) && | |
314 | !(ch_flags & NVM_CHANNEL_RADAR)) | |
315 | ? "" : "not "); | |
316 | } | |
317 | ||
318 | return n_channels; | |
319 | } | |
320 | ||
33158fef EL |
321 | static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg, |
322 | struct iwl_nvm_data *data, | |
6ca89f1f JB |
323 | struct ieee80211_sta_vht_cap *vht_cap, |
324 | u8 tx_chains, u8 rx_chains) | |
33158fef | 325 | { |
6ca89f1f JB |
326 | int num_rx_ants = num_of_ant(rx_chains); |
327 | int num_tx_ants = num_of_ant(tx_chains); | |
48e6de61 | 328 | |
33158fef EL |
329 | vht_cap->vht_supported = true; |
330 | ||
331 | vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | | |
332 | IEEE80211_VHT_CAP_RXSTBC_1 | | |
333 | IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | | |
e36b766d | 334 | 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | |
33158fef EL |
335 | 7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; |
336 | ||
6ca89f1f | 337 | if (num_tx_ants > 1) |
5f7a6f9b | 338 | vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; |
6ca89f1f JB |
339 | else |
340 | vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; | |
5f7a6f9b | 341 | |
33158fef EL |
342 | if (iwlwifi_mod_params.amsdu_size_8K) |
343 | vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; | |
344 | ||
345 | vht_cap->vht_mcs.rx_mcs_map = | |
346 | cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | | |
347 | IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | | |
348 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | | |
349 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | | |
350 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | | |
351 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | | |
352 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | | |
353 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); | |
354 | ||
6ca89f1f JB |
355 | if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { |
356 | vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; | |
33158fef EL |
357 | /* this works because NOT_SUPPORTED == 3 */ |
358 | vht_cap->vht_mcs.rx_mcs_map |= | |
359 | cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); | |
360 | } | |
361 | ||
362 | vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; | |
363 | } | |
364 | ||
b1e1adfa | 365 | static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg, |
77db0a3c EH |
366 | struct iwl_nvm_data *data, |
367 | const __le16 *ch_section, bool enable_vht, | |
368 | u8 tx_chains, u8 rx_chains) | |
b1e1adfa | 369 | { |
77db0a3c | 370 | int n_channels; |
b1e1adfa JB |
371 | int n_used = 0; |
372 | struct ieee80211_supported_band *sband; | |
373 | ||
77db0a3c EH |
374 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) |
375 | n_channels = iwl_init_channel_map( | |
376 | dev, cfg, data, | |
377 | &ch_section[NVM_CHANNELS]); | |
378 | else | |
379 | n_channels = iwl_init_channel_map( | |
380 | dev, cfg, data, | |
381 | &ch_section[NVM_CHANNELS_FAMILY_8000]); | |
382 | ||
b1e1adfa JB |
383 | sband = &data->bands[IEEE80211_BAND_2GHZ]; |
384 | sband->band = IEEE80211_BAND_2GHZ; | |
385 | sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; | |
386 | sband->n_bitrates = N_RATES_24; | |
387 | n_used += iwl_init_sband_channels(data, sband, n_channels, | |
388 | IEEE80211_BAND_2GHZ); | |
9ce4fa72 EG |
389 | iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ, |
390 | tx_chains, rx_chains); | |
b1e1adfa JB |
391 | |
392 | sband = &data->bands[IEEE80211_BAND_5GHZ]; | |
393 | sband->band = IEEE80211_BAND_5GHZ; | |
394 | sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; | |
395 | sband->n_bitrates = N_RATES_52; | |
396 | n_used += iwl_init_sband_channels(data, sband, n_channels, | |
397 | IEEE80211_BAND_5GHZ); | |
9ce4fa72 EG |
398 | iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ, |
399 | tx_chains, rx_chains); | |
bfc824b0 | 400 | if (enable_vht) |
6ca89f1f JB |
401 | iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap, |
402 | tx_chains, rx_chains); | |
b1e1adfa JB |
403 | |
404 | if (n_channels != n_used) | |
405 | IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", | |
406 | n_used, n_channels); | |
407 | } | |
408 | ||
77db0a3c EH |
409 | static int iwl_get_sku(const struct iwl_cfg *cfg, |
410 | const __le16 *nvm_sw) | |
411 | { | |
412 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
413 | return le16_to_cpup(nvm_sw + SKU); | |
414 | else | |
415 | return le32_to_cpup((__le32 *)(nvm_sw + SKU_FAMILY_8000)); | |
416 | } | |
417 | ||
418 | static int iwl_get_nvm_version(const struct iwl_cfg *cfg, | |
419 | const __le16 *nvm_sw) | |
420 | { | |
421 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
422 | return le16_to_cpup(nvm_sw + NVM_VERSION); | |
423 | else | |
424 | return le32_to_cpup((__le32 *)(nvm_sw + | |
425 | NVM_VERSION_FAMILY_8000)); | |
426 | } | |
427 | ||
428 | static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, | |
429 | const __le16 *nvm_sw) | |
430 | { | |
431 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
432 | return le16_to_cpup(nvm_sw + RADIO_CFG); | |
433 | else | |
434 | return le32_to_cpup((__le32 *)(nvm_sw + RADIO_CFG_FAMILY_8000)); | |
435 | } | |
436 | ||
437 | #define N_HW_ADDRS_MASK_FAMILY_8000 0xF | |
438 | static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, | |
439 | const __le16 *nvm_sw) | |
440 | { | |
441 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
442 | return le16_to_cpup(nvm_sw + N_HW_ADDRS); | |
443 | else | |
444 | return le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)) | |
445 | & N_HW_ADDRS_MASK_FAMILY_8000; | |
446 | } | |
447 | ||
448 | static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, | |
449 | struct iwl_nvm_data *data, | |
450 | u32 radio_cfg) | |
451 | { | |
452 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { | |
453 | data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); | |
454 | data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); | |
455 | data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); | |
456 | data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); | |
77db0a3c EH |
457 | return; |
458 | } | |
459 | ||
460 | /* set the radio configuration for family 8000 */ | |
461 | data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg); | |
462 | data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg); | |
463 | data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg); | |
464 | data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg); | |
77db0a3c EH |
465 | } |
466 | ||
467 | static void iwl_set_hw_address(const struct iwl_cfg *cfg, | |
468 | struct iwl_nvm_data *data, | |
469 | const __le16 *nvm_sec) | |
470 | { | |
9f32e017 | 471 | const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR); |
77db0a3c EH |
472 | |
473 | /* The byte order is little endian 16 bit, meaning 214365 */ | |
474 | data->hw_addr[0] = hw_addr[1]; | |
475 | data->hw_addr[1] = hw_addr[0]; | |
476 | data->hw_addr[2] = hw_addr[3]; | |
477 | data->hw_addr[3] = hw_addr[2]; | |
478 | data->hw_addr[4] = hw_addr[5]; | |
479 | data->hw_addr[5] = hw_addr[4]; | |
480 | } | |
481 | ||
6a68a39f EH |
482 | static void iwl_set_hw_address_family_8000(struct device *dev, |
483 | const struct iwl_cfg *cfg, | |
9f32e017 EH |
484 | struct iwl_nvm_data *data, |
485 | const __le16 *mac_override, | |
486 | const __le16 *nvm_hw) | |
487 | { | |
488 | const u8 *hw_addr; | |
489 | ||
490 | if (mac_override) { | |
491 | hw_addr = (const u8 *)(mac_override + | |
492 | MAC_ADDRESS_OVERRIDE_FAMILY_8000); | |
493 | ||
494 | /* The byte order is little endian 16 bit, meaning 214365 */ | |
495 | data->hw_addr[0] = hw_addr[1]; | |
496 | data->hw_addr[1] = hw_addr[0]; | |
497 | data->hw_addr[2] = hw_addr[3]; | |
498 | data->hw_addr[3] = hw_addr[2]; | |
499 | data->hw_addr[4] = hw_addr[5]; | |
500 | data->hw_addr[5] = hw_addr[4]; | |
501 | ||
6a68a39f | 502 | if (is_valid_ether_addr(data->hw_addr)) |
9f32e017 | 503 | return; |
6a68a39f EH |
504 | |
505 | IWL_ERR_DEV(dev, | |
506 | "mac address from nvm override section is not valid\n"); | |
9f32e017 EH |
507 | } |
508 | ||
6a68a39f | 509 | if (nvm_hw) { |
1e0b393a EH |
510 | /* read the MAC address from OTP */ |
511 | if (!dev_is_pci(dev) || (data->nvm_version < 0xE08)) { | |
512 | /* read the mac address from the WFPM location */ | |
513 | hw_addr = (const u8 *)(nvm_hw + | |
514 | HW_ADDR0_WFPM_FAMILY_8000); | |
515 | data->hw_addr[0] = hw_addr[3]; | |
516 | data->hw_addr[1] = hw_addr[2]; | |
517 | data->hw_addr[2] = hw_addr[1]; | |
518 | data->hw_addr[3] = hw_addr[0]; | |
519 | ||
520 | hw_addr = (const u8 *)(nvm_hw + | |
521 | HW_ADDR1_WFPM_FAMILY_8000); | |
522 | data->hw_addr[4] = hw_addr[1]; | |
523 | data->hw_addr[5] = hw_addr[0]; | |
524 | } else if ((data->nvm_version >= 0xE08) && | |
525 | (data->nvm_version < 0xE0B)) { | |
526 | /* read "reverse order" from the PCIe location */ | |
527 | hw_addr = (const u8 *)(nvm_hw + | |
528 | HW_ADDR0_PCIE_FAMILY_8000); | |
529 | data->hw_addr[5] = hw_addr[2]; | |
530 | data->hw_addr[4] = hw_addr[1]; | |
531 | data->hw_addr[3] = hw_addr[0]; | |
532 | ||
533 | hw_addr = (const u8 *)(nvm_hw + | |
534 | HW_ADDR1_PCIE_FAMILY_8000); | |
535 | data->hw_addr[2] = hw_addr[3]; | |
536 | data->hw_addr[1] = hw_addr[2]; | |
537 | data->hw_addr[0] = hw_addr[1]; | |
538 | } else { | |
539 | /* read from the PCIe location */ | |
540 | hw_addr = (const u8 *)(nvm_hw + | |
541 | HW_ADDR0_PCIE_FAMILY_8000); | |
542 | data->hw_addr[5] = hw_addr[0]; | |
543 | data->hw_addr[4] = hw_addr[1]; | |
544 | data->hw_addr[3] = hw_addr[2]; | |
545 | ||
546 | hw_addr = (const u8 *)(nvm_hw + | |
547 | HW_ADDR1_PCIE_FAMILY_8000); | |
548 | data->hw_addr[2] = hw_addr[1]; | |
549 | data->hw_addr[1] = hw_addr[2]; | |
550 | data->hw_addr[0] = hw_addr[3]; | |
551 | } | |
ca55eb47 EH |
552 | if (!is_valid_ether_addr(data->hw_addr)) |
553 | IWL_ERR_DEV(dev, | |
554 | "mac address from hw section is not valid\n"); | |
1e0b393a | 555 | |
6a68a39f EH |
556 | return; |
557 | } | |
9f32e017 | 558 | |
6a68a39f | 559 | IWL_ERR_DEV(dev, "mac address is not found\n"); |
9f32e017 EH |
560 | } |
561 | ||
b1e1adfa JB |
562 | struct iwl_nvm_data * |
563 | iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg, | |
564 | const __le16 *nvm_hw, const __le16 *nvm_sw, | |
77db0a3c EH |
565 | const __le16 *nvm_calib, const __le16 *regulatory, |
566 | const __le16 *mac_override, u8 tx_chains, u8 rx_chains) | |
b1e1adfa JB |
567 | { |
568 | struct iwl_nvm_data *data; | |
77db0a3c EH |
569 | u32 sku; |
570 | u32 radio_cfg; | |
571 | ||
572 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
573 | data = kzalloc(sizeof(*data) + | |
574 | sizeof(struct ieee80211_channel) * | |
575 | IWL_NUM_CHANNELS, | |
576 | GFP_KERNEL); | |
577 | else | |
578 | data = kzalloc(sizeof(*data) + | |
579 | sizeof(struct ieee80211_channel) * | |
580 | IWL_NUM_CHANNELS_FAMILY_8000, | |
581 | GFP_KERNEL); | |
b1e1adfa JB |
582 | if (!data) |
583 | return NULL; | |
584 | ||
77db0a3c | 585 | data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); |
b1e1adfa | 586 | |
77db0a3c EH |
587 | radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw); |
588 | iwl_set_radio_cfg(cfg, data, radio_cfg); | |
b1e1adfa | 589 | |
77db0a3c | 590 | sku = iwl_get_sku(cfg, nvm_sw); |
b1e1adfa JB |
591 | data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; |
592 | data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; | |
593 | data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; | |
77db0a3c | 594 | data->sku_cap_11ac_enable = sku & NVM_SKU_CAP_11AC_ENABLE; |
b1e1adfa JB |
595 | if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) |
596 | data->sku_cap_11n_enable = false; | |
597 | ||
77db0a3c | 598 | data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); |
b1e1adfa | 599 | |
77db0a3c EH |
600 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
601 | /* Checking for required sections */ | |
602 | if (!nvm_calib) { | |
603 | IWL_ERR_DEV(dev, | |
604 | "Can't parse empty Calib NVM sections\n"); | |
1270c416 | 605 | kfree(data); |
77db0a3c EH |
606 | return NULL; |
607 | } | |
608 | /* in family 8000 Xtal calibration values moved to OTP */ | |
609 | data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); | |
610 | data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); | |
b1e1adfa JB |
611 | } |
612 | ||
77db0a3c EH |
613 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
614 | iwl_set_hw_address(cfg, data, nvm_hw); | |
b1e1adfa | 615 | |
77db0a3c EH |
616 | iwl_init_sbands(dev, cfg, data, nvm_sw, |
617 | sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains, | |
618 | rx_chains); | |
619 | } else { | |
620 | /* MAC address in family 8000 */ | |
6a68a39f EH |
621 | iwl_set_hw_address_family_8000(dev, cfg, data, mac_override, |
622 | nvm_hw); | |
b1e1adfa | 623 | |
77db0a3c EH |
624 | iwl_init_sbands(dev, cfg, data, regulatory, |
625 | sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains, | |
626 | rx_chains); | |
627 | } | |
b1e1adfa | 628 | |
33b2f684 | 629 | data->calib_version = 255; |
b1e1adfa JB |
630 | |
631 | return data; | |
632 | } | |
48e29340 | 633 | IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); |