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b1e1adfa JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
b1e1adfa JB |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
b1e1adfa JB |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
b1e1adfa JB |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | *****************************************************************************/ | |
64 | #include <linux/types.h> | |
65 | #include <linux/slab.h> | |
66 | #include <linux/export.h> | |
9f32e017 | 67 | #include <linux/etherdevice.h> |
1e0b393a | 68 | #include <linux/pci.h> |
48e29340 | 69 | #include "iwl-drv.h" |
b1e1adfa JB |
70 | #include "iwl-modparams.h" |
71 | #include "iwl-nvm-parse.h" | |
72 | ||
73 | /* NVM offsets (in words) definitions */ | |
74 | enum wkp_nvm_offsets { | |
75 | /* NVM HW-Section offset (in words) definitions */ | |
76 | HW_ADDR = 0x15, | |
77 | ||
77db0a3c | 78 | /* NVM SW-Section offset (in words) definitions */ |
b1e1adfa JB |
79 | NVM_SW_SECTION = 0x1C0, |
80 | NVM_VERSION = 0, | |
81 | RADIO_CFG = 1, | |
82 | SKU = 2, | |
83 | N_HW_ADDRS = 3, | |
84 | NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, | |
85 | ||
77db0a3c | 86 | /* NVM calibration section offset (in words) definitions */ |
b1e1adfa JB |
87 | NVM_CALIB_SECTION = 0x2B8, |
88 | XTAL_CALIB = 0x316 - NVM_CALIB_SECTION | |
89 | }; | |
90 | ||
77db0a3c EH |
91 | enum family_8000_nvm_offsets { |
92 | /* NVM HW-Section offset (in words) definitions */ | |
1e0b393a EH |
93 | HW_ADDR0_WFPM_FAMILY_8000 = 0x12, |
94 | HW_ADDR1_WFPM_FAMILY_8000 = 0x16, | |
95 | HW_ADDR0_PCIE_FAMILY_8000 = 0x8A, | |
96 | HW_ADDR1_PCIE_FAMILY_8000 = 0x8E, | |
77db0a3c EH |
97 | MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1, |
98 | ||
99 | /* NVM SW-Section offset (in words) definitions */ | |
100 | NVM_SW_SECTION_FAMILY_8000 = 0x1C0, | |
101 | NVM_VERSION_FAMILY_8000 = 0, | |
102 | RADIO_CFG_FAMILY_8000 = 2, | |
103 | SKU_FAMILY_8000 = 4, | |
104 | N_HW_ADDRS_FAMILY_8000 = 5, | |
105 | ||
106 | /* NVM REGULATORY -Section offset (in words) definitions */ | |
107 | NVM_CHANNELS_FAMILY_8000 = 0, | |
108 | ||
109 | /* NVM calibration section offset (in words) definitions */ | |
110 | NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8, | |
111 | XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000 | |
112 | }; | |
113 | ||
b1e1adfa JB |
114 | /* SKU Capabilities (actual values from NVM definition) */ |
115 | enum nvm_sku_bits { | |
116 | NVM_SKU_CAP_BAND_24GHZ = BIT(0), | |
117 | NVM_SKU_CAP_BAND_52GHZ = BIT(1), | |
118 | NVM_SKU_CAP_11N_ENABLE = BIT(2), | |
bfc824b0 | 119 | NVM_SKU_CAP_11AC_ENABLE = BIT(3), |
b1e1adfa JB |
120 | }; |
121 | ||
b1e1adfa JB |
122 | /* |
123 | * These are the channel numbers in the order that they are stored in the NVM | |
124 | */ | |
125 | static const u8 iwl_nvm_channels[] = { | |
126 | /* 2.4 GHz */ | |
127 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
128 | /* 5 GHz */ | |
129 | 36, 40, 44 , 48, 52, 56, 60, 64, | |
130 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, | |
131 | 149, 153, 157, 161, 165 | |
132 | }; | |
133 | ||
77db0a3c EH |
134 | static const u8 iwl_nvm_channels_family_8000[] = { |
135 | /* 2.4 GHz */ | |
9b1c9a66 | 136 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, |
77db0a3c EH |
137 | /* 5 GHz */ |
138 | 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, | |
139 | 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, | |
140 | 149, 153, 157, 161, 165, 169, 173, 177, 181 | |
141 | }; | |
142 | ||
749f1fe1 | 143 | #define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) |
77db0a3c | 144 | #define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000) |
749f1fe1 | 145 | #define NUM_2GHZ_CHANNELS 14 |
9b1c9a66 | 146 | #define NUM_2GHZ_CHANNELS_FAMILY_8000 14 |
749f1fe1 EH |
147 | #define FIRST_2GHZ_HT_MINUS 5 |
148 | #define LAST_2GHZ_HT_PLUS 9 | |
149 | #define LAST_5GHZ_HT 161 | |
b1e1adfa | 150 | |
b1e1adfa JB |
151 | /* rate data (static) */ |
152 | static struct ieee80211_rate iwl_cfg80211_rates[] = { | |
153 | { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, | |
154 | { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, | |
155 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
156 | { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, | |
157 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
158 | { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, | |
159 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, | |
160 | { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, | |
161 | { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, | |
162 | { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, | |
163 | { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, | |
164 | { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, | |
165 | { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, | |
166 | { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, | |
167 | { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, | |
168 | }; | |
169 | #define RATES_24_OFFS 0 | |
170 | #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) | |
171 | #define RATES_52_OFFS 4 | |
172 | #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) | |
173 | ||
174 | /** | |
175 | * enum iwl_nvm_channel_flags - channel flags in NVM | |
176 | * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo | |
177 | * @NVM_CHANNEL_IBSS: usable as an IBSS channel | |
178 | * @NVM_CHANNEL_ACTIVE: active scanning allowed | |
179 | * @NVM_CHANNEL_RADAR: radar detection required | |
9ee6dace DS |
180 | * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed |
181 | * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS | |
182 | * on same channel on 2.4 or same UNII band on 5.2 | |
b1e1adfa JB |
183 | * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?) |
184 | * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) | |
33158fef EL |
185 | * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) |
186 | * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) | |
b1e1adfa JB |
187 | */ |
188 | enum iwl_nvm_channel_flags { | |
189 | NVM_CHANNEL_VALID = BIT(0), | |
190 | NVM_CHANNEL_IBSS = BIT(1), | |
191 | NVM_CHANNEL_ACTIVE = BIT(3), | |
192 | NVM_CHANNEL_RADAR = BIT(4), | |
9ee6dace DS |
193 | NVM_CHANNEL_INDOOR_ONLY = BIT(5), |
194 | NVM_CHANNEL_GO_CONCURRENT = BIT(6), | |
b1e1adfa JB |
195 | NVM_CHANNEL_WIDE = BIT(8), |
196 | NVM_CHANNEL_40MHZ = BIT(9), | |
33158fef EL |
197 | NVM_CHANNEL_80MHZ = BIT(10), |
198 | NVM_CHANNEL_160MHZ = BIT(11), | |
b1e1adfa JB |
199 | }; |
200 | ||
201 | #define CHECK_AND_PRINT_I(x) \ | |
202 | ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "") | |
203 | ||
770ceda6 AN |
204 | static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz, |
205 | u16 nvm_flags) | |
206 | { | |
207 | u32 flags = IEEE80211_CHAN_NO_HT40; | |
208 | ||
209 | if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) { | |
210 | if (ch_num <= LAST_2GHZ_HT_PLUS) | |
211 | flags &= ~IEEE80211_CHAN_NO_HT40PLUS; | |
212 | if (ch_num >= FIRST_2GHZ_HT_MINUS) | |
213 | flags &= ~IEEE80211_CHAN_NO_HT40MINUS; | |
214 | } else if (ch_num <= LAST_5GHZ_HT && (nvm_flags & NVM_CHANNEL_40MHZ)) { | |
215 | if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) | |
216 | flags &= ~IEEE80211_CHAN_NO_HT40PLUS; | |
217 | else | |
218 | flags &= ~IEEE80211_CHAN_NO_HT40MINUS; | |
219 | } | |
220 | if (!(nvm_flags & NVM_CHANNEL_80MHZ)) | |
221 | flags |= IEEE80211_CHAN_NO_80MHZ; | |
222 | if (!(nvm_flags & NVM_CHANNEL_160MHZ)) | |
223 | flags |= IEEE80211_CHAN_NO_160MHZ; | |
224 | ||
225 | if (!(nvm_flags & NVM_CHANNEL_IBSS)) | |
226 | flags |= IEEE80211_CHAN_NO_IR; | |
227 | ||
228 | if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) | |
229 | flags |= IEEE80211_CHAN_NO_IR; | |
230 | ||
231 | if (nvm_flags & NVM_CHANNEL_RADAR) | |
232 | flags |= IEEE80211_CHAN_RADAR; | |
233 | ||
234 | if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) | |
235 | flags |= IEEE80211_CHAN_INDOOR_ONLY; | |
236 | ||
237 | /* Set the GO concurrent flag only in case that NO_IR is set. | |
238 | * Otherwise it is meaningless | |
239 | */ | |
240 | if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && | |
241 | (flags & IEEE80211_CHAN_NO_IR)) | |
242 | flags |= IEEE80211_CHAN_GO_CONCURRENT; | |
243 | ||
244 | return flags; | |
245 | } | |
246 | ||
b1e1adfa JB |
247 | static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, |
248 | struct iwl_nvm_data *data, | |
770ceda6 AN |
249 | const __le16 * const nvm_ch_flags, |
250 | bool lar_supported) | |
b1e1adfa JB |
251 | { |
252 | int ch_idx; | |
253 | int n_channels = 0; | |
254 | struct ieee80211_channel *channel; | |
255 | u16 ch_flags; | |
256 | bool is_5ghz; | |
749f1fe1 | 257 | int num_of_ch, num_2ghz_channels; |
77db0a3c EH |
258 | const u8 *nvm_chan; |
259 | ||
260 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { | |
261 | num_of_ch = IWL_NUM_CHANNELS; | |
262 | nvm_chan = &iwl_nvm_channels[0]; | |
749f1fe1 | 263 | num_2ghz_channels = NUM_2GHZ_CHANNELS; |
77db0a3c EH |
264 | } else { |
265 | num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000; | |
266 | nvm_chan = &iwl_nvm_channels_family_8000[0]; | |
749f1fe1 | 267 | num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000; |
77db0a3c | 268 | } |
b1e1adfa | 269 | |
77db0a3c | 270 | for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { |
b1e1adfa | 271 | ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx); |
c5128654 | 272 | |
749f1fe1 | 273 | if (ch_idx >= num_2ghz_channels && |
c5128654 | 274 | !data->sku_cap_band_52GHz_enable) |
a76f3bfe | 275 | continue; |
c5128654 | 276 | |
770ceda6 | 277 | if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) { |
a76f3bfe EP |
278 | /* |
279 | * Channels might become valid later if lar is | |
280 | * supported, hence we still want to add them to | |
281 | * the list of supported channels to cfg80211. | |
282 | */ | |
b1e1adfa JB |
283 | IWL_DEBUG_EEPROM(dev, |
284 | "Ch. %d Flags %x [%sGHz] - No traffic\n", | |
77db0a3c | 285 | nvm_chan[ch_idx], |
b1e1adfa | 286 | ch_flags, |
749f1fe1 | 287 | (ch_idx >= num_2ghz_channels) ? |
b1e1adfa JB |
288 | "5.2" : "2.4"); |
289 | continue; | |
290 | } | |
291 | ||
292 | channel = &data->channels[n_channels]; | |
293 | n_channels++; | |
294 | ||
77db0a3c | 295 | channel->hw_value = nvm_chan[ch_idx]; |
749f1fe1 | 296 | channel->band = (ch_idx < num_2ghz_channels) ? |
b1e1adfa JB |
297 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; |
298 | channel->center_freq = | |
299 | ieee80211_channel_to_frequency( | |
300 | channel->hw_value, channel->band); | |
301 | ||
b1e1adfa JB |
302 | /* Initialize regulatory-based run-time data */ |
303 | ||
88f2fd73 MG |
304 | /* |
305 | * Default value - highest tx power value. max_power | |
306 | * is not used in mvm, and is used for backwards compatibility | |
307 | */ | |
22d059a5 | 308 | channel->max_power = IWL_DEFAULT_MAX_TX_POWER; |
b1e1adfa | 309 | is_5ghz = channel->band == IEEE80211_BAND_5GHZ; |
770ceda6 AN |
310 | |
311 | /* don't put limitations in case we're using LAR */ | |
312 | if (!lar_supported) | |
313 | channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], | |
314 | ch_idx, is_5ghz, | |
315 | ch_flags); | |
316 | else | |
317 | channel->flags = 0; | |
318 | ||
b1e1adfa | 319 | IWL_DEBUG_EEPROM(dev, |
9ee6dace | 320 | "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", |
b1e1adfa JB |
321 | channel->hw_value, |
322 | is_5ghz ? "5.2" : "2.4", | |
323 | CHECK_AND_PRINT_I(VALID), | |
324 | CHECK_AND_PRINT_I(IBSS), | |
325 | CHECK_AND_PRINT_I(ACTIVE), | |
326 | CHECK_AND_PRINT_I(RADAR), | |
327 | CHECK_AND_PRINT_I(WIDE), | |
9ee6dace DS |
328 | CHECK_AND_PRINT_I(INDOOR_ONLY), |
329 | CHECK_AND_PRINT_I(GO_CONCURRENT), | |
b1e1adfa JB |
330 | ch_flags, |
331 | channel->max_power, | |
332 | ((ch_flags & NVM_CHANNEL_IBSS) && | |
333 | !(ch_flags & NVM_CHANNEL_RADAR)) | |
334 | ? "" : "not "); | |
335 | } | |
336 | ||
337 | return n_channels; | |
338 | } | |
339 | ||
33158fef EL |
340 | static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg, |
341 | struct iwl_nvm_data *data, | |
6ca89f1f JB |
342 | struct ieee80211_sta_vht_cap *vht_cap, |
343 | u8 tx_chains, u8 rx_chains) | |
33158fef | 344 | { |
6ca89f1f JB |
345 | int num_rx_ants = num_of_ant(rx_chains); |
346 | int num_tx_ants = num_of_ant(tx_chains); | |
c064ddf3 EH |
347 | unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?: |
348 | IEEE80211_VHT_MAX_AMPDU_1024K); | |
48e6de61 | 349 | |
33158fef EL |
350 | vht_cap->vht_supported = true; |
351 | ||
352 | vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | | |
353 | IEEE80211_VHT_CAP_RXSTBC_1 | | |
354 | IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | | |
e36b766d | 355 | 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | |
c064ddf3 EH |
356 | max_ampdu_exponent << |
357 | IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; | |
33158fef | 358 | |
a3576ff2 ES |
359 | if (cfg->ht_params->ldpc) |
360 | vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; | |
361 | ||
6ca89f1f | 362 | if (num_tx_ants > 1) |
5f7a6f9b | 363 | vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; |
6ca89f1f JB |
364 | else |
365 | vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; | |
5f7a6f9b | 366 | |
33158fef EL |
367 | if (iwlwifi_mod_params.amsdu_size_8K) |
368 | vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; | |
369 | ||
370 | vht_cap->vht_mcs.rx_mcs_map = | |
371 | cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | | |
372 | IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | | |
373 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | | |
374 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | | |
375 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | | |
376 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | | |
377 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | | |
378 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); | |
379 | ||
6ca89f1f JB |
380 | if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { |
381 | vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; | |
33158fef EL |
382 | /* this works because NOT_SUPPORTED == 3 */ |
383 | vht_cap->vht_mcs.rx_mcs_map |= | |
384 | cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); | |
385 | } | |
386 | ||
387 | vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; | |
388 | } | |
389 | ||
b1e1adfa | 390 | static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg, |
77db0a3c EH |
391 | struct iwl_nvm_data *data, |
392 | const __le16 *ch_section, bool enable_vht, | |
770ceda6 | 393 | u8 tx_chains, u8 rx_chains, bool lar_supported) |
b1e1adfa | 394 | { |
77db0a3c | 395 | int n_channels; |
b1e1adfa JB |
396 | int n_used = 0; |
397 | struct ieee80211_supported_band *sband; | |
398 | ||
77db0a3c EH |
399 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) |
400 | n_channels = iwl_init_channel_map( | |
401 | dev, cfg, data, | |
770ceda6 | 402 | &ch_section[NVM_CHANNELS], lar_supported); |
77db0a3c EH |
403 | else |
404 | n_channels = iwl_init_channel_map( | |
405 | dev, cfg, data, | |
770ceda6 AN |
406 | &ch_section[NVM_CHANNELS_FAMILY_8000], |
407 | lar_supported); | |
77db0a3c | 408 | |
b1e1adfa JB |
409 | sband = &data->bands[IEEE80211_BAND_2GHZ]; |
410 | sband->band = IEEE80211_BAND_2GHZ; | |
411 | sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; | |
412 | sband->n_bitrates = N_RATES_24; | |
413 | n_used += iwl_init_sband_channels(data, sband, n_channels, | |
414 | IEEE80211_BAND_2GHZ); | |
9ce4fa72 EG |
415 | iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ, |
416 | tx_chains, rx_chains); | |
b1e1adfa JB |
417 | |
418 | sband = &data->bands[IEEE80211_BAND_5GHZ]; | |
419 | sband->band = IEEE80211_BAND_5GHZ; | |
420 | sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; | |
421 | sband->n_bitrates = N_RATES_52; | |
422 | n_used += iwl_init_sband_channels(data, sband, n_channels, | |
423 | IEEE80211_BAND_5GHZ); | |
9ce4fa72 EG |
424 | iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ, |
425 | tx_chains, rx_chains); | |
bfc824b0 | 426 | if (enable_vht) |
6ca89f1f JB |
427 | iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap, |
428 | tx_chains, rx_chains); | |
b1e1adfa JB |
429 | |
430 | if (n_channels != n_used) | |
431 | IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", | |
432 | n_used, n_channels); | |
433 | } | |
434 | ||
77db0a3c EH |
435 | static int iwl_get_sku(const struct iwl_cfg *cfg, |
436 | const __le16 *nvm_sw) | |
437 | { | |
438 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
439 | return le16_to_cpup(nvm_sw + SKU); | |
440 | else | |
441 | return le32_to_cpup((__le32 *)(nvm_sw + SKU_FAMILY_8000)); | |
442 | } | |
443 | ||
444 | static int iwl_get_nvm_version(const struct iwl_cfg *cfg, | |
445 | const __le16 *nvm_sw) | |
446 | { | |
447 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
448 | return le16_to_cpup(nvm_sw + NVM_VERSION); | |
449 | else | |
450 | return le32_to_cpup((__le32 *)(nvm_sw + | |
451 | NVM_VERSION_FAMILY_8000)); | |
452 | } | |
453 | ||
454 | static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, | |
455 | const __le16 *nvm_sw) | |
456 | { | |
457 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
458 | return le16_to_cpup(nvm_sw + RADIO_CFG); | |
459 | else | |
460 | return le32_to_cpup((__le32 *)(nvm_sw + RADIO_CFG_FAMILY_8000)); | |
461 | } | |
462 | ||
463 | #define N_HW_ADDRS_MASK_FAMILY_8000 0xF | |
464 | static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, | |
465 | const __le16 *nvm_sw) | |
466 | { | |
467 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
468 | return le16_to_cpup(nvm_sw + N_HW_ADDRS); | |
469 | else | |
470 | return le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)) | |
471 | & N_HW_ADDRS_MASK_FAMILY_8000; | |
472 | } | |
473 | ||
474 | static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, | |
475 | struct iwl_nvm_data *data, | |
476 | u32 radio_cfg) | |
477 | { | |
478 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { | |
479 | data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); | |
480 | data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); | |
481 | data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); | |
482 | data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); | |
77db0a3c EH |
483 | return; |
484 | } | |
485 | ||
486 | /* set the radio configuration for family 8000 */ | |
487 | data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg); | |
488 | data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg); | |
489 | data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg); | |
490 | data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg); | |
a0544272 MH |
491 | data->valid_tx_ant = NVM_RF_CFG_TX_ANT_MSK_FAMILY_8000(radio_cfg); |
492 | data->valid_rx_ant = NVM_RF_CFG_RX_ANT_MSK_FAMILY_8000(radio_cfg); | |
77db0a3c EH |
493 | } |
494 | ||
495 | static void iwl_set_hw_address(const struct iwl_cfg *cfg, | |
496 | struct iwl_nvm_data *data, | |
497 | const __le16 *nvm_sec) | |
498 | { | |
9f32e017 | 499 | const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR); |
77db0a3c EH |
500 | |
501 | /* The byte order is little endian 16 bit, meaning 214365 */ | |
502 | data->hw_addr[0] = hw_addr[1]; | |
503 | data->hw_addr[1] = hw_addr[0]; | |
504 | data->hw_addr[2] = hw_addr[3]; | |
505 | data->hw_addr[3] = hw_addr[2]; | |
506 | data->hw_addr[4] = hw_addr[5]; | |
507 | data->hw_addr[5] = hw_addr[4]; | |
508 | } | |
509 | ||
6a68a39f EH |
510 | static void iwl_set_hw_address_family_8000(struct device *dev, |
511 | const struct iwl_cfg *cfg, | |
9f32e017 EH |
512 | struct iwl_nvm_data *data, |
513 | const __le16 *mac_override, | |
514 | const __le16 *nvm_hw) | |
515 | { | |
516 | const u8 *hw_addr; | |
517 | ||
518 | if (mac_override) { | |
519 | hw_addr = (const u8 *)(mac_override + | |
520 | MAC_ADDRESS_OVERRIDE_FAMILY_8000); | |
521 | ||
522 | /* The byte order is little endian 16 bit, meaning 214365 */ | |
523 | data->hw_addr[0] = hw_addr[1]; | |
524 | data->hw_addr[1] = hw_addr[0]; | |
525 | data->hw_addr[2] = hw_addr[3]; | |
526 | data->hw_addr[3] = hw_addr[2]; | |
527 | data->hw_addr[4] = hw_addr[5]; | |
528 | data->hw_addr[5] = hw_addr[4]; | |
529 | ||
6a68a39f | 530 | if (is_valid_ether_addr(data->hw_addr)) |
9f32e017 | 531 | return; |
6a68a39f EH |
532 | |
533 | IWL_ERR_DEV(dev, | |
534 | "mac address from nvm override section is not valid\n"); | |
9f32e017 EH |
535 | } |
536 | ||
6a68a39f | 537 | if (nvm_hw) { |
1e0b393a EH |
538 | /* read the MAC address from OTP */ |
539 | if (!dev_is_pci(dev) || (data->nvm_version < 0xE08)) { | |
540 | /* read the mac address from the WFPM location */ | |
541 | hw_addr = (const u8 *)(nvm_hw + | |
542 | HW_ADDR0_WFPM_FAMILY_8000); | |
543 | data->hw_addr[0] = hw_addr[3]; | |
544 | data->hw_addr[1] = hw_addr[2]; | |
545 | data->hw_addr[2] = hw_addr[1]; | |
546 | data->hw_addr[3] = hw_addr[0]; | |
547 | ||
548 | hw_addr = (const u8 *)(nvm_hw + | |
549 | HW_ADDR1_WFPM_FAMILY_8000); | |
550 | data->hw_addr[4] = hw_addr[1]; | |
551 | data->hw_addr[5] = hw_addr[0]; | |
552 | } else if ((data->nvm_version >= 0xE08) && | |
553 | (data->nvm_version < 0xE0B)) { | |
554 | /* read "reverse order" from the PCIe location */ | |
555 | hw_addr = (const u8 *)(nvm_hw + | |
556 | HW_ADDR0_PCIE_FAMILY_8000); | |
557 | data->hw_addr[5] = hw_addr[2]; | |
558 | data->hw_addr[4] = hw_addr[1]; | |
559 | data->hw_addr[3] = hw_addr[0]; | |
560 | ||
561 | hw_addr = (const u8 *)(nvm_hw + | |
562 | HW_ADDR1_PCIE_FAMILY_8000); | |
563 | data->hw_addr[2] = hw_addr[3]; | |
564 | data->hw_addr[1] = hw_addr[2]; | |
565 | data->hw_addr[0] = hw_addr[1]; | |
566 | } else { | |
567 | /* read from the PCIe location */ | |
568 | hw_addr = (const u8 *)(nvm_hw + | |
569 | HW_ADDR0_PCIE_FAMILY_8000); | |
570 | data->hw_addr[5] = hw_addr[0]; | |
571 | data->hw_addr[4] = hw_addr[1]; | |
572 | data->hw_addr[3] = hw_addr[2]; | |
573 | ||
574 | hw_addr = (const u8 *)(nvm_hw + | |
575 | HW_ADDR1_PCIE_FAMILY_8000); | |
576 | data->hw_addr[2] = hw_addr[1]; | |
577 | data->hw_addr[1] = hw_addr[2]; | |
578 | data->hw_addr[0] = hw_addr[3]; | |
579 | } | |
ca55eb47 EH |
580 | if (!is_valid_ether_addr(data->hw_addr)) |
581 | IWL_ERR_DEV(dev, | |
582 | "mac address from hw section is not valid\n"); | |
1e0b393a | 583 | |
6a68a39f EH |
584 | return; |
585 | } | |
9f32e017 | 586 | |
6a68a39f | 587 | IWL_ERR_DEV(dev, "mac address is not found\n"); |
9f32e017 EH |
588 | } |
589 | ||
b1e1adfa JB |
590 | struct iwl_nvm_data * |
591 | iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg, | |
592 | const __le16 *nvm_hw, const __le16 *nvm_sw, | |
77db0a3c | 593 | const __le16 *nvm_calib, const __le16 *regulatory, |
770ceda6 AN |
594 | const __le16 *mac_override, u8 tx_chains, u8 rx_chains, |
595 | bool lar_supported) | |
b1e1adfa JB |
596 | { |
597 | struct iwl_nvm_data *data; | |
77db0a3c EH |
598 | u32 sku; |
599 | u32 radio_cfg; | |
600 | ||
601 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
602 | data = kzalloc(sizeof(*data) + | |
603 | sizeof(struct ieee80211_channel) * | |
604 | IWL_NUM_CHANNELS, | |
605 | GFP_KERNEL); | |
606 | else | |
607 | data = kzalloc(sizeof(*data) + | |
608 | sizeof(struct ieee80211_channel) * | |
609 | IWL_NUM_CHANNELS_FAMILY_8000, | |
610 | GFP_KERNEL); | |
b1e1adfa JB |
611 | if (!data) |
612 | return NULL; | |
613 | ||
77db0a3c | 614 | data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); |
b1e1adfa | 615 | |
77db0a3c EH |
616 | radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw); |
617 | iwl_set_radio_cfg(cfg, data, radio_cfg); | |
a0544272 MH |
618 | if (data->valid_tx_ant) |
619 | tx_chains &= data->valid_tx_ant; | |
620 | if (data->valid_rx_ant) | |
621 | rx_chains &= data->valid_rx_ant; | |
b1e1adfa | 622 | |
77db0a3c | 623 | sku = iwl_get_sku(cfg, nvm_sw); |
b1e1adfa JB |
624 | data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; |
625 | data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; | |
626 | data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; | |
77db0a3c | 627 | data->sku_cap_11ac_enable = sku & NVM_SKU_CAP_11AC_ENABLE; |
b1e1adfa JB |
628 | if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) |
629 | data->sku_cap_11n_enable = false; | |
630 | ||
77db0a3c | 631 | data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); |
b1e1adfa | 632 | |
77db0a3c EH |
633 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
634 | /* Checking for required sections */ | |
635 | if (!nvm_calib) { | |
636 | IWL_ERR_DEV(dev, | |
637 | "Can't parse empty Calib NVM sections\n"); | |
1270c416 | 638 | kfree(data); |
77db0a3c EH |
639 | return NULL; |
640 | } | |
641 | /* in family 8000 Xtal calibration values moved to OTP */ | |
642 | data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); | |
643 | data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); | |
b1e1adfa JB |
644 | } |
645 | ||
77db0a3c EH |
646 | if (cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
647 | iwl_set_hw_address(cfg, data, nvm_hw); | |
b1e1adfa | 648 | |
77db0a3c EH |
649 | iwl_init_sbands(dev, cfg, data, nvm_sw, |
650 | sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains, | |
770ceda6 | 651 | rx_chains, lar_supported); |
77db0a3c EH |
652 | } else { |
653 | /* MAC address in family 8000 */ | |
6a68a39f EH |
654 | iwl_set_hw_address_family_8000(dev, cfg, data, mac_override, |
655 | nvm_hw); | |
b1e1adfa | 656 | |
77db0a3c EH |
657 | iwl_init_sbands(dev, cfg, data, regulatory, |
658 | sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains, | |
770ceda6 | 659 | rx_chains, lar_supported); |
77db0a3c | 660 | } |
b1e1adfa | 661 | |
33b2f684 | 662 | data->calib_version = 255; |
b1e1adfa JB |
663 | |
664 | return data; | |
665 | } | |
48e29340 | 666 | IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); |
af45a900 AN |
667 | |
668 | static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan, | |
669 | int ch_idx, u16 nvm_flags) | |
670 | { | |
671 | u32 flags = NL80211_RRF_NO_HT40; | |
672 | ||
673 | if (ch_idx < NUM_2GHZ_CHANNELS && | |
674 | (nvm_flags & NVM_CHANNEL_40MHZ)) { | |
675 | if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) | |
676 | flags &= ~NL80211_RRF_NO_HT40PLUS; | |
677 | if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) | |
678 | flags &= ~NL80211_RRF_NO_HT40MINUS; | |
679 | } else if (nvm_chan[ch_idx] <= LAST_5GHZ_HT && | |
680 | (nvm_flags & NVM_CHANNEL_40MHZ)) { | |
681 | if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) | |
682 | flags &= ~NL80211_RRF_NO_HT40PLUS; | |
683 | else | |
684 | flags &= ~NL80211_RRF_NO_HT40MINUS; | |
685 | } | |
686 | ||
687 | if (!(nvm_flags & NVM_CHANNEL_80MHZ)) | |
688 | flags |= NL80211_RRF_NO_80MHZ; | |
689 | if (!(nvm_flags & NVM_CHANNEL_160MHZ)) | |
690 | flags |= NL80211_RRF_NO_160MHZ; | |
691 | ||
af45a900 AN |
692 | if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) |
693 | flags |= NL80211_RRF_NO_IR; | |
694 | ||
695 | if (nvm_flags & NVM_CHANNEL_RADAR) | |
696 | flags |= NL80211_RRF_DFS; | |
697 | ||
698 | if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) | |
699 | flags |= NL80211_RRF_NO_OUTDOOR; | |
700 | ||
701 | /* Set the GO concurrent flag only in case that NO_IR is set. | |
702 | * Otherwise it is meaningless | |
703 | */ | |
704 | if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && | |
705 | (flags & NL80211_RRF_NO_IR)) | |
706 | flags |= NL80211_RRF_GO_CONCURRENT; | |
707 | ||
708 | return flags; | |
709 | } | |
710 | ||
711 | struct ieee80211_regdomain * | |
162ee3c9 AN |
712 | iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, |
713 | int num_of_ch, __le32 *channels, u16 fw_mcc) | |
af45a900 AN |
714 | { |
715 | int ch_idx; | |
716 | u16 ch_flags, prev_ch_flags = 0; | |
162ee3c9 AN |
717 | const u8 *nvm_chan = cfg->device_family == IWL_DEVICE_FAMILY_8000 ? |
718 | iwl_nvm_channels_family_8000 : iwl_nvm_channels; | |
af45a900 AN |
719 | struct ieee80211_regdomain *regd; |
720 | int size_of_regd; | |
721 | struct ieee80211_reg_rule *rule; | |
722 | enum ieee80211_band band; | |
723 | int center_freq, prev_center_freq = 0; | |
724 | int valid_rules = 0; | |
725 | bool new_rule; | |
726 | ||
727 | if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) | |
728 | return ERR_PTR(-EINVAL); | |
729 | ||
730 | IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", | |
731 | num_of_ch); | |
732 | ||
733 | /* build a regdomain rule for every valid channel */ | |
734 | size_of_regd = | |
735 | sizeof(struct ieee80211_regdomain) + | |
736 | num_of_ch * sizeof(struct ieee80211_reg_rule); | |
737 | ||
738 | regd = kzalloc(size_of_regd, GFP_KERNEL); | |
739 | if (!regd) | |
740 | return ERR_PTR(-ENOMEM); | |
741 | ||
742 | for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { | |
743 | ch_flags = (u16)__le32_to_cpup(channels + ch_idx); | |
744 | band = (ch_idx < NUM_2GHZ_CHANNELS) ? | |
745 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
746 | center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], | |
747 | band); | |
748 | new_rule = false; | |
749 | ||
750 | if (!(ch_flags & NVM_CHANNEL_VALID)) { | |
751 | IWL_DEBUG_DEV(dev, IWL_DL_LAR, | |
752 | "Ch. %d Flags %x [%sGHz] - No traffic\n", | |
753 | nvm_chan[ch_idx], | |
754 | ch_flags, | |
755 | (ch_idx >= NUM_2GHZ_CHANNELS) ? | |
756 | "5.2" : "2.4"); | |
757 | continue; | |
758 | } | |
759 | ||
760 | /* we can't continue the same rule */ | |
761 | if (ch_idx == 0 || prev_ch_flags != ch_flags || | |
762 | center_freq - prev_center_freq > 20) { | |
763 | valid_rules++; | |
764 | new_rule = true; | |
765 | } | |
766 | ||
767 | rule = ®d->reg_rules[valid_rules - 1]; | |
768 | ||
769 | if (new_rule) | |
770 | rule->freq_range.start_freq_khz = | |
771 | MHZ_TO_KHZ(center_freq - 10); | |
772 | ||
773 | rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); | |
774 | ||
775 | /* this doesn't matter - not used by FW */ | |
776 | rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); | |
777 | rule->power_rule.max_eirp = DBM_TO_MBM(20); | |
778 | ||
779 | rule->flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, | |
780 | ch_flags); | |
781 | ||
782 | /* rely on auto-calculation to merge BW of contiguous chans */ | |
783 | rule->flags |= NL80211_RRF_AUTO_BW; | |
784 | rule->freq_range.max_bandwidth_khz = 0; | |
785 | ||
786 | prev_ch_flags = ch_flags; | |
787 | prev_center_freq = center_freq; | |
788 | ||
789 | IWL_DEBUG_DEV(dev, IWL_DL_LAR, | |
bdf2fae8 | 790 | "Ch. %d [%sGHz] %s%s%s%s%s%s%s%s%s(0x%02x): Ad-Hoc %ssupported\n", |
af45a900 AN |
791 | center_freq, |
792 | band == IEEE80211_BAND_5GHZ ? "5.2" : "2.4", | |
793 | CHECK_AND_PRINT_I(VALID), | |
af45a900 AN |
794 | CHECK_AND_PRINT_I(ACTIVE), |
795 | CHECK_AND_PRINT_I(RADAR), | |
796 | CHECK_AND_PRINT_I(WIDE), | |
797 | CHECK_AND_PRINT_I(40MHZ), | |
798 | CHECK_AND_PRINT_I(80MHZ), | |
799 | CHECK_AND_PRINT_I(160MHZ), | |
800 | CHECK_AND_PRINT_I(INDOOR_ONLY), | |
801 | CHECK_AND_PRINT_I(GO_CONCURRENT), | |
802 | ch_flags, | |
bdf2fae8 | 803 | ((ch_flags & NVM_CHANNEL_ACTIVE) && |
af45a900 AN |
804 | !(ch_flags & NVM_CHANNEL_RADAR)) |
805 | ? "" : "not "); | |
806 | } | |
807 | ||
808 | regd->n_reg_rules = valid_rules; | |
809 | ||
810 | /* set alpha2 from FW. */ | |
811 | regd->alpha2[0] = fw_mcc >> 8; | |
812 | regd->alpha2[1] = fw_mcc & 0xff; | |
813 | ||
814 | return regd; | |
815 | } | |
816 | IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); |