Revert "iwlwifi: use correct fw file in 8000 b-step"
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-nvm-parse.c
CommitLineData
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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
8b4139dc 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
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10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
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27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
8b4139dc 35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
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36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64#include <linux/types.h>
65#include <linux/slab.h>
66#include <linux/export.h>
9f32e017 67#include <linux/etherdevice.h>
1e0b393a 68#include <linux/pci.h>
48e29340 69#include "iwl-drv.h"
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70#include "iwl-modparams.h"
71#include "iwl-nvm-parse.h"
72
73/* NVM offsets (in words) definitions */
74enum wkp_nvm_offsets {
75 /* NVM HW-Section offset (in words) definitions */
76 HW_ADDR = 0x15,
77
77db0a3c 78 /* NVM SW-Section offset (in words) definitions */
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79 NVM_SW_SECTION = 0x1C0,
80 NVM_VERSION = 0,
81 RADIO_CFG = 1,
82 SKU = 2,
83 N_HW_ADDRS = 3,
84 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
85
77db0a3c 86 /* NVM calibration section offset (in words) definitions */
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87 NVM_CALIB_SECTION = 0x2B8,
88 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
89};
90
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91enum family_8000_nvm_offsets {
92 /* NVM HW-Section offset (in words) definitions */
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93 HW_ADDR0_WFPM_FAMILY_8000 = 0x12,
94 HW_ADDR1_WFPM_FAMILY_8000 = 0x16,
95 HW_ADDR0_PCIE_FAMILY_8000 = 0x8A,
96 HW_ADDR1_PCIE_FAMILY_8000 = 0x8E,
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97 MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1,
98
99 /* NVM SW-Section offset (in words) definitions */
100 NVM_SW_SECTION_FAMILY_8000 = 0x1C0,
101 NVM_VERSION_FAMILY_8000 = 0,
102 RADIO_CFG_FAMILY_8000 = 2,
103 SKU_FAMILY_8000 = 4,
104 N_HW_ADDRS_FAMILY_8000 = 5,
105
106 /* NVM REGULATORY -Section offset (in words) definitions */
107 NVM_CHANNELS_FAMILY_8000 = 0,
108
109 /* NVM calibration section offset (in words) definitions */
110 NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8,
111 XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000
112};
113
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114/* SKU Capabilities (actual values from NVM definition) */
115enum nvm_sku_bits {
116 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
117 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
118 NVM_SKU_CAP_11N_ENABLE = BIT(2),
bfc824b0 119 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
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120};
121
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122/*
123 * These are the channel numbers in the order that they are stored in the NVM
124 */
125static const u8 iwl_nvm_channels[] = {
126 /* 2.4 GHz */
127 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
128 /* 5 GHz */
129 36, 40, 44 , 48, 52, 56, 60, 64,
130 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
131 149, 153, 157, 161, 165
132};
133
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EH
134static const u8 iwl_nvm_channels_family_8000[] = {
135 /* 2.4 GHz */
9b1c9a66 136 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
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EH
137 /* 5 GHz */
138 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
139 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
140 149, 153, 157, 161, 165, 169, 173, 177, 181
141};
142
749f1fe1 143#define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
77db0a3c 144#define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000)
749f1fe1 145#define NUM_2GHZ_CHANNELS 14
9b1c9a66 146#define NUM_2GHZ_CHANNELS_FAMILY_8000 14
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EH
147#define FIRST_2GHZ_HT_MINUS 5
148#define LAST_2GHZ_HT_PLUS 9
149#define LAST_5GHZ_HT 161
b1e1adfa 150
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JB
151/* rate data (static) */
152static struct ieee80211_rate iwl_cfg80211_rates[] = {
153 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
154 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
156 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
158 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
160 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
161 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
162 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
163 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
164 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
165 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
166 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
167 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
168};
169#define RATES_24_OFFS 0
170#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
171#define RATES_52_OFFS 4
172#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
173
174/**
175 * enum iwl_nvm_channel_flags - channel flags in NVM
176 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
177 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
178 * @NVM_CHANNEL_ACTIVE: active scanning allowed
179 * @NVM_CHANNEL_RADAR: radar detection required
9ee6dace
DS
180 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
181 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
182 * on same channel on 2.4 or same UNII band on 5.2
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183 * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
184 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
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185 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
186 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
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187 */
188enum iwl_nvm_channel_flags {
189 NVM_CHANNEL_VALID = BIT(0),
190 NVM_CHANNEL_IBSS = BIT(1),
191 NVM_CHANNEL_ACTIVE = BIT(3),
192 NVM_CHANNEL_RADAR = BIT(4),
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DS
193 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
194 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
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JB
195 NVM_CHANNEL_WIDE = BIT(8),
196 NVM_CHANNEL_40MHZ = BIT(9),
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197 NVM_CHANNEL_80MHZ = BIT(10),
198 NVM_CHANNEL_160MHZ = BIT(11),
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199};
200
201#define CHECK_AND_PRINT_I(x) \
202 ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
203
204static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
205 struct iwl_nvm_data *data,
206 const __le16 * const nvm_ch_flags)
207{
208 int ch_idx;
209 int n_channels = 0;
210 struct ieee80211_channel *channel;
211 u16 ch_flags;
212 bool is_5ghz;
749f1fe1 213 int num_of_ch, num_2ghz_channels;
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EH
214 const u8 *nvm_chan;
215
216 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
217 num_of_ch = IWL_NUM_CHANNELS;
218 nvm_chan = &iwl_nvm_channels[0];
749f1fe1 219 num_2ghz_channels = NUM_2GHZ_CHANNELS;
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EH
220 } else {
221 num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000;
222 nvm_chan = &iwl_nvm_channels_family_8000[0];
749f1fe1 223 num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000;
77db0a3c 224 }
b1e1adfa 225
77db0a3c 226 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
b1e1adfa 227 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
c5128654 228
749f1fe1 229 if (ch_idx >= num_2ghz_channels &&
c5128654
EG
230 !data->sku_cap_band_52GHz_enable)
231 ch_flags &= ~NVM_CHANNEL_VALID;
232
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JB
233 if (!(ch_flags & NVM_CHANNEL_VALID)) {
234 IWL_DEBUG_EEPROM(dev,
235 "Ch. %d Flags %x [%sGHz] - No traffic\n",
77db0a3c 236 nvm_chan[ch_idx],
b1e1adfa 237 ch_flags,
749f1fe1 238 (ch_idx >= num_2ghz_channels) ?
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JB
239 "5.2" : "2.4");
240 continue;
241 }
242
243 channel = &data->channels[n_channels];
244 n_channels++;
245
77db0a3c 246 channel->hw_value = nvm_chan[ch_idx];
749f1fe1 247 channel->band = (ch_idx < num_2ghz_channels) ?
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JB
248 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
249 channel->center_freq =
250 ieee80211_channel_to_frequency(
251 channel->hw_value, channel->band);
252
253 /* TODO: Need to be dependent to the NVM */
254 channel->flags = IEEE80211_CHAN_NO_HT40;
749f1fe1 255 if (ch_idx < num_2ghz_channels &&
b1e1adfa 256 (ch_flags & NVM_CHANNEL_40MHZ)) {
77db0a3c 257 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
b1e1adfa 258 channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
77db0a3c 259 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
b1e1adfa 260 channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
77db0a3c 261 } else if (nvm_chan[ch_idx] <= LAST_5GHZ_HT &&
b1e1adfa 262 (ch_flags & NVM_CHANNEL_40MHZ)) {
749f1fe1 263 if ((ch_idx - num_2ghz_channels) % 2 == 0)
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JB
264 channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
265 else
266 channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
267 }
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EL
268 if (!(ch_flags & NVM_CHANNEL_80MHZ))
269 channel->flags |= IEEE80211_CHAN_NO_80MHZ;
270 if (!(ch_flags & NVM_CHANNEL_160MHZ))
271 channel->flags |= IEEE80211_CHAN_NO_160MHZ;
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JB
272
273 if (!(ch_flags & NVM_CHANNEL_IBSS))
8fe02e16 274 channel->flags |= IEEE80211_CHAN_NO_IR;
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JB
275
276 if (!(ch_flags & NVM_CHANNEL_ACTIVE))
8fe02e16 277 channel->flags |= IEEE80211_CHAN_NO_IR;
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JB
278
279 if (ch_flags & NVM_CHANNEL_RADAR)
280 channel->flags |= IEEE80211_CHAN_RADAR;
281
9ee6dace
DS
282 if (ch_flags & NVM_CHANNEL_INDOOR_ONLY)
283 channel->flags |= IEEE80211_CHAN_INDOOR_ONLY;
284
285 /* Set the GO concurrent flag only in case that NO_IR is set.
286 * Otherwise it is meaningless
287 */
288 if ((ch_flags & NVM_CHANNEL_GO_CONCURRENT) &&
289 (channel->flags & IEEE80211_CHAN_NO_IR))
290 channel->flags |= IEEE80211_CHAN_GO_CONCURRENT;
291
b1e1adfa
JB
292 /* Initialize regulatory-based run-time data */
293
88f2fd73
MG
294 /*
295 * Default value - highest tx power value. max_power
296 * is not used in mvm, and is used for backwards compatibility
297 */
22d059a5 298 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
b1e1adfa
JB
299 is_5ghz = channel->band == IEEE80211_BAND_5GHZ;
300 IWL_DEBUG_EEPROM(dev,
9ee6dace 301 "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
b1e1adfa
JB
302 channel->hw_value,
303 is_5ghz ? "5.2" : "2.4",
304 CHECK_AND_PRINT_I(VALID),
305 CHECK_AND_PRINT_I(IBSS),
306 CHECK_AND_PRINT_I(ACTIVE),
307 CHECK_AND_PRINT_I(RADAR),
308 CHECK_AND_PRINT_I(WIDE),
9ee6dace
DS
309 CHECK_AND_PRINT_I(INDOOR_ONLY),
310 CHECK_AND_PRINT_I(GO_CONCURRENT),
b1e1adfa
JB
311 ch_flags,
312 channel->max_power,
313 ((ch_flags & NVM_CHANNEL_IBSS) &&
314 !(ch_flags & NVM_CHANNEL_RADAR))
315 ? "" : "not ");
316 }
317
318 return n_channels;
319}
320
33158fef
EL
321static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
322 struct iwl_nvm_data *data,
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JB
323 struct ieee80211_sta_vht_cap *vht_cap,
324 u8 tx_chains, u8 rx_chains)
33158fef 325{
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JB
326 int num_rx_ants = num_of_ant(rx_chains);
327 int num_tx_ants = num_of_ant(tx_chains);
c064ddf3
EH
328 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
329 IEEE80211_VHT_MAX_AMPDU_1024K);
48e6de61 330
33158fef
EL
331 vht_cap->vht_supported = true;
332
333 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
334 IEEE80211_VHT_CAP_RXSTBC_1 |
335 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
e36b766d 336 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
c064ddf3
EH
337 max_ampdu_exponent <<
338 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
33158fef 339
a3576ff2
ES
340 if (cfg->ht_params->ldpc)
341 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
342
6ca89f1f 343 if (num_tx_ants > 1)
5f7a6f9b 344 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
6ca89f1f
JB
345 else
346 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
5f7a6f9b 347
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EL
348 if (iwlwifi_mod_params.amsdu_size_8K)
349 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
350
351 vht_cap->vht_mcs.rx_mcs_map =
352 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
353 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
354 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
355 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
356 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
357 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
358 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
359 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
360
6ca89f1f
JB
361 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
362 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
33158fef
EL
363 /* this works because NOT_SUPPORTED == 3 */
364 vht_cap->vht_mcs.rx_mcs_map |=
365 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
366 }
367
368 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
369}
370
b1e1adfa 371static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
77db0a3c
EH
372 struct iwl_nvm_data *data,
373 const __le16 *ch_section, bool enable_vht,
374 u8 tx_chains, u8 rx_chains)
b1e1adfa 375{
77db0a3c 376 int n_channels;
b1e1adfa
JB
377 int n_used = 0;
378 struct ieee80211_supported_band *sband;
379
77db0a3c
EH
380 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
381 n_channels = iwl_init_channel_map(
382 dev, cfg, data,
383 &ch_section[NVM_CHANNELS]);
384 else
385 n_channels = iwl_init_channel_map(
386 dev, cfg, data,
387 &ch_section[NVM_CHANNELS_FAMILY_8000]);
388
b1e1adfa
JB
389 sband = &data->bands[IEEE80211_BAND_2GHZ];
390 sband->band = IEEE80211_BAND_2GHZ;
391 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
392 sband->n_bitrates = N_RATES_24;
393 n_used += iwl_init_sband_channels(data, sband, n_channels,
394 IEEE80211_BAND_2GHZ);
9ce4fa72
EG
395 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ,
396 tx_chains, rx_chains);
b1e1adfa
JB
397
398 sband = &data->bands[IEEE80211_BAND_5GHZ];
399 sband->band = IEEE80211_BAND_5GHZ;
400 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
401 sband->n_bitrates = N_RATES_52;
402 n_used += iwl_init_sband_channels(data, sband, n_channels,
403 IEEE80211_BAND_5GHZ);
9ce4fa72
EG
404 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ,
405 tx_chains, rx_chains);
bfc824b0 406 if (enable_vht)
6ca89f1f
JB
407 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
408 tx_chains, rx_chains);
b1e1adfa
JB
409
410 if (n_channels != n_used)
411 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
412 n_used, n_channels);
413}
414
77db0a3c
EH
415static int iwl_get_sku(const struct iwl_cfg *cfg,
416 const __le16 *nvm_sw)
417{
418 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
419 return le16_to_cpup(nvm_sw + SKU);
420 else
421 return le32_to_cpup((__le32 *)(nvm_sw + SKU_FAMILY_8000));
422}
423
424static int iwl_get_nvm_version(const struct iwl_cfg *cfg,
425 const __le16 *nvm_sw)
426{
427 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
428 return le16_to_cpup(nvm_sw + NVM_VERSION);
429 else
430 return le32_to_cpup((__le32 *)(nvm_sw +
431 NVM_VERSION_FAMILY_8000));
432}
433
434static int iwl_get_radio_cfg(const struct iwl_cfg *cfg,
435 const __le16 *nvm_sw)
436{
437 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
438 return le16_to_cpup(nvm_sw + RADIO_CFG);
439 else
440 return le32_to_cpup((__le32 *)(nvm_sw + RADIO_CFG_FAMILY_8000));
441}
442
443#define N_HW_ADDRS_MASK_FAMILY_8000 0xF
444static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg,
445 const __le16 *nvm_sw)
446{
447 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
448 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
449 else
450 return le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000))
451 & N_HW_ADDRS_MASK_FAMILY_8000;
452}
453
454static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
455 struct iwl_nvm_data *data,
456 u32 radio_cfg)
457{
458 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
459 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
460 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
461 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
462 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
77db0a3c
EH
463 return;
464 }
465
466 /* set the radio configuration for family 8000 */
467 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg);
468 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg);
469 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg);
470 data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg);
77db0a3c
EH
471}
472
473static void iwl_set_hw_address(const struct iwl_cfg *cfg,
474 struct iwl_nvm_data *data,
475 const __le16 *nvm_sec)
476{
9f32e017 477 const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR);
77db0a3c
EH
478
479 /* The byte order is little endian 16 bit, meaning 214365 */
480 data->hw_addr[0] = hw_addr[1];
481 data->hw_addr[1] = hw_addr[0];
482 data->hw_addr[2] = hw_addr[3];
483 data->hw_addr[3] = hw_addr[2];
484 data->hw_addr[4] = hw_addr[5];
485 data->hw_addr[5] = hw_addr[4];
486}
487
6a68a39f
EH
488static void iwl_set_hw_address_family_8000(struct device *dev,
489 const struct iwl_cfg *cfg,
9f32e017
EH
490 struct iwl_nvm_data *data,
491 const __le16 *mac_override,
492 const __le16 *nvm_hw)
493{
494 const u8 *hw_addr;
495
496 if (mac_override) {
497 hw_addr = (const u8 *)(mac_override +
498 MAC_ADDRESS_OVERRIDE_FAMILY_8000);
499
500 /* The byte order is little endian 16 bit, meaning 214365 */
501 data->hw_addr[0] = hw_addr[1];
502 data->hw_addr[1] = hw_addr[0];
503 data->hw_addr[2] = hw_addr[3];
504 data->hw_addr[3] = hw_addr[2];
505 data->hw_addr[4] = hw_addr[5];
506 data->hw_addr[5] = hw_addr[4];
507
6a68a39f 508 if (is_valid_ether_addr(data->hw_addr))
9f32e017 509 return;
6a68a39f
EH
510
511 IWL_ERR_DEV(dev,
512 "mac address from nvm override section is not valid\n");
9f32e017
EH
513 }
514
6a68a39f 515 if (nvm_hw) {
1e0b393a
EH
516 /* read the MAC address from OTP */
517 if (!dev_is_pci(dev) || (data->nvm_version < 0xE08)) {
518 /* read the mac address from the WFPM location */
519 hw_addr = (const u8 *)(nvm_hw +
520 HW_ADDR0_WFPM_FAMILY_8000);
521 data->hw_addr[0] = hw_addr[3];
522 data->hw_addr[1] = hw_addr[2];
523 data->hw_addr[2] = hw_addr[1];
524 data->hw_addr[3] = hw_addr[0];
525
526 hw_addr = (const u8 *)(nvm_hw +
527 HW_ADDR1_WFPM_FAMILY_8000);
528 data->hw_addr[4] = hw_addr[1];
529 data->hw_addr[5] = hw_addr[0];
530 } else if ((data->nvm_version >= 0xE08) &&
531 (data->nvm_version < 0xE0B)) {
532 /* read "reverse order" from the PCIe location */
533 hw_addr = (const u8 *)(nvm_hw +
534 HW_ADDR0_PCIE_FAMILY_8000);
535 data->hw_addr[5] = hw_addr[2];
536 data->hw_addr[4] = hw_addr[1];
537 data->hw_addr[3] = hw_addr[0];
538
539 hw_addr = (const u8 *)(nvm_hw +
540 HW_ADDR1_PCIE_FAMILY_8000);
541 data->hw_addr[2] = hw_addr[3];
542 data->hw_addr[1] = hw_addr[2];
543 data->hw_addr[0] = hw_addr[1];
544 } else {
545 /* read from the PCIe location */
546 hw_addr = (const u8 *)(nvm_hw +
547 HW_ADDR0_PCIE_FAMILY_8000);
548 data->hw_addr[5] = hw_addr[0];
549 data->hw_addr[4] = hw_addr[1];
550 data->hw_addr[3] = hw_addr[2];
551
552 hw_addr = (const u8 *)(nvm_hw +
553 HW_ADDR1_PCIE_FAMILY_8000);
554 data->hw_addr[2] = hw_addr[1];
555 data->hw_addr[1] = hw_addr[2];
556 data->hw_addr[0] = hw_addr[3];
557 }
ca55eb47
EH
558 if (!is_valid_ether_addr(data->hw_addr))
559 IWL_ERR_DEV(dev,
560 "mac address from hw section is not valid\n");
1e0b393a 561
6a68a39f
EH
562 return;
563 }
9f32e017 564
6a68a39f 565 IWL_ERR_DEV(dev, "mac address is not found\n");
9f32e017
EH
566}
567
b1e1adfa
JB
568struct iwl_nvm_data *
569iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg,
570 const __le16 *nvm_hw, const __le16 *nvm_sw,
77db0a3c
EH
571 const __le16 *nvm_calib, const __le16 *regulatory,
572 const __le16 *mac_override, u8 tx_chains, u8 rx_chains)
b1e1adfa
JB
573{
574 struct iwl_nvm_data *data;
77db0a3c
EH
575 u32 sku;
576 u32 radio_cfg;
577
578 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
579 data = kzalloc(sizeof(*data) +
580 sizeof(struct ieee80211_channel) *
581 IWL_NUM_CHANNELS,
582 GFP_KERNEL);
583 else
584 data = kzalloc(sizeof(*data) +
585 sizeof(struct ieee80211_channel) *
586 IWL_NUM_CHANNELS_FAMILY_8000,
587 GFP_KERNEL);
b1e1adfa
JB
588 if (!data)
589 return NULL;
590
77db0a3c 591 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
b1e1adfa 592
77db0a3c
EH
593 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw);
594 iwl_set_radio_cfg(cfg, data, radio_cfg);
b1e1adfa 595
77db0a3c 596 sku = iwl_get_sku(cfg, nvm_sw);
b1e1adfa
JB
597 data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
598 data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
599 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
77db0a3c 600 data->sku_cap_11ac_enable = sku & NVM_SKU_CAP_11AC_ENABLE;
b1e1adfa
JB
601 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
602 data->sku_cap_11n_enable = false;
603
77db0a3c 604 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
b1e1adfa 605
77db0a3c
EH
606 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
607 /* Checking for required sections */
608 if (!nvm_calib) {
609 IWL_ERR_DEV(dev,
610 "Can't parse empty Calib NVM sections\n");
1270c416 611 kfree(data);
77db0a3c
EH
612 return NULL;
613 }
614 /* in family 8000 Xtal calibration values moved to OTP */
615 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
616 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
b1e1adfa
JB
617 }
618
77db0a3c
EH
619 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
620 iwl_set_hw_address(cfg, data, nvm_hw);
b1e1adfa 621
77db0a3c
EH
622 iwl_init_sbands(dev, cfg, data, nvm_sw,
623 sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
624 rx_chains);
625 } else {
626 /* MAC address in family 8000 */
6a68a39f
EH
627 iwl_set_hw_address_family_8000(dev, cfg, data, mac_override,
628 nvm_hw);
b1e1adfa 629
77db0a3c
EH
630 iwl_init_sbands(dev, cfg, data, regulatory,
631 sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
632 rx_chains);
633 }
b1e1adfa 634
33b2f684 635 data->calib_version = 255;
b1e1adfa
JB
636
637 return data;
638}
48e29340 639IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
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