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5da4b55f MA |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved. |
5da4b55f MA |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
5da4b55f MA |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
5da4b55f MA |
33 | #include <linux/init.h> |
34 | ||
35 | #include <net/mac80211.h> | |
36 | ||
37 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 38 | #include "iwl-dev.h" |
5da4b55f | 39 | #include "iwl-core.h" |
39b73fb1 | 40 | #include "iwl-io.h" |
5a36ba0e | 41 | #include "iwl-commands.h" |
5da4b55f MA |
42 | #include "iwl-debug.h" |
43 | #include "iwl-power.h" | |
5da4b55f MA |
44 | |
45 | /* | |
e312c24c | 46 | * Setting power level allows the card to go to sleep when not busy. |
5da4b55f | 47 | * |
e312c24c JB |
48 | * We calculate a sleep command based on the required latency, which |
49 | * we get from mac80211. In order to handle thermal throttling, we can | |
50 | * also use pre-defined power levels. | |
5da4b55f MA |
51 | */ |
52 | ||
e312c24c JB |
53 | /* |
54 | * For now, keep using power level 1 instead of automatically | |
55 | * adjusting ... | |
56 | */ | |
57 | bool no_sleep_autoadjust = true; | |
58 | module_param(no_sleep_autoadjust, bool, S_IRUGO); | |
59 | MODULE_PARM_DESC(no_sleep_autoadjust, | |
60 | "don't automatically adjust sleep level " | |
61 | "according to maximum network latency"); | |
5da4b55f | 62 | |
e312c24c JB |
63 | /* |
64 | * This defines the old power levels. They are still used by default | |
65 | * (level 1) and for thermal throttle (levels 3 through 5) | |
66 | */ | |
67 | ||
68 | struct iwl_power_vec_entry { | |
69 | struct iwl_powertable_cmd cmd; | |
4ad177b5 | 70 | u8 no_dtim; /* number of skip dtim */ |
e312c24c JB |
71 | }; |
72 | ||
73 | #define IWL_DTIM_RANGE_0_MAX 2 | |
74 | #define IWL_DTIM_RANGE_1_MAX 10 | |
5da4b55f | 75 | |
7af2c460 JB |
76 | #define NOSLP cpu_to_le16(0), 0, 0 |
77 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0 | |
35162ba7 WYG |
78 | #define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK | \ |
79 | IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \ | |
80 | IWL_POWER_ADVANCE_PM_ENA_MSK) | |
81 | #define ASLP_TOUT(T) cpu_to_le32(T) | |
7af2c460 JB |
82 | #define TU_TO_USEC 1024 |
83 | #define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC) | |
84 | #define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \ | |
85 | cpu_to_le32(X1), \ | |
86 | cpu_to_le32(X2), \ | |
87 | cpu_to_le32(X3), \ | |
88 | cpu_to_le32(X4)} | |
5da4b55f | 89 | /* default power management (not Tx power) table values */ |
e312c24c | 90 | /* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */ |
4ad177b5 | 91 | /* DTIM 0 - 2 */ |
7af2c460 | 92 | static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = { |
4ad177b5 | 93 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0}, |
5da4b55f MA |
94 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0}, |
95 | {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0}, | |
96 | {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1}, | |
97 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2} | |
98 | }; | |
99 | ||
100 | ||
e312c24c | 101 | /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */ |
4ad177b5 | 102 | /* DTIM 3 - 10 */ |
7af2c460 | 103 | static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = { |
5da4b55f MA |
104 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, |
105 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0}, | |
106 | {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0}, | |
107 | {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1}, | |
4ad177b5 | 108 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2} |
5da4b55f MA |
109 | }; |
110 | ||
e312c24c | 111 | /* for DTIM period > IWL_DTIM_RANGE_1_MAX */ |
4ad177b5 | 112 | /* DTIM 11 - */ |
7af2c460 | 113 | static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = { |
5da4b55f MA |
114 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, |
115 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
116 | {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
117 | {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
118 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
119 | }; | |
120 | ||
35162ba7 WYG |
121 | /* advance power management */ |
122 | /* DTIM 0 - 2 */ | |
123 | static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = { | |
124 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
125 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
126 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
127 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
128 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
129 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
130 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
131 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
132 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
133 | SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2} | |
134 | }; | |
135 | ||
136 | ||
137 | /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */ | |
138 | /* DTIM 3 - 10 */ | |
139 | static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = { | |
140 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
141 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
142 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
143 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
144 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
145 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
146 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
147 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
148 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
149 | SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2} | |
150 | }; | |
151 | ||
152 | /* for DTIM period > IWL_DTIM_RANGE_1_MAX */ | |
153 | /* DTIM 11 - */ | |
154 | static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = { | |
155 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
156 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
157 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
158 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
159 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
160 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
161 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
162 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
163 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
164 | SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2} | |
165 | }; | |
166 | ||
e312c24c JB |
167 | static void iwl_static_sleep_cmd(struct iwl_priv *priv, |
168 | struct iwl_powertable_cmd *cmd, | |
169 | enum iwl_power_level lvl, int period) | |
170 | { | |
171 | const struct iwl_power_vec_entry *table; | |
4ad177b5 WYG |
172 | int max_sleep[IWL_POWER_VEC_SIZE] = { 0 }; |
173 | int i; | |
174 | u8 skip; | |
175 | u32 slp_itrvl; | |
e312c24c | 176 | |
35162ba7 WYG |
177 | if (priv->cfg->adv_pm) { |
178 | table = apm_range_2; | |
179 | if (period <= IWL_DTIM_RANGE_1_MAX) | |
180 | table = apm_range_1; | |
181 | if (period <= IWL_DTIM_RANGE_0_MAX) | |
182 | table = apm_range_0; | |
183 | } else { | |
184 | table = range_2; | |
185 | if (period <= IWL_DTIM_RANGE_1_MAX) | |
186 | table = range_1; | |
187 | if (period <= IWL_DTIM_RANGE_0_MAX) | |
188 | table = range_0; | |
189 | } | |
e312c24c JB |
190 | |
191 | BUG_ON(lvl < 0 || lvl >= IWL_POWER_NUM); | |
192 | ||
193 | *cmd = table[lvl].cmd; | |
194 | ||
195 | if (period == 0) { | |
4ad177b5 | 196 | skip = 0; |
e312c24c | 197 | period = 1; |
4ad177b5 WYG |
198 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) |
199 | max_sleep[i] = 1; | |
200 | ||
e312c24c | 201 | } else { |
4ad177b5 WYG |
202 | skip = table[lvl].no_dtim; |
203 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) | |
204 | max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]); | |
205 | max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1; | |
e312c24c JB |
206 | } |
207 | ||
4ad177b5 WYG |
208 | slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]); |
209 | /* figure out the listen interval based on dtim period and skip */ | |
210 | if (slp_itrvl == 0xFF) | |
211 | cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] = | |
212 | cpu_to_le32(period * (skip + 1)); | |
213 | ||
214 | slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]); | |
215 | if (slp_itrvl > period) | |
216 | cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] = | |
217 | cpu_to_le32((slp_itrvl / period) * period); | |
218 | ||
219 | if (skip) | |
e312c24c | 220 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; |
4ad177b5 | 221 | else |
e312c24c | 222 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; |
e312c24c | 223 | |
1f37daf3 WYG |
224 | if (priv->cfg->base_params->shadow_reg_enable) |
225 | cmd->flags |= IWL_POWER_SHADOW_REG_ENA; | |
226 | else | |
227 | cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA; | |
228 | ||
e366176e WYG |
229 | if (priv->cfg->bt_params && |
230 | priv->cfg->bt_params->advanced_bt_coexist) { | |
231 | if (!priv->cfg->bt_params->bt_sco_disable) | |
232 | cmd->flags |= IWL_POWER_BT_SCO_ENA; | |
233 | else | |
234 | cmd->flags &= ~IWL_POWER_BT_SCO_ENA; | |
235 | } | |
236 | ||
237 | ||
4ad177b5 | 238 | slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]); |
570af86e | 239 | if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL) |
4ad177b5 | 240 | cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] = |
570af86e | 241 | cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL); |
4ad177b5 WYG |
242 | |
243 | /* enforce max sleep interval */ | |
244 | for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) { | |
245 | if (le32_to_cpu(cmd->sleep_interval[i]) > | |
246 | (max_sleep[i] * period)) | |
247 | cmd->sleep_interval[i] = | |
248 | cpu_to_le32(max_sleep[i] * period); | |
249 | if (i != (IWL_POWER_VEC_SIZE - 1)) { | |
250 | if (le32_to_cpu(cmd->sleep_interval[i]) > | |
251 | le32_to_cpu(cmd->sleep_interval[i+1])) | |
252 | cmd->sleep_interval[i] = | |
253 | cmd->sleep_interval[i+1]; | |
254 | } | |
255 | } | |
e312c24c JB |
256 | |
257 | if (priv->power_data.pci_pm) | |
258 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
259 | else | |
260 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
261 | ||
4ad177b5 WYG |
262 | IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n", |
263 | skip, period); | |
e312c24c JB |
264 | IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1); |
265 | } | |
266 | ||
e312c24c JB |
267 | static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv, |
268 | struct iwl_powertable_cmd *cmd) | |
5da4b55f | 269 | { |
e312c24c | 270 | memset(cmd, 0, sizeof(*cmd)); |
5da4b55f | 271 | |
e312c24c JB |
272 | if (priv->power_data.pci_pm) |
273 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
5da4b55f | 274 | |
e312c24c | 275 | IWL_DEBUG_POWER(priv, "Sleep command for CAM\n"); |
5da4b55f MA |
276 | } |
277 | ||
e312c24c JB |
278 | static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv, |
279 | struct iwl_powertable_cmd *cmd, | |
280 | int dynps_ms, int wakeup_period) | |
5da4b55f | 281 | { |
4c561a02 JB |
282 | /* |
283 | * These are the original power level 3 sleep successions. The | |
284 | * device may behave better with such succession and was also | |
285 | * only tested with that. Just like the original sleep commands, | |
286 | * also adjust the succession here to the wakeup_period below. | |
287 | * The ranges are the same as for the sleep commands, 0-2, 3-9 | |
288 | * and >10, which is selected based on the DTIM interval for | |
289 | * the sleep index but here we use the wakeup period since that | |
290 | * is what we need to do for the latency requirements. | |
291 | */ | |
292 | static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 }; | |
293 | static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 }; | |
294 | static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF }; | |
295 | const u8 *slp_succ = slp_succ_r0; | |
5cd19c5f | 296 | int i; |
5da4b55f | 297 | |
4c561a02 JB |
298 | if (wakeup_period > IWL_DTIM_RANGE_0_MAX) |
299 | slp_succ = slp_succ_r1; | |
300 | if (wakeup_period > IWL_DTIM_RANGE_1_MAX) | |
301 | slp_succ = slp_succ_r2; | |
302 | ||
e312c24c | 303 | memset(cmd, 0, sizeof(*cmd)); |
5cd19c5f | 304 | |
e312c24c JB |
305 | cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK | |
306 | IWL_POWER_FAST_PD; /* no use seeing frames for others */ | |
5da4b55f | 307 | |
e312c24c JB |
308 | if (priv->power_data.pci_pm) |
309 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
5da4b55f | 310 | |
1f37daf3 WYG |
311 | if (priv->cfg->base_params->shadow_reg_enable) |
312 | cmd->flags |= IWL_POWER_SHADOW_REG_ENA; | |
313 | else | |
314 | cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA; | |
315 | ||
e366176e WYG |
316 | if (priv->cfg->bt_params && |
317 | priv->cfg->bt_params->advanced_bt_coexist) { | |
318 | if (!priv->cfg->bt_params->bt_sco_disable) | |
319 | cmd->flags |= IWL_POWER_BT_SCO_ENA; | |
320 | else | |
321 | cmd->flags &= ~IWL_POWER_BT_SCO_ENA; | |
322 | } | |
323 | ||
e312c24c JB |
324 | cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms); |
325 | cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms); | |
5da4b55f | 326 | |
5cd19c5f | 327 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) |
4c561a02 JB |
328 | cmd->sleep_interval[i] = |
329 | cpu_to_le32(min_t(int, slp_succ[i], wakeup_period)); | |
e312c24c JB |
330 | |
331 | IWL_DEBUG_POWER(priv, "Automatic sleep command\n"); | |
332 | } | |
5da4b55f | 333 | |
e312c24c JB |
334 | static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd) |
335 | { | |
336 | IWL_DEBUG_POWER(priv, "Sending power/sleep command\n"); | |
e1623446 TW |
337 | IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags); |
338 | IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
339 | IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
340 | IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
5da4b55f MA |
341 | le32_to_cpu(cmd->sleep_interval[0]), |
342 | le32_to_cpu(cmd->sleep_interval[1]), | |
343 | le32_to_cpu(cmd->sleep_interval[2]), | |
344 | le32_to_cpu(cmd->sleep_interval[3]), | |
345 | le32_to_cpu(cmd->sleep_interval[4])); | |
346 | ||
e312c24c JB |
347 | return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD, |
348 | sizeof(struct iwl_powertable_cmd), cmd); | |
5da4b55f MA |
349 | } |
350 | ||
ac4f5457 SG |
351 | static void iwl_power_build_cmd(struct iwl_priv *priv, |
352 | struct iwl_powertable_cmd *cmd) | |
5da4b55f | 353 | { |
4d695921 | 354 | bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS; |
e312c24c | 355 | int dtimper; |
5da4b55f | 356 | |
3a065ab3 | 357 | dtimper = priv->hw->conf.ps_dtim_period ?: 1; |
e312c24c | 358 | |
7cb1b088 | 359 | if (priv->cfg->base_params->broken_powersave) |
ac4f5457 | 360 | iwl_power_sleep_cam_cmd(priv, cmd); |
7cb1b088 | 361 | else if (priv->cfg->base_params->supports_idle && |
78f5fb7f | 362 | priv->hw->conf.flags & IEEE80211_CONF_IDLE) |
ac4f5457 | 363 | iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20); |
0975cc8f | 364 | else if (priv->cfg->ops->lib->tt_ops.lower_power_detection && |
6ddbf8cd WYG |
365 | priv->cfg->ops->lib->tt_ops.tt_power_mode && |
366 | priv->cfg->ops->lib->tt_ops.lower_power_detection(priv)) { | |
367 | /* in thermal throttling low power state */ | |
ac4f5457 | 368 | iwl_static_sleep_cmd(priv, cmd, |
6ddbf8cd | 369 | priv->cfg->ops->lib->tt_ops.tt_power_mode(priv), dtimper); |
0975cc8f | 370 | } else if (!enabled) |
ac4f5457 | 371 | iwl_power_sleep_cam_cmd(priv, cmd); |
e312c24c | 372 | else if (priv->power_data.debug_sleep_level_override >= 0) |
ac4f5457 | 373 | iwl_static_sleep_cmd(priv, cmd, |
e312c24c JB |
374 | priv->power_data.debug_sleep_level_override, |
375 | dtimper); | |
376 | else if (no_sleep_autoadjust) | |
ac4f5457 | 377 | iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper); |
e312c24c | 378 | else |
ac4f5457 | 379 | iwl_power_fill_sleep_cmd(priv, cmd, |
e312c24c JB |
380 | priv->hw->conf.dynamic_ps_timeout, |
381 | priv->hw->conf.max_sleep_period); | |
ac4f5457 SG |
382 | } |
383 | ||
384 | int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd, | |
385 | bool force) | |
386 | { | |
387 | int ret; | |
388 | bool update_chains; | |
389 | ||
390 | lockdep_assert_held(&priv->mutex); | |
391 | ||
392 | /* Don't update the RX chain when chain noise calibration is running */ | |
393 | update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE || | |
394 | priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE; | |
395 | ||
396 | if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force) | |
397 | return 0; | |
398 | ||
399 | if (!iwl_is_ready_rf(priv)) | |
400 | return -EIO; | |
401 | ||
402 | /* scan complete use sleep_power_next, need to be updated */ | |
403 | memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd)); | |
404 | if (test_bit(STATUS_SCANNING, &priv->status) && !force) { | |
405 | IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n"); | |
406 | return 0; | |
407 | } | |
408 | ||
409 | if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK) | |
410 | set_bit(STATUS_POWER_PMI, &priv->status); | |
5da4b55f | 411 | |
ac4f5457 SG |
412 | ret = iwl_set_power(priv, cmd); |
413 | if (!ret) { | |
414 | if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)) | |
415 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
416 | ||
417 | if (priv->cfg->ops->lib->update_chain_flags && update_chains) | |
418 | priv->cfg->ops->lib->update_chain_flags(priv); | |
419 | else if (priv->cfg->ops->lib->update_chain_flags) | |
420 | IWL_DEBUG_POWER(priv, | |
3a780d25 | 421 | "Cannot update the power, chain noise " |
a71c8f62 WT |
422 | "calibration running: %d\n", |
423 | priv->chain_noise_data.state); | |
ac4f5457 SG |
424 | |
425 | memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)); | |
426 | } else | |
427 | IWL_ERR(priv, "set power fail, ret = %d", ret); | |
5da4b55f MA |
428 | |
429 | return ret; | |
430 | } | |
ac4f5457 SG |
431 | EXPORT_SYMBOL(iwl_power_set_mode); |
432 | ||
433 | int iwl_power_update_mode(struct iwl_priv *priv, bool force) | |
434 | { | |
435 | struct iwl_powertable_cmd cmd; | |
436 | ||
437 | iwl_power_build_cmd(priv, &cmd); | |
438 | return iwl_power_set_mode(priv, &cmd, force); | |
439 | } | |
5da4b55f MA |
440 | EXPORT_SYMBOL(iwl_power_update_mode); |
441 | ||
a96a27f9 | 442 | /* initialize to default */ |
5da4b55f MA |
443 | void iwl_power_initialize(struct iwl_priv *priv) |
444 | { | |
e312c24c JB |
445 | u16 lctl = iwl_pcie_link_ctl(priv); |
446 | ||
447 | priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); | |
448 | ||
449 | priv->power_data.debug_sleep_level_override = -1; | |
450 | ||
451 | memset(&priv->power_data.sleep_cmd, 0, | |
452 | sizeof(priv->power_data.sleep_cmd)); | |
5da4b55f MA |
453 | } |
454 | EXPORT_SYMBOL(iwl_power_initialize); |