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5da4b55f MA |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved. |
5da4b55f MA |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
5da4b55f MA |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
5da4b55f MA |
33 | #include <linux/init.h> |
34 | ||
35 | #include <net/mac80211.h> | |
36 | ||
37 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 38 | #include "iwl-dev.h" |
3f1e5f4a | 39 | #include "iwl-agn.h" |
5da4b55f | 40 | #include "iwl-core.h" |
39b73fb1 | 41 | #include "iwl-io.h" |
5a36ba0e | 42 | #include "iwl-commands.h" |
5da4b55f MA |
43 | #include "iwl-debug.h" |
44 | #include "iwl-power.h" | |
bdfbf092 | 45 | #include "iwl-trans.h" |
48f20d35 | 46 | #include "iwl-shared.h" |
5da4b55f MA |
47 | |
48 | /* | |
e312c24c | 49 | * Setting power level allows the card to go to sleep when not busy. |
5da4b55f | 50 | * |
e312c24c JB |
51 | * We calculate a sleep command based on the required latency, which |
52 | * we get from mac80211. In order to handle thermal throttling, we can | |
53 | * also use pre-defined power levels. | |
5da4b55f MA |
54 | */ |
55 | ||
e312c24c JB |
56 | /* |
57 | * This defines the old power levels. They are still used by default | |
58 | * (level 1) and for thermal throttle (levels 3 through 5) | |
59 | */ | |
60 | ||
61 | struct iwl_power_vec_entry { | |
62 | struct iwl_powertable_cmd cmd; | |
4ad177b5 | 63 | u8 no_dtim; /* number of skip dtim */ |
e312c24c JB |
64 | }; |
65 | ||
66 | #define IWL_DTIM_RANGE_0_MAX 2 | |
67 | #define IWL_DTIM_RANGE_1_MAX 10 | |
5da4b55f | 68 | |
7af2c460 JB |
69 | #define NOSLP cpu_to_le16(0), 0, 0 |
70 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0 | |
35162ba7 WYG |
71 | #define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK | \ |
72 | IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \ | |
73 | IWL_POWER_ADVANCE_PM_ENA_MSK) | |
74 | #define ASLP_TOUT(T) cpu_to_le32(T) | |
7af2c460 JB |
75 | #define TU_TO_USEC 1024 |
76 | #define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC) | |
77 | #define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \ | |
78 | cpu_to_le32(X1), \ | |
79 | cpu_to_le32(X2), \ | |
80 | cpu_to_le32(X3), \ | |
81 | cpu_to_le32(X4)} | |
5da4b55f | 82 | /* default power management (not Tx power) table values */ |
e312c24c | 83 | /* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */ |
4ad177b5 | 84 | /* DTIM 0 - 2 */ |
7af2c460 | 85 | static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = { |
4ad177b5 | 86 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0}, |
5da4b55f MA |
87 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0}, |
88 | {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0}, | |
89 | {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1}, | |
90 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2} | |
91 | }; | |
92 | ||
93 | ||
e312c24c | 94 | /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */ |
4ad177b5 | 95 | /* DTIM 3 - 10 */ |
7af2c460 | 96 | static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = { |
5da4b55f MA |
97 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, |
98 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0}, | |
99 | {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0}, | |
100 | {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1}, | |
4ad177b5 | 101 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2} |
5da4b55f MA |
102 | }; |
103 | ||
e312c24c | 104 | /* for DTIM period > IWL_DTIM_RANGE_1_MAX */ |
4ad177b5 | 105 | /* DTIM 11 - */ |
7af2c460 | 106 | static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = { |
5da4b55f MA |
107 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, |
108 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
109 | {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
110 | {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
111 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
112 | }; | |
113 | ||
35162ba7 WYG |
114 | /* advance power management */ |
115 | /* DTIM 0 - 2 */ | |
116 | static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = { | |
117 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
118 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
119 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
120 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
121 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
122 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
123 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
124 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
125 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
126 | SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2} | |
127 | }; | |
128 | ||
129 | ||
130 | /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */ | |
131 | /* DTIM 3 - 10 */ | |
132 | static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = { | |
133 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
134 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
135 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
136 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
137 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
138 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
139 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
140 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
141 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
142 | SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2} | |
143 | }; | |
144 | ||
145 | /* for DTIM period > IWL_DTIM_RANGE_1_MAX */ | |
146 | /* DTIM 11 - */ | |
147 | static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = { | |
148 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
149 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
150 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
151 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
152 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
153 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
154 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
155 | SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0}, | |
156 | {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50), | |
157 | SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2} | |
158 | }; | |
159 | ||
e312c24c JB |
160 | static void iwl_static_sleep_cmd(struct iwl_priv *priv, |
161 | struct iwl_powertable_cmd *cmd, | |
162 | enum iwl_power_level lvl, int period) | |
163 | { | |
164 | const struct iwl_power_vec_entry *table; | |
4ad177b5 WYG |
165 | int max_sleep[IWL_POWER_VEC_SIZE] = { 0 }; |
166 | int i; | |
167 | u8 skip; | |
168 | u32 slp_itrvl; | |
e312c24c | 169 | |
38622419 | 170 | if (cfg(priv)->adv_pm) { |
35162ba7 WYG |
171 | table = apm_range_2; |
172 | if (period <= IWL_DTIM_RANGE_1_MAX) | |
173 | table = apm_range_1; | |
174 | if (period <= IWL_DTIM_RANGE_0_MAX) | |
175 | table = apm_range_0; | |
176 | } else { | |
177 | table = range_2; | |
178 | if (period <= IWL_DTIM_RANGE_1_MAX) | |
179 | table = range_1; | |
180 | if (period <= IWL_DTIM_RANGE_0_MAX) | |
181 | table = range_0; | |
182 | } | |
e312c24c | 183 | |
3e41ace5 JB |
184 | if (WARN_ON(lvl < 0 || lvl >= IWL_POWER_NUM)) |
185 | memset(cmd, 0, sizeof(*cmd)); | |
186 | else | |
187 | *cmd = table[lvl].cmd; | |
e312c24c JB |
188 | |
189 | if (period == 0) { | |
4ad177b5 | 190 | skip = 0; |
e312c24c | 191 | period = 1; |
4ad177b5 WYG |
192 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) |
193 | max_sleep[i] = 1; | |
194 | ||
e312c24c | 195 | } else { |
4ad177b5 WYG |
196 | skip = table[lvl].no_dtim; |
197 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) | |
198 | max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]); | |
199 | max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1; | |
e312c24c JB |
200 | } |
201 | ||
4ad177b5 WYG |
202 | slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]); |
203 | /* figure out the listen interval based on dtim period and skip */ | |
204 | if (slp_itrvl == 0xFF) | |
205 | cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] = | |
206 | cpu_to_le32(period * (skip + 1)); | |
207 | ||
208 | slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]); | |
209 | if (slp_itrvl > period) | |
210 | cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] = | |
211 | cpu_to_le32((slp_itrvl / period) * period); | |
212 | ||
213 | if (skip) | |
e312c24c | 214 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; |
4ad177b5 | 215 | else |
e312c24c | 216 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; |
e312c24c | 217 | |
fd656935 | 218 | if (hw_params(priv).shadow_reg_enable) |
1f37daf3 WYG |
219 | cmd->flags |= IWL_POWER_SHADOW_REG_ENA; |
220 | else | |
221 | cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA; | |
222 | ||
88e58fc5 | 223 | if (iwl_advanced_bt_coexist(priv)) { |
38622419 | 224 | if (!cfg(priv)->bt_params->bt_sco_disable) |
e366176e WYG |
225 | cmd->flags |= IWL_POWER_BT_SCO_ENA; |
226 | else | |
227 | cmd->flags &= ~IWL_POWER_BT_SCO_ENA; | |
228 | } | |
229 | ||
230 | ||
4ad177b5 | 231 | slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]); |
570af86e | 232 | if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL) |
4ad177b5 | 233 | cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] = |
570af86e | 234 | cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL); |
4ad177b5 WYG |
235 | |
236 | /* enforce max sleep interval */ | |
237 | for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) { | |
238 | if (le32_to_cpu(cmd->sleep_interval[i]) > | |
239 | (max_sleep[i] * period)) | |
240 | cmd->sleep_interval[i] = | |
241 | cpu_to_le32(max_sleep[i] * period); | |
242 | if (i != (IWL_POWER_VEC_SIZE - 1)) { | |
243 | if (le32_to_cpu(cmd->sleep_interval[i]) > | |
244 | le32_to_cpu(cmd->sleep_interval[i+1])) | |
245 | cmd->sleep_interval[i] = | |
246 | cmd->sleep_interval[i+1]; | |
247 | } | |
248 | } | |
e312c24c | 249 | |
d57fa99d | 250 | if (priv->power_data.bus_pm) |
e312c24c JB |
251 | cmd->flags |= IWL_POWER_PCI_PM_MSK; |
252 | else | |
253 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
254 | ||
4ad177b5 WYG |
255 | IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n", |
256 | skip, period); | |
e312c24c JB |
257 | IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1); |
258 | } | |
259 | ||
e312c24c JB |
260 | static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv, |
261 | struct iwl_powertable_cmd *cmd) | |
5da4b55f | 262 | { |
e312c24c | 263 | memset(cmd, 0, sizeof(*cmd)); |
5da4b55f | 264 | |
d57fa99d | 265 | if (priv->power_data.bus_pm) |
e312c24c | 266 | cmd->flags |= IWL_POWER_PCI_PM_MSK; |
5da4b55f | 267 | |
e312c24c | 268 | IWL_DEBUG_POWER(priv, "Sleep command for CAM\n"); |
5da4b55f MA |
269 | } |
270 | ||
e312c24c JB |
271 | static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv, |
272 | struct iwl_powertable_cmd *cmd, | |
273 | int dynps_ms, int wakeup_period) | |
5da4b55f | 274 | { |
4c561a02 JB |
275 | /* |
276 | * These are the original power level 3 sleep successions. The | |
277 | * device may behave better with such succession and was also | |
278 | * only tested with that. Just like the original sleep commands, | |
279 | * also adjust the succession here to the wakeup_period below. | |
280 | * The ranges are the same as for the sleep commands, 0-2, 3-9 | |
281 | * and >10, which is selected based on the DTIM interval for | |
282 | * the sleep index but here we use the wakeup period since that | |
283 | * is what we need to do for the latency requirements. | |
284 | */ | |
285 | static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 }; | |
286 | static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 }; | |
287 | static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF }; | |
288 | const u8 *slp_succ = slp_succ_r0; | |
5cd19c5f | 289 | int i; |
5da4b55f | 290 | |
4c561a02 JB |
291 | if (wakeup_period > IWL_DTIM_RANGE_0_MAX) |
292 | slp_succ = slp_succ_r1; | |
293 | if (wakeup_period > IWL_DTIM_RANGE_1_MAX) | |
294 | slp_succ = slp_succ_r2; | |
295 | ||
e312c24c | 296 | memset(cmd, 0, sizeof(*cmd)); |
5cd19c5f | 297 | |
e312c24c JB |
298 | cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK | |
299 | IWL_POWER_FAST_PD; /* no use seeing frames for others */ | |
5da4b55f | 300 | |
d57fa99d | 301 | if (priv->power_data.bus_pm) |
e312c24c | 302 | cmd->flags |= IWL_POWER_PCI_PM_MSK; |
5da4b55f | 303 | |
fd656935 | 304 | if (hw_params(priv).shadow_reg_enable) |
1f37daf3 WYG |
305 | cmd->flags |= IWL_POWER_SHADOW_REG_ENA; |
306 | else | |
307 | cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA; | |
308 | ||
88e58fc5 | 309 | if (iwl_advanced_bt_coexist(priv)) { |
38622419 | 310 | if (!cfg(priv)->bt_params->bt_sco_disable) |
e366176e WYG |
311 | cmd->flags |= IWL_POWER_BT_SCO_ENA; |
312 | else | |
313 | cmd->flags &= ~IWL_POWER_BT_SCO_ENA; | |
314 | } | |
315 | ||
e312c24c JB |
316 | cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms); |
317 | cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms); | |
5da4b55f | 318 | |
5cd19c5f | 319 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) |
4c561a02 JB |
320 | cmd->sleep_interval[i] = |
321 | cpu_to_le32(min_t(int, slp_succ[i], wakeup_period)); | |
e312c24c JB |
322 | |
323 | IWL_DEBUG_POWER(priv, "Automatic sleep command\n"); | |
324 | } | |
5da4b55f | 325 | |
e312c24c JB |
326 | static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd) |
327 | { | |
328 | IWL_DEBUG_POWER(priv, "Sending power/sleep command\n"); | |
e1623446 TW |
329 | IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags); |
330 | IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
331 | IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
332 | IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
5da4b55f MA |
333 | le32_to_cpu(cmd->sleep_interval[0]), |
334 | le32_to_cpu(cmd->sleep_interval[1]), | |
335 | le32_to_cpu(cmd->sleep_interval[2]), | |
336 | le32_to_cpu(cmd->sleep_interval[3]), | |
337 | le32_to_cpu(cmd->sleep_interval[4])); | |
338 | ||
e6bb4c9c | 339 | return iwl_trans_send_cmd_pdu(trans(priv), POWER_TABLE_CMD, CMD_SYNC, |
e312c24c | 340 | sizeof(struct iwl_powertable_cmd), cmd); |
5da4b55f MA |
341 | } |
342 | ||
ac4f5457 SG |
343 | static void iwl_power_build_cmd(struct iwl_priv *priv, |
344 | struct iwl_powertable_cmd *cmd) | |
5da4b55f | 345 | { |
4d695921 | 346 | bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS; |
e312c24c | 347 | int dtimper; |
5da4b55f | 348 | |
3a065ab3 | 349 | dtimper = priv->hw->conf.ps_dtim_period ?: 1; |
e312c24c | 350 | |
57210f7c | 351 | if (priv->shrd->wowlan) |
c8ac61cf | 352 | iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper); |
38622419 | 353 | else if (!cfg(priv)->base_params->no_idle_support && |
f3529108 | 354 | priv->hw->conf.flags & IEEE80211_CONF_IDLE) |
ac4f5457 | 355 | iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20); |
f42e7662 | 356 | else if (iwl_tt_is_low_power_state(priv)) { |
6ddbf8cd | 357 | /* in thermal throttling low power state */ |
ac4f5457 | 358 | iwl_static_sleep_cmd(priv, cmd, |
f42e7662 | 359 | iwl_tt_current_power_mode(priv), dtimper); |
0975cc8f | 360 | } else if (!enabled) |
ac4f5457 | 361 | iwl_power_sleep_cam_cmd(priv, cmd); |
e312c24c | 362 | else if (priv->power_data.debug_sleep_level_override >= 0) |
ac4f5457 | 363 | iwl_static_sleep_cmd(priv, cmd, |
e312c24c JB |
364 | priv->power_data.debug_sleep_level_override, |
365 | dtimper); | |
f7538168 WYG |
366 | else if (iwlagn_mod_params.no_sleep_autoadjust) { |
367 | if (iwlagn_mod_params.power_level > IWL_POWER_INDEX_1 && | |
368 | iwlagn_mod_params.power_level <= IWL_POWER_INDEX_5) | |
369 | iwl_static_sleep_cmd(priv, cmd, | |
370 | iwlagn_mod_params.power_level, dtimper); | |
371 | else | |
372 | iwl_static_sleep_cmd(priv, cmd, | |
373 | IWL_POWER_INDEX_1, dtimper); | |
374 | } else | |
ac4f5457 | 375 | iwl_power_fill_sleep_cmd(priv, cmd, |
e312c24c JB |
376 | priv->hw->conf.dynamic_ps_timeout, |
377 | priv->hw->conf.max_sleep_period); | |
ac4f5457 SG |
378 | } |
379 | ||
380 | int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd, | |
381 | bool force) | |
382 | { | |
383 | int ret; | |
384 | bool update_chains; | |
385 | ||
6ac2f839 | 386 | lockdep_assert_held(&priv->shrd->mutex); |
ac4f5457 SG |
387 | |
388 | /* Don't update the RX chain when chain noise calibration is running */ | |
389 | update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE || | |
390 | priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE; | |
391 | ||
392 | if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force) | |
393 | return 0; | |
394 | ||
845a9c0d | 395 | if (!iwl_is_ready_rf(priv->shrd)) |
ac4f5457 SG |
396 | return -EIO; |
397 | ||
398 | /* scan complete use sleep_power_next, need to be updated */ | |
399 | memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd)); | |
63013ae3 | 400 | if (test_bit(STATUS_SCANNING, &priv->shrd->status) && !force) { |
ac4f5457 SG |
401 | IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n"); |
402 | return 0; | |
403 | } | |
404 | ||
405 | if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK) | |
63013ae3 | 406 | set_bit(STATUS_POWER_PMI, &priv->shrd->status); |
5da4b55f | 407 | |
ac4f5457 SG |
408 | ret = iwl_set_power(priv, cmd); |
409 | if (!ret) { | |
410 | if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)) | |
63013ae3 | 411 | clear_bit(STATUS_POWER_PMI, &priv->shrd->status); |
ac4f5457 | 412 | |
6b6db91c FD |
413 | if (update_chains) |
414 | iwl_update_chain_flags(priv); | |
415 | else | |
ac4f5457 | 416 | IWL_DEBUG_POWER(priv, |
3a780d25 | 417 | "Cannot update the power, chain noise " |
a71c8f62 WT |
418 | "calibration running: %d\n", |
419 | priv->chain_noise_data.state); | |
ac4f5457 SG |
420 | |
421 | memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)); | |
422 | } else | |
423 | IWL_ERR(priv, "set power fail, ret = %d", ret); | |
5da4b55f MA |
424 | |
425 | return ret; | |
426 | } | |
ac4f5457 SG |
427 | |
428 | int iwl_power_update_mode(struct iwl_priv *priv, bool force) | |
429 | { | |
430 | struct iwl_powertable_cmd cmd; | |
431 | ||
432 | iwl_power_build_cmd(priv, &cmd); | |
433 | return iwl_power_set_mode(priv, &cmd, force); | |
434 | } | |
5da4b55f | 435 | |
a96a27f9 | 436 | /* initialize to default */ |
5da4b55f MA |
437 | void iwl_power_initialize(struct iwl_priv *priv) |
438 | { | |
26bfc0cf | 439 | priv->power_data.bus_pm = bus_get_pm_support(bus(priv)); |
e312c24c JB |
440 | |
441 | priv->power_data.debug_sleep_level_override = -1; | |
442 | ||
443 | memset(&priv->power_data.sleep_cmd, 0, | |
444 | sizeof(priv->power_data.sleep_cmd)); | |
5da4b55f | 445 | } |