[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-power.c

/******************************************************************************
 *
 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *****************************************************************************/


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>

#include <net/mac80211.h>

#include "iwl-eeprom.h"
#include "iwl-dev.h"
#include "iwl-agn.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-commands.h"
#include "iwl-debug.h"
#include "iwl-power.h"
#include "iwl-trans.h"
#include "iwl-shared.h"

/*
 * Setting power level allows the card to go to sleep when not busy.
 *
 * We calculate a sleep command based on the required latency, which
 * we get from mac80211. In order to handle thermal throttling, we can
 * also use pre-defined power levels.
 */

/*
 * This defines the old power levels. They are still used by default
 * (level 1) and for thermal throttle (levels 3 through 5)
 */

struct iwl_power_vec_entry {
	struct iwl_powertable_cmd cmd;
	u8 no_dtim;	/* number of skip dtim */
};

#define IWL_DTIM_RANGE_0_MAX	2
#define IWL_DTIM_RANGE_1_MAX	10

#define NOSLP cpu_to_le16(0), 0, 0
#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK |	\
		IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
		IWL_POWER_ADVANCE_PM_ENA_MSK)
#define ASLP_TOUT(T) cpu_to_le32(T)
#define TU_TO_USEC 1024
#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
				     cpu_to_le32(X1), \
				     cpu_to_le32(X2), \
				     cpu_to_le32(X3), \
				     cpu_to_le32(X4)}
/* default power management (not Tx power) table values */
/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
};


/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
};

/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
};

/* advance power management */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};


/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
};

/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};

static void iwl_static_sleep_cmd(struct iwl_priv *priv,
				 struct iwl_powertable_cmd *cmd,
				 enum iwl_power_level lvl, int period)
{
	const struct iwl_power_vec_entry *table;
	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	int i;
	u8 skip;
	u32 slp_itrvl;

	if (cfg(priv)->adv_pm) {
		table = apm_range_2;
		if (period <= IWL_DTIM_RANGE_1_MAX)
			table = apm_range_1;
		if (period <= IWL_DTIM_RANGE_0_MAX)
			table = apm_range_0;
	} else {
		table = range_2;
		if (period <= IWL_DTIM_RANGE_1_MAX)
			table = range_1;
		if (period <= IWL_DTIM_RANGE_0_MAX)
			table = range_0;
	}

	if (WARN_ON(lvl < 0 || lvl >= IWL_POWER_NUM))
		memset(cmd, 0, sizeof(*cmd));
	else
		*cmd = table[lvl].cmd;

	if (period == 0) {
		skip = 0;
		period = 1;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] =  1;

	} else {
		skip = table[lvl].no_dtim;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
		max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
	}

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	/* figure out the listen interval based on dtim period and skip */
	if (slp_itrvl == 0xFF)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(period * (skip + 1));

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > period)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32((slp_itrvl / period) * period);

	if (skip)
		cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
	else
		cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;

	if (cfg(priv)->base_params->shadow_reg_enable)
		cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
	else
		cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;

	if (iwl_advanced_bt_coexist(priv)) {
		if (!cfg(priv)->bt_params->bt_sco_disable)
			cmd->flags |= IWL_POWER_BT_SCO_ENA;
		else
			cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	}


	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);

	/* enforce max sleep interval */
	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
		if (le32_to_cpu(cmd->sleep_interval[i]) >
		    (max_sleep[i] * period))
			cmd->sleep_interval[i] =
				cpu_to_le32(max_sleep[i] * period);
		if (i != (IWL_POWER_VEC_SIZE - 1)) {
			if (le32_to_cpu(cmd->sleep_interval[i]) >
			    le32_to_cpu(cmd->sleep_interval[i+1]))
				cmd->sleep_interval[i] =
					cmd->sleep_interval[i+1];
		}
	}

	if (priv->power_data.bus_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;
	else
		cmd->flags &= ~IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
			skip, period);
	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
}

static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
				    struct iwl_powertable_cmd *cmd)
{
	memset(cmd, 0, sizeof(*cmd));

	if (priv->power_data.bus_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
}

static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
{
	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
			le32_to_cpu(cmd->sleep_interval[0]),
			le32_to_cpu(cmd->sleep_interval[1]),
			le32_to_cpu(cmd->sleep_interval[2]),
			le32_to_cpu(cmd->sleep_interval[3]),
			le32_to_cpu(cmd->sleep_interval[4]));

	return iwl_dvm_send_cmd_pdu(priv, POWER_TABLE_CMD, CMD_SYNC,
				sizeof(struct iwl_powertable_cmd), cmd);
}

static void iwl_power_build_cmd(struct iwl_priv *priv,
				struct iwl_powertable_cmd *cmd)
{
	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
	int dtimper;

	dtimper = priv->hw->conf.ps_dtim_period ?: 1;

	if (priv->wowlan)
		iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper);
	else if (!cfg(priv)->base_params->no_idle_support &&
		 priv->hw->conf.flags & IEEE80211_CONF_IDLE)
		iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
	else if (iwl_tt_is_low_power_state(priv)) {
		/* in thermal throttling low power state */
		iwl_static_sleep_cmd(priv, cmd,
		    iwl_tt_current_power_mode(priv), dtimper);
	} else if (!enabled)
		iwl_power_sleep_cam_cmd(priv, cmd);
	else if (priv->power_data.debug_sleep_level_override >= 0)
		iwl_static_sleep_cmd(priv, cmd,
				     priv->power_data.debug_sleep_level_override,
				     dtimper);
	else {
		if (iwlagn_mod_params.power_level > IWL_POWER_INDEX_1 &&
		    iwlagn_mod_params.power_level <= IWL_POWER_INDEX_5)
			iwl_static_sleep_cmd(priv, cmd,
				iwlagn_mod_params.power_level, dtimper);
		else
			iwl_static_sleep_cmd(priv, cmd,
				IWL_POWER_INDEX_1, dtimper);
	}
}

int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
		       bool force)
{
	int ret;
	bool update_chains;

	lockdep_assert_held(&priv->mutex);

	/* Don't update the RX chain when chain noise calibration is running */
	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
			priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;

	if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
		return 0;

	if (!iwl_is_ready_rf(priv))
		return -EIO;

	/* scan complete use sleep_power_next, need to be updated */
	memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
	if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
		IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
		return 0;
	}

	if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
		iwl_dvm_set_pmi(priv, true);

	ret = iwl_set_power(priv, cmd);
	if (!ret) {
		if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
			iwl_dvm_set_pmi(priv, false);

		if (update_chains)
			iwl_update_chain_flags(priv);
		else
			IWL_DEBUG_POWER(priv,
					"Cannot update the power, chain noise "
					"calibration running: %d\n",
					priv->chain_noise_data.state);

		memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
	} else
		IWL_ERR(priv, "set power fail, ret = %d", ret);

	return ret;
}

int iwl_power_update_mode(struct iwl_priv *priv, bool force)
{
	struct iwl_powertable_cmd cmd;

	iwl_power_build_cmd(priv, &cmd);
	return iwl_power_set_mode(priv, &cmd, force);
}

/* initialize to default */
void iwl_power_initialize(struct iwl_priv *priv)
{
	priv->power_data.bus_pm = trans(priv)->pm_support;

	priv->power_data.debug_sleep_level_override = -1;

	memset(&priv->power_data.sleep_cmd, 0,
		sizeof(priv->power_data.sleep_cmd));
}
Commit	Line	Data
5da4b55f MA	1	/******************************************************************************
5da4b55f MA	2	*
4e318262	3	* Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
5da4b55f MA	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
759ef89f	25	* Intel Linux Wireless <ilw@linux.intel.com>
5da4b55f MA	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*****************************************************************************/
	28
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
5a0e3ad6	32	#include <linux/slab.h>
5da4b55f MA	33	#include <linux/init.h>
	34
	35	#include <net/mac80211.h>
	36
	37	#include "iwl-eeprom.h"
3e0d4cb1	38	#include "iwl-dev.h"
3f1e5f4a	39	#include "iwl-agn.h"
5da4b55f	40	#include "iwl-core.h"
39b73fb1	41	#include "iwl-io.h"
5a36ba0e	42	#include "iwl-commands.h"
5da4b55f MA	43	#include "iwl-debug.h"
5da4b55f MA	44	#include "iwl-power.h"
bdfbf092	45	#include "iwl-trans.h"
48f20d35	46	#include "iwl-shared.h"
5da4b55f MA	47
5da4b55f MA	48	/*
e312c24c	49	* Setting power level allows the card to go to sleep when not busy.
5da4b55f	50	*
e312c24c JB	51	* We calculate a sleep command based on the required latency, which
	52	* we get from mac80211. In order to handle thermal throttling, we can
	53	* also use pre-defined power levels.
5da4b55f MA	54	*/
5da4b55f MA	55
e312c24c JB	56	/*
	57	* This defines the old power levels. They are still used by default
	58	* (level 1) and for thermal throttle (levels 3 through 5)
	59	*/
	60
	61	struct iwl_power_vec_entry {
	62	struct iwl_powertable_cmd cmd;
4ad177b5	63	u8 no_dtim; /* number of skip dtim */
e312c24c JB	64	};
	65
	66	#define IWL_DTIM_RANGE_0_MAX 2
	67	#define IWL_DTIM_RANGE_1_MAX 10
5da4b55f	68
7af2c460 JB	69	#define NOSLP cpu_to_le16(0), 0, 0
7af2c460 JB	70	#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
35162ba7 WYG	71	#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK \| \
	72	IWL_POWER_POWER_MANAGEMENT_ENA_MSK \| \
	73	IWL_POWER_ADVANCE_PM_ENA_MSK)
	74	#define ASLP_TOUT(T) cpu_to_le32(T)
7af2c460 JB	75	#define TU_TO_USEC 1024
	76	#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
	77	#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
	78	cpu_to_le32(X1), \
	79	cpu_to_le32(X2), \
	80	cpu_to_le32(X3), \
	81	cpu_to_le32(X4)}
5da4b55f	82	/* default power management (not Tx power) table values */
e312c24c	83	/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
4ad177b5	84	/* DTIM 0 - 2 */
7af2c460	85	static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
4ad177b5	86	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
5da4b55f MA	87	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	88	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	89	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	90	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
	91	};
	92
	93
e312c24c	94	/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
4ad177b5	95	/* DTIM 3 - 10 */
7af2c460	96	static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
5da4b55f MA	97	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	98	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	99	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	100	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
4ad177b5	101	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
5da4b55f MA	102	};
5da4b55f MA	103
e312c24c	104	/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
4ad177b5	105	/* DTIM 11 - */
7af2c460	106	static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
5da4b55f MA	107	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	108	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	109	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	110	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	111	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
	112	};
	113
35162ba7 WYG	114	/* advance power management */
	115	/* DTIM 0 - 2 */
	116	static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
	117	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	118	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	119	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	120	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	121	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	122	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	123	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	124	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	125	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	126	SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
	127	};
	128
	129
	130	/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
	131	/* DTIM 3 - 10 */
	132	static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
	133	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	134	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	135	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	136	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	137	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	138	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	139	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	140	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	141	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	142	SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
	143	};
	144
	145	/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
	146	/* DTIM 11 - */
	147	static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
	148	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	149	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	150	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	151	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	152	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	153	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	154	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	155	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	156	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	157	SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
	158	};
	159
e312c24c JB	160	static void iwl_static_sleep_cmd(struct iwl_priv *priv,
	161	struct iwl_powertable_cmd *cmd,
	162	enum iwl_power_level lvl, int period)
	163	{
	164	const struct iwl_power_vec_entry *table;
4ad177b5 WYG	165	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	166	int i;
	167	u8 skip;
	168	u32 slp_itrvl;
e312c24c	169
38622419	170	if (cfg(priv)->adv_pm) {
35162ba7 WYG	171	table = apm_range_2;
	172	if (period <= IWL_DTIM_RANGE_1_MAX)
	173	table = apm_range_1;
	174	if (period <= IWL_DTIM_RANGE_0_MAX)
	175	table = apm_range_0;
	176	} else {
	177	table = range_2;
	178	if (period <= IWL_DTIM_RANGE_1_MAX)
	179	table = range_1;
	180	if (period <= IWL_DTIM_RANGE_0_MAX)
	181	table = range_0;
	182	}
e312c24c	183
3e41ace5 JB	184	if (WARN_ON(lvl < 0 \|\| lvl >= IWL_POWER_NUM))
	185	memset(cmd, 0, sizeof(*cmd));
	186	else
	187	*cmd = table[lvl].cmd;
e312c24c JB	188
e312c24c JB	189	if (period == 0) {
4ad177b5	190	skip = 0;
e312c24c	191	period = 1;
4ad177b5 WYG	192	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	193	max_sleep[i] = 1;
	194
e312c24c	195	} else {
4ad177b5 WYG	196	skip = table[lvl].no_dtim;
	197	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	198	max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
	199	max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
e312c24c JB	200	}
e312c24c JB	201
4ad177b5 WYG	202	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	203	/* figure out the listen interval based on dtim period and skip */
	204	if (slp_itrvl == 0xFF)
	205	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	206	cpu_to_le32(period * (skip + 1));
	207
	208	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	209	if (slp_itrvl > period)
	210	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	211	cpu_to_le32((slp_itrvl / period) * period);
	212
	213	if (skip)
e312c24c	214	cmd->flags \|= IWL_POWER_SLEEP_OVER_DTIM_MSK;
4ad177b5	215	else
e312c24c	216	cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
e312c24c	217
0dde86b2	218	if (cfg(priv)->base_params->shadow_reg_enable)
1f37daf3 WYG	219	cmd->flags \|= IWL_POWER_SHADOW_REG_ENA;
	220	else
	221	cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
	222
88e58fc5	223	if (iwl_advanced_bt_coexist(priv)) {
38622419	224	if (!cfg(priv)->bt_params->bt_sco_disable)
e366176e WYG	225	cmd->flags \|= IWL_POWER_BT_SCO_ENA;
	226	else
	227	cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	228	}
	229
	230
4ad177b5	231	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
570af86e	232	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
4ad177b5	233	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
570af86e	234	cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
4ad177b5 WYG	235
	236	/* enforce max sleep interval */
	237	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
	238	if (le32_to_cpu(cmd->sleep_interval[i]) >
	239	(max_sleep[i] * period))
	240	cmd->sleep_interval[i] =
	241	cpu_to_le32(max_sleep[i] * period);
	242	if (i != (IWL_POWER_VEC_SIZE - 1)) {
	243	if (le32_to_cpu(cmd->sleep_interval[i]) >
	244	le32_to_cpu(cmd->sleep_interval[i+1]))
	245	cmd->sleep_interval[i] =
	246	cmd->sleep_interval[i+1];
	247	}
	248	}
e312c24c	249
d57fa99d	250	if (priv->power_data.bus_pm)
e312c24c JB	251	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
	252	else
	253	cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
	254
4ad177b5 WYG	255	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
4ad177b5 WYG	256	skip, period);
e312c24c JB	257	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
	258	}
	259
e312c24c JB	260	static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
e312c24c JB	261	struct iwl_powertable_cmd *cmd)
5da4b55f	262	{
e312c24c	263	memset(cmd, 0, sizeof(*cmd));
5da4b55f	264
d57fa99d	265	if (priv->power_data.bus_pm)
e312c24c	266	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	267
e312c24c	268	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
5da4b55f MA	269	}
5da4b55f MA	270
e312c24c JB	271	static int iwl_set_power(struct iwl_priv priv, struct iwl_powertable_cmd cmd)
	272	{
	273	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
e1623446 TW	274	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	275	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	276	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	277	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
5da4b55f MA	278	le32_to_cpu(cmd->sleep_interval[0]),
	279	le32_to_cpu(cmd->sleep_interval[1]),
	280	le32_to_cpu(cmd->sleep_interval[2]),
	281	le32_to_cpu(cmd->sleep_interval[3]),
	282	le32_to_cpu(cmd->sleep_interval[4]));
	283
e10a0533	284	return iwl_dvm_send_cmd_pdu(priv, POWER_TABLE_CMD, CMD_SYNC,
e312c24c	285	sizeof(struct iwl_powertable_cmd), cmd);
5da4b55f MA	286	}
5da4b55f MA	287
ac4f5457 SG	288	static void iwl_power_build_cmd(struct iwl_priv *priv,
ac4f5457 SG	289	struct iwl_powertable_cmd *cmd)
5da4b55f	290	{
4d695921	291	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
e312c24c	292	int dtimper;
5da4b55f	293
3a065ab3	294	dtimper = priv->hw->conf.ps_dtim_period ?: 1;
e312c24c	295
15b86bff	296	if (priv->wowlan)
c8ac61cf	297	iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper);
38622419	298	else if (!cfg(priv)->base_params->no_idle_support &&
f3529108	299	priv->hw->conf.flags & IEEE80211_CONF_IDLE)
ac4f5457	300	iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
f42e7662	301	else if (iwl_tt_is_low_power_state(priv)) {
6ddbf8cd	302	/* in thermal throttling low power state */
ac4f5457	303	iwl_static_sleep_cmd(priv, cmd,
f42e7662	304	iwl_tt_current_power_mode(priv), dtimper);
0975cc8f	305	} else if (!enabled)
ac4f5457	306	iwl_power_sleep_cam_cmd(priv, cmd);
e312c24c	307	else if (priv->power_data.debug_sleep_level_override >= 0)
ac4f5457	308	iwl_static_sleep_cmd(priv, cmd,
e312c24c JB	309	priv->power_data.debug_sleep_level_override,
e312c24c JB	310	dtimper);
84965795	311	else {
f7538168 WYG	312	if (iwlagn_mod_params.power_level > IWL_POWER_INDEX_1 &&
	313	iwlagn_mod_params.power_level <= IWL_POWER_INDEX_5)
	314	iwl_static_sleep_cmd(priv, cmd,
	315	iwlagn_mod_params.power_level, dtimper);
	316	else
	317	iwl_static_sleep_cmd(priv, cmd,
	318	IWL_POWER_INDEX_1, dtimper);
84965795	319	}
ac4f5457 SG	320	}
	321
	322	int iwl_power_set_mode(struct iwl_priv priv, struct iwl_powertable_cmd cmd,
	323	bool force)
	324	{
	325	int ret;
	326	bool update_chains;
	327
b1eea297	328	lockdep_assert_held(&priv->mutex);
ac4f5457 SG	329
	330	/* Don't update the RX chain when chain noise calibration is running */
	331	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE \|\|
	332	priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
	333
	334	if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
	335	return 0;
	336
83626404	337	if (!iwl_is_ready_rf(priv))
ac4f5457 SG	338	return -EIO;
	339
	340	/* scan complete use sleep_power_next, need to be updated */
	341	memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
83626404	342	if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
ac4f5457 SG	343	IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
	344	return 0;
	345	}
	346
	347	if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
47107e84	348	iwl_dvm_set_pmi(priv, true);
5da4b55f	349
ac4f5457 SG	350	ret = iwl_set_power(priv, cmd);
	351	if (!ret) {
	352	if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
47107e84	353	iwl_dvm_set_pmi(priv, false);
ac4f5457	354
6b6db91c FD	355	if (update_chains)
	356	iwl_update_chain_flags(priv);
	357	else
ac4f5457	358	IWL_DEBUG_POWER(priv,
3a780d25	359	"Cannot update the power, chain noise "
a71c8f62 WT	360	"calibration running: %d\n",
a71c8f62 WT	361	priv->chain_noise_data.state);
ac4f5457 SG	362
	363	memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
	364	} else
	365	IWL_ERR(priv, "set power fail, ret = %d", ret);
5da4b55f MA	366
	367	return ret;
	368	}
ac4f5457 SG	369
	370	int iwl_power_update_mode(struct iwl_priv *priv, bool force)
	371	{
	372	struct iwl_powertable_cmd cmd;
	373
	374	iwl_power_build_cmd(priv, &cmd);
	375	return iwl_power_set_mode(priv, &cmd, force);
	376	}
5da4b55f	377
a96a27f9	378	/* initialize to default */
5da4b55f MA	379	void iwl_power_initialize(struct iwl_priv *priv)
5da4b55f MA	380	{
f6d0e9be	381	priv->power_data.bus_pm = trans(priv)->pm_support;
e312c24c JB	382
	383	priv->power_data.debug_sleep_level_override = -1;
	384
	385	memset(&priv->power_data.sleep_cmd, 0,
	386	sizeof(priv->power_data.sleep_cmd));
5da4b55f	387	}