[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-power.c

/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *****************************************************************************/


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>

#include <net/mac80211.h>

#include "iwl-eeprom.h"
#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-commands.h"
#include "iwl-debug.h"
#include "iwl-power.h"

/*
 * Setting power level allows the card to go to sleep when not busy.
 *
 * We calculate a sleep command based on the required latency, which
 * we get from mac80211. In order to handle thermal throttling, we can
 * also use pre-defined power levels.
 */

/*
 * For now, keep using power level 1 instead of automatically
 * adjusting ...
 */
bool no_sleep_autoadjust = true;
module_param(no_sleep_autoadjust, bool, S_IRUGO);
MODULE_PARM_DESC(no_sleep_autoadjust,
		 "don't automatically adjust sleep level "
		 "according to maximum network latency");

/*
 * This defines the old power levels. They are still used by default
 * (level 1) and for thermal throttle (levels 3 through 5)
 */

struct iwl_power_vec_entry {
	struct iwl_powertable_cmd cmd;
	u8 no_dtim;	/* number of skip dtim */
};

#define IWL_DTIM_RANGE_0_MAX	2
#define IWL_DTIM_RANGE_1_MAX	10

#define NOSLP cpu_to_le16(0), 0, 0
#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK |	\
		IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
		IWL_POWER_ADVANCE_PM_ENA_MSK)
#define ASLP_TOUT(T) cpu_to_le32(T)
#define TU_TO_USEC 1024
#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
				     cpu_to_le32(X1), \
				     cpu_to_le32(X2), \
				     cpu_to_le32(X3), \
				     cpu_to_le32(X4)}
/* default power management (not Tx power) table values */
/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
};


/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
};

/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
};

/* advance power management */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};


/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
};

/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};

static void iwl_static_sleep_cmd(struct iwl_priv *priv,
				 struct iwl_powertable_cmd *cmd,
				 enum iwl_power_level lvl, int period)
{
	const struct iwl_power_vec_entry *table;
	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	int i;
	u8 skip;
	u32 slp_itrvl;

	if (priv->cfg->adv_pm) {
		table = apm_range_2;
		if (period <= IWL_DTIM_RANGE_1_MAX)
			table = apm_range_1;
		if (period <= IWL_DTIM_RANGE_0_MAX)
			table = apm_range_0;
	} else {
		table = range_2;
		if (period <= IWL_DTIM_RANGE_1_MAX)
			table = range_1;
		if (period <= IWL_DTIM_RANGE_0_MAX)
			table = range_0;
	}

	if (WARN_ON(lvl < 0 || lvl >= IWL_POWER_NUM))
		memset(cmd, 0, sizeof(*cmd));
	else
		*cmd = table[lvl].cmd;

	if (period == 0) {
		skip = 0;
		period = 1;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] =  1;

	} else {
		skip = table[lvl].no_dtim;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
		max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
	}

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	/* figure out the listen interval based on dtim period and skip */
	if (slp_itrvl == 0xFF)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(period * (skip + 1));

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > period)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32((slp_itrvl / period) * period);

	if (skip)
		cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
	else
		cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;

	if (priv->cfg->base_params->shadow_reg_enable)
		cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
	else
		cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;

	if (iwl_advanced_bt_coexist(priv)) {
		if (!priv->cfg->bt_params->bt_sco_disable)
			cmd->flags |= IWL_POWER_BT_SCO_ENA;
		else
			cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	}


	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);

	/* enforce max sleep interval */
	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
		if (le32_to_cpu(cmd->sleep_interval[i]) >
		    (max_sleep[i] * period))
			cmd->sleep_interval[i] =
				cpu_to_le32(max_sleep[i] * period);
		if (i != (IWL_POWER_VEC_SIZE - 1)) {
			if (le32_to_cpu(cmd->sleep_interval[i]) >
			    le32_to_cpu(cmd->sleep_interval[i+1]))
				cmd->sleep_interval[i] =
					cmd->sleep_interval[i+1];
		}
	}

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;
	else
		cmd->flags &= ~IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
			skip, period);
	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
}

static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
				    struct iwl_powertable_cmd *cmd)
{
	memset(cmd, 0, sizeof(*cmd));

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
}

static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
				     struct iwl_powertable_cmd *cmd,
				     int dynps_ms, int wakeup_period)
{
	/*
	 * These are the original power level 3 sleep successions. The
	 * device may behave better with such succession and was also
	 * only tested with that. Just like the original sleep commands,
	 * also adjust the succession here to the wakeup_period below.
	 * The ranges are the same as for the sleep commands, 0-2, 3-9
	 * and >10, which is selected based on the DTIM interval for
	 * the sleep index but here we use the wakeup period since that
	 * is what we need to do for the latency requirements.
	 */
	static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
	static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
	static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
	const u8 *slp_succ = slp_succ_r0;
	int i;

	if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
		slp_succ = slp_succ_r1;
	if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
		slp_succ = slp_succ_r2;

	memset(cmd, 0, sizeof(*cmd));

	cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
		     IWL_POWER_FAST_PD; /* no use seeing frames for others */

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;

	if (priv->cfg->base_params->shadow_reg_enable)
		cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
	else
		cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;

	if (iwl_advanced_bt_coexist(priv)) {
		if (!priv->cfg->bt_params->bt_sco_disable)
			cmd->flags |= IWL_POWER_BT_SCO_ENA;
		else
			cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	}

	cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
	cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);

	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
		cmd->sleep_interval[i] =
			cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));

	IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
}

static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
{
	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
			le32_to_cpu(cmd->sleep_interval[0]),
			le32_to_cpu(cmd->sleep_interval[1]),
			le32_to_cpu(cmd->sleep_interval[2]),
			le32_to_cpu(cmd->sleep_interval[3]),
			le32_to_cpu(cmd->sleep_interval[4]));

	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
				sizeof(struct iwl_powertable_cmd), cmd);
}

static void iwl_power_build_cmd(struct iwl_priv *priv,
				struct iwl_powertable_cmd *cmd)
{
	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
	int dtimper;

	dtimper = priv->hw->conf.ps_dtim_period ?: 1;

	if (priv->hw->conf.flags & IEEE80211_CONF_IDLE)
		iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
	else if (iwl_tt_is_low_power_state(priv)) {
		/* in thermal throttling low power state */
		iwl_static_sleep_cmd(priv, cmd,
		    iwl_tt_current_power_mode(priv), dtimper);
	} else if (!enabled)
		iwl_power_sleep_cam_cmd(priv, cmd);
	else if (priv->power_data.debug_sleep_level_override >= 0)
		iwl_static_sleep_cmd(priv, cmd,
				     priv->power_data.debug_sleep_level_override,
				     dtimper);
	else if (no_sleep_autoadjust)
		iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
	else
		iwl_power_fill_sleep_cmd(priv, cmd,
					 priv->hw->conf.dynamic_ps_timeout,
					 priv->hw->conf.max_sleep_period);
}

int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
		       bool force)
{
	int ret;
	bool update_chains;

	lockdep_assert_held(&priv->mutex);

	/* Don't update the RX chain when chain noise calibration is running */
	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
			priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;

	if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
		return 0;

	if (!iwl_is_ready_rf(priv))
		return -EIO;

	/* scan complete use sleep_power_next, need to be updated */
	memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
	if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
		IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
		return 0;
	}

	if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
		set_bit(STATUS_POWER_PMI, &priv->status);

	ret = iwl_set_power(priv, cmd);
	if (!ret) {
		if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
			clear_bit(STATUS_POWER_PMI, &priv->status);

		if (priv->cfg->ops->lib->update_chain_flags && update_chains)
			priv->cfg->ops->lib->update_chain_flags(priv);
		else if (priv->cfg->ops->lib->update_chain_flags)
			IWL_DEBUG_POWER(priv,
					"Cannot update the power, chain noise "
					"calibration running: %d\n",
					priv->chain_noise_data.state);

		memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
	} else
		IWL_ERR(priv, "set power fail, ret = %d", ret);

	return ret;
}

int iwl_power_update_mode(struct iwl_priv *priv, bool force)
{
	struct iwl_powertable_cmd cmd;

	iwl_power_build_cmd(priv, &cmd);
	return iwl_power_set_mode(priv, &cmd, force);
}

/* initialize to default */
void iwl_power_initialize(struct iwl_priv *priv)
{
	u16 lctl = iwl_pcie_link_ctl(priv);

	priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);

	priv->power_data.debug_sleep_level_override = -1;

	memset(&priv->power_data.sleep_cmd, 0,
		sizeof(priv->power_data.sleep_cmd));
}
Commit	Line	Data
5da4b55f MA	1	/******************************************************************************
5da4b55f MA	2	*
901069c7	3	* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
5da4b55f MA	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
759ef89f	25	* Intel Linux Wireless <ilw@linux.intel.com>
5da4b55f MA	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*****************************************************************************/
	28
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
5a0e3ad6	32	#include <linux/slab.h>
5da4b55f MA	33	#include <linux/init.h>
	34
	35	#include <net/mac80211.h>
	36
	37	#include "iwl-eeprom.h"
3e0d4cb1	38	#include "iwl-dev.h"
5da4b55f	39	#include "iwl-core.h"
39b73fb1	40	#include "iwl-io.h"
5a36ba0e	41	#include "iwl-commands.h"
5da4b55f MA	42	#include "iwl-debug.h"
5da4b55f MA	43	#include "iwl-power.h"
5da4b55f MA	44
5da4b55f MA	45	/*
e312c24c	46	* Setting power level allows the card to go to sleep when not busy.
5da4b55f	47	*
e312c24c JB	48	* We calculate a sleep command based on the required latency, which
	49	* we get from mac80211. In order to handle thermal throttling, we can
	50	* also use pre-defined power levels.
5da4b55f MA	51	*/
5da4b55f MA	52
e312c24c JB	53	/*
	54	* For now, keep using power level 1 instead of automatically
	55	* adjusting ...
	56	*/
	57	bool no_sleep_autoadjust = true;
	58	module_param(no_sleep_autoadjust, bool, S_IRUGO);
	59	MODULE_PARM_DESC(no_sleep_autoadjust,
	60	"don't automatically adjust sleep level "
	61	"according to maximum network latency");
5da4b55f	62
e312c24c JB	63	/*
	64	* This defines the old power levels. They are still used by default
	65	* (level 1) and for thermal throttle (levels 3 through 5)
	66	*/
	67
	68	struct iwl_power_vec_entry {
	69	struct iwl_powertable_cmd cmd;
4ad177b5	70	u8 no_dtim; /* number of skip dtim */
e312c24c JB	71	};
	72
	73	#define IWL_DTIM_RANGE_0_MAX 2
	74	#define IWL_DTIM_RANGE_1_MAX 10
5da4b55f	75
7af2c460 JB	76	#define NOSLP cpu_to_le16(0), 0, 0
7af2c460 JB	77	#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
35162ba7 WYG	78	#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK \| \
	79	IWL_POWER_POWER_MANAGEMENT_ENA_MSK \| \
	80	IWL_POWER_ADVANCE_PM_ENA_MSK)
	81	#define ASLP_TOUT(T) cpu_to_le32(T)
7af2c460 JB	82	#define TU_TO_USEC 1024
	83	#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
	84	#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
	85	cpu_to_le32(X1), \
	86	cpu_to_le32(X2), \
	87	cpu_to_le32(X3), \
	88	cpu_to_le32(X4)}
5da4b55f	89	/* default power management (not Tx power) table values */
e312c24c	90	/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
4ad177b5	91	/* DTIM 0 - 2 */
7af2c460	92	static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
4ad177b5	93	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
5da4b55f MA	94	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	95	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	96	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	97	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
	98	};
	99
	100
e312c24c	101	/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
4ad177b5	102	/* DTIM 3 - 10 */
7af2c460	103	static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
5da4b55f MA	104	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	105	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	106	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	107	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
4ad177b5	108	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
5da4b55f MA	109	};
5da4b55f MA	110
e312c24c	111	/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
4ad177b5	112	/* DTIM 11 - */
7af2c460	113	static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
5da4b55f MA	114	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	115	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	116	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	117	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	118	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
	119	};
	120
35162ba7 WYG	121	/* advance power management */
	122	/* DTIM 0 - 2 */
	123	static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
	124	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	125	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	126	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	127	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	128	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	129	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	130	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	131	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	132	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	133	SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
	134	};
	135
	136
	137	/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
	138	/* DTIM 3 - 10 */
	139	static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
	140	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	141	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	142	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	143	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	144	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	145	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	146	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	147	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	148	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	149	SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
	150	};
	151
	152	/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
	153	/* DTIM 11 - */
	154	static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
	155	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	156	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	157	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	158	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	159	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	160	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	161	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	162	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	163	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	164	SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
	165	};
	166
e312c24c JB	167	static void iwl_static_sleep_cmd(struct iwl_priv *priv,
	168	struct iwl_powertable_cmd *cmd,
	169	enum iwl_power_level lvl, int period)
	170	{
	171	const struct iwl_power_vec_entry *table;
4ad177b5 WYG	172	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	173	int i;
	174	u8 skip;
	175	u32 slp_itrvl;
e312c24c	176
35162ba7 WYG	177	if (priv->cfg->adv_pm) {
	178	table = apm_range_2;
	179	if (period <= IWL_DTIM_RANGE_1_MAX)
	180	table = apm_range_1;
	181	if (period <= IWL_DTIM_RANGE_0_MAX)
	182	table = apm_range_0;
	183	} else {
	184	table = range_2;
	185	if (period <= IWL_DTIM_RANGE_1_MAX)
	186	table = range_1;
	187	if (period <= IWL_DTIM_RANGE_0_MAX)
	188	table = range_0;
	189	}
e312c24c	190
3e41ace5 JB	191	if (WARN_ON(lvl < 0 \|\| lvl >= IWL_POWER_NUM))
	192	memset(cmd, 0, sizeof(*cmd));
	193	else
	194	*cmd = table[lvl].cmd;
e312c24c JB	195
e312c24c JB	196	if (period == 0) {
4ad177b5	197	skip = 0;
e312c24c	198	period = 1;
4ad177b5 WYG	199	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	200	max_sleep[i] = 1;
	201
e312c24c	202	} else {
4ad177b5 WYG	203	skip = table[lvl].no_dtim;
	204	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	205	max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
	206	max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
e312c24c JB	207	}
e312c24c JB	208
4ad177b5 WYG	209	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	210	/* figure out the listen interval based on dtim period and skip */
	211	if (slp_itrvl == 0xFF)
	212	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	213	cpu_to_le32(period * (skip + 1));
	214
	215	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	216	if (slp_itrvl > period)
	217	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	218	cpu_to_le32((slp_itrvl / period) * period);
	219
	220	if (skip)
e312c24c	221	cmd->flags \|= IWL_POWER_SLEEP_OVER_DTIM_MSK;
4ad177b5	222	else
e312c24c	223	cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
e312c24c	224
1f37daf3 WYG	225	if (priv->cfg->base_params->shadow_reg_enable)
	226	cmd->flags \|= IWL_POWER_SHADOW_REG_ENA;
	227	else
	228	cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
	229
88e58fc5	230	if (iwl_advanced_bt_coexist(priv)) {
e366176e WYG	231	if (!priv->cfg->bt_params->bt_sco_disable)
	232	cmd->flags \|= IWL_POWER_BT_SCO_ENA;
	233	else
	234	cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	235	}
	236
	237
4ad177b5	238	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
570af86e	239	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
4ad177b5	240	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
570af86e	241	cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
4ad177b5 WYG	242
	243	/* enforce max sleep interval */
	244	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
	245	if (le32_to_cpu(cmd->sleep_interval[i]) >
	246	(max_sleep[i] * period))
	247	cmd->sleep_interval[i] =
	248	cpu_to_le32(max_sleep[i] * period);
	249	if (i != (IWL_POWER_VEC_SIZE - 1)) {
	250	if (le32_to_cpu(cmd->sleep_interval[i]) >
	251	le32_to_cpu(cmd->sleep_interval[i+1]))
	252	cmd->sleep_interval[i] =
	253	cmd->sleep_interval[i+1];
	254	}
	255	}
e312c24c JB	256
	257	if (priv->power_data.pci_pm)
	258	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
	259	else
	260	cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
	261
4ad177b5 WYG	262	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
4ad177b5 WYG	263	skip, period);
e312c24c JB	264	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
	265	}
	266
e312c24c JB	267	static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
e312c24c JB	268	struct iwl_powertable_cmd *cmd)
5da4b55f	269	{
e312c24c	270	memset(cmd, 0, sizeof(*cmd));
5da4b55f	271
e312c24c JB	272	if (priv->power_data.pci_pm)
e312c24c JB	273	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	274
e312c24c	275	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
5da4b55f MA	276	}
5da4b55f MA	277
e312c24c JB	278	static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
	279	struct iwl_powertable_cmd *cmd,
	280	int dynps_ms, int wakeup_period)
5da4b55f	281	{
4c561a02 JB	282	/*
	283	* These are the original power level 3 sleep successions. The
	284	* device may behave better with such succession and was also
	285	* only tested with that. Just like the original sleep commands,
	286	* also adjust the succession here to the wakeup_period below.
	287	* The ranges are the same as for the sleep commands, 0-2, 3-9
	288	* and >10, which is selected based on the DTIM interval for
	289	* the sleep index but here we use the wakeup period since that
	290	* is what we need to do for the latency requirements.
	291	*/
	292	static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
	293	static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
	294	static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
	295	const u8 *slp_succ = slp_succ_r0;
5cd19c5f	296	int i;
5da4b55f	297
4c561a02 JB	298	if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
	299	slp_succ = slp_succ_r1;
	300	if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
	301	slp_succ = slp_succ_r2;
	302
e312c24c	303	memset(cmd, 0, sizeof(*cmd));
5cd19c5f	304
e312c24c JB	305	cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK \|
e312c24c JB	306	IWL_POWER_FAST_PD; /* no use seeing frames for others */
5da4b55f	307
e312c24c JB	308	if (priv->power_data.pci_pm)
e312c24c JB	309	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	310
1f37daf3 WYG	311	if (priv->cfg->base_params->shadow_reg_enable)
	312	cmd->flags \|= IWL_POWER_SHADOW_REG_ENA;
	313	else
	314	cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
	315
88e58fc5	316	if (iwl_advanced_bt_coexist(priv)) {
e366176e WYG	317	if (!priv->cfg->bt_params->bt_sco_disable)
	318	cmd->flags \|= IWL_POWER_BT_SCO_ENA;
	319	else
	320	cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	321	}
	322
e312c24c JB	323	cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
e312c24c JB	324	cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
5da4b55f	325
5cd19c5f	326	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
4c561a02 JB	327	cmd->sleep_interval[i] =
4c561a02 JB	328	cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));
e312c24c JB	329
	330	IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
	331	}
5da4b55f	332
e312c24c JB	333	static int iwl_set_power(struct iwl_priv priv, struct iwl_powertable_cmd cmd)
	334	{
	335	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
e1623446 TW	336	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	337	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	338	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	339	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
5da4b55f MA	340	le32_to_cpu(cmd->sleep_interval[0]),
	341	le32_to_cpu(cmd->sleep_interval[1]),
	342	le32_to_cpu(cmd->sleep_interval[2]),
	343	le32_to_cpu(cmd->sleep_interval[3]),
	344	le32_to_cpu(cmd->sleep_interval[4]));
	345
e312c24c JB	346	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
e312c24c JB	347	sizeof(struct iwl_powertable_cmd), cmd);
5da4b55f MA	348	}
5da4b55f MA	349
ac4f5457 SG	350	static void iwl_power_build_cmd(struct iwl_priv *priv,
ac4f5457 SG	351	struct iwl_powertable_cmd *cmd)
5da4b55f	352	{
4d695921	353	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
e312c24c	354	int dtimper;
5da4b55f	355
3a065ab3	356	dtimper = priv->hw->conf.ps_dtim_period ?: 1;
e312c24c	357
23c0fcc6	358	if (priv->hw->conf.flags & IEEE80211_CONF_IDLE)
ac4f5457	359	iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
f42e7662	360	else if (iwl_tt_is_low_power_state(priv)) {
6ddbf8cd	361	/* in thermal throttling low power state */
ac4f5457	362	iwl_static_sleep_cmd(priv, cmd,
f42e7662	363	iwl_tt_current_power_mode(priv), dtimper);
0975cc8f	364	} else if (!enabled)
ac4f5457	365	iwl_power_sleep_cam_cmd(priv, cmd);
e312c24c	366	else if (priv->power_data.debug_sleep_level_override >= 0)
ac4f5457	367	iwl_static_sleep_cmd(priv, cmd,
e312c24c JB	368	priv->power_data.debug_sleep_level_override,
	369	dtimper);
	370	else if (no_sleep_autoadjust)
ac4f5457	371	iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
e312c24c	372	else
ac4f5457	373	iwl_power_fill_sleep_cmd(priv, cmd,
e312c24c JB	374	priv->hw->conf.dynamic_ps_timeout,
e312c24c JB	375	priv->hw->conf.max_sleep_period);
ac4f5457 SG	376	}
	377
	378	int iwl_power_set_mode(struct iwl_priv priv, struct iwl_powertable_cmd cmd,
	379	bool force)
	380	{
	381	int ret;
	382	bool update_chains;
	383
	384	lockdep_assert_held(&priv->mutex);
	385
	386	/* Don't update the RX chain when chain noise calibration is running */
	387	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE \|\|
	388	priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
	389
	390	if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
	391	return 0;
	392
	393	if (!iwl_is_ready_rf(priv))
	394	return -EIO;
	395
	396	/* scan complete use sleep_power_next, need to be updated */
	397	memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
	398	if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
	399	IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
	400	return 0;
	401	}
	402
	403	if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
	404	set_bit(STATUS_POWER_PMI, &priv->status);
5da4b55f	405
ac4f5457 SG	406	ret = iwl_set_power(priv, cmd);
	407	if (!ret) {
	408	if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
	409	clear_bit(STATUS_POWER_PMI, &priv->status);
	410
	411	if (priv->cfg->ops->lib->update_chain_flags && update_chains)
	412	priv->cfg->ops->lib->update_chain_flags(priv);
	413	else if (priv->cfg->ops->lib->update_chain_flags)
	414	IWL_DEBUG_POWER(priv,
3a780d25	415	"Cannot update the power, chain noise "
a71c8f62 WT	416	"calibration running: %d\n",
a71c8f62 WT	417	priv->chain_noise_data.state);
ac4f5457 SG	418
	419	memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
	420	} else
	421	IWL_ERR(priv, "set power fail, ret = %d", ret);
5da4b55f MA	422
	423	return ret;
	424	}
ac4f5457 SG	425
	426	int iwl_power_update_mode(struct iwl_priv *priv, bool force)
	427	{
	428	struct iwl_powertable_cmd cmd;
	429
	430	iwl_power_build_cmd(priv, &cmd);
	431	return iwl_power_set_mode(priv, &cmd, force);
	432	}
5da4b55f	433
a96a27f9	434	/* initialize to default */
5da4b55f MA	435	void iwl_power_initialize(struct iwl_priv *priv)
5da4b55f MA	436	{
e312c24c JB	437	u16 lctl = iwl_pcie_link_ctl(priv);
	438
	439	priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
	440
	441	priv->power_data.debug_sleep_level_override = -1;
	442
	443	memset(&priv->power_data.sleep_cmd, 0,
	444	sizeof(priv->power_data.sleep_cmd));
5da4b55f	445	}