[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-power.c

/******************************************************************************
 *
 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *****************************************************************************/


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>

#include <net/mac80211.h>

#include "iwl-eeprom.h"
#include "iwl-dev.h"
#include "iwl-agn.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-commands.h"
#include "iwl-debug.h"
#include "iwl-power.h"

/*
 * Setting power level allows the card to go to sleep when not busy.
 *
 * We calculate a sleep command based on the required latency, which
 * we get from mac80211. In order to handle thermal throttling, we can
 * also use pre-defined power levels.
 */

/*
 * This defines the old power levels. They are still used by default
 * (level 1) and for thermal throttle (levels 3 through 5)
 */

struct iwl_power_vec_entry {
	struct iwl_powertable_cmd cmd;
	u8 no_dtim;	/* number of skip dtim */
};

#define IWL_DTIM_RANGE_0_MAX	2
#define IWL_DTIM_RANGE_1_MAX	10

#define NOSLP cpu_to_le16(0), 0, 0
#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK |	\
		IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
		IWL_POWER_ADVANCE_PM_ENA_MSK)
#define ASLP_TOUT(T) cpu_to_le32(T)
#define TU_TO_USEC 1024
#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
				     cpu_to_le32(X1), \
				     cpu_to_le32(X2), \
				     cpu_to_le32(X3), \
				     cpu_to_le32(X4)}
/* default power management (not Tx power) table values */
/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
};


/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
};

/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
};

/* advance power management */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};


/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
};

/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
		SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};

static void iwl_static_sleep_cmd(struct iwl_priv *priv,
				 struct iwl_powertable_cmd *cmd,
				 enum iwl_power_level lvl, int period)
{
	const struct iwl_power_vec_entry *table;
	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	int i;
	u8 skip;
	u32 slp_itrvl;

	if (priv->cfg->adv_pm) {
		table = apm_range_2;
		if (period <= IWL_DTIM_RANGE_1_MAX)
			table = apm_range_1;
		if (period <= IWL_DTIM_RANGE_0_MAX)
			table = apm_range_0;
	} else {
		table = range_2;
		if (period <= IWL_DTIM_RANGE_1_MAX)
			table = range_1;
		if (period <= IWL_DTIM_RANGE_0_MAX)
			table = range_0;
	}

	if (WARN_ON(lvl < 0 || lvl >= IWL_POWER_NUM))
		memset(cmd, 0, sizeof(*cmd));
	else
		*cmd = table[lvl].cmd;

	if (period == 0) {
		skip = 0;
		period = 1;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] =  1;

	} else {
		skip = table[lvl].no_dtim;
		for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
			max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
		max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
	}

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	/* figure out the listen interval based on dtim period and skip */
	if (slp_itrvl == 0xFF)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(period * (skip + 1));

	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > period)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32((slp_itrvl / period) * period);

	if (skip)
		cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
	else
		cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;

	if (priv->cfg->base_params->shadow_reg_enable)
		cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
	else
		cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;

	if (iwl_advanced_bt_coexist(priv)) {
		if (!priv->cfg->bt_params->bt_sco_disable)
			cmd->flags |= IWL_POWER_BT_SCO_ENA;
		else
			cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	}


	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
		cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
			cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);

	/* enforce max sleep interval */
	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
		if (le32_to_cpu(cmd->sleep_interval[i]) >
		    (max_sleep[i] * period))
			cmd->sleep_interval[i] =
				cpu_to_le32(max_sleep[i] * period);
		if (i != (IWL_POWER_VEC_SIZE - 1)) {
			if (le32_to_cpu(cmd->sleep_interval[i]) >
			    le32_to_cpu(cmd->sleep_interval[i+1]))
				cmd->sleep_interval[i] =
					cmd->sleep_interval[i+1];
		}
	}

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;
	else
		cmd->flags &= ~IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
			skip, period);
	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
}

static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
				    struct iwl_powertable_cmd *cmd)
{
	memset(cmd, 0, sizeof(*cmd));

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;

	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
}

static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
				     struct iwl_powertable_cmd *cmd,
				     int dynps_ms, int wakeup_period)
{
	/*
	 * These are the original power level 3 sleep successions. The
	 * device may behave better with such succession and was also
	 * only tested with that. Just like the original sleep commands,
	 * also adjust the succession here to the wakeup_period below.
	 * The ranges are the same as for the sleep commands, 0-2, 3-9
	 * and >10, which is selected based on the DTIM interval for
	 * the sleep index but here we use the wakeup period since that
	 * is what we need to do for the latency requirements.
	 */
	static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
	static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
	static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
	const u8 *slp_succ = slp_succ_r0;
	int i;

	if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
		slp_succ = slp_succ_r1;
	if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
		slp_succ = slp_succ_r2;

	memset(cmd, 0, sizeof(*cmd));

	cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
		     IWL_POWER_FAST_PD; /* no use seeing frames for others */

	if (priv->power_data.pci_pm)
		cmd->flags |= IWL_POWER_PCI_PM_MSK;

	if (priv->cfg->base_params->shadow_reg_enable)
		cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
	else
		cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;

	if (iwl_advanced_bt_coexist(priv)) {
		if (!priv->cfg->bt_params->bt_sco_disable)
			cmd->flags |= IWL_POWER_BT_SCO_ENA;
		else
			cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	}

	cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
	cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);

	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
		cmd->sleep_interval[i] =
			cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));

	IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
}

static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
{
	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
			le32_to_cpu(cmd->sleep_interval[0]),
			le32_to_cpu(cmd->sleep_interval[1]),
			le32_to_cpu(cmd->sleep_interval[2]),
			le32_to_cpu(cmd->sleep_interval[3]),
			le32_to_cpu(cmd->sleep_interval[4]));

	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
				sizeof(struct iwl_powertable_cmd), cmd);
}

static void iwl_power_build_cmd(struct iwl_priv *priv,
				struct iwl_powertable_cmd *cmd)
{
	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
	int dtimper;

	dtimper = priv->hw->conf.ps_dtim_period ?: 1;

	if (priv->hw->conf.flags & IEEE80211_CONF_IDLE)
		iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
	else if (iwl_tt_is_low_power_state(priv)) {
		/* in thermal throttling low power state */
		iwl_static_sleep_cmd(priv, cmd,
		    iwl_tt_current_power_mode(priv), dtimper);
	} else if (!enabled)
		iwl_power_sleep_cam_cmd(priv, cmd);
	else if (priv->power_data.debug_sleep_level_override >= 0)
		iwl_static_sleep_cmd(priv, cmd,
				     priv->power_data.debug_sleep_level_override,
				     dtimper);
	else if (iwlagn_mod_params.no_sleep_autoadjust)
		iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
	else
		iwl_power_fill_sleep_cmd(priv, cmd,
					 priv->hw->conf.dynamic_ps_timeout,
					 priv->hw->conf.max_sleep_period);
}

int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
		       bool force)
{
	int ret;
	bool update_chains;

	lockdep_assert_held(&priv->mutex);

	/* Don't update the RX chain when chain noise calibration is running */
	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
			priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;

	if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
		return 0;

	if (!iwl_is_ready_rf(priv))
		return -EIO;

	/* scan complete use sleep_power_next, need to be updated */
	memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
	if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
		IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
		return 0;
	}

	if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
		set_bit(STATUS_POWER_PMI, &priv->status);

	ret = iwl_set_power(priv, cmd);
	if (!ret) {
		if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
			clear_bit(STATUS_POWER_PMI, &priv->status);

		if (priv->cfg->ops->lib->update_chain_flags && update_chains)
			priv->cfg->ops->lib->update_chain_flags(priv);
		else if (priv->cfg->ops->lib->update_chain_flags)
			IWL_DEBUG_POWER(priv,
					"Cannot update the power, chain noise "
					"calibration running: %d\n",
					priv->chain_noise_data.state);

		memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
	} else
		IWL_ERR(priv, "set power fail, ret = %d", ret);

	return ret;
}

int iwl_power_update_mode(struct iwl_priv *priv, bool force)
{
	struct iwl_powertable_cmd cmd;

	iwl_power_build_cmd(priv, &cmd);
	return iwl_power_set_mode(priv, &cmd, force);
}

/* initialize to default */
void iwl_power_initialize(struct iwl_priv *priv)
{
	u16 lctl = iwl_pcie_link_ctl(priv);

	priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);

	priv->power_data.debug_sleep_level_override = -1;

	memset(&priv->power_data.sleep_cmd, 0,
		sizeof(priv->power_data.sleep_cmd));
}
Commit	Line	Data
5da4b55f MA	1	/******************************************************************************
5da4b55f MA	2	*
901069c7	3	* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
5da4b55f MA	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
759ef89f	25	* Intel Linux Wireless <ilw@linux.intel.com>
5da4b55f MA	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*****************************************************************************/
	28
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
5a0e3ad6	32	#include <linux/slab.h>
5da4b55f MA	33	#include <linux/init.h>
	34
	35	#include <net/mac80211.h>
	36
	37	#include "iwl-eeprom.h"
3e0d4cb1	38	#include "iwl-dev.h"
3f1e5f4a	39	#include "iwl-agn.h"
5da4b55f	40	#include "iwl-core.h"
39b73fb1	41	#include "iwl-io.h"
5a36ba0e	42	#include "iwl-commands.h"
5da4b55f MA	43	#include "iwl-debug.h"
5da4b55f MA	44	#include "iwl-power.h"
5da4b55f MA	45
5da4b55f MA	46	/*
e312c24c	47	* Setting power level allows the card to go to sleep when not busy.
5da4b55f	48	*
e312c24c JB	49	* We calculate a sleep command based on the required latency, which
	50	* we get from mac80211. In order to handle thermal throttling, we can
	51	* also use pre-defined power levels.
5da4b55f MA	52	*/
5da4b55f MA	53
e312c24c JB	54	/*
	55	* This defines the old power levels. They are still used by default
	56	* (level 1) and for thermal throttle (levels 3 through 5)
	57	*/
	58
	59	struct iwl_power_vec_entry {
	60	struct iwl_powertable_cmd cmd;
4ad177b5	61	u8 no_dtim; /* number of skip dtim */
e312c24c JB	62	};
	63
	64	#define IWL_DTIM_RANGE_0_MAX 2
	65	#define IWL_DTIM_RANGE_1_MAX 10
5da4b55f	66
7af2c460 JB	67	#define NOSLP cpu_to_le16(0), 0, 0
7af2c460 JB	68	#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
35162ba7 WYG	69	#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK \| \
	70	IWL_POWER_POWER_MANAGEMENT_ENA_MSK \| \
	71	IWL_POWER_ADVANCE_PM_ENA_MSK)
	72	#define ASLP_TOUT(T) cpu_to_le32(T)
7af2c460 JB	73	#define TU_TO_USEC 1024
	74	#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
	75	#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
	76	cpu_to_le32(X1), \
	77	cpu_to_le32(X2), \
	78	cpu_to_le32(X3), \
	79	cpu_to_le32(X4)}
5da4b55f	80	/* default power management (not Tx power) table values */
e312c24c	81	/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
4ad177b5	82	/* DTIM 0 - 2 */
7af2c460	83	static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
4ad177b5	84	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
5da4b55f MA	85	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	86	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	87	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	88	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
	89	};
	90
	91
e312c24c	92	/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
4ad177b5	93	/* DTIM 3 - 10 */
7af2c460	94	static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
5da4b55f MA	95	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	96	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	97	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	98	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
4ad177b5	99	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
5da4b55f MA	100	};
5da4b55f MA	101
e312c24c	102	/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
4ad177b5	103	/* DTIM 11 - */
7af2c460	104	static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
5da4b55f MA	105	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	106	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	107	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	108	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	109	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
	110	};
	111
35162ba7 WYG	112	/* advance power management */
	113	/* DTIM 0 - 2 */
	114	static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
	115	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	116	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	117	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	118	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	119	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	120	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	121	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	122	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	123	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	124	SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
	125	};
	126
	127
	128	/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
	129	/* DTIM 3 - 10 */
	130	static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
	131	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	132	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	133	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	134	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	135	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	136	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	137	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	138	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	139	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	140	SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
	141	};
	142
	143	/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
	144	/* DTIM 11 - */
	145	static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
	146	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	147	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	148	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	149	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	150	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	151	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	152	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	153	SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
	154	{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
	155	SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
	156	};
	157
e312c24c JB	158	static void iwl_static_sleep_cmd(struct iwl_priv *priv,
	159	struct iwl_powertable_cmd *cmd,
	160	enum iwl_power_level lvl, int period)
	161	{
	162	const struct iwl_power_vec_entry *table;
4ad177b5 WYG	163	int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
	164	int i;
	165	u8 skip;
	166	u32 slp_itrvl;
e312c24c	167
35162ba7 WYG	168	if (priv->cfg->adv_pm) {
	169	table = apm_range_2;
	170	if (period <= IWL_DTIM_RANGE_1_MAX)
	171	table = apm_range_1;
	172	if (period <= IWL_DTIM_RANGE_0_MAX)
	173	table = apm_range_0;
	174	} else {
	175	table = range_2;
	176	if (period <= IWL_DTIM_RANGE_1_MAX)
	177	table = range_1;
	178	if (period <= IWL_DTIM_RANGE_0_MAX)
	179	table = range_0;
	180	}
e312c24c	181
3e41ace5 JB	182	if (WARN_ON(lvl < 0 \|\| lvl >= IWL_POWER_NUM))
	183	memset(cmd, 0, sizeof(*cmd));
	184	else
	185	*cmd = table[lvl].cmd;
e312c24c JB	186
e312c24c JB	187	if (period == 0) {
4ad177b5	188	skip = 0;
e312c24c	189	period = 1;
4ad177b5 WYG	190	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	191	max_sleep[i] = 1;
	192
e312c24c	193	} else {
4ad177b5 WYG	194	skip = table[lvl].no_dtim;
	195	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
	196	max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
	197	max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
e312c24c JB	198	}
e312c24c JB	199
4ad177b5 WYG	200	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	201	/* figure out the listen interval based on dtim period and skip */
	202	if (slp_itrvl == 0xFF)
	203	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	204	cpu_to_le32(period * (skip + 1));
	205
	206	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
	207	if (slp_itrvl > period)
	208	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
	209	cpu_to_le32((slp_itrvl / period) * period);
	210
	211	if (skip)
e312c24c	212	cmd->flags \|= IWL_POWER_SLEEP_OVER_DTIM_MSK;
4ad177b5	213	else
e312c24c	214	cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
e312c24c	215
1f37daf3 WYG	216	if (priv->cfg->base_params->shadow_reg_enable)
	217	cmd->flags \|= IWL_POWER_SHADOW_REG_ENA;
	218	else
	219	cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
	220
88e58fc5	221	if (iwl_advanced_bt_coexist(priv)) {
e366176e WYG	222	if (!priv->cfg->bt_params->bt_sco_disable)
	223	cmd->flags \|= IWL_POWER_BT_SCO_ENA;
	224	else
	225	cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	226	}
	227
	228
4ad177b5	229	slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
570af86e	230	if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
4ad177b5	231	cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
570af86e	232	cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
4ad177b5 WYG	233
	234	/* enforce max sleep interval */
	235	for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
	236	if (le32_to_cpu(cmd->sleep_interval[i]) >
	237	(max_sleep[i] * period))
	238	cmd->sleep_interval[i] =
	239	cpu_to_le32(max_sleep[i] * period);
	240	if (i != (IWL_POWER_VEC_SIZE - 1)) {
	241	if (le32_to_cpu(cmd->sleep_interval[i]) >
	242	le32_to_cpu(cmd->sleep_interval[i+1]))
	243	cmd->sleep_interval[i] =
	244	cmd->sleep_interval[i+1];
	245	}
	246	}
e312c24c JB	247
	248	if (priv->power_data.pci_pm)
	249	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
	250	else
	251	cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
	252
4ad177b5 WYG	253	IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
4ad177b5 WYG	254	skip, period);
e312c24c JB	255	IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
	256	}
	257
e312c24c JB	258	static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
e312c24c JB	259	struct iwl_powertable_cmd *cmd)
5da4b55f	260	{
e312c24c	261	memset(cmd, 0, sizeof(*cmd));
5da4b55f	262
e312c24c JB	263	if (priv->power_data.pci_pm)
e312c24c JB	264	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	265
e312c24c	266	IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
5da4b55f MA	267	}
5da4b55f MA	268
e312c24c JB	269	static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
	270	struct iwl_powertable_cmd *cmd,
	271	int dynps_ms, int wakeup_period)
5da4b55f	272	{
4c561a02 JB	273	/*
	274	* These are the original power level 3 sleep successions. The
	275	* device may behave better with such succession and was also
	276	* only tested with that. Just like the original sleep commands,
	277	* also adjust the succession here to the wakeup_period below.
	278	* The ranges are the same as for the sleep commands, 0-2, 3-9
	279	* and >10, which is selected based on the DTIM interval for
	280	* the sleep index but here we use the wakeup period since that
	281	* is what we need to do for the latency requirements.
	282	*/
	283	static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
	284	static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
	285	static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
	286	const u8 *slp_succ = slp_succ_r0;
5cd19c5f	287	int i;
5da4b55f	288
4c561a02 JB	289	if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
	290	slp_succ = slp_succ_r1;
	291	if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
	292	slp_succ = slp_succ_r2;
	293
e312c24c	294	memset(cmd, 0, sizeof(*cmd));
5cd19c5f	295
e312c24c JB	296	cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK \|
e312c24c JB	297	IWL_POWER_FAST_PD; /* no use seeing frames for others */
5da4b55f	298
e312c24c JB	299	if (priv->power_data.pci_pm)
e312c24c JB	300	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	301
1f37daf3 WYG	302	if (priv->cfg->base_params->shadow_reg_enable)
	303	cmd->flags \|= IWL_POWER_SHADOW_REG_ENA;
	304	else
	305	cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
	306
88e58fc5	307	if (iwl_advanced_bt_coexist(priv)) {
e366176e WYG	308	if (!priv->cfg->bt_params->bt_sco_disable)
	309	cmd->flags \|= IWL_POWER_BT_SCO_ENA;
	310	else
	311	cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
	312	}
	313
e312c24c JB	314	cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
e312c24c JB	315	cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
5da4b55f	316
5cd19c5f	317	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
4c561a02 JB	318	cmd->sleep_interval[i] =
4c561a02 JB	319	cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));
e312c24c JB	320
	321	IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
	322	}
5da4b55f	323
e312c24c JB	324	static int iwl_set_power(struct iwl_priv priv, struct iwl_powertable_cmd cmd)
	325	{
	326	IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
e1623446 TW	327	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	328	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	329	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	330	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
5da4b55f MA	331	le32_to_cpu(cmd->sleep_interval[0]),
	332	le32_to_cpu(cmd->sleep_interval[1]),
	333	le32_to_cpu(cmd->sleep_interval[2]),
	334	le32_to_cpu(cmd->sleep_interval[3]),
	335	le32_to_cpu(cmd->sleep_interval[4]));
	336
e312c24c JB	337	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
e312c24c JB	338	sizeof(struct iwl_powertable_cmd), cmd);
5da4b55f MA	339	}
5da4b55f MA	340
ac4f5457 SG	341	static void iwl_power_build_cmd(struct iwl_priv *priv,
ac4f5457 SG	342	struct iwl_powertable_cmd *cmd)
5da4b55f	343	{
4d695921	344	bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
e312c24c	345	int dtimper;
5da4b55f	346
3a065ab3	347	dtimper = priv->hw->conf.ps_dtim_period ?: 1;
e312c24c	348
23c0fcc6	349	if (priv->hw->conf.flags & IEEE80211_CONF_IDLE)
ac4f5457	350	iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
f42e7662	351	else if (iwl_tt_is_low_power_state(priv)) {
6ddbf8cd	352	/* in thermal throttling low power state */
ac4f5457	353	iwl_static_sleep_cmd(priv, cmd,
f42e7662	354	iwl_tt_current_power_mode(priv), dtimper);
0975cc8f	355	} else if (!enabled)
ac4f5457	356	iwl_power_sleep_cam_cmd(priv, cmd);
e312c24c	357	else if (priv->power_data.debug_sleep_level_override >= 0)
ac4f5457	358	iwl_static_sleep_cmd(priv, cmd,
e312c24c JB	359	priv->power_data.debug_sleep_level_override,
e312c24c JB	360	dtimper);
3f1e5f4a	361	else if (iwlagn_mod_params.no_sleep_autoadjust)
ac4f5457	362	iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
e312c24c	363	else
ac4f5457	364	iwl_power_fill_sleep_cmd(priv, cmd,
e312c24c JB	365	priv->hw->conf.dynamic_ps_timeout,
e312c24c JB	366	priv->hw->conf.max_sleep_period);
ac4f5457 SG	367	}
	368
	369	int iwl_power_set_mode(struct iwl_priv priv, struct iwl_powertable_cmd cmd,
	370	bool force)
	371	{
	372	int ret;
	373	bool update_chains;
	374
	375	lockdep_assert_held(&priv->mutex);
	376
	377	/* Don't update the RX chain when chain noise calibration is running */
	378	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE \|\|
	379	priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
	380
	381	if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
	382	return 0;
	383
	384	if (!iwl_is_ready_rf(priv))
	385	return -EIO;
	386
	387	/* scan complete use sleep_power_next, need to be updated */
	388	memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
	389	if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
	390	IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
	391	return 0;
	392	}
	393
	394	if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
	395	set_bit(STATUS_POWER_PMI, &priv->status);
5da4b55f	396
ac4f5457 SG	397	ret = iwl_set_power(priv, cmd);
	398	if (!ret) {
	399	if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
	400	clear_bit(STATUS_POWER_PMI, &priv->status);
	401
	402	if (priv->cfg->ops->lib->update_chain_flags && update_chains)
	403	priv->cfg->ops->lib->update_chain_flags(priv);
	404	else if (priv->cfg->ops->lib->update_chain_flags)
	405	IWL_DEBUG_POWER(priv,
3a780d25	406	"Cannot update the power, chain noise "
a71c8f62 WT	407	"calibration running: %d\n",
a71c8f62 WT	408	priv->chain_noise_data.state);
ac4f5457 SG	409
	410	memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
	411	} else
	412	IWL_ERR(priv, "set power fail, ret = %d", ret);
5da4b55f MA	413
	414	return ret;
	415	}
ac4f5457 SG	416
	417	int iwl_power_update_mode(struct iwl_priv *priv, bool force)
	418	{
	419	struct iwl_powertable_cmd cmd;
	420
	421	iwl_power_build_cmd(priv, &cmd);
	422	return iwl_power_set_mode(priv, &cmd, force);
	423	}
5da4b55f	424
a96a27f9	425	/* initialize to default */
5da4b55f MA	426	void iwl_power_initialize(struct iwl_priv *priv)
5da4b55f MA	427	{
e312c24c JB	428	u16 lctl = iwl_pcie_link_ctl(priv);
	429
	430	priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
	431
	432	priv->power_data.debug_sleep_level_override = -1;
	433
	434	memset(&priv->power_data.sleep_cmd, 0,
	435	sizeof(priv->power_data.sleep_cmd));
5da4b55f	436	}