[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-power.c

/******************************************************************************
 *
 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *****************************************************************************/


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>

#include <net/mac80211.h>

#include "iwl-eeprom.h"
#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-commands.h"
#include "iwl-debug.h"
#include "iwl-power.h"

/*
 * Setting power level allow the card to go to sleep when not busy.
 *
 * The power level is set to INDEX_1 (the least deep state) by
 * default, and will, in the future, be the deepest state unless
 * otherwise required by pm_qos network latency requirements.
 *
 * Using INDEX_1 without pm_qos is ok because mac80211 will disable
 * PS when even checking every beacon for the TIM bit would exceed
 * the required latency.
 */

#define IWL_POWER_RANGE_0_MAX  (2)
#define IWL_POWER_RANGE_1_MAX  (10)


#define NOSLP cpu_to_le16(0), 0, 0
#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
#define TU_TO_USEC 1024
#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
				     cpu_to_le32(X1), \
				     cpu_to_le32(X2), \
				     cpu_to_le32(X3), \
				     cpu_to_le32(X4)}
/* default power management (not Tx power) table values */
/* for DTIM period 0 through IWL_POWER_RANGE_0_MAX */
static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
	{{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
};


/* for DTIM period IWL_POWER_RANGE_0_MAX + 1 through IWL_POWER_RANGE_1_MAX */
static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
	{{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 7, 10, 10)}, 2}
};

/* for DTIM period > IWL_POWER_RANGE_1_MAX */
static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
	{{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
};


/* set card power command */
static int iwl_set_power(struct iwl_priv *priv, void *cmd)
{
	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
				sizeof(struct iwl_powertable_cmd), cmd);
}

/* initialize to default */
static void iwl_power_init_handle(struct iwl_priv *priv)
{
	struct iwl_power_mgr *pow_data;
	int size = sizeof(struct iwl_power_vec_entry) * IWL_POWER_NUM;
	struct iwl_powertable_cmd *cmd;
	int i;
	u16 lctl;

	IWL_DEBUG_POWER(priv, "Initialize power \n");

	pow_data = &priv->power_data;

	memset(pow_data, 0, sizeof(*pow_data));

	memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
	memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
	memcpy(&pow_data->pwr_range_2[0], &range_2[0], size);

	lctl = iwl_pcie_link_ctl(priv);

	IWL_DEBUG_POWER(priv, "adjust power command flags\n");

	for (i = 0; i < IWL_POWER_NUM; i++) {
		cmd = &pow_data->pwr_range_0[i].cmd;

		if (lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN)
			cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
		else
			cmd->flags |= IWL_POWER_PCI_PM_MSK;
	}
}

/* adjust power command according to DTIM period and power level*/
static int iwl_update_power_cmd(struct iwl_priv *priv,
				struct iwl_powertable_cmd *cmd, u16 mode)
{
	struct iwl_power_vec_entry *range;
	struct iwl_power_mgr *pow_data;
	int i;
	u32 max_sleep = 0;
	u8 period;
	bool skip;

	if (mode > IWL_POWER_INDEX_5) {
		IWL_DEBUG_POWER(priv, "Error invalid power mode \n");
		return -EINVAL;
	}

	pow_data = &priv->power_data;

	if (pow_data->dtim_period <= IWL_POWER_RANGE_0_MAX)
		range = &pow_data->pwr_range_0[0];
	else if (pow_data->dtim_period <= IWL_POWER_RANGE_1_MAX)
		range = &pow_data->pwr_range_1[0];
	else
		range = &pow_data->pwr_range_2[0];

	period = pow_data->dtim_period;
	memcpy(cmd, &range[mode].cmd, sizeof(struct iwl_powertable_cmd));

	if (period == 0) {
		period = 1;
		skip = false;
	} else {
		skip = !!range[mode].no_dtim;
	}

	if (skip) {
		__le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
		max_sleep = le32_to_cpu(slp_itrvl);
		if (max_sleep == 0xFF)
			max_sleep = period * (skip + 1);
		else if (max_sleep >  period)
			max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
		cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
	} else {
		max_sleep = period;
		cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
	}

	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
		if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
			cmd->sleep_interval[i] = cpu_to_le32(max_sleep);

	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
			le32_to_cpu(cmd->sleep_interval[0]),
			le32_to_cpu(cmd->sleep_interval[1]),
			le32_to_cpu(cmd->sleep_interval[2]),
			le32_to_cpu(cmd->sleep_interval[3]),
			le32_to_cpu(cmd->sleep_interval[4]));

	return 0;
}


/*
 * compute the final power mode index
 */
int iwl_power_update_mode(struct iwl_priv *priv, bool force)
{
	struct iwl_power_mgr *setting = &(priv->power_data);
	int ret = 0;
	u16 uninitialized_var(final_mode);
	bool update_chains;

	/* Don't update the RX chain when chain noise calibration is running */
	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
			priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;

	final_mode = priv->power_data.user_power_setting;

	if (setting->power_disabled)
		final_mode = IWL_POWER_MODE_CAM;

	if (iwl_is_ready_rf(priv) &&
	    ((setting->power_mode != final_mode) || force)) {
		struct iwl_powertable_cmd cmd;

		if (final_mode != IWL_POWER_MODE_CAM)
			set_bit(STATUS_POWER_PMI, &priv->status);

		iwl_update_power_cmd(priv, &cmd, final_mode);
		cmd.keep_alive_beacons = 0;

		if (final_mode == IWL_POWER_INDEX_5)
			cmd.flags |= IWL_POWER_FAST_PD;

		ret = iwl_set_power(priv, &cmd);

		if (final_mode == IWL_POWER_MODE_CAM)
			clear_bit(STATUS_POWER_PMI, &priv->status);

		if (priv->cfg->ops->lib->update_chain_flags && update_chains)
			priv->cfg->ops->lib->update_chain_flags(priv);
		else
			IWL_DEBUG_POWER(priv, "Cannot update the power, chain noise "
					"calibration running: %d\n",
					priv->chain_noise_data.state);
		if (!ret)
			setting->power_mode = final_mode;
	}

	return ret;
}
EXPORT_SYMBOL(iwl_power_update_mode);

/* set user_power_setting */
int iwl_power_set_user_mode(struct iwl_priv *priv, u16 mode)
{
	if (mode >= IWL_POWER_NUM)
		return -EINVAL;

	priv->power_data.user_power_setting = mode;

	return iwl_power_update_mode(priv, 0);
}
EXPORT_SYMBOL(iwl_power_set_user_mode);

/* initialize to default */
void iwl_power_initialize(struct iwl_priv *priv)
{
	iwl_power_init_handle(priv);
	priv->power_data.user_power_setting = IWL_POWER_INDEX_1;
	/* default to disabled until mac80211 says otherwise */
	priv->power_data.power_disabled = 1;
}
EXPORT_SYMBOL(iwl_power_initialize);
Commit	Line	Data
5da4b55f MA	1	/******************************************************************************
5da4b55f MA	2	*
01f8162a	3	* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5da4b55f MA	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
759ef89f	25	* Intel Linux Wireless <ilw@linux.intel.com>
5da4b55f MA	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*****************************************************************************/
	28
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
5da4b55f MA	32	#include <linux/init.h>
	33
	34	#include <net/mac80211.h>
	35
	36	#include "iwl-eeprom.h"
3e0d4cb1	37	#include "iwl-dev.h"
5da4b55f	38	#include "iwl-core.h"
5a36ba0e	39	#include "iwl-commands.h"
5da4b55f MA	40	#include "iwl-debug.h"
5da4b55f MA	41	#include "iwl-power.h"
5da4b55f MA	42
5da4b55f MA	43	/*
7af2c460	44	* Setting power level allow the card to go to sleep when not busy.
5da4b55f	45	*
7af2c460 JB	46	* The power level is set to INDEX_1 (the least deep state) by
	47	* default, and will, in the future, be the deepest state unless
	48	* otherwise required by pm_qos network latency requirements.
5da4b55f	49	*
7af2c460 JB	50	* Using INDEX_1 without pm_qos is ok because mac80211 will disable
	51	* PS when even checking every beacon for the TIM bit would exceed
	52	* the required latency.
5da4b55f MA	53	*/
5da4b55f MA	54
5da4b55f MA	55	#define IWL_POWER_RANGE_0_MAX (2)
	56	#define IWL_POWER_RANGE_1_MAX (10)
	57
	58
7af2c460 JB	59	#define NOSLP cpu_to_le16(0), 0, 0
	60	#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
	61	#define TU_TO_USEC 1024
	62	#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
	63	#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
	64	cpu_to_le32(X1), \
	65	cpu_to_le32(X2), \
	66	cpu_to_le32(X3), \
	67	cpu_to_le32(X4)}
5da4b55f	68	/* default power management (not Tx power) table values */
7af2c460 JB	69	/* for DTIM period 0 through IWL_POWER_RANGE_0_MAX */
7af2c460 JB	70	static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
5da4b55f MA	71	{{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
	72	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	73	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
	74	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
	75	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
	76	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
	77	};
	78
	79
7af2c460 JB	80	/* for DTIM period IWL_POWER_RANGE_0_MAX + 1 through IWL_POWER_RANGE_1_MAX */
7af2c460 JB	81	static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
5da4b55f MA	82	{{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
	83	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
	84	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
	85	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
	86	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
	87	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 7, 10, 10)}, 2}
	88	};
	89
7af2c460 JB	90	/* for DTIM period > IWL_POWER_RANGE_1_MAX */
7af2c460 JB	91	static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
5da4b55f MA	92	{{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
	93	{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
	94	{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
	95	{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	96	{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
	97	{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
	98	};
	99
d25aabb0	100
ca579617 MA	101	/* set card power command */
	102	static int iwl_set_power(struct iwl_priv priv, void cmd)
	103	{
f0f74a0e JB	104	return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
f0f74a0e JB	105	sizeof(struct iwl_powertable_cmd), cmd);
ca579617	106	}
5da4b55f MA	107
5da4b55f MA	108	/* initialize to default */
5cd19c5f	109	static void iwl_power_init_handle(struct iwl_priv *priv)
5da4b55f	110	{
5da4b55f	111	struct iwl_power_mgr *pow_data;
7af2c460	112	int size = sizeof(struct iwl_power_vec_entry) * IWL_POWER_NUM;
e7b63581 TW	113	struct iwl_powertable_cmd *cmd;
e7b63581 TW	114	int i;
3fdb68de	115	u16 lctl;
5da4b55f	116
e1623446	117	IWL_DEBUG_POWER(priv, "Initialize power \n");
5da4b55f	118
5cd19c5f	119	pow_data = &priv->power_data;
5da4b55f MA	120
	121	memset(pow_data, 0, sizeof(*pow_data));
	122
	123	memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
	124	memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
	125	memcpy(&pow_data->pwr_range_2[0], &range_2[0], size);
	126
3fdb68de	127	lctl = iwl_pcie_link_ctl(priv);
5da4b55f	128
e1623446	129	IWL_DEBUG_POWER(priv, "adjust power command flags\n");
5da4b55f	130
7af2c460	131	for (i = 0; i < IWL_POWER_NUM; i++) {
e7b63581	132	cmd = &pow_data->pwr_range_0[i].cmd;
5da4b55f	133
3fdb68de	134	if (lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN)
e7b63581 TW	135	cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
	136	else
	137	cmd->flags \|= IWL_POWER_PCI_PM_MSK;
5da4b55f	138	}
5da4b55f MA	139	}
5da4b55f MA	140
a96a27f9	141	/* adjust power command according to DTIM period and power level*/
5cd19c5f WT	142	static int iwl_update_power_cmd(struct iwl_priv *priv,
5cd19c5f WT	143	struct iwl_powertable_cmd *cmd, u16 mode)
5da4b55f	144	{
5da4b55f	145	struct iwl_power_vec_entry *range;
5da4b55f	146	struct iwl_power_mgr *pow_data;
5cd19c5f WT	147	int i;
	148	u32 max_sleep = 0;
	149	u8 period;
	150	bool skip;
5da4b55f MA	151
5da4b55f MA	152	if (mode > IWL_POWER_INDEX_5) {
e1623446	153	IWL_DEBUG_POWER(priv, "Error invalid power mode \n");
5cd19c5f	154	return -EINVAL;
5da4b55f	155	}
5cd19c5f WT	156
5cd19c5f WT	157	pow_data = &priv->power_data;
5da4b55f MA	158
	159	if (pow_data->dtim_period <= IWL_POWER_RANGE_0_MAX)
	160	range = &pow_data->pwr_range_0[0];
	161	else if (pow_data->dtim_period <= IWL_POWER_RANGE_1_MAX)
	162	range = &pow_data->pwr_range_1[0];
	163	else
	164	range = &pow_data->pwr_range_2[0];
	165
	166	period = pow_data->dtim_period;
ca579617	167	memcpy(cmd, &range[mode].cmd, sizeof(struct iwl_powertable_cmd));
5da4b55f MA	168
	169	if (period == 0) {
	170	period = 1;
5cd19c5f	171	skip = false;
5da4b55f	172	} else {
5cd19c5f WT	173	skip = !!range[mode].no_dtim;
	174	}
	175
	176	if (skip) {
5da4b55f MA	177	__le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
	178	max_sleep = le32_to_cpu(slp_itrvl);
	179	if (max_sleep == 0xFF)
	180	max_sleep = period * (skip + 1);
	181	else if (max_sleep > period)
	182	max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
	183	cmd->flags \|= IWL_POWER_SLEEP_OVER_DTIM_MSK;
5cd19c5f WT	184	} else {
	185	max_sleep = period;
	186	cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
5da4b55f MA	187	}
5da4b55f MA	188
5cd19c5f	189	for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
5da4b55f MA	190	if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
5da4b55f MA	191	cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
5da4b55f	192
e1623446 TW	193	IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
	194	IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
	195	IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
	196	IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
5da4b55f MA	197	le32_to_cpu(cmd->sleep_interval[0]),
	198	le32_to_cpu(cmd->sleep_interval[1]),
	199	le32_to_cpu(cmd->sleep_interval[2]),
	200	le32_to_cpu(cmd->sleep_interval[3]),
	201	le32_to_cpu(cmd->sleep_interval[4]));
	202
5cd19c5f	203	return 0;
5da4b55f MA	204	}
	205
	206
	207	/*
a33c2f47	208	* compute the final power mode index
5da4b55f	209	*/
04816448	210	int iwl_power_update_mode(struct iwl_priv *priv, bool force)
5da4b55f MA	211	{
	212	struct iwl_power_mgr *setting = &(priv->power_data);
	213	int ret = 0;
	214	u16 uninitialized_var(final_mode);
a71c8f62	215	bool update_chains;
5da4b55f	216
04816448	217	/* Don't update the RX chain when chain noise calibration is running */
a71c8f62 WT	218	update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE \|\|
a71c8f62 WT	219	priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
04816448	220
7af2c460	221	final_mode = priv->power_data.user_power_setting;
5da4b55f	222
7af2c460	223	if (setting->power_disabled)
5da4b55f MA	224	final_mode = IWL_POWER_MODE_CAM;
5da4b55f MA	225
7af2c460	226	if (iwl_is_ready_rf(priv) &&
04816448	227	((setting->power_mode != final_mode) \|\| force)) {
ca579617	228	struct iwl_powertable_cmd cmd;
5da4b55f MA	229
	230	if (final_mode != IWL_POWER_MODE_CAM)
	231	set_bit(STATUS_POWER_PMI, &priv->status);
	232
5cd19c5f	233	iwl_update_power_cmd(priv, &cmd, final_mode);
5da4b55f MA	234	cmd.keep_alive_beacons = 0;
	235
	236	if (final_mode == IWL_POWER_INDEX_5)
	237	cmd.flags \|= IWL_POWER_FAST_PD;
	238
ca579617	239	ret = iwl_set_power(priv, &cmd);
5da4b55f MA	240
	241	if (final_mode == IWL_POWER_MODE_CAM)
	242	clear_bit(STATUS_POWER_PMI, &priv->status);
5da4b55f	243
a71c8f62	244	if (priv->cfg->ops->lib->update_chain_flags && update_chains)
5da4b55f	245	priv->cfg->ops->lib->update_chain_flags(priv);
a71c8f62	246	else
e1623446	247	IWL_DEBUG_POWER(priv, "Cannot update the power, chain noise "
a71c8f62 WT	248	"calibration running: %d\n",
a71c8f62 WT	249	priv->chain_noise_data.state);
5da4b55f MA	250	if (!ret)
	251	setting->power_mode = final_mode;
	252	}
	253
	254	return ret;
	255	}
	256	EXPORT_SYMBOL(iwl_power_update_mode);
	257
5da4b55f MA	258	/* set user_power_setting */
	259	int iwl_power_set_user_mode(struct iwl_priv *priv, u16 mode)
	260	{
7af2c460	261	if (mode >= IWL_POWER_NUM)
5da4b55f MA	262	return -EINVAL;
	263
	264	priv->power_data.user_power_setting = mode;
	265
04816448	266	return iwl_power_update_mode(priv, 0);
5da4b55f MA	267	}
	268	EXPORT_SYMBOL(iwl_power_set_user_mode);
	269
a96a27f9	270	/* initialize to default */
5da4b55f MA	271	void iwl_power_initialize(struct iwl_priv *priv)
5da4b55f MA	272	{
5da4b55f	273	iwl_power_init_handle(priv);
7af2c460 JB	274	priv->power_data.user_power_setting = IWL_POWER_INDEX_1;
	275	/* default to disabled until mac80211 says otherwise */
	276	priv->power_data.power_disabled = 1;
5da4b55f MA	277	}
5da4b55f MA	278	EXPORT_SYMBOL(iwl_power_initialize);